[CPU] Support avx isa by default
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parent
debd27a9f2
commit
57da3c73fe
4
build.sh
4
build.sh
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@ -60,7 +60,7 @@ usage()
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echo " -l Compile with python dependency, default on"
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echo " -S Enable enable download cmake compile dependency from gitee , default off"
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echo " -k Enable make clean, clean up compilation generated cache "
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echo " -W Enable x86_64 SSE or AVX instruction set, use [sse|avx|neon|off], default off"
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echo " -W Enable x86_64 SSE or AVX instruction set, use [sse|avx|neon|off], default off for lite and avx for CPU"
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echo " -H Enable hidden"
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echo " -L Link and specify Tensor-RT library path, default disable Tensor-RT lib linking"
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}
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@ -387,7 +387,7 @@ build_mindspore()
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echo "start build mindspore project."
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mkdir -pv "${BUILD_PATH}/mindspore"
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cd "${BUILD_PATH}/mindspore"
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CMAKE_ARGS="-DDEBUG_MODE=$DEBUG_MODE -DBUILD_PATH=$BUILD_PATH -DX86_64_SIMD=${X86_64_SIMD}"
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CMAKE_ARGS="-DDEBUG_MODE=$DEBUG_MODE -DBUILD_PATH=$BUILD_PATH"
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if [[ "X$ENABLE_COVERAGE" = "Xon" ]]; then
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CMAKE_ARGS="${CMAKE_ARGS} -DENABLE_COVERAGE=ON"
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fi
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@ -6,18 +6,13 @@ include_directories(${CMAKE_SOURCE_DIR}/mindspore/core/mindrt/include)
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include_directories(${CMAKE_SOURCE_DIR}/mindspore/core/mindrt/src)
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if(ENABLE_CPU)
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if(${CMAKE_HOST_SYSTEM_PROCESSOR} MATCHES "aarch64")
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set(PLATFORM_ARM64 "on")
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set(X86_64_SIMD "off")
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elseif("${X86_64_SIMD}" STREQUAL "off")
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set(X86_64_SIMD "avx")
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endif()
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include_directories(${CMAKE_CURRENT_SOURCE_DIR}/backend/kernel_compiler/cpu)
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if("${X86_64_SIMD}" STREQUAL "sse")
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add_compile_definitions(ENABLE_SSE)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -msse4.1 -msse4.2")
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -msse4.1 -msse4.2")
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endif()
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if("${X86_64_SIMD}" STREQUAL "avx")
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add_compile_definitions(ENABLE_SSE)
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add_compile_definitions(ENABLE_AVX)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -msse4.1 -msse4.2 -mfma -mavx -mavx2")
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set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -msse4.1 -msse4.2 -mfma -mavx -mavx2")
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endif()
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add_subdirectory(backend/kernel_compiler/cpu/nnacl)
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endif()
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@ -13,9 +13,6 @@ if(PLATFORM_ARM32 OR PLATFORM_ARM64)
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-ffunction-sections -fdata-sections -ffast-math")
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endif()
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endif()
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if(ENABLE_CPU)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fPIC")
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endif()
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if("${X86_64_SIMD}" STREQUAL "avx")
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -msse4.1 -mavx -mavx2 -mfma")
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endif()
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@ -59,21 +56,27 @@ if(APPLE)
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set_source_files_properties(${ASSEMBLY_SRC} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp")
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endif()
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########################### build nnacl static library ########################
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########################### build nnacl library ########################
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string(REPLACE "-fvisibility=hidden" "-fvisibility=default" CMAKE_C_FLAGS "${CMAKE_C_FLAGS}")
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add_library(nnacl_mid OBJECT ${KERNEL_SRC} ${TRAIN_SRC} ${ASSEMBLY_SRC})
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if(ENABLE_CPU)
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add_library(nnacl SHARED $<TARGET_OBJECTS:nnacl_mid>)
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add_library(nnacl SHARED ${KERNEL_SRC} ${TRAIN_SRC} ${ASSEMBLY_SRC})
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if(${CMAKE_HOST_SYSTEM_PROCESSOR} MATCHES "aarch64")
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target_compile_definitions(nnacl PRIVATE ENABLE_ARM ENABLE_ARM64 ENABLE_NEON)
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target_compile_options(nnacl PRIVATE -ffast-math -flax-vector-conversions)
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elseif("${X86_64_SIMD}" STREQUAL "sse")
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target_compile_definitions(nnacl PRIVATE ENABLE_SSE)
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elseif("${X86_64_SIMD}" STREQUAL "avx")
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target_compile_definitions(nnacl PRIVATE ENABLE_SSE ENABLE_AVX)
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endif()
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target_compile_options(nnacl PRIVATE -fPIC)
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if(NOT CMAKE_SYSTEM_NAME MATCHES "Windows")
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target_link_options(nnacl PRIVATE -Wl,-z,relro,-z,now)
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endif()
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else()
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add_library(nnacl_mid OBJECT ${KERNEL_SRC} ${TRAIN_SRC} ${ASSEMBLY_SRC})
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add_library(nnacl STATIC $<TARGET_OBJECTS:nnacl_mid>)
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endif()
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if(NOT ENABLE_CPU)
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add_dependencies(nnacl_mid fbs_src)
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endif()
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########################### arm fp16 build optimize library ########################
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if(ENABLE_FP16)
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add_subdirectory(${NNACL_DIR}/optimize)
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@ -86,7 +86,11 @@ int LRelu(const float *src, int length, float *dst, float alpha) {
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for (; i < length - 4; i += 4) {
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MS_FLOAT32X4 src_tmp = MS_LDQ_F32(src + i);
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MS_FLOAT32X4 mul_tmp = MS_MULQ_N_F32(src_tmp, alpha);
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#ifdef ENABLE_ARM
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MS_UINT32X4 mask = MS_CMPGTQ_F32(src_tmp, MS_MOVQ_F32(0.0f));
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#else
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MS_FLOAT32X4 mask = MS_CMPGTQ_F32(src_tmp, MS_MOVQ_F32(0.0f));
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#endif
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MS_STQ_F32(dst + i, MS_BLENDQ_F32(mul_tmp, src_tmp, mask));
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}
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#endif
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@ -29,6 +29,7 @@
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#ifdef ENABLE_ARM
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#define MS_FLOAT32X4 float32x4_t
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#define MS_INT32X4 int32x4_t
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#define MS_UINT32X4 uint32x4_t
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#define MS_LDQ_F32 vld1q_f32
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#define MS_LDQ_EPI32 vld1q_s32
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#define MS_ADDQ_F32 vaddq_f32
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