clean up extra trace messages in SidebandSingle workload
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parent
7e5ad88780
commit
7d17e00003
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@ -170,14 +170,11 @@ struct SidebandSingleWorkload : TestWorkload {
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try {
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// tr.setOption(FDBTransactionOptions::CAUSAL_WRITE_RISKY);
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tr.set(messageKey, LiteralStringRef("deadbeef"));
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TraceEvent("DebugSidebandBeforeCommit");
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wait(tr.commit());
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commitVersion = tr.getCommittedVersion();
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TraceEvent("DebugSidebandAfterCommit").detail("CommitVersion", commitVersion);
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break;
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} catch (Error& e) {
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if (e.code() == error_code_commit_unknown_result) {
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TraceEvent("DebugSidebandUnknownResult");
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unknown = true;
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++self->messages;
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checker.updates.send(SidebandMessage(key, invalidVersion));
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@ -202,10 +199,8 @@ struct SidebandSingleWorkload : TestWorkload {
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state Transaction tr(cx);
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loop {
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try {
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TraceEvent("DebugSidebandCacheGetBefore");
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tr.setOption(FDBTransactionOptions::USE_GRV_CACHE);
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state Optional<Value> val = wait(tr.get(messageKey));
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TraceEvent("DebugSidebandCacheGetAfter");
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if (!val.present()) {
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TraceEvent(SevError, "CausalConsistencyError1", self->interf.id())
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.detail("MessageKey", messageKey.toString().c_str())
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@ -214,15 +209,12 @@ struct SidebandSingleWorkload : TestWorkload {
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tr.getReadVersion().get()); // will assert that ReadVersion is set
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++self->consistencyErrors;
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} else if (val.get() != LiteralStringRef("deadbeef")) {
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TraceEvent("DebugSidebandOldBeef");
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// check again without cache, and if it's the same, that's expected
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state Transaction tr2(cx);
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state Optional<Value> val2;
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loop {
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try {
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TraceEvent("DebugSidebandNoCacheGetBefore");
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wait(store(val2, tr2.get(messageKey)));
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TraceEvent("DebugSidebandNoCacheGetAfter");
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break;
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} catch (Error& e) {
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TraceEvent("DebugSidebandNoCacheError").error(e, true);
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