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env-xs-ov-00-bpu/rtl/uFTB/FauFTBWay.sv

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update rtl source code with H-extension
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// Generated by CIRCT firtool-1.62.0
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
update rtl source code with H-extension
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module FauFTBWay( // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
input clock, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
input reset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
input [15:0] io_req_tag, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [3:0] io_resp_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [11:0] io_resp_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [1:0] io_resp_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [3:0] io_resp_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [19:0] io_resp_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [1:0] io_resp_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output [3:0] io_resp_pftAddr, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_carry, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_always_taken_0, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_always_taken_1, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_resp_hit, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [15:0] io_update_req_tag, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
output io_update_hit, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [3:0] io_write_entry_brSlots_0_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [11:0] io_write_entry_brSlots_0_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [1:0] io_write_entry_brSlots_0_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_brSlots_0_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [3:0] io_write_entry_tailSlot_offset, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [19:0] io_write_entry_tailSlot_lower, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [1:0] io_write_entry_tailSlot_tarStat, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_tailSlot_sharing, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_tailSlot_valid, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [3:0] io_write_entry_pftAddr, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_carry, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_always_taken_0, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input io_write_entry_always_taken_1, // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
input [15:0] io_write_tag // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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);
update rtl source code with H-extension
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reg [3:0] data_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [11:0] data_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [1:0] data_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [3:0] data_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [19:0] data_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [1:0] data_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [3:0] data_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg data_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
reg [15:0] tag; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:58:16]
reg valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22]
always @(posedge clock) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
if (io_write_valid) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:45:14]
data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_tailSlot_offset <= io_write_entry_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_tailSlot_lower <= io_write_entry_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_tailSlot_valid <= io_write_entry_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_pftAddr <= io_write_entry_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_carry <= io_write_entry_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_always_taken_0 <= io_write_entry_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
data_always_taken_1 <= io_write_entry_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:57:17]
tag <= io_write_tag; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:58:16]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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end
end // always @(posedge)
update rtl source code with H-extension
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always @(posedge clock or posedge reset) begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
if (reset) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
valid <= 1'h0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22]
else // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
valid <= io_write_valid & ~valid | valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22, :68:25, :69:{11,19}, :70:13]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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end // always @(posedge, posedge)
update rtl source code with H-extension
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`ifdef ENABLE_INITIAL_REG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
`ifdef FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
`FIRRTL_BEFORE_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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`endif // FIRRTL_BEFORE_INITIAL
update rtl source code with H-extension
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logic [31:0] _RANDOM[0:2]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
initial begin // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
`ifdef INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
`INIT_RANDOM_PROLOG_ // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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`endif // INIT_RANDOM_PROLOG_
update rtl source code with H-extension
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`ifdef RANDOMIZE_REG_INIT // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
update rtl source code with H-extension
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_RANDOM[i] = `RANDOM; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
end // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
data_brSlots_0_offset = _RANDOM[2'h0][4:1]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_brSlots_0_lower = _RANDOM[2'h0][16:5]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_brSlots_0_valid = _RANDOM[2'h0][20]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_tailSlot_offset = _RANDOM[2'h0][24:21]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_tailSlot_sharing = _RANDOM[2'h1][15]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_tailSlot_valid = _RANDOM[2'h1][16]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_pftAddr = _RANDOM[2'h1][20:17]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_carry = _RANDOM[2'h1][21]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_always_taken_0 = _RANDOM[2'h1][26]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
data_always_taken_1 = _RANDOM[2'h1][27]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17, :58:16]
valid = _RANDOM[2'h2][12]; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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`endif // RANDOMIZE_REG_INIT
update rtl source code with H-extension
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if (reset) // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
valid = 1'h0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:59:22]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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end // initial
update rtl source code with H-extension
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`ifdef FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
`FIRRTL_AFTER_INITIAL // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
update rtl source code with H-extension
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assign io_resp_brSlots_0_offset = data_brSlots_0_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_brSlots_0_lower = data_brSlots_0_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_brSlots_0_valid = data_brSlots_0_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_tailSlot_offset = data_tailSlot_offset; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_tailSlot_lower = data_tailSlot_lower; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_tailSlot_sharing = data_tailSlot_sharing; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_tailSlot_valid = data_tailSlot_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_pftAddr = data_pftAddr; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_carry = data_carry; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_always_taken_0 = data_always_taken_0; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_always_taken_1 = data_always_taken_1; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17]
assign io_resp_hit = tag == io_req_tag & valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :62:{22,37}]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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assign io_update_hit =
update rtl source code with H-extension
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tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; // @[src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :64:{26,49,59}, :65:{35,58}]
initial BPU sub moudle build makefile contain uFTB,Tage_SC,FTB
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endmodule