mirror of https://github.com/llvm/circt.git
512cc7a817
Make `ImportVerilog` honor the `singleUnit` option by either adding all source files to a single preprocessor (single unit), or creating a fresh preprocessor for every single file (multiple units). Fixes #6680. |
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| .. | ||
| include | ||
| commandline.sv | ||
| preprocess-errors.sv | ||
| preprocess-multiple-files.sv | ||
| preprocess.sv | ||