mirror of https://github.com/llvm/circt.git
0de3af4d44
Add a test to check that arcilator can simulate a simple clock divider. This exercises a corner case of arcilator's simulation model scheduling, where a state updating its value can trigger other states and module outptus to update their values. In this case, a cascade of clock edges is generated by feeding one state's output into the clock input of the next state. |
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|---|---|---|
| .. | ||
| basic.mlir | ||
| clock-divider.mlir | ||
| counter.mlir | ||
| div-by-zero.mlir | ||
| dpi.mlir | ||
| err-not-found.mlir | ||
| err-not-func.mlir | ||
| err-wrong-func.mlir | ||
| initial-shift-reg.mlir | ||
| lifecycle.mlir | ||
| print.mlir | ||
| reg.mlir | ||
| runtime-environment.mlir | ||