Convert tests to use "invalidate" and not "is invalid". The latter is
supposed to be illegal in FIRRTL >=3.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Reject parsing registers that use the "reg with" syntax if the FIRRTL
version is 3 or higher.
Towards #7731.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
FIRRTL spec 3.0.0 dropped support for the "reg with" syntax for specifying
a register with a reset in favor of the simpler "regreset" syntax. Update
all tests to use this new syntax.
This is preparing to start rejecting this syntax if the reported FIRRTL
version is 3.0.0+.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Migrate all FIRRTL tests to FIRRTL spec version 3.0+. Many tests were
still using "a <= b" and "c is invalid" syntax which was deprecated in
FIRRTL 3.0. This was _not_ deprecated in CIRCT's FIRRTL parser, though.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Expand the API of the InstanceInfo analysis to include queries for if
something is in the "effective" design. This is equivalent to querying if
something is not under a layer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Extend the existing InstanceInfo analysis to track information about if a
module is in the "design". The design is defined is everything that is or
is under the design-under-test, but is not in a layer. I.e., this
excludes things that are in layers.
This is added because it is not possible to compute this using the
existing information about something being under the DUT or under a layer.
A module could have mixed instantiation under the DUT and mixed
instantiation under a layer, yet not be in the design.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Manually format the MLIR in the emit-metadata.mlir test as the current
state is difficult for me to read. This doesn't cleanup the FileCheck
lines.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Update the CreateSiFiveMetadata pass to use the InstanceInfo analysis to
check if modules/memories are instantiated under the effective DUT as
opposed to using custom logic to check this.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This fixes https://github.com/llvm/circt/issues/7716. Aggregate constant verifier rejects unknown attributes hence hw.aggregate_constant cannot be used for attributes defined by other dialects (in this case seq.const_clock) was rejected even when hw.aggregate_create allows users to create clock type arrays. This PR loosen the restriction by allowing TypedAttribute.
This commits also adds TypedAttrInterface to seq.const_clock and support its lowering.
Fix a bug where the internal `underDut` member was not correctly asserted
if the top module is the DUT.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Move annotations used only for a lit test into the test as inline
annotations. This annotaiton file is only used for that test and is never
optionally included, e.g., there are multiple RUN lines and only some of
them use the annotation file.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
This changes the OM dialect Class/ExternClass to use a return style
field name/type specifier syntax and, for non-extern class, a terminator
op in the style of hw.output.
Change the `CheckLayers` pass to use the `InstanceInfo` analysis. This
new analysis makes the error checking trivial. However, the error
reporting is still somewhat tedious.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Previously, cosim store its ESI channel to cosim channel name in the
`implDetails`. DMA engines to make channel communication work in real
hardware need this information as well.
Pass the current services table when requesting bundle ports. Not (yet)
used in CIRCT but is required for an internal DMA engine. Useful for any
DMA engine but we haven't open sourced any.
The service request wiring code now picks up connection requests issued
by service generators previously run. This allows hierarchical services.
Too difficult to test with CIRCT tests. Will be tested in the PyCDE
tests in a subsequent PR.
We're already doing a best-effort preservation of discardable attributes through `narrowOperationWidth`. I cannot think of a reason why the inherent two-state attribute should not be carried over.
Add the `MergeIfs` pass to the Arc dialect. This pass covers a handful
of control flow optimizations that are valuable to pick up after
`hw.module`s have been linearized and lowered into `arc.model` ops:
- It moves operations closer to their earliest user, if possible sinking
them into blocks if all uses are nested in the same block.
- It merges adjacent `scf.if` operations with the same condition.
- It moves operations in between two `scf.if` operations ahead of the
first if op to allow them to be merged.
The `MergeIfs` pass can operate on SSACFG regions. It assigns an integer
order to each operation and considers that order to determine up to
which point operations can be moved without moving beyond their first
use and without crossing interfering side-effecting ops. The pass is
aware of side-effects, and in particular uses the non-aliasing between
`arc.state` and `arc.memory` to track read/write side-effects at a
per-state level, which allows for fairly aggressive optimization. Other
side-effecting ops act as a hard barrier and will not be moved or moved
over.
This pass supersedes the very effective `GroupResetsAndEnables` pass
we have been using until now. The latter relies on the
`LegalizeStateUpdate` pass to run at a later point however, which will
be removed in a future PR, thus making this new pass necessary.
This is a preparatory step for a later PR that overhauls the LowerState
pass. That rewrite will make the `arc.clock_tree` and `arc.passthrough`
ops obsolete, which is why they are not present in the tests.
* Define type conversion mapping rwprobe<T> -> passive(T)
* Forceable support (passive read of data result)
* RWProbeOp support (materialize target, to passive)
* Reject {force,release}{,_initial}
Add some basic tests.
Remove the `RegionKindInterface` from `arc.model` such that its body
region becomes an SSACFG region. The current implementation of the
LowerState pass already creates models which honor SSA dominance, and
future improvements to the Arc dialect will benefit from models
enforcing dominance.
Add the `arc.final` op to complement the existing `arc.initial`. The
body of `arc.final` is executed after the last time step, when the
simulation is shut down. This corresponds to SystemVerilog's `final`
procedure, and can also be used to report statistics about which `cover`
statements were hit, or to check if an `eventually` property has been
satisfied.
The `arc.final` op is extracted into a `*_final` function. The contract
with the user is that the `*_final` function must be called exactly once
after the last call to `*_eval`. The simulation lifetime now looks like
this:
```
design_initial()
design_eval()
design_eval()
design_eval()
...
design_eval()
design_final()
```
The `arc.sim.instantiate` op inserts a corresponding call to `*_final`
when lowering to LLVM.
Slightly tweak the summary and description fields of a few Arc ops and
add missing tests for `arc.state_write` and `arc.state_read` to the
basic Arc dialect test.
We used to duplicate InvalidValues to their uses, so that each use could
be inferred separately. This was because InvalidValues were considered
constants, and things like CSE might combine many unknown-width invalid
values, and we wanted to counteract this affect. InvalidValues are no
longer pure, and so will not be CSE'd away this way anymore, making this
code no longer needed.
UnifyTypes works by setting the LHS's expression to point at the RHS's.
Running declareVars on the LHS before unifying the expressions is
pointless, as these VarExprs will just end up dangling. This change
stops creating the useless VarExprs.
This changes InferWidths to stop eagerly creating KnownExprs for every
operation with a known width result, and instead creates them when
needed for an actual expression.
We are currently storing all allocated expressions in a single giant
vector, which we later use to find VarExprs and DerivedExprs. This
changes it to keep two separate dedicated vectors which only store the
type of exprs we are interested in. It would be nice if we could iterate
over all objects in a SpecificBumpPtrAllocator, but they don't expose
such an API.
The KnownExpr always has a known width, but it stores this width using
the Expr base class' memoized solution field. To make things a bit
clearer, add an accessor for this value that doesn't return an
optional width.
Schuyler Eldridge