This change moves two InferfaceInstanceOp and GetModportOp to use the
symbol user op interface when checking the referenced operation. This
significantly reduces the cost of verifying this.
Making this an inherent attribute means that it will be stored in the
properties of the operation. Some module-like classes already had
declared it as an input, but our older modules kinds did not.
Make ExpandWhen's folding of the when condition into LTL properties work
for more inputs. This used to be very brittle and the condition would
be mapped to a new implication around the entire property:
when (a):
assert(@(posedge clock) b |-> c)
used to become
assert(a |-> @(posedge clock) b |-> c)
This commit improves on this by always pushing implications behind
clocks, and by merging implications like `a |-> b |-> c` into a single
`(a & b) |-> c`. As a result, ExpandWhens now produces the following
output, which is more in line with what users expect:
assert(@(posedge clock) a & b |-> c)
Also add a FIR-to-Verilog test to nail this behavior down and ensure we
don't regress on user expectations.
Extend `ltl.and`, `ltl.or`, and `ltl.intersect` to infer their return
type as `i1` if all operands are `i1`. Also add a canonicalization
method that replaces these ops with `comb.and` and `comb.or` if they
operate entirely on `i1`.
HWInstanceLike is currently 'empty' and thus essentially the same as InstanceGraphInstanceOpInterface. On the other hand, HWModuleLike deals with port names and hw::InstanceOp caches them and verifies they match the referenced module's port names. This PR basically makes this behavior part of what it means to be an HWInstanceLike. If one has an instance operation that does not deal with port names, it's still possible to just make it an InstanceGraphInstanceOpInterface directly
Extend circt-test to export the input MLIR file as Verilog and then run
all discovered tests through a simple SymbiYosys runner script. This is
currently very rigid: all tests are always run, and they all run through
the exact same runner script. In the future, we'll want to add filtering
mechanisms to include and exclude tests, and pick among multiple runner
scripts for each test.
Also add a basic integration test that builds an adder from discrete
logic gates and then verifies it through multiple `verif.formal` ops.
To run this you need to have SymbiYosys installed. In the future we'll
want to have `circt-bmc` and other CIRCT-based verification tools
available as runners as well.
Add the `TestSuite` and `Test` classes to represent the discovered
tests. Instead of directly printing ops to the output, first traverse
the provided MLIR module and populate a test suite object with the
discovered tests. Then print the list of tests in the test suite.
A separate test discovery step will later allow us to discover tests via
other means, for example, by scanning an entire Verilog directory for
marker comments.
Avoid the ambigous "token" term and use the same naming as the Moore dialect for
a part of a formatting string.
Signed-off-by: Leon Hielscher <hielscher@fzi.de>
Drop the `let constructor` line from the Verif pass definitions. This
causes TableGen to automatically generate the constructors for these
passes, and also handle pass options if we ever decide to add them.
This requires adding a `...Pass` to the end of each pass def to produce
a constructor name of the form `create...Pass()`.
* create register based on type
* support calyx constant op and the corresponding emitter
Co-authored-by: Chris Gyurgyik <Gyurgyikcp@gmail.com>
---------
Co-authored-by: Chris Gyurgyik <Gyurgyikcp@gmail.com>
This enables properties in the FIRRTL dialect. Some op parsers which
called `inferReturnTypes` had to be updated to store inherent attributes
as properties on the OperationState, as the call to `inferReturnTypes`
expects properties to have already been populated. This is a change
that we should make for all operation parsers and builders, to make
things faster, but is not strictly necessary at this time.
This is a big change to clean up our implementation of
`inferReturnTypes` in an effort to get ourselves ready to enable
properties in the FIRRTL dialect. We had structured our API so that
`inferReturnType` would call out to a simpler version of itself with
some of the useless arguments removed. This prevented us from using op
adaptors to abstract over whether or not an inherent attribute was
contained inside the attr-dict or the properties.
This change keeps the old structure of a two level API, but with
different boundaries: The large API takes all arguments, creates an
adapter, pulls out the necessary attributes and then calls in to the
simpler interface. FIRParser uses the simpler API when inferring return
types. The simpler interface is now specific to each operation and not
common with other operations.
This last change caused a problem for `parsePrimExp`, which relied on a
generic interface to create all expressions. This function is now
templated over exactly how many arguments the specific prim op takes,
parses exactly that many, and splats them out when calling
`inferReturnType`. As an upside to this, we can also call a more
specific builder for each operation, which should speed up building
operations when we move to properties.
Ensure the ordering of the fields of a bundle, when its cast to a UInt.
This commit ensures that the left-to-right order of fields is the high-to-low-order.
This adds a conversion pass from AIG dialect to Comb dialect. AndInverterOp can be easily converted into comb.and + comb.xor + hw.constant.
This enables us to utilize core dialects tools for synthesis results without any addition. Primarly use case is running LEC on IR before and after synthesis.
Slightly tweak the `verif.contract`, `verif.require`, and `verif.ensure`
ops to match the usage outlined in the Verif dialect documentation. This
also adjusts the operands and constraints slightly.
Add a test to check that arcilator can simulate a simple clock divider.
This exercises a corner case of arcilator's simulation model scheduling,
where a state updating its value can trigger other states and module
outptus to update their values. In this case, a cascade of clock edges
is generated by feeding one state's output into the clock input of the
next state.
This is a complete rewrite of the `LowerState` pass that makes the
`LegalizeStateUpdate` pass obsolete.
The old implementation of `LowerState` produces `arc.model`s that still
contain read-after-write conflicts. This primarily happens because the
pass simply emits `arc.state_write` operations that write updated values
to simulation memory for each `arc.state`, and any user of `arc.state`
would use an `arc.state_read` operation to retrieve the original value
of the state before any writes occurred. Memories are similar. The Arc
dialect considers `arc.state_write` and `arc.memory_write` operations to
be _deferred_ writes until the `LegalizeStateUpdate` pass runs, at which
point they become _immediate_ since the legalization inserts the
necessary temporaries to resolve the read-after-write conflicts.
The previous implementation would also not handle state-to-output and
state-to-side-effecting-op propagation paths correctly. When a model's
eval function is called, registers are updated to their new value, and
any outputs that combinatorially depend on those new values should also
immediately update. Similarly, operations such as asserts or debug
trackers should observe new values for states immediately after they
have been written. However, since all writes are considered deferred,
there is no way for `LowerState` to produce a mixture of operations that
depend on a register's _old_ state (because they are used to compute a
register's new state), and on a _new_ state because they are
combinatorially derived values.
This new implementation of `LowerState` completely avoids
read-after-write conflicts. It does this by changing the way modules are
lowered in two ways:
**Phases:** The pass tracks in which _phase_ of the simulation lifecycle
a value is needed and allows for operations to have different lowerings
in different phases. An `arc.state` operation for example requires its
inputs, enable, and reset to be computed based on the _old_ value they
had, i.e. the value the end of the previous call to the model's eval
function. The clock however has to be computed based on the _new_ value
it has in the current call to eval. Therefore, the ops defining the
inputs, enable, and reset are lowered in the _old_ phase, while the ops
defining the clock are lowered in the _new_ phase. The `arc.state` op
lowering will then write its _new_ value to simulation storage.
This phase tracking allows registers to be used as the clock for other
registers: since the clocks require _new_ values, registers serving as
clock to others are lowered first, such that the dependent registers can
immediately react to the updated clock. It also allows for module
outputs and side-effecting ops based on `arc.state`s to be scheduled
after the states have been updated, since they depend on the state's
_new_ value.
The pass also covers the situation where an operation depends on a
module input and a state, and feeds into a module output as well as
another state. In this situation that operation has to be lowered twice:
once for the _old_ phase to serve as input to the subsequent state, and
once for the _new_ phase to compute the new module output.
In addition to the _old_ and _new_ phases representing the previous and
current call to eval, the pass also models an _initial_ and _final_
phase. These are used for `seq.initial` and `llhd.final` ops, and in
order to compute the initial values for states. If an `arc.state` op has
an initial value operand it is lowered in the _initial_ phase. Similarly
for the ops in `llhd.final`. The pass places all ops lowered in the
initial and final phases into corresponding `arc.initial` and
`arc.final` ops. At a later point we may want to generate the
`*_initial`, `*_eval`, and `*_final` functions directly.
**No more clock trees:** The new implementation also no longer generates
`arc.clock_tree` and `arc.passthrough` operations. These were a holdover
from the early days of the Arc dialect, where no eval function would be
generated. Instead, the user was required to directly call clock
functions. This was never able to model clocks changing at the exact
same moment, or having clocks derived from registers and other
combinatorial operations. Since Arc has since switched to generating an
eval function that can accurately interleave the effects of different
clocks, grouping ops by clock tree is no longer needed. In fact,
removing the clock tree ops allows for the pass to more efficiently
interleave the operations from different clock domains.
The Rocket core in the circt/arc-tests repository still works with this
new implementation of LowerState. In combination with the MergeIfs pass
the performance stays the same.
I have renamed the implementation and test files to make the git diffs
easier to read. The names will be changed back in a follow-up commit.
Fixes#6390.
In FIRRTL, all expression operations have a `validate` hook which can be
used to check operands and attributes before passing them in to
`inferResultTypes`. FIRParser will verify the same invariants right
before calling `validate`, making it redundant. Since `validate` is
only called from the parser, we can delete the entire hook.
Add a region verifier to OM dialect's Class Op. This verifies that the
terminator returns the right number of fields with the correct types that
match the declared type of the Class Op.
Fixes#7736.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add a few examples of how contracts can be used to modularize formal
verification. These will likely become integration tests once the
machinery to execute them is in place.
verif.assume can be used to annotate pre-condtion directly in the
IR. This is quite useful when verifying transformation which involves
undefined values. For example when lowering comb.shl to AIG, the
conversion pass chooses arbitary values for out-of-bounds situation.
So we cannot verify the equivalence unless we specify the pre-condtion
with verif.assume
The `aig.cut` operation represents a cut in the And-Inverter-Graph.
This operation is variadic and can take multiple inputs and outputs,
which corresponds to the input and output edges in AIG conceptually.
This adds a conversion pass from Comb to AIG. Currently conversion patterns for variadic `comb.or/and`
and binary xor are supported. There will be a follow up to implement conversion patterns for arithmetic ops.
This commit adds AIG LowerVariadic pass to lower variadic AndInverter
op to have at most two operands. This makes IR closer to traditinal
AIG representation combined with LowerWordToBits pass
This commit adds `aig.and_inv` op that represents an And-Inverter in AIG.
DenseBoolArray `inverted` field specifies if each operand is inverted.
This commit also adds a basic canonicalizer for it.
This change enables the use of operation properties for more dialects in
CIRCT. The option to *not* use properties is going to be removed in a
future release of MLIR, but as well we expect this change to bring a
performance improvement.
For all these dialects, the only change required was to properly infer
return types. Some operations were hardcoded to search through the
attributes, and the attribute was moved to the property storage. By
using the generated adaptor classes, we can abstract over where the
interesting attribute is stored.
For future work, some code may be refactored for further performance
wins now that we are using properties. In particular usages `setAttr`
and `getAttr` may be made faster by using a less generic op
transformation interface.
Add support for invalidation syntax that invalidates an instance or a
memory. This was never technically supported before, though it should
have been. Previously, this was only supported through the "is invalid"
path which is has been deprecated for FIRRTL versions >=3.
Fixes#7730.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Get rid of usages of the deprecated '<=' connect syntax that is not
supported in FIRRTL versions >=3.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Andrew Young