mirror of https://github.com/llvm/circt.git
Advanced LayerSink (#7548)
This commit is contained in:
Robert Young
GitHub
parent
c0e31955ce
commit
ec8ffaf4fe
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@ -195,6 +195,8 @@ std::unique_ptr<mlir::Pass> createLayerMergePass();
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std::unique_ptr<mlir::Pass> createLayerSinkPass();
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std::unique_ptr<mlir::Pass> createAdvancedLayerSinkPass();
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std::unique_ptr<mlir::Pass> createMaterializeDebugInfoPass();
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std::unique_ptr<mlir::Pass> createLintingPass();
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@ -857,6 +857,15 @@ def LayerSink : Pass<"firrtl-layer-sink", "firrtl::FModuleOp"> {
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];
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}
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def AdvancedLayerSink : Pass<"firrtl-advanced-layer-sink", "firrtl::CircuitOp"> {
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let summary = "Sink operations into layer blocks";
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let description = [{
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This pass sinks ops into layers, whenever possible, to minimize unused
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hardware in the design.
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}];
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let constructor = "::circt::firrtl::createAdvancedLayerSinkPass()";
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}
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def MaterializeDebugInfo :
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Pass<"firrtl-materialize-debug-info", "firrtl::FModuleOp"> {
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let summary = "Generate debug ops to track FIRRTL values";
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@ -98,6 +98,7 @@ public:
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bool shouldConvertProbesToSignals() const { return probesToSignals; }
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bool shouldReplaceSequentialMemories() const { return replSeqMem; }
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bool shouldDisableOptimization() const { return disableOptimization; }
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bool shouldAdvancedLayerSink() const { return advancedLayerSink; }
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bool shouldLowerMemories() const { return lowerMemories; }
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bool shouldDedup() const { return !noDedup; }
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bool shouldEnableDebugInfo() const { return enableDebugInfo; }
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@ -231,6 +232,11 @@ public:
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return *this;
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}
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FirtoolOptions &setAdvancedLayerSink(bool value) {
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advancedLayerSink = value;
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return *this;
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}
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FirtoolOptions &setLowerMemories(bool value) {
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lowerMemories = value;
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return *this;
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@ -382,6 +388,7 @@ private:
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bool disableAggressiveMergeConnections;
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bool emitOMIR;
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std::string omirOutFile;
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bool advancedLayerSink;
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bool lowerMemories;
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std::string blackBoxRootPath;
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bool replSeqMem;
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@ -0,0 +1,458 @@
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//===- AdvancedLayerSink.cpp - Sink ops into layer blocks -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass sinks operations into layer blocks.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/FIRRTL/FIRRTLInstanceGraph.h"
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#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
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#include "circt/Dialect/FIRRTL/Passes.h"
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#include "circt/Support/Debug.h"
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#include "mlir/IR/Dominance.h"
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#include "mlir/IR/Iterators.h"
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#include "mlir/IR/Threading.h"
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#include "mlir/Interfaces/ControlFlowInterfaces.h"
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#include "mlir/Interfaces/SideEffectInterfaces.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/ControlFlowSinkUtils.h"
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#define DEBUG_TYPE "firrtl-layer-sink"
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namespace circt {
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namespace firrtl {
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#define GEN_PASS_DEF_ADVANCEDLAYERSINK
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#include "circt/Dialect/FIRRTL/Passes.h.inc"
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} // namespace firrtl
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} // namespace circt
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using namespace circt;
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using namespace firrtl;
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using namespace mlir;
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//===----------------------------------------------------------------------===//
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// Helpers
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//===----------------------------------------------------------------------===//
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// NOLINTBEGIN(misc-no-recursion)
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namespace {
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/// Walk the ops in `block` bottom-up, back-to-front order. The block walk API
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/// in upstream MLIR, although it takes an Iterator parameter, will always walk
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/// the top block front-to-back. This walk function will actually walk the ops
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/// under `block` back-to-front.
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template <typename T>
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void walkBwd(Block *block, T &&f) {
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for (auto &op :
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llvm::make_early_inc_range(llvm::reverse(block->getOperations()))) {
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for (auto ®ion : op.getRegions())
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for (auto &block : region.getBlocks())
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walkBwd(&block, f);
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f(&op);
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}
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}
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} // namespace
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// NOLINTEND(misc-no-recursion)
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static bool isAncestor(Block *block, Block *other) {
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if (block == other)
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return true;
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return block->getParent()->isProperAncestor(other->getParent());
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}
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//===----------------------------------------------------------------------===//
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// Effectfulness Analysis.
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//===----------------------------------------------------------------------===//
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/// A table that can determine whether an operation is effectful.
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namespace {
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class EffectInfo {
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public:
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EffectInfo(CircuitOp circuit, InstanceGraph &instanceGraph) {
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DenseSet<InstanceGraphNode *> visited;
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for (auto *root : instanceGraph) {
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for (auto *node : llvm::post_order_ext(root, visited)) {
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auto *op = node->getModule().getOperation();
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update(op);
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}
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}
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}
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/// True if the given operation is NOT moveable due to some effect.
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bool effectful(Operation *op) const {
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if (!AnnotationSet(op).canBeDeleted() || hasDontTouch(op))
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return true;
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if (auto name = dyn_cast<FNamableOp>(op))
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if (!name.hasDroppableName())
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return true;
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if (op->getNumRegions() != 0)
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return true;
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if (auto instance = dyn_cast<InstanceOp>(op))
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return effectfulModules.contains(instance.getModuleNameAttr().getAttr());
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if (isa<FConnectLike, WireOp, RegResetOp, RegOp, MemOp, NodeOp>(op))
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return false;
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return !(mlir::isMemoryEffectFree(op) ||
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mlir::hasSingleEffect<mlir::MemoryEffects::Allocate>(op) ||
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mlir::hasSingleEffect<mlir::MemoryEffects::Read>(op));
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}
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private:
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/// Record whether the module contains any effectful ops.
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void update(FModuleOp module) {
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module.getBodyBlock()->walk([&](Operation *op) {
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if (effectful(op)) {
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markEffectful(module);
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return WalkResult::interrupt();
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}
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return WalkResult::advance();
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});
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}
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void update(FModuleLike module) {
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if (!AnnotationSet(module).canBeDeleted())
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return markEffectful(module);
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auto *op = module.getOperation();
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// Regular modules may be pure.
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if (auto m = dyn_cast<FModuleOp>(op))
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return update(m);
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// Memory modules are pure.
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if (auto m = dyn_cast<FMemModuleOp>(op))
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return;
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// All other kinds of modules are effectful.
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// intmodules, extmodules, classes.
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return markEffectful(module);
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}
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void update(Operation *op) {
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if (auto module = dyn_cast<FModuleLike>(op))
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update(module);
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}
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/// Record that the given module contains an effectful operation.
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void markEffectful(FModuleLike module) {
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effectfulModules.insert(module.getModuleNameAttr());
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}
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DenseSet<StringAttr> effectfulModules;
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};
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} // namespace
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//===----------------------------------------------------------------------===//
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// Demands Analysis.
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//===----------------------------------------------------------------------===//
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namespace {
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/// The LCA of the blocks in which a value is used/demanded. Lattice value.
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struct Demand {
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constexpr Demand() : Demand(nullptr) {}
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constexpr Demand(Block *block) : block(block) {}
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constexpr Demand merge(Demand other) const {
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if (block == other.block)
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return Demand(block);
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if (other.block == nullptr)
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return Demand(block);
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if (block == nullptr)
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return Demand(other.block);
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auto *b = block;
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while (b && !isAncestor(b, other.block))
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b = b->getParentOp()->getBlock();
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return Demand(b);
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}
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bool mergeIn(Demand other) {
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auto prev = *this;
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auto next = merge(other);
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*this = next;
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return prev != next;
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}
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constexpr bool operator==(Demand rhs) const { return block == rhs.block; }
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constexpr bool operator!=(Demand rhs) const { return block != rhs.block; }
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constexpr operator bool() const { return block; }
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Block *block;
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};
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} // namespace
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/// True if this operation is a good site to sink operations.
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static bool isValidDest(Operation *op) {
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return op && (isa<LayerBlockOp>(op) || isa<FModuleOp>(op));
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}
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/// True if we are prevented from sinking operations into the regions of the op.
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static bool isBarrier(Operation *op) { return !isValidDest(op); }
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/// Adjust the demand based on the location of the op being demanded. Ideally,
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/// we can sink an op directly to its site of use. However, there are two
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/// issues.
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///
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/// 1) Typically, an op will dominate every demand, but for hardware
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/// declarations such as wires, the declaration will demand any connections
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/// driving it. In this case, the relationship is reversed: the demander
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/// dominates the demandee. This can cause us to pull connect-like ops up and
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/// and out of their enclosing block (ref-defines can be buried under
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/// layerblocks). To avoid this, we set an upper bound on the demand: the
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/// enclosing block of the demandee.
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///
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/// 2) not all regions are valid sink targets. If there is a sink-barrier
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/// between the operation and its demand, we adjust the demand upwards so that
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/// there is no sink barrier between the demandee and the demand site.
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static Demand clamp(Operation *op, Demand demand) {
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if (!demand)
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return nullptr;
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auto *upper = op->getBlock();
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assert(upper && "this should not be called on a top-level operation.");
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if (!isAncestor(upper, demand.block))
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demand = upper;
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for (auto *i = demand.block; i != upper; i = i->getParentOp()->getBlock())
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if (isBarrier(i->getParentOp()))
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demand = i->getParentOp()->getBlock();
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return demand;
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}
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namespace {
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struct DemandInfo {
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using WorkStack = std::vector<Operation *>;
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DemandInfo(const EffectInfo &, FModuleOp);
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Demand getDemandFor(Operation *op) const { return table.lookup(op); }
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/// Starting at effectful ops and output ports, propagate the demand of values
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/// through the design, running until fixpoint. At the end, we have an
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/// accurate picture of where every operation can be sunk, while preserving
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/// effects in the program.
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void run(const EffectInfo &, FModuleOp, WorkStack &);
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/// Update the demand for the given op. If the demand changes, place the op
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/// onto the worklist.
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void update(WorkStack &work, Operation *op, Demand demand) {
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if (table[op].mergeIn(clamp(op, demand)))
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work.push_back(op);
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}
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void update(WorkStack &work, Value value, Demand demand) {
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if (auto result = dyn_cast<OpResult>(value))
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update(work, cast<OpResult>(value).getOwner(), demand);
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}
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void updateConnects(WorkStack &, Value, Demand);
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void updateConnects(WorkStack &, Operation *, Demand);
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llvm::DenseMap<Operation *, Demand> table;
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};
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} // namespace
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DemandInfo::DemandInfo(const EffectInfo &effectInfo, FModuleOp module) {
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WorkStack work;
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Block *body = module.getBodyBlock();
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ArrayRef<bool> dirs = module.getPortDirections();
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for (unsigned i = 0, e = module.getNumPorts(); i < e; ++i)
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if (direction::get(dirs[i]) == Direction::Out)
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updateConnects(work, body->getArgument(i), module.getBodyBlock());
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module.getBodyBlock()->walk([&](Operation *op) {
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if (effectInfo.effectful(op))
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update(work, op, op->getBlock());
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});
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run(effectInfo, module, work);
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}
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void DemandInfo::run(const EffectInfo &effectInfo, FModuleOp, WorkStack &work) {
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while (!work.empty()) {
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auto *op = work.back();
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work.pop_back();
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auto demand = getDemandFor(op);
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for (auto operand : op->getOperands())
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update(work, operand, demand);
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updateConnects(work, op, demand);
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}
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}
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// The value represents a hardware declaration, such as a wire or port. Search
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// backwards through uses, looking through aliasing operations such as
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// subfields, to find connects that drive the given value. All driving
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// connects of a value are demanded by the same region as the value. If the
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// demand of the connect op is updated, then the demand will propagate
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// forwards to its operands through the normal forward-propagation of demand.
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void DemandInfo::updateConnects(WorkStack &work, Value value, Demand demand) {
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struct StackElement {
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Value value;
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Value::user_iterator it;
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};
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SmallVector<StackElement> stack;
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stack.push_back({value, value.user_begin()});
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while (!stack.empty()) {
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auto &top = stack.back();
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auto end = top.value.user_end();
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while (true) {
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if (top.it == end) {
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stack.pop_back();
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break;
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}
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auto *user = *(top.it++);
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if (auto connect = dyn_cast<FConnectLike>(user)) {
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if (connect.getDest() == top.value) {
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update(work, connect, demand);
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}
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continue;
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}
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if (isa<SubfieldOp, SubindexOp, SubaccessOp, ObjectSubfieldOp>(user)) {
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for (auto result : user->getResults())
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stack.push_back({result, result.user_begin()});
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break;
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}
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}
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}
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}
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void DemandInfo::updateConnects(WorkStack &work, Operation *op, Demand demand) {
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if (isa<WireOp, RegResetOp, RegOp, MemOp, ObjectOp>(op)) {
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for (auto result : op->getResults())
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updateConnects(work, result, demand);
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} else if (auto inst = dyn_cast<InstanceOp>(op)) {
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auto dirs = inst.getPortDirections();
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for (unsigned i = 0, e = inst->getNumResults(); i < e; ++i) {
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if (direction::get(dirs[i]) == Direction::In)
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updateConnects(work, inst.getResult(i), demand);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// ModuleLayerSink
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//===----------------------------------------------------------------------===//
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namespace {
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class ModuleLayerSink {
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public:
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static bool run(FModuleOp module, const EffectInfo &effectInfo) {
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return ModuleLayerSink(module, effectInfo)();
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}
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private:
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ModuleLayerSink(FModuleOp module, const EffectInfo &effectInfo)
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: module(module), effectInfo(effectInfo) {}
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bool operator()();
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void moveLayersToBack(Operation *op);
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void moveLayersToBack(Block *block);
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FModuleOp module;
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const EffectInfo &effectInfo;
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bool changed;
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};
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} // namespace
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// NOLINTNEXTLINE(misc-no-recursion)
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void ModuleLayerSink::moveLayersToBack(Operation *op) {
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for (auto &r : op->getRegions())
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for (auto &b : r.getBlocks())
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moveLayersToBack(&b);
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}
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// NOLINTNEXTLINE(misc-no-recursion)
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void ModuleLayerSink::moveLayersToBack(Block *block) {
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auto i = block->rbegin();
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auto e = block->rend();
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// Leave layerblocks that are already "at the back" where they are.
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while (i != e) {
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auto *op = &*i;
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moveLayersToBack(op);
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if (!isa<LayerBlockOp>(op))
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break;
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++i;
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}
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if (i == e)
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return;
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// We have found a non-layerblock op at position `i`.
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// Any block in front of `i`, will be moved to after `i`.
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auto *ip = &*i;
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while (i != e) {
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auto *op = &*i;
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moveLayersToBack(op);
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if (isa<LayerBlockOp>(op)) {
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++i;
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op->moveAfter(ip);
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changed = true;
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} else {
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++i;
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}
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}
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}
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bool ModuleLayerSink::operator()() {
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moveLayersToBack(module.getBodyBlock());
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DemandInfo demandInfo(effectInfo, module);
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walkBwd(module.getBodyBlock(), [&](Operation *op) {
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auto demand = demandInfo.getDemandFor(op);
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if (!demand) {
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op->erase();
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changed = true;
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return;
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}
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if (demand == op->getBlock())
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return;
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op->moveBefore(demand.block, demand.block->begin());
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changed = true;
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});
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return changed;
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}
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//===----------------------------------------------------------------------===//
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// LayerSinkPass
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//===----------------------------------------------------------------------===//
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namespace {
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/// A control-flow sink pass.
|
||||
struct AdvancedLayerSinkPass final
|
||||
: public circt::firrtl::impl::AdvancedLayerSinkBase<AdvancedLayerSinkPass> {
|
||||
void runOnOperation() override;
|
||||
};
|
||||
} // namespace
|
||||
|
||||
void AdvancedLayerSinkPass::runOnOperation() {
|
||||
auto circuit = getOperation();
|
||||
LLVM_DEBUG(debugPassHeader(this)
|
||||
<< "\n"
|
||||
<< "Circuit: '" << circuit.getName() << "'\n";);
|
||||
auto &instanceGraph = getAnalysis<InstanceGraph>();
|
||||
EffectInfo effectInfo(circuit, instanceGraph);
|
||||
|
||||
std::atomic<bool> changed(false);
|
||||
parallelForEach(&getContext(), circuit.getOps<FModuleOp>(),
|
||||
[&](FModuleOp module) {
|
||||
if (ModuleLayerSink::run(module, effectInfo))
|
||||
changed = true;
|
||||
});
|
||||
|
||||
if (!changed)
|
||||
markAllAnalysesPreserved();
|
||||
else
|
||||
markAnalysesPreserved<InstanceGraph>();
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pass Constructor
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
std::unique_ptr<mlir::Pass> circt::firrtl::createAdvancedLayerSinkPass() {
|
||||
return std::make_unique<AdvancedLayerSinkPass>();
|
||||
}
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
add_circt_dialect_library(CIRCTFIRRTLTransforms
|
||||
AssignOutputDirs.cpp
|
||||
AddSeqMemPorts.cpp
|
||||
AdvancedLayerSink.cpp
|
||||
AssignOutputDirs.cpp
|
||||
BlackBoxReader.cpp
|
||||
CheckCombLoops.cpp
|
||||
CheckLayers.cpp
|
||||
|
|
|
|||
|
|
@ -135,11 +135,14 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
|
|||
if (opt.shouldConvertProbesToSignals())
|
||||
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createProbesToSignalsPass());
|
||||
|
||||
{
|
||||
auto &modulePM = pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>();
|
||||
modulePM.addPass(firrtl::createLayerMergePass());
|
||||
modulePM.addPass(firrtl::createLayerSinkPass());
|
||||
}
|
||||
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
|
||||
firrtl::createLayerMergePass());
|
||||
|
||||
if (opt.shouldAdvancedLayerSink())
|
||||
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createAdvancedLayerSinkPass());
|
||||
else
|
||||
pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
|
||||
firrtl::createLayerSinkPass());
|
||||
|
||||
pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInlinerPass());
|
||||
|
||||
|
|
@ -564,6 +567,11 @@ struct FirtoolCmdOptions {
|
|||
"output-omir", llvm::cl::desc("File name for the output omir"),
|
||||
llvm::cl::init("")};
|
||||
|
||||
llvm::cl::opt<bool> advancedLayerSink{
|
||||
"advanced-layer-sink",
|
||||
llvm::cl::desc("Sink logic into layer blocks (advanced)"),
|
||||
llvm::cl::init(false)};
|
||||
|
||||
llvm::cl::opt<bool> lowerMemories{
|
||||
"lower-memories",
|
||||
llvm::cl::desc("Lower memories to have memories with masks as an "
|
||||
|
|
@ -747,10 +755,11 @@ circt::firtool::FirtoolOptions::FirtoolOptions()
|
|||
exportChiselInterface(false), chiselInterfaceOutDirectory(""),
|
||||
vbToBV(false), noDedup(false), companionMode(firrtl::CompanionMode::Bind),
|
||||
disableAggressiveMergeConnections(false), emitOMIR(true), omirOutFile(""),
|
||||
lowerMemories(false), blackBoxRootPath(""), replSeqMem(false),
|
||||
replSeqMemFile(""), extractTestCode(false), ignoreReadEnableMem(false),
|
||||
disableRandom(RandomKind::None), outputAnnotationFilename(""),
|
||||
enableAnnotationWarning(false), addMuxPragmas(false),
|
||||
advancedLayerSink(false), lowerMemories(false), blackBoxRootPath(""),
|
||||
replSeqMem(false), replSeqMemFile(""), extractTestCode(false),
|
||||
ignoreReadEnableMem(false), disableRandom(RandomKind::None),
|
||||
outputAnnotationFilename(""), enableAnnotationWarning(false),
|
||||
addMuxPragmas(false),
|
||||
verificationFlavor(firrtl::VerificationFlavor::None),
|
||||
emitSeparateAlwaysBlocks(false), etcDisableInstanceExtraction(false),
|
||||
etcDisableRegisterExtraction(false), etcDisableModuleInlining(false),
|
||||
|
|
@ -782,6 +791,7 @@ circt::firtool::FirtoolOptions::FirtoolOptions()
|
|||
clOptions->disableAggressiveMergeConnections;
|
||||
emitOMIR = clOptions->emitOMIR;
|
||||
omirOutFile = clOptions->omirOutFile;
|
||||
advancedLayerSink = clOptions->advancedLayerSink;
|
||||
lowerMemories = clOptions->lowerMemories;
|
||||
blackBoxRootPath = clOptions->blackBoxRootPath;
|
||||
replSeqMem = clOptions->replSeqMem;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,717 @@
|
|||
// RUN: circt-opt -pass-pipeline="builtin.module(firrtl.circuit(firrtl-advanced-layer-sink))" -allow-unregistered-dialect %s | FileCheck %s
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Movement of layers to the back of their containing block.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// using interesting_name to prevent layer-sink from deleting unused wires.
|
||||
|
||||
firrtl.circuit "Top" {
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {}
|
||||
}
|
||||
|
||||
// Empty layerblock.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {}
|
||||
}
|
||||
}
|
||||
|
||||
// Empty layerblock in layerblock.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @B bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: firrtl.layerblock @A::@B {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@B {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Layerblock at end already.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @B bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%w = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Layerblock NOT at end already.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {
|
||||
}
|
||||
%w = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
// Parent layerblock at end already, nested layerblock NOT at end.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @B bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A::@B {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@B {
|
||||
}
|
||||
%w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Parent layerblock NOT at end already, nested layerblock NOT at end.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @B bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A::@B {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@B {
|
||||
}
|
||||
%w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
%w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
// Moving a layer past an op preserves the ordering of layerblocks.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @A1 bind {}
|
||||
firrtl.layer @A2 bind {}
|
||||
firrtl.layer @A3 bind {}
|
||||
}
|
||||
firrtl.layer @B bind {}
|
||||
firrtl.layer @C bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A::@A1 {
|
||||
// CHECK: }
|
||||
// CHECK: firrtl.layerblock @A::@A2 {
|
||||
// CHECK: }
|
||||
// CHECK: firrtl.layerblock @A::@A3 {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: firrtl.layerblock @B {
|
||||
// CHECK: }
|
||||
// CHECK: firrtl.layerblock @C {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@A1 {
|
||||
}
|
||||
firrtl.layerblock @A::@A2 {
|
||||
}
|
||||
%w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
firrtl.layerblock @A::@A3 {
|
||||
}
|
||||
}
|
||||
firrtl.layerblock @B {
|
||||
}
|
||||
%w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
firrtl.layerblock @C {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Parent layerblock NOT at end already, nested layerblock NOT at end.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @B bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A::@B {
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@B {
|
||||
}
|
||||
%w2 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
%w1 = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Basic Sinking.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Sink a chain of expressions.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %0 = firrtl.not %c0_ui1 : (!firrtl.uint<1>) -> !firrtl.uint<1>
|
||||
// CHECK: %node = firrtl.node %0 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%0 = firrtl.not %c0_ui1 : (!firrtl.uint<1>) -> !firrtl.uint<1>
|
||||
%node = firrtl.node %0 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Sink a chain of expressions rooted at an input port.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %0 = firrtl.not %port : (!firrtl.uint<1>) -> !firrtl.uint<1>
|
||||
// CHECK: %node = firrtl.node %0 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %port : !firrtl.uint<1>) {
|
||||
%0 = firrtl.not %port : (!firrtl.uint<1>) -> !firrtl.uint<1>
|
||||
%node = firrtl.node %0 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Sink a node to the LCA of its uses.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {
|
||||
firrtl.layer @A1 bind {}
|
||||
firrtl.layer @A2 bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %node = firrtl.node %port : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A::@A1 {
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: firrtl.layerblock @A::@A2 {
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
%node = firrtl.node %port : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
firrtl.layerblock @A::@A1 {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
firrtl.layerblock @A::@A2 {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output ports are demands: The unknown op should drag %node into layerblock
|
||||
// @A, but the connection to %port, which uses %node as a source, will prevent
|
||||
// the sinking of node into the layerblock.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @Top(out %port: !firrtl.uint<1>) {
|
||||
%c = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%0 = firrtl.not %port : (!firrtl.uint<1>) -> !firrtl.uint<1>
|
||||
%node = firrtl.node %c : !firrtl.uint<1>
|
||||
firrtl.connect %port, %node : !firrtl.uint<1>, !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sinking Loops.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Sink a loop between two wires.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w1 = firrtl.wire : !firrtl.uint<1>
|
||||
// CHECK: %w2 = firrtl.wire : !firrtl.uint<1>
|
||||
// CHECK: firrtl.matchingconnect %w1, %w2 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.matchingconnect %w2, %w1 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%w2) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%w1 = firrtl.wire : !firrtl.uint<1>
|
||||
%w2 = firrtl.wire : !firrtl.uint<1>
|
||||
firrtl.matchingconnect %w1, %w2 : !firrtl.uint<1>
|
||||
firrtl.matchingconnect %w2, %w1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%w2) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Sink a self-connected register.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(in %clock: !firrtl.clock, in %reset: !firrtl.asyncreset) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %r = firrtl.regreset %clock, %reset, %c0_ui1 : !firrtl.clock, !firrtl.asyncreset, !firrtl.uint<1>, !firrtl.uint<1>
|
||||
// CHECK: firrtl.matchingconnect %r, %r : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%r) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %clock: !firrtl.clock, in %reset: !firrtl.asyncreset) {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%r = firrtl.regreset %clock, %reset, %c0_ui1 : !firrtl.clock, !firrtl.asyncreset, !firrtl.uint<1>, !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%r) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
firrtl.matchingconnect %r, %r : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sinking Instances.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Pure instances can be moved.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @Pure(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
firrtl.matchingconnect %o, %i : !firrtl.uint<1>
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %pure_i, %pure_o = firrtl.instance pure @Pure(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
// CHECK: firrtl.matchingconnect %pure_i, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%pure_o) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%pure_i, %pure_o = firrtl.instance pure @Pure(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %pure_i, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%pure_o) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Effectful instances cannot be moved.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @Effectful(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
firrtl.matchingconnect %o, %i : !firrtl.uint<1>
|
||||
"unknown"() : () -> ()
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %effectful_i, %effectful_o = firrtl.instance effectful @Effectful(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
// CHECK: firrtl.matchingconnect %effectful_i, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: "unknown"(%effectful_o) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%effectful_i, %effectful_o = firrtl.instance effectful @Effectful(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %effectful_i, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%effectful_o) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Parents of effectful instances cannot be moved.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @Effectful(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
firrtl.matchingconnect %o, %i : !firrtl.uint<1>
|
||||
"unknown"() : () -> ()
|
||||
}
|
||||
firrtl.module @EffectfulParent(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
%effectful_i, %effectful_o = firrtl.instance effectful @Effectful(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %effectful_i, %i : !firrtl.uint<1>
|
||||
firrtl.matchingconnect %o, %effectful_o : !firrtl.uint<1>
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %parent_i, %parent_o = firrtl.instance parent @EffectfulParent(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
// CHECK: firrtl.matchingconnect %parent_i, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: "unknown"(%parent_o) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%parent_i, %parent_o = firrtl.instance parent @EffectfulParent(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %parent_i, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%parent_o) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Modules with a layerblock cannot be moved, regardless of effectfulness. This
|
||||
// would result in a bind-under-bind.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @HasLayerblock(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
firrtl.matchingconnect %o, %i : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %hasLayerblock_i, %hasLayerblock_o = firrtl.instance hasLayerblock @HasLayerblock(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
// CHECK: firrtl.matchingconnect %hasLayerblock_i, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: "unknown"(%hasLayerblock_o) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%hasLayerblock_i, %hasLayerblock_o = firrtl.instance hasLayerblock @HasLayerblock(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %hasLayerblock_i, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%hasLayerblock_o) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Parents of modules with a layerblock cannot be moved.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
firrtl.module @HasLayerblock(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
firrtl.matchingconnect %o, %i : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {}
|
||||
}
|
||||
firrtl.module @HasLayerblockParent(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>) {
|
||||
%hasLayerblock_i, %hasLayerblock_o = firrtl.instance hasLayerblock @HasLayerblock(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %hasLayerblock_i, %i : !firrtl.uint<1>
|
||||
firrtl.matchingconnect %o, %hasLayerblock_o : !firrtl.uint<1>
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %hasLayerblockParent_i, %hasLayerblockParent_o = firrtl.instance hasLayerblockParent @HasLayerblockParent(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
// CHECK: firrtl.matchingconnect %hasLayerblockParent_i, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: "unknown"(%hasLayerblockParent_o) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%hasLayerblockParent_i, %hasLayerblockParent_o = firrtl.instance hasLayerblockParent @HasLayerblockParent(in i: !firrtl.uint<1>, out o: !firrtl.uint<1>)
|
||||
firrtl.matchingconnect %hasLayerblockParent_i, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%hasLayerblockParent_o) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Connects at end / dominance preservation.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Connect gets dragged forwards into layerblock.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%c0_ui1) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %w = firrtl.wire : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: %0 = firrtl.subfield %w[a] : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: %1 = firrtl.subfield %w[b] : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
// CHECK: firrtl.matchingconnect %0, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: firrtl.matchingconnect %1, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%1) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%w = firrtl.wire : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
%0 = firrtl.subfield %w[a] : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
%1 = firrtl.subfield %w[b] : !firrtl.bundle<a: uint<1>, b: uint<1>>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%1) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
"unknown"(%c0_ui1) : (!firrtl.uint<1>) -> ()
|
||||
firrtl.matchingconnect %0, %c0_ui1 : !firrtl.uint<1>
|
||||
firrtl.matchingconnect %1, %c0_ui1 : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
// Check that layer-sink doesn't accidentally un-nest layerblocks while
|
||||
// rearranging the order of ops.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @L1 bind {
|
||||
firrtl.layer @L2 bind {}
|
||||
}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: firrtl.layerblock @L1 {
|
||||
// CHECK: firrtl.layerblock @L1::@L2 {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %w = firrtl.wire : !firrtl.uint<1>
|
||||
// CHECK: firrtl.matchingconnect %w, %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%w) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%w = firrtl.wire : !firrtl.uint<1>
|
||||
firrtl.layerblock @L1 {
|
||||
firrtl.layerblock @L1::@L2 {
|
||||
"unknown"(%w) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
firrtl.matchingconnect %w, %c0_ui1 : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Connects that are buried in layerblocks, will stay in layerblocks.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Ref-define buried inside layerblock drives a coloured probe port.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(out %port: !firrtl.probe<uint<1>, @A>) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %0 = firrtl.ref.send %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: %1 = firrtl.ref.cast %0 : (!firrtl.probe<uint<1>>) -> !firrtl.probe<uint<1>, @A>
|
||||
// CHECK: firrtl.ref.define %port, %1 : !firrtl.probe<uint<1>, @A>
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(out %port: !firrtl.probe<uint<1>, @A>) {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%0 = firrtl.ref.send %c0_ui1 : !firrtl.uint<1>
|
||||
%1 = firrtl.ref.cast %0 : (!firrtl.probe<uint<1>>) -> !firrtl.probe<uint<1>, @A>
|
||||
firrtl.layerblock @A {
|
||||
firrtl.ref.define %port, %1 : !firrtl.probe<uint<1>, @A>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Ref-define buried inside layerblock drives a coloured wire.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top() {
|
||||
// CHECK: %w = firrtl.wire : !firrtl.probe<uint<1>, @A>
|
||||
// CHECK: "unknown"(%w) : (!firrtl.probe<uint<1>, @A>) -> ()
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// CHECK: %0 = firrtl.ref.send %c0_ui1 : !firrtl.uint<1>
|
||||
// CHECK: %1 = firrtl.ref.cast %0 : (!firrtl.probe<uint<1>>) -> !firrtl.probe<uint<1>, @A>
|
||||
// CHECK: firrtl.ref.define %w, %1 : !firrtl.probe<uint<1>, @A>
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top() {
|
||||
%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
|
||||
%0 = firrtl.ref.send %c0_ui1 : !firrtl.uint<1>
|
||||
%1 = firrtl.ref.cast %0 : (!firrtl.probe<uint<1>>) -> !firrtl.probe<uint<1>, @A>
|
||||
%w = firrtl.wire : !firrtl.probe<uint<1>, @A>
|
||||
"unknown"(%w) : (!firrtl.probe<uint<1>, @A>) -> ()
|
||||
firrtl.layerblock @A {
|
||||
firrtl.ref.define %w, %1 : !firrtl.probe<uint<1>, @A>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Sinking through Whens.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Sink an op that is used under a when, without sinking into the when.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %node = firrtl.node %port : !firrtl.uint<1>
|
||||
// CHECK: firrtl.when %port : !firrtl.uint<1> {
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
%node = firrtl.node %port : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
firrtl.when %port : !firrtl.uint<1> {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Sink an op that is used under both arms of a when, without sinking into the when.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %node = firrtl.node %port : !firrtl.uint<1>
|
||||
// CHECK: firrtl.when %port : !firrtl.uint<1> {
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: } else {
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
%node = firrtl.node %port : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
firrtl.when %port : !firrtl.uint<1> {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
} else {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Check that sinking occurs within a when.
|
||||
firrtl.circuit "Top" {
|
||||
firrtl.layer @A bind {}
|
||||
// CHECK: firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
// CHECK: firrtl.when %port : !firrtl.uint<1> {
|
||||
// CHECK: firrtl.layerblock @A {
|
||||
// CHECK: %node = firrtl.node %port : !firrtl.uint<1>
|
||||
// CHECK: "unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
// CHECK: }
|
||||
firrtl.module @Top(in %port: !firrtl.uint<1>) {
|
||||
firrtl.when %port : !firrtl.uint<1> {
|
||||
%node = firrtl.node %port : !firrtl.uint<1>
|
||||
firrtl.layerblock @A {
|
||||
"unknown"(%node) : (!firrtl.uint<1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Misc
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Tests of things which do not currently sink, but should.
|
||||
//
|
||||
// CHECK-LABEL: firrtl.circuit "LayerSinkExpectedFailures"
|
||||
firrtl.circuit "LayerSinkExpectedFailures" {
|
||||
firrtl.layer @Subaccess bind {}
|
||||
firrtl.layer @Subfield bind {}
|
||||
firrtl.layer @Subindex bind {}
|
||||
|
||||
// CHECK: firrtl.module @LayerSinkExpectedFailures
|
||||
firrtl.module @LayerSinkExpectedFailures(in %a: !firrtl.uint<1>) {
|
||||
// CHECK-NEXT: firrtl.layerblock @Subaccess {
|
||||
// CHECK-NEXT: %wire_subaccess = firrtl.wire
|
||||
// CHECK-NEXT: %0 = firrtl.subaccess %wire_subaccess[%a] : !firrtl.vector<uint<1>, 2>, !firrtl.uint<1>
|
||||
// CHECK-NEXT: firrtl.matchingconnect %0, %0 : !firrtl.uint<1>
|
||||
// CHECK-NEXT: "unknown"(%wire_subaccess) : (!firrtl.vector<uint<1>, 2>) -> ()
|
||||
// CHECK-NEXT: }
|
||||
%wire_subaccess = firrtl.wire : !firrtl.vector<uint<1>, 2>
|
||||
%0 = firrtl.subaccess %wire_subaccess[%a] : !firrtl.vector<uint<1>, 2>, !firrtl.uint<1>
|
||||
firrtl.matchingconnect %0, %0 : !firrtl.uint<1>
|
||||
firrtl.layerblock @Subaccess {
|
||||
"unknown"(%wire_subaccess) : (!firrtl.vector<uint<1>, 2>) -> ()
|
||||
}
|
||||
|
||||
// CHECK-NEXT: firrtl.layerblock @Subfield {
|
||||
// CHECK-NEXT: %wire_subfield = firrtl.wire
|
||||
// CHECK-NEXT: %0 = firrtl.subfield %wire_subfield[a]
|
||||
// CHECK-NEXT: firrtl.matchingconnect %0, %0
|
||||
// CHECK-NEXT: "unknown"(%wire_subfield) : (!firrtl.bundle<a: uint<1>>) -> ()
|
||||
// CHECK-NEXT: }
|
||||
%wire_subfield = firrtl.wire : !firrtl.bundle<a: uint<1>>
|
||||
%1 = firrtl.subfield %wire_subfield[a] : !firrtl.bundle<a: uint<1>>
|
||||
firrtl.matchingconnect %1, %1 : !firrtl.uint<1>
|
||||
firrtl.layerblock @Subfield {
|
||||
"unknown"(%wire_subfield) : (!firrtl.bundle<a: uint<1>>) -> ()
|
||||
}
|
||||
|
||||
// CHECK-NEXT: firrtl.layerblock @Subindex {
|
||||
// CHECK-NEXT: %wire_subindex = firrtl.wire
|
||||
// CHECK-NEXT: %0 = firrtl.subindex %wire_subindex[0]
|
||||
// CHECK-NEXT: firrtl.matchingconnect %0, %0
|
||||
// CHECK-NEXT: "unknown"(%wire_subindex) : (!firrtl.vector<uint<1>, 1>) -> ()
|
||||
// CHECK-NEXT: }
|
||||
%wire_subindex = firrtl.wire : !firrtl.vector<uint<1>, 1>
|
||||
%2 = firrtl.subindex %wire_subindex[0] : !firrtl.vector<uint<1>, 1>
|
||||
firrtl.matchingconnect %2, %2 : !firrtl.uint<1>
|
||||
firrtl.layerblock @Subindex {
|
||||
"unknown"(%wire_subindex) : (!firrtl.vector<uint<1>, 1>) -> ()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
firrtl.circuit "Sub" {
|
||||
firrtl.layer @Subfield bind {}
|
||||
firrtl.module @Sub() {
|
||||
%w = firrtl.wire {annotations = [{class = "firrtl.transforms.DontTouchAnnotation"}]} : !firrtl.bundle<a: uint<1>>
|
||||
%w_a = firrtl.subfield %w[a] : !firrtl.bundle<a: uint<1>>
|
||||
%z = firrtl.constant 0 : !firrtl.uint<1>
|
||||
// {{op connects to a destination which is defined outside its enclosing layer block}}
|
||||
firrtl.matchingconnect %w_a, %z: !firrtl.uint<1>
|
||||
firrtl.layerblock @Subfield {
|
||||
firrtl.node %w_a : !firrtl.uint<1>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
// RUN: circt-opt %s -split-input-file | circt-opt -split-input-file
|
||||
// RUN: firtool %s -split-input-file
|
||||
// RUN: firtool %s -preserve-values=named -split-input-file
|
||||
// These tests are just for demonstrating RefOps, and expected to not error.
|
||||
|
||||
// Simple 1 level read from wire.
|
||||
|
|
@ -27,7 +27,7 @@ firrtl.circuit "SimpleRead" {
|
|||
firrtl.ref.define %_a, %1 : !firrtl.probe<uint<1>>
|
||||
}
|
||||
firrtl.module @SimpleRead() {
|
||||
%bar_a = firrtl.instance bar @Bar(out _a: !firrtl.probe<uint<1>>)
|
||||
%bar_a = firrtl.instance bar interesting_name @Bar(out _a: !firrtl.probe<uint<1>>)
|
||||
%a = firrtl.wire : !firrtl.uint<1>
|
||||
%0 = firrtl.ref.resolve %bar_a : !firrtl.probe<uint<1>>
|
||||
firrtl.matchingconnect %a, %0 : !firrtl.uint<1>
|
||||
|
|
@ -48,7 +48,7 @@ firrtl.circuit "ForwardToInstance" {
|
|||
firrtl.ref.define %_a, %bar_2 : !firrtl.probe<uint<1>>
|
||||
}
|
||||
firrtl.module @ForwardToInstance() {
|
||||
%bar_a = firrtl.instance bar @Bar(out _a: !firrtl.probe<uint<1>>)
|
||||
%bar_a = firrtl.instance bar interesting_name @Bar(out _a: !firrtl.probe<uint<1>>)
|
||||
%a = firrtl.wire : !firrtl.uint<1>
|
||||
%0 = firrtl.ref.resolve %bar_a : !firrtl.probe<uint<1>>
|
||||
firrtl.matchingconnect %a, %0 : !firrtl.uint<1>
|
||||
|
|
@ -74,7 +74,7 @@ firrtl.circuit "ForwardToInstance" {
|
|||
}
|
||||
firrtl.module @ForwardToInstance() {
|
||||
%bar_a = firrtl.instance bar @Bar(out _a: !firrtl.probe<uint<1>>)
|
||||
%a = firrtl.wire : !firrtl.uint<1>
|
||||
%a = firrtl.wire interesting_name : !firrtl.uint<1>
|
||||
// Reader 2
|
||||
%0 = firrtl.ref.resolve %bar_a : !firrtl.probe<uint<1>>
|
||||
firrtl.matchingconnect %a, %0 : !firrtl.uint<1>
|
||||
|
|
@ -98,8 +98,8 @@ firrtl.circuit "DUT" {
|
|||
firrtl.ref.define %ref_out2, %2 : !firrtl.probe<uint<4>>
|
||||
}
|
||||
firrtl.module @DUT() {
|
||||
%view_out1, %view_out2 = firrtl.instance sub @Submodule(out ref_out1: !firrtl.probe<uint<1>>, out ref_out2: !firrtl.probe<uint<4>>)
|
||||
%view_in1, %view_in2 = firrtl.instance MyView_companion @MyView_companion(in ref_in1: !firrtl.uint<1>, in ref_in2: !firrtl.uint<4>)
|
||||
%view_out1, %view_out2 = firrtl.instance sub interesting_name @Submodule(out ref_out1: !firrtl.probe<uint<1>>, out ref_out2: !firrtl.probe<uint<4>>)
|
||||
%view_in1, %view_in2 = firrtl.instance MyView_companion interesting_name @MyView_companion(in ref_in1: !firrtl.uint<1>, in ref_in2: !firrtl.uint<4>)
|
||||
|
||||
%1 = firrtl.ref.resolve %view_out1 : !firrtl.probe<uint<1>>
|
||||
%2 = firrtl.ref.resolve %view_out2 : !firrtl.probe<uint<4>>
|
||||
|
|
@ -155,7 +155,7 @@ firrtl.circuit "Issue3715" {
|
|||
}
|
||||
}
|
||||
firrtl.module @Issue3715(in %p: !firrtl.uint<1>) {
|
||||
%test_in, %test_x = firrtl.instance test @Test(in p: !firrtl.uint<1>, out x: !firrtl.probe<uint<2>>)
|
||||
%test_in, %test_x = firrtl.instance test interesting_name @Test(in p: !firrtl.uint<1>, out x: !firrtl.probe<uint<2>>)
|
||||
firrtl.matchingconnect %test_in, %p : !firrtl.uint<1>
|
||||
%x = firrtl.ref.resolve %test_x : !firrtl.probe<uint<2>>
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue