terapines
/
circt
mirror of https://github.com/llvm/circt.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[FIRRTL] Bump minimum to 2.0.0, remove partial conect (#5075) 

Bump minimum supported FIRRTL to 2.0.0.
"FIRRTL version" is now required as a result.

Remove parsing of the FIRRTL partial connect operator ("<-").  This has,
for a very long time, been almost unreachable from Chisel-emitted FIRRTL
and is now impossible to emit from Chisel.  This has also been completely
removed from the FIRRTL spec in version 2.0.0.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Will Dietz <will.dietz@sifive.com>
This commit is contained in:
Schuyler Eldridge 2024-06-11 12:07:18 -04:00 committed by GitHub
parent 640d59cf0d
commit d9a3a95cca
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
87 changed files with 1470 additions and 1454 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/circt/Dialect/FIRRTL/FIRParser.h
View File

@ -107,10 +107,9 @@ struct FIRVersion {
uint16_t patch;
};
constexpr FIRVersion minimumFIRVersion(0, 2, 0);
constexpr FIRVersion minimumFIRVersion(2, 0, 0);
constexpr FIRVersion nextFIRVersion(3, 3, 0);
constexpr FIRVersion exportFIRVersion(4, 0, 0);
constexpr FIRVersion defaultFIRVersion(1, 0, 0);
template <typename T>
T &operator<<(T &os, FIRVersion version) {

5
integration_test/Dialect/FIRRTL/SFCTests/GrandCentralInterfaces/Wire.fir
View File

@ -2,6 +2,7 @@
; RUN: firtool --verilog --annotation-file %s.anno.json %s > %t.one-file.sv && verilator --sv --lint-only %t.one-file.sv
; REQUIRES: verilator
FIRRTL version 4.0.0
circuit Top :
module Submodule :
input clock : Clock
@ -33,7 +34,7 @@ circuit Top :
output io : { }
wire _WIRE : UInt<1>
_WIRE <= UInt<1>("h0")
_WIRE <= UInt<1>(0h0)
module DUT :
input clock : Clock
@ -74,7 +75,7 @@ circuit Top :
out.uint <= submodule.out.uint
inst MyView_companion of MyView_companion
module Top :
public module Top :
input clock : Clock
input reset : UInt<1>
input in : { uint : UInt<1>, vec : UInt<1>[2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}

1571
integration_test/EmitVerilog/exampleCodeGen.fir
View File

File diff suppressed because it is too large Load Diff

9
integration_test/EmitVerilog/verilog_equiv.fir
View File

@ -9,8 +9,9 @@
;--- test_mod.fir
FIRRTL version 4.0.0
circuit test_mod :
module test_mod :
public module test_mod :
input a: UInt<1>
output b: UInt<1>
b <= a
@ -26,8 +27,9 @@ endmodule
;--- test_unary.fir
FIRRTL version 4.0.0
circuit test_unary :
module test_unary :
public module test_unary :
input uin4: UInt<4>
input sin4: SInt<4>
output out_xorr_u: UInt<1>
@ -137,8 +139,9 @@ endmodule
;--- test_prim.fir
FIRRTL version 4.0.0
circuit test_prim :
module test_prim :
public module test_prim :
input uina4: UInt<4>
input uinb4: UInt<4>
input sina4: SInt<4>

66
lib/Dialect/FIRRTL/FIRRTLTypes.cpp
View File

@ -973,72 +973,6 @@ bool firrtl::areTypesEquivalent(FIRRTLType destFType, FIRRTLType srcFType,
return destType.getConstType(false) == srcType.getConstType(false);
}
/// Returns whether the two types are weakly equivalent.
bool firrtl::areTypesWeaklyEquivalent(FIRRTLType destFType, FIRRTLType srcFType,
bool destFlip, bool srcFlip,
bool destOuterTypeIsConst,
bool srcOuterTypeIsConst) {
auto destType = type_dyn_cast<FIRRTLBaseType>(destFType);
auto srcType = type_dyn_cast<FIRRTLBaseType>(srcFType);
// For non-base types, only equivalent if identical.
if (!destType || !srcType)
return destFType == srcFType;
bool srcIsConst = srcOuterTypeIsConst || srcFType.isConst();
bool destIsConst = destOuterTypeIsConst || destFType.isConst();
// Vector types can be connected if their element types are weakly equivalent.
// Size doesn't matter.
auto destVectorType = type_dyn_cast<FVectorType>(destType);
auto srcVectorType = type_dyn_cast<FVectorType>(srcType);
if (destVectorType && srcVectorType)
return areTypesWeaklyEquivalent(destVectorType.getElementType(),
srcVectorType.getElementType(), destFlip,
srcFlip, destIsConst, srcIsConst);
// Bundle types are weakly equivalent if all common elements are weakly
// equivalent. Non-matching fields are ignored. Flips are "pushed" into
// recursive weak type equivalence checks.
auto destBundleType = type_dyn_cast<BundleType>(destType);
auto srcBundleType = type_dyn_cast<BundleType>(srcType);
if (destBundleType && srcBundleType)
return llvm::all_of(destBundleType, [&](auto destElt) -> bool {
auto destField = destElt.name.getValue();
auto srcElt = srcBundleType.getElement(destField);
// If the src doesn't contain the destination's field, that's okay.
if (!srcElt)
return true;
return areTypesWeaklyEquivalent(
destElt.type, srcElt->type, destFlip ^ destElt.isFlip,
srcFlip ^ srcElt->isFlip, destOuterTypeIsConst, srcOuterTypeIsConst);
});
// Ground types require leaf flippedness and const compatibility
if (destFlip != srcFlip)
return false;
if (destFlip && srcIsConst && !destIsConst)
return false;
if (srcFlip && destIsConst && !srcIsConst)
return false;
// Reset types can be driven by UInt<1>, AsyncReset, or Reset types.
if (type_isa<ResetType>(destType))
return srcType.isResetType();
// Reset types can drive UInt<1>, AsyncReset, or Reset types.
if (type_isa<ResetType>(srcType))
return destType.isResetType();
// Ground types can be connected if their passive, widthless versions
// are equal and are const and flip compatible
auto widthlessDestType = destType.getWidthlessType();
auto widthlessSrcType = srcType.getWidthlessType();
return widthlessDestType.getConstType(false) ==
widthlessSrcType.getConstType(false);
}
/// Returns whether the srcType can be const-casted to the destType.
bool firrtl::areTypesConstCastable(FIRRTLType destFType, FIRRTLType srcFType,
bool srcOuterTypeIsConst) {

2
lib/Dialect/FIRRTL/Import/FIRLexer.cpp
View File

@ -261,8 +261,6 @@ FIRToken FIRLexer::lexTokenImpl() {
case ']':
return formToken(FIRToken::r_square, tokStart);
case '<':
if (*curPtr == '-')
return ++curPtr, formToken(FIRToken::less_minus, tokStart);
if (*curPtr == '=')
return ++curPtr, formToken(FIRToken::less_equal, tokStart);
return formToken(FIRToken::less, tokStart);

129
lib/Dialect/FIRRTL/Import/FIRParser.cpp
View File

@ -1636,9 +1636,6 @@ private:
// the representation simpler and more consistent.
void emitInvalidate(Value val) { emitInvalidate(val, foldFlow(val)); }
/// Emit the logic for a partial connect using standard connect.
void emitPartialConnect(ImplicitLocOpBuilder &builder, Value dst, Value src);
/// Parse an @info marker if present and inform locationProcessor about it.
ParseResult parseOptionalInfo() {
LocationAttr loc;
@ -1802,77 +1799,6 @@ void FIRStmtParser::emitInvalidate(Value val, Flow flow) {
});
}
void FIRStmtParser::emitPartialConnect(ImplicitLocOpBuilder &builder, Value dst,
Value src) {
auto dstType = type_dyn_cast<FIRRTLBaseType>(dst.getType());
auto srcType = type_dyn_cast<FIRRTLBaseType>(src.getType());
if (!dstType || !srcType)
return emitConnect(builder, dst, src);
if (type_isa<AnalogType>(dstType)) {
builder.create<AttachOp>(ArrayRef<Value>{dst, src});
} else if (dstType == srcType && !dstType.containsAnalog()) {
emitConnect(builder, dst, src);
} else if (auto dstBundle = type_dyn_cast<BundleType>(dstType)) {
auto srcBundle = type_cast<BundleType>(srcType);
auto numElements = dstBundle.getNumElements();
for (size_t dstIndex = 0; dstIndex < numElements; ++dstIndex) {
// Find a matching field by name in the other bundle.
auto &dstElement = dstBundle.getElements()[dstIndex];
auto name = dstElement.name;
auto maybe = srcBundle.getElementIndex(name);
// If there was no matching field name, don't connect this one.
if (!maybe)
continue;
auto dstRef = moduleContext.getCachedSubaccess(dst, dstIndex);
if (!dstRef) {
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointAfterValue(dst);
dstRef = builder.create<SubfieldOp>(dst, dstIndex);
}
// We are pulling two fields from the cache. If the dstField was a
// pointer into the cache, then the lookup for srcField might invalidate
// it. So, we just copy dstField into a local.
auto dstField = dstRef;
auto srcIndex = *maybe;
auto &srcField = moduleContext.getCachedSubaccess(src, srcIndex);
if (!srcField) {
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointAfterValue(src);
srcField = builder.create<SubfieldOp>(src, srcIndex);
}
if (!dstElement.isFlip)
emitPartialConnect(builder, dstField, srcField);
else
emitPartialConnect(builder, srcField, dstField);
}
} else if (auto dstVector = type_dyn_cast<FVectorType>(dstType)) {
auto srcVector = type_cast<FVectorType>(srcType);
auto dstNumElements = dstVector.getNumElements();
auto srcNumEelemnts = srcVector.getNumElements();
// Partial connect will connect all elements up to the end of the array.
auto numElements = std::min(dstNumElements, srcNumEelemnts);
for (size_t i = 0; i != numElements; ++i) {
auto &dstRef = moduleContext.getCachedSubaccess(dst, i);
if (!dstRef) {
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointAfterValue(dst);
dstRef = builder.create<SubindexOp>(dst, i);
}
auto dstField = dstRef; // copy to ensure not invalidated
auto &srcField = moduleContext.getCachedSubaccess(src, i);
if (!srcField) {
OpBuilder::InsertionGuard guard(builder);
builder.setInsertionPointAfterValue(src);
srcField = builder.create<SubindexOp>(src, i);
}
emitPartialConnect(builder, dstField, srcField);
}
} else {
emitConnect(builder, dst, src);
}
}
//===-------------------------------
// FIRStmtParser Expression Parsing.
@ -2519,7 +2445,6 @@ FIRStmtParser::parseExpWithLeadingKeyword(FIRToken keyword) {
case FIRToken::l_square: // exp `[` index `]`
case FIRToken::kw_is: // exp is invalid
case FIRToken::less_equal: // exp <= thing
case FIRToken::less_minus: // exp <- thing
break;
}
@ -3876,7 +3801,6 @@ ParseResult FIRStmtParser::parseLayerBlockOrGroup(unsigned indent) {
}
/// leading-exp-stmt ::= exp '<=' exp info?
/// ::= exp '<-' exp info?
/// ::= exp 'is' 'invalid' info?
ParseResult FIRStmtParser::parseLeadingExpStmt(Value lhs) {
auto loc = getToken().getLoc();
@ -3893,18 +3817,8 @@ ParseResult FIRStmtParser::parseLeadingExpStmt(Value lhs) {
}
auto kind = getToken().getKind();
switch (kind) {
case FIRToken::less_equal:
break;
case FIRToken::less_minus:
if (removedFeature({2, 0, 0}, "partial connects"))
return failure();
break;
default:
return emitError() << "unexpected token '" << getToken().getSpelling()
<< "' in statement",
failure();
}
if (getToken().isNot(FIRToken::less_equal))
return emitError("expected '<=' in statement");
consumeToken();
Value rhs;
@ -3921,19 +3835,11 @@ ParseResult FIRStmtParser::parseLeadingExpStmt(Value lhs) {
if (lhsType.containsReference() || rhsType.containsReference())
return emitError(loc, "cannot connect types containing references");
if (kind == FIRToken::less_equal) {
if (!areTypesEquivalent(lhsType, rhsType))
return emitError(loc, "cannot connect non-equivalent type ")
<< rhsType << " to " << lhsType;
emitConnect(builder, lhs, rhs);
} else {
assert(kind == FIRToken::less_minus && "unexpected kind");
if (!areTypesWeaklyEquivalent(lhsType, rhsType))
return emitError(loc,
"cannot partially connect non-weakly-equivalent type ")
<< rhsType << " to " << lhsType;
emitPartialConnect(builder, lhs, rhs);
}
assert(kind == FIRToken::less_equal && "unexpected kind");
if (!areTypesEquivalent(lhsType, rhsType))
return emitError(loc, "cannot connect non-equivalent type ")
<< rhsType << " to " << lhsType;
emitConnect(builder, lhs, rhs);
return success();
}
@ -5412,17 +5318,17 @@ ParseResult FIRCircuitParser::parseCircuit(
mlir::TimingScope &ts) {
auto indent = getIndentation();
if (consumeIf(FIRToken::kw_FIRRTL)) {
if (!indent.has_value())
return emitError("'FIRRTL' must be first token on its line"), failure();
if (parseToken(FIRToken::kw_version, "expected version after 'FIRRTL'") ||
parseVersionLit("expected version literal"))
return failure();
indent = getIndentation();
}
if (parseToken(FIRToken::kw_FIRRTL, "expected 'FIRRTL'"))
return failure();
if (!indent.has_value())
return emitError("'FIRRTL' must be first token on its line");
if (parseToken(FIRToken::kw_version, "expected version after 'FIRRTL'") ||
parseVersionLit("expected version literal"))
return failure();
indent = getIndentation();
if (!indent.has_value())
return emitError("'circuit' must be first token on its line"), failure();
return emitError("'circuit' must be first token on its line");
unsigned circuitIndent = *indent;
LocWithInfo info(getToken().getLoc(), this);
@ -5601,8 +5507,7 @@ circt::firrtl::importFIRFile(SourceMgr &sourceMgr, MLIRContext *context,
/*column=*/0)));
SharedParserConstants state(context, options);
FIRLexer lexer(sourceMgr, context);
FIRVersion version = defaultFIRVersion;
if (FIRCircuitParser(state, lexer, *module, version)
if (FIRCircuitParser(state, lexer, *module, minimumFIRVersion)
.parseCircuit(annotationsBufs, omirBufs, ts))
return nullptr;

1
lib/Dialect/FIRRTL/Import/FIRTokenKinds.def
View File

@ -74,7 +74,6 @@ TOK_PUNCTUATION(l_square, "[")
TOK_PUNCTUATION(r_square, "]")
TOK_PUNCTUATION(less, "<")
TOK_PUNCTUATION(less_equal, "<=")
TOK_PUNCTUATION(less_minus, "<-")
TOK_PUNCTUATION(greater, ">")
TOK_PUNCTUATION(equal, "=")
TOK_PUNCTUATION(equal_greater, "=>")

3
test/Dialect/FIRRTL/SFCTests/ExtractSeqMems/Compose.fir
View File

@ -19,6 +19,7 @@
; - Inject DUT Hierarchy
; - Prefixing
FIRRTL version 4.0.0
circuit TestHarness : %[[
{
"class":"sifive.enterprise.firrtl.NestedPrefixModulesAnnotation",
@ -119,7 +120,7 @@ circuit TestHarness : %[[
; TESTHARNESS: Prefix_DUTModule dut
; TESTHARNESS-NOT: mem_ext mem_ext
; TESTHARNESS-NOT: Prefix_mem_ext mem_ext
module TestHarness :
public module TestHarness :
input clock : Clock
input reset : UInt<1>
output io : { foo : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}, bar : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}}

3
test/Dialect/FIRRTL/SFCTests/ExtractSeqMems/Simple2.fir
View File

@ -10,6 +10,7 @@
; Extracted from test/scala/firrtl/ExtractSeqMems.scala
FIRRTL version 4.0.0
circuit TestHarness : %[[
{
"class":"sifive.enterprise.firrtl.ExtractSeqMemsFileAnnotation",
@ -44,7 +45,7 @@ circuit TestHarness : %[[
; TESTHARNESS: module TestHarness
; TESTHARNESS: DUTModule dut
; TESTHARNESS: mem_ext mem_ext
module TestHarness :
public module TestHarness :
input clock : Clock
input reset : UInt<1>
output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}

3
test/Dialect/FIRRTL/SFCTests/GrandCentralInterfaces/Companion.fir
View File

@ -2,6 +2,7 @@
; RUN: firtool %s --grand-central-companion-mode=drop | FileCheck %s --check-prefixes=DROP
; RUN: firtool %s --grand-central-companion-mode=bind | FileCheck %s --check-prefixes=BIND
FIRRTL version 4.0.0
circuit Foo : %[[
{
"class": "sifive.enterprise.grandcentral.GrandCentralView$SerializedViewAnnotation",
@ -48,7 +49,7 @@ circuit Foo : %[[
assert(clock, a, UInt<1>(1), "hello")
module Foo :
public module Foo :
input clock: Clock
input a_in: UInt<1>

5
test/Dialect/FIRRTL/SFCTests/GrandCentralInterfaces/HWRename.fir
View File

@ -1,11 +1,12 @@
; RUN: firtool --annotation-file %S/HWRename.anno.json %s | FileCheck %s
FIRRTL version 4.0.0
circuit Top:
module Companion :
output io : { }
wire _WIRE : UInt<1>
_WIRE <= UInt<1>("h0")
_WIRE <= UInt<1>(0h0)
module DUT:
input a: UInt<1>
@ -18,7 +19,7 @@ circuit Top:
inst companion of Companion
module Top:
public module Top:
input a: UInt<1>
output b: UInt<1>

7
test/Dialect/FIRRTL/SFCTests/GrandCentralInterfaces/PortDelete.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool %s | FileCheck %s
FIRRTL version 4.0.0
circuit PortDelete : %[[
{
"class": "sifive.enterprise.grandcentral.GrandCentralView$SerializedViewAnnotation",
@ -45,17 +46,17 @@ circuit PortDelete : %[[
module MyView_companion :
wire _WIRE : UInt<1>
_WIRE <= UInt<1>("h0")
_WIRE <= UInt<1>(0h0)
module DUT :
output out : UInt<1>
wire w : UInt<1>
w <= UInt<1>("h1")
w <= UInt<1>(0h1)
out <= w
inst MyView_companion of MyView_companion
module PortDelete :
public module PortDelete :
output out : UInt<1>
inst dut of DUT

7
test/Dialect/FIRRTL/SFCTests/GrandCentralInterfaces/Wire.fir
View File

@ -5,6 +5,7 @@
; RUN: firtool --no-dedup --lowering-options=emitBindComments --annotation-file %s.anno.json --annotation-file %s.Prefix.anno.json %s | FileCheck %s --check-prefixes PREFIX
; RUN: firtool --no-dedup --annotation-file %s.anno.json %s --disable-opt
FIRRTL version 4.0.0
circuit Top :
extmodule BlackBox_DUT :
input a : UInt<1>
@ -36,7 +37,7 @@ circuit Top :
w.multivec[1][0] <= in.multivec[1][0]
w.multivec[1][1] <= in.multivec[1][1]
w.multivec[1][2] <= in.multivec[1][2]
w.uint <= UInt<1>("h1")
w.uint <= UInt<1>(0h1)
out.otherOther.other.sint <= w.otherOther.other.sint
out.otherOther.other.uint <= w.otherOther.other.uint
out.vecOfBundle[0].sint <= w.vecOfBundle[0].sint
@ -82,7 +83,7 @@ circuit Top :
tap.b <= r
wire _WIRE : UInt<1>
_WIRE <= UInt<1>("h0")
_WIRE <= UInt<1>(0h0)
module DUT :
input clock : Clock
@ -148,7 +149,7 @@ circuit Top :
inst ext of ExtModuleWithPort
module Top :
public module Top :
input clock : Clock
input reset : UInt<1>
input in : { uint : UInt<1>, vec : UInt<1>[2], multivec : UInt<1>[3][2], vecOfBundle : { uint : UInt<4>, sint : SInt<2>}[2], otherOther : { other : { uint : UInt<4>, sint : SInt<2>}}}

3
test/Dialect/FIRRTL/SFCTests/async-reset-verilog.fir
View File

@ -7,8 +7,9 @@
; Every async reset reg should generate its own always block.
; CHECK-LABEL: module Foo(
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock0 : Clock
input clock1 : Clock
input syncReset : UInt<1>

55
test/Dialect/FIRRTL/SFCTests/async-reset.fir
View File

@ -3,17 +3,18 @@
; - test/scala/firrtlTests/AsyncResetSpec.scala
; Complex literals should be allowed as reset values for AsyncReset.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input x : UInt<1>[4]
output z : UInt<1>[4]
wire literal : UInt<1>[4]
literal[0] <= UInt<1>("h00")
literal[1] <= UInt<1>("h00")
literal[2] <= UInt<1>("h00")
literal[3] <= UInt<1>("h00")
literal[0] <= UInt<1>(0h00)
literal[1] <= UInt<1>(0h00)
literal[2] <= UInt<1>(0h00)
literal[3] <= UInt<1>(0h00)
; CHECK: %r_0 = firrtl.regreset %clock, %reset, %c0_ui1
; CHECK: %r_1 = firrtl.regreset %clock, %reset, %c0_ui1
; CHECK: %r_2 = firrtl.regreset %clock, %reset, %c0_ui1
@ -26,20 +27,21 @@ circuit Foo:
; Complex literals of complex literals should be allowed as reset values for
; AsyncReset.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input x : UInt<1>[4]
output z : UInt<1>[4]
wire literal : UInt<1>[2]
literal[0] <= UInt<1>("h01")
literal[1] <= UInt<1>("h01")
literal[0] <= UInt<1>(0h01)
literal[1] <= UInt<1>(0h01)
wire complex_literal : UInt<1>[4]
complex_literal[0] <= literal[0]
complex_literal[1] <= literal[1]
complex_literal[2] <= UInt<1>("h00")
complex_literal[3] <= UInt<1>("h00")
complex_literal[2] <= UInt<1>(0h00)
complex_literal[3] <= UInt<1>(0h00)
; CHECK: %r_0 = firrtl.regreset %clock, %reset, %c1_ui1
; CHECK: %r_1 = firrtl.regreset %clock, %reset, %c1_ui1
; CHECK: %r_2 = firrtl.regreset %clock, %reset, %c0_ui1
@ -51,20 +53,21 @@ circuit Foo:
// -----
; Literals of bundle literals should be allowed as reset values for AsyncReset.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input x : UInt<1>[4]
output z : UInt<1>[4]
wire bundle : {a: UInt<1>, b: UInt<1>}
bundle.a <= UInt<1>("h01")
bundle.b <= UInt<1>("h01")
bundle.a <= UInt<1>(0h01)
bundle.b <= UInt<1>(0h01)
wire complex_literal : UInt<1>[4]
complex_literal[0] <= bundle.a
complex_literal[1] <= bundle.b
complex_literal[2] <= UInt<1>("h00")
complex_literal[3] <= UInt<1>("h00")
complex_literal[2] <= UInt<1>(0h00)
complex_literal[3] <= UInt<1>(0h00)
; CHECK: %r_0 = firrtl.regreset %clock, %reset, %c1_ui1
; CHECK: %r_1 = firrtl.regreset %clock, %reset, %c1_ui1
; CHECK: %r_2 = firrtl.regreset %clock, %reset, %c0_ui1
@ -76,8 +79,9 @@ circuit Foo:
// -----
; Cast literals should be allowed as reset values for AsyncReset.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input x : SInt<4>
@ -90,7 +94,7 @@ circuit Foo:
; CHECK: %r2 = firrtl.regreset %clock, %reset, %c-1_si4
reg r2 : SInt<4>, clock with : (reset => (reset, w))
r2 <= x
node n = UInt("hf")
node n = UInt(0hf)
w <= asSInt(n)
y <= r2
z <= r
@ -98,19 +102,20 @@ circuit Foo:
// -----
; Unassigned asynchronously reset registers should properly constantprop.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
output z : UInt<1>[4]
wire literal : UInt<1>[2]
literal[0] <= UInt<1>("h01")
literal[1] <= UInt<1>("h01")
literal[0] <= UInt<1>(0h01)
literal[1] <= UInt<1>(0h01)
wire complex_literal : UInt<1>[4]
complex_literal[0] <= literal[0]
complex_literal[1] <= literal[1]
complex_literal[2] <= UInt<1>("h00")
complex_literal[3] <= UInt<1>("h00")
complex_literal[2] <= UInt<1>(0h00)
complex_literal[3] <= UInt<1>(0h00)
reg r : UInt<1>[4], clock with : (reset => (reset, complex_literal))
z <= r
; CHECK: firrtl.matchingconnect %z_0, %c1_ui1
@ -122,8 +127,9 @@ circuit Foo:
; Constantly assigned asynchronously reset registers should properly
; constantprop.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
output z : UInt<1>
@ -136,8 +142,9 @@ circuit Foo:
; Constantly assigned and initialized asynchronously reset registers should
; properly constantprop.
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
output z : UInt<1>

3
test/Dialect/FIRRTL/SFCTests/complex-asserts.fir
View File

@ -3,10 +3,11 @@
; Tests extracted from:
; - test/scala/firrtl/extractverif/ExtractAssertsSpec.scala
FIRRTL version 4.0.0
circuit Foo:
; expected-error @below {{module contains 10 printf-encoded verification operation(s), which are no longer supported.}}
; expected-note @below {{For more information, see https://github.com/llvm/circt/issues/6970}}
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input predicate1 : UInt<1>

3
test/Dialect/FIRRTL/SFCTests/complex-assumes.fir
View File

@ -2,10 +2,11 @@
; Tests extracted from:
; - test/scala/firrtl/extractverif/ExtractAssumesSpec.scala
FIRRTL version 4.0.0
circuit Foo:
; expected-error @below {{module contains 8 printf-encoded verification operation(s), which are no longer supported.}}
; expected-note @below {{For more information, see https://github.com/llvm/circt/issues/6970}}
module Foo:
public module Foo:
input clock : Clock
input reset : AsyncReset
input predicate1 : UInt<1>

3
test/Dialect/FIRRTL/SFCTests/constant-data-taps.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool --verilog %s | FileCheck %s
FIRRTL version 4.0.0
circuit ConstantSinking : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -16,7 +17,7 @@ circuit ConstantSinking : %[[
"target":"~ConstantSinking|ConstantSinking>t"
}
]]
module ConstantSinking:
public module ConstantSinking:
output out : UInt<1>
wire t : UInt<1>
out <= t

11
test/Dialect/FIRRTL/SFCTests/data-taps-errors.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool %s --split-input-file -verify-diagnostics
FIRRTL version 4.0.0
circuit TapBetweenWhens : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -12,10 +13,10 @@ circuit TapBetweenWhens : %[[
]
}
]]
module TapBetweenWhens :
public module TapBetweenWhens :
input c1: UInt<1>
input c2: UInt<1>
output o: UInt
output o: UInt<1>
when c1:
; expected-error @below {{This value is involved with a Wiring Problem where the destination}}
@ -32,6 +33,7 @@ circuit TapBetweenWhens : %[[
; // -----
FIRRTL version 4.0.0
circuit NoSafeInsertionPoint : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -44,7 +46,7 @@ circuit NoSafeInsertionPoint : %[[
]
}
]]
module NoSafeInsertionPoint :
public module NoSafeInsertionPoint :
input c: UInt<1>
output o: UInt<1>
@ -60,6 +62,7 @@ circuit NoSafeInsertionPoint : %[[
; // -----
FIRRTL version 4.0.0
; expected-error @below {{Unable to apply annotation}}
circuit Top : %[[
{
@ -152,7 +155,7 @@ circuit Top : %[[
inst b of Bar
module Top:
public module Top:
inst foo of Foo

3
test/Dialect/FIRRTL/SFCTests/data-taps-flip-errors.fir
View File

@ -2,6 +2,7 @@
; Test tapping a bundle with flips, sink also has flips.
; Tap sink must be passive.
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -18,7 +19,7 @@ circuit Top : %[[
input x: {a : UInt<2>, flip b: UInt<2>}
x.b <= UInt<2>(2)
module Top :
public module Top :
input x: {a : UInt<2>, flip b: UInt<2>}
output tap : {a : UInt<2>, flip b: UInt<2>}

6
test/Dialect/FIRRTL/SFCTests/data-taps-flip.fir
View File

@ -18,6 +18,7 @@
; NOREF-DAG: firrtl.matchingconnect %[[A]],
; NOREF-DAG: %[[B:.+]] = firrtl.subfield %[[OUT_PORT]][b]
; NOREF-DAG: firrtl.matchingconnect %[[B]],
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -34,7 +35,7 @@ circuit Top : %[[
input x: {a : UInt<2>, flip b: UInt<2>}
x.b <= UInt<2>(2)
module Top :
public module Top :
input x: {a : UInt<2>, flip b: UInt<2>}
output tap : {a : UInt<2>, b: UInt<2>}
@ -50,6 +51,7 @@ circuit Top : %[[
; CHECK-LABEL: circuit "Local"
; NOREF-LABEL: circuit "Local"
FIRRTL version 4.0.0
circuit Local: %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -67,7 +69,7 @@ circuit Local: %[[
]
}
]]
module Local:
public module Local:
input x: {a : UInt<2>, flip b: UInt<2>}
output tap : {a : UInt<2>, b: UInt<2>}

3
test/Dialect/FIRRTL/SFCTests/data-taps-no-ref-type.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool -lower-annotations-no-ref-type-ports %s | FileCheck %s
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -28,7 +29,7 @@ circuit Foo: %[[
wire a: UInt<1>
a is invalid
module Foo:
public module Foo:
inst bar of Bar
inst baz of Baz

9
test/Dialect/FIRRTL/SFCTests/data-taps-wiring-xmr.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool %s --split-input-file | FileCheck %s
FIRRTL version 4.0.0
circuit SinkThroughWhens: %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -34,7 +35,7 @@ circuit SinkThroughWhens: %[[
inst leaf of Leaf
leaf.c <= c
module SinkThroughWhens :
public module SinkThroughWhens :
input c: UInt<1>
wire val : UInt<3>
@ -45,6 +46,7 @@ circuit SinkThroughWhens: %[[
; // -----
FIRRTL version 4.0.0
circuit TapWhenVal : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -58,7 +60,7 @@ circuit TapWhenVal : %[[
}
]]
; CHECK-LABEL: module TapWhenVal
module TapWhenVal :
public module TapWhenVal :
input c: UInt<1>
output o: UInt<1>
@ -74,6 +76,7 @@ circuit TapWhenVal : %[[
; // -----
FIRRTL version 4.0.0
circuit TapIntoWhen : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -87,7 +90,7 @@ circuit TapIntoWhen : %[[
}
]]
; CHECK-LABEL: module TapIntoWhen
module TapIntoWhen :
public module TapIntoWhen :
input c: UInt<1>
output o: UInt<1>

8
test/Dialect/FIRRTL/SFCTests/data-taps-xmr.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool --verilog %s --split-input-file | FileCheck %s
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -79,7 +80,7 @@ circuit Top : %[[
inst b of Bar
module Top:
public module Top:
inst foo of Foo
@ -122,6 +123,7 @@ circuit Top : %[[
; XMR references should work through 'when's.
; https://github.com/llvm/circt/issues/4334
FIRRTL version 4.0.0
circuit Top : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -164,9 +166,9 @@ circuit Top : %[[
; CHECK-EMPTY:
; CHECK-NEXT: assign o = 3'h2;
; CHECK-NEXT: endmodule
module Top :
public module Top :
input c: UInt<1>
output o: UInt
output o: UInt<3>
wire val : UInt<3>
val <= UInt(1)

15
test/Dialect/FIRRTL/SFCTests/data-taps.fir
View File

@ -7,6 +7,7 @@
; This test was extracted from:
; - github.com/sifive/$internal:
; - src/test/scala/grandcentral/DataTapsTest.scala
FIRRTL version 4.0.0
circuit Top : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -100,7 +101,7 @@ circuit Top : %[[
signed.io.in <= io.in
io.out <= signed.io.out
module Top :
public module Top :
input clock : Clock
input reset : UInt<1>
output io : { flip in : UInt<1>, out : UInt<1>}
@ -135,6 +136,7 @@ circuit Top : %[[
; // -----
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -177,7 +179,7 @@ circuit Top : %[[
g <= inv
f <= inv
module Top:
public module Top:
output io : { b : UInt<1>, c : UInt<1>, d: UInt<1> }
inst foo of Foo
@ -208,6 +210,7 @@ circuit Top : %[[
; // -----
FIRRTL version 4.0.0
circuit TestHarness : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -224,7 +227,7 @@ circuit TestHarness : %[[
"target": "~TestHarness|Test>inv"
}
]]
module TestHarness :
public module TestHarness :
output io : UInt<1>
inst system of Top
io <= system.io
@ -261,6 +264,7 @@ circuit TestHarness : %[[
; // -----
FIRRTL version 4.0.0
circuit Top : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
@ -480,7 +484,7 @@ circuit Top : %[[
tap_10 is invalid
tap_11 is invalid
module Top :
public module Top :
output port_Top : UInt<1>
port_Top is invalid
@ -541,6 +545,7 @@ circuit Top : %[[
; // -----
FIRRTL version 4.0.0
circuit Top : %[[
{
"class":"firrtl.transforms.DontTouchAnnotation",
@ -571,7 +576,7 @@ circuit Top : %[[
io.out <= sum
module Top :
public module Top :
output io : { flip in : UInt<8>, out : UInt<8>}
output taps : UInt<8>[2]

3
test/Dialect/FIRRTL/SFCTests/dedup-errors.fir
View File

@ -2,6 +2,7 @@
; Tests extracted from:
; - test/scala/firrtlTests/transforms/DedupTests.scala
FIRRTL version 4.0.0
; "modules should not be deduped if the NoCircuitDedupAnnotation is supplied"
;
; CHECK-LABEL: firrtl.circuit "Top"
@ -22,7 +23,7 @@ circuit Top: %[[
output b: UInt<1>
b <= a
; CHECK: firrtl.module @Top(
module Top:
public module Top:
input a: UInt<1>
output b: UInt<1>

78
test/Dialect/FIRRTL/SFCTests/dedup.fir
View File

@ -15,9 +15,10 @@
; "The module A should be deduped"
;
; CHECK-LABEL: firrtl.circuit "Top0"
FIRRTL version 4.0.0
circuit Top0 :
; CHECK: firrtl.module @Top0
module Top0 :
public module Top0 :
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
inst a2 of A_
@ -34,9 +35,10 @@ circuit Top0 :
; "The module A and B should be deduped"
;
; CHECK-LABEL: firrtl.circuit "Top1"
FIRRTL version 4.0.0
circuit Top1 :
; CHECK: firrtl.module @Top1
module Top1 :
public module Top1 :
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
inst a2 of A_
@ -64,9 +66,10 @@ circuit Top1 :
; "The module A and B with comments should be deduped"
;
; CHECK-LABEL: firrtl.circuit "Top2"
FIRRTL version 4.0.0
circuit Top2 :
; CHECK: firrtl.module @Top2
module Top2 :
public module Top2 :
; CHECK: firrtl.instance a1 @A(
; CHECK: firrtl.instance a2 @A(
inst a1 of A
@ -93,9 +96,10 @@ circuit Top2 :
; "A_ but not A should be deduped if not annotated"
;
; CHECK-LABEL: firrtl.circuit "Top3"
FIRRTL version 4.0.0
circuit Top3 :
; CHECK: firrtl.module @Top3
module Top3 :
public module Top3 :
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
inst a2 of A_
@ -112,9 +116,10 @@ circuit Top3 :
; "Extmodules with the same defname and parameters should dedup"
;
; CHECK-LABEL: firrtl.circuit "Top4"
FIRRTL version 4.0.0
circuit Top4 :
; CHECK: firrtl.module @Top4
module Top4 :
public module Top4 :
output out: UInt<1>
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
@ -146,9 +151,10 @@ circuit Top4 :
; "Extmodules with different defname should NOT dedup"
;
; CHECK-LABEL: firrtl.circuit "Top5"
FIRRTL version 4.0.0
circuit Top5 :
; CHECK: firrtl.module @Top5
module Top5 :
public module Top5 :
output out: UInt<1>
; CHECK-NEXT: firrtl.instance a1 @A(
; CHECK-NEXT: firrtl.instance a2 @A_(
@ -179,9 +185,10 @@ circuit Top5 :
; "Extmodules with different parameters should NOT dedup"
;
; CHECK-LABEL: firrtl.circuit "Top6"
FIRRTL version 4.0.0
circuit Top6 :
; CHECK: firrtl.module @Top6
module Top6 :
public module Top6 :
output out: UInt<1>
; CHECK-NEXT: firrtl.instance a1 @A(
; CHECK-NEXT: firrtl.instance a2 @A_(
@ -209,13 +216,14 @@ circuit Top6 :
parameter N = 1
; // -----
; "Modules with aggregate ports that are (partial)? connected should NOT dedup if
; their port names differ".
; "Modules with aggregate ports that are connected should NOT dedup if their
; port names differ".
;
; Since the MFC support expanding connects and partial connects when the port
; names differ, this now testing that the modules succesfully dedup.
;
; CHECK-LABEL: firrtl.circuit "FooAndBarModule0"
FIRRTL version 4.0.0
circuit FooAndBarModule0 :
; CHECK: firrtl.module private @FooModule
module FooModule :
@ -226,20 +234,21 @@ circuit FooAndBarModule0 :
output io : {flip bar : UInt<1>, buzz : UInt<1>}
io.buzz <= io.bar
; CHECK: firrtl.module @FooAndBarModule0
module FooAndBarModule0 :
public module FooAndBarModule0 :
output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}}
; CHECK: firrtl.instance foo @FooModule
; CHECK: firrtl.instance bar @FooModule
inst foo of FooModule
inst bar of BarModule
io.foo <- foo.io
io.foo <= foo.io
io.bar <= bar.io
; // -----
; "Modules with aggregate ports that are (partial)? connected should dedup if
; their port names are the same".
; "Modules with aggregate ports that are connected should dedup if their port
; names are the same".
;
; CHECK-LABEL: firrtl.circuit "FooAndBarModule1"
FIRRTL version 4.0.0
circuit FooAndBarModule1 :
; CHECK: firrtl.module private @FooModule
module FooModule :
@ -250,21 +259,22 @@ circuit FooAndBarModule1 :
output io : {flip foo : UInt<1>, fuzz : UInt<1>}
io.fuzz <= io.foo
; CHECK: firrtl.module @FooAndBarModule1
module FooAndBarModule1 :
public module FooAndBarModule1 :
output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip foo : UInt<1>, fuzz : UInt<1>}}
; CHECK-COUNT-2: firrtl.instance {{(foo|bar)}} @FooModule
inst foo of FooModule
inst bar of BarModule
io.foo <= foo.io
io.bar <- bar.io
io.bar <= bar.io
; // -----
; "The module A and B should be deduped with the first module in order".
;
; CHECK-LABEL: firrtl.circuit "Top7"
FIRRTL version 4.0.0
circuit Top7 :
; CHECK: firrtl.module @Top7
module Top7 :
public module Top7 :
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
inst a2 of A_
@ -290,9 +300,10 @@ circuit Top7 :
; "The module A and A_ should be deduped with fields that sort of match".
;
; CHECK-LABEL: firrtl.circuit "Top8"
FIRRTL version 4.0.0
circuit Top8 :
; CHECK: firrtl.module @Top8
module Top8 :
public module Top8 :
; CHECK-COUNT-2: firrtl.instance {{a(1|2)}} @A(
inst a1 of A
inst a2 of A_
@ -313,6 +324,7 @@ circuit Top8 :
; "The module A and A_ should dedup with different annotation targets".
;
; CHECK-LABEL: firrtl.circuit "Top9"
FIRRTL version 4.0.0
circuit Top9 : %[[
{
"class":"circt.test",
@ -323,7 +335,7 @@ circuit Top9 : %[[
; CHECK: firrtl.module @Top9
; CHECK-NEXT: firrtl.instance a1 sym @[[a1Sym]] @A(
; CHECK-NEXT: firrtl.instance a2 @A(
module Top9 :
public module Top9 :
inst a1 of A
inst a2 of A_
; CHECK: module private @A(
@ -345,6 +357,7 @@ circuit Top9 : %[[
; "The module A and A_ should dedup with the same annotation targets".
;
; CHECK-LABEL: firrtl.circuit "Top10"
FIRRTL version 4.0.0
circuit Top10 : %[[
{
"class":"circt.test",
@ -362,7 +375,7 @@ circuit Top10 : %[[
; CHECK: firrtl.module @Top10
; CHECK-NEXT: firrtl.instance a1 sym @[[a1Sym]] @A(
; CHECK-NEXT: firrtl.instance a2 sym @[[a2Sym]] @A(
module Top10 :
public module Top10 :
inst a1 of A
inst a2 of A_
; CHECK: module private @A(
@ -385,6 +398,7 @@ circuit Top10 : %[[
; different names".
;
; CHECK-LABEL: firrtl.circuit "Top11"
FIRRTL version 4.0.0
circuit Top11 : %[[
{
"class":"circt.test",
@ -400,7 +414,7 @@ circuit Top11 : %[[
; CHECK-NOT: hw.hierpath
; CHECK: hw.hierpath private @[[nlaSym2:[_a-zA-Z0-9]+]] [@Top11::@[[a1sym:[_a-zA-Z0-9]+]], @A]
; CHECK: hw.hierpath private @[[nlaSym1:[_a-zA-Z0-9]+]] [@Top11::@[[a1Sym]], @A]
module Top11 :
public module Top11 :
inst a1 of A
a1 is invalid
inst a2 of A_
@ -424,13 +438,14 @@ circuit Top11 : %[[
; "main should not be deduped even if it's the last module"
;
; CHECK-LABEL: firrtl.circuit "main"
FIRRTL version 4.0.0
circuit main:
module dupe:
input in: UInt<8>
output out: UInt<8>
out <= in
; CHECK: firrtl.module @main
module main:
public module main:
input in: UInt<8>
output out: UInt<8>
out <= in
@ -439,6 +454,7 @@ circuit main:
; "The deduping module A and A_ should rename instances and signals that have different names"
;
; CHECK-LABEL: firrtl.circuit "Top12"
FIRRTL version 4.0.0
circuit Top12 : %[[
{
"class":"circt.test",
@ -464,7 +480,7 @@ circuit Top12 : %[[
; CHECK: hw.hierpath private @[[nla_a:[_a-zA-Z0-9]+]] [@Top12::@[[aSym:[_a-zA-Z0-9]+]], @A::@[[bSym:[_a-zA-Z0-9]+]], @B]
; CHECK: hw.hierpath private @[[nla_a_:[_a-zA-Z0-9]+]] [@Top12::@[[a_Sym:[_a-zA-Z0-9]+]], @A::@[[bSym]], @B]
; CHECK: firrtl.module @Top12
module Top12 :
public module Top12 :
; CHECK-NEXT: firrtl.instance a sym @[[aSym]] @A()
inst a of A
; CHECK-NEXT: firrtl.instance a_ sym @[[a_Sym]] @A()
@ -498,6 +514,7 @@ circuit Top12 : %[[
; how a multi-target annotation would be scattered.
;
; CHECK-LABEL: firrtl.circuit "Top13"
FIRRTL version 4.0.0
circuit Top13 : %[[
{
"class":"circt.test",
@ -533,7 +550,7 @@ circuit Top13 : %[[
; CHECK-SAME: @C::@[[dSym]],
; CHECK-SAME: @D]
; CHECK-NEXT: firrtl.module @Top13
module Top13 :
public module Top13 :
; CHECK-NEXT: firrtl.instance a sym @[[aSym]]
; CHECK-SAME: @A()
inst a of A
@ -583,6 +600,7 @@ circuit Top13 : %[[
; instances".
;
; CHECK-LABEL: firrtl.circuit "Top14"
FIRRTL version 4.0.0
circuit Top14 : %[[
{
"class":"circt.test",
@ -696,7 +714,7 @@ circuit Top14 : %[[
; CHECK-SAME: @B::@[[BcSym]],
; CHECK-SAME: @C]
; CHECK-NEXT: firrtl.module @Top14
module Top14 :
public module Top14 :
; CHECK-NEXT: firrtl.instance b sym @[[TopbSym]]
; CHECK-SAME: @B()
inst b of B
@ -754,6 +772,7 @@ circuit Top14 : %[[
; strings) and is unlikely to occur in CIRCT due to the use of field IDs.
;
; CHECK-LABEL: firrtl.circuit "Top15"
FIRRTL version 4.0.0
circuit Top15 : %[[
{
"class":"circt.test",
@ -771,7 +790,7 @@ circuit Top15 : %[[
; CHECK: hw.hierpath private @[[nla_1:[_a-zA-Z0-9]+]]
; CHECK-SAME: [@Top15::@[[topaSym:[_a-zA-Z0-9]+]], @a]
; CHECK: firrtl.module @Top15
module Top15:
public module Top15:
input ia: {z: {y: {x: UInt<1>}}, a: UInt<1> un: UInt<2>}
input ib: {a: {b: {c: UInt<1>}}, z: UInt<1> un: UInt<2>}
output oa: {z: {y: {x: UInt<1>}}, a: UInt<1> un: UInt<2>}
@ -815,6 +834,7 @@ circuit Top15 : %[[
; and annotations should be remapped".
;
; CHECK-LABEL: firrtl.circuit "Top16"
FIRRTL version 4.0.0
circuit Top16 : %[[
{
"class": "circt.test",
@ -823,7 +843,7 @@ circuit Top16 : %[[
}
]]
; CHECK: firrtl.module @Top16
module Top16 :
public module Top16 :
output out: UInt<1>
; CHECK: instance a1 @A(
; CHECK-NOT: SourceAnnotation
@ -850,6 +870,7 @@ circuit Top16 : %[[
; any other annotation due to deduplication.
;
; CHECK-LABEL: firrtl.circuit "Top17"
FIRRTL version 4.0.0
circuit Top17 : %[[
{
"class":"firrtl.transforms.DontTouchAnnotation",
@ -859,7 +880,7 @@ circuit Top17 : %[[
; CHECK: firrtl.module @Top17
; CHECK-NEXT: firrtl.instance a1 @A(
; CHECK-NEXT: firrtl.instance a2 @A(
module Top17 :
public module Top17 :
inst a1 of A
inst a2 of A_
; CHECK: module private @A(
@ -886,6 +907,7 @@ circuit Top17 : %[[
; Scala FIRRTL Compiler and we should make a decision on what to do with this.
;
; CHECK-LABEL: firrtl.circuit "Top18"
FIRRTL version 4.0.0
circuit Top18 : %[[
{
"class":"firrtl.transforms.DontTouchAnnotation",
@ -899,7 +921,7 @@ circuit Top18 : %[[
; CHECK: firrtl.module @Top18
; CHECK-NEXT: firrtl.instance a1 @A(
; CHECK-NEXT: firrtl.instance a2 @A(
module Top18 :
public module Top18 :
inst a1 of A
inst a2 of A_
; CHECK: module private @A(

3
test/Dialect/FIRRTL/SFCTests/directories.fir
View File

@ -6,6 +6,7 @@
; RUN: firtool %s -disable-all-randomization -disable-opt -annotation-file %s.memtoregofvec.anno.json -annotation-file %s.markdut.anno.json | FileCheck %s -check-prefixes=CHECK,MEMTOREG_DUT
; RUN: firtool %s -disable-all-randomization -disable-opt -repl-seq-mem -repl-seq-mem-file=mems.conf -annotation-file %s.sitestblackboxes.anno.json --ir-verilog | FileCheck %s -check-prefix=MLIR_OUT
FIRRTL version 4.0.0
circuit TestHarness:
; Foo* are instantiated only by the TestHarness
module Foo:
@ -98,7 +99,7 @@ circuit TestHarness:
inst baz_bbox of Baz_BlackBox
; This is the Test Harness, i.e., the top of the design.
module TestHarness:
public module TestHarness:
inst foo of Foo
inst foo_bbox of Foo_BlackBox

1
test/Dialect/FIRRTL/SFCTests/emit-metadata.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool --verify-diagnostics --verilog %s | FileCheck %s
FIRRTL version 4.0.0
circuit Foo : %[[{
"class": "firrtl.transforms.BlackBoxInlineAnno",
"name": "hello.v",

3
test/Dialect/FIRRTL/SFCTests/emit-omir.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool --repl-seq-mem --repl-seq-mem-file="dummy" --emit-omir %s | FileCheck %s
FIRRTL version 4.0.0
circuit Foo : %[[
{
"class": "freechips.rocketchip.objectmodel.OMIRFileAnnotation",
@ -69,7 +70,7 @@ circuit Foo : %[[
]]
extmodule MySRAM:
defname = MySRAM
module Foo :
public module Foo :
input unsigned : UInt<29>
input zeroW : UInt<0>
output signed : UInt<31>

6
test/Dialect/FIRRTL/SFCTests/invalid-interpretations.fir
View File

@ -4,8 +4,9 @@
; context-sensitive interpretation of invalid.
; CHECK-LABEL: module InvalidInterpretations
FIRRTL version 4.0.0
circuit InvalidInterpretations:
module InvalidInterpretations:
public module InvalidInterpretations:
input clock: Clock
input reset: UInt<1>
input cond: UInt<1>
@ -48,8 +49,9 @@ circuit InvalidInterpretations:
; See: https://github.com/llvm/circt/issues/2782
; CHECK-LABEL: module InvalidInOtherModule
FIRRTL version 4.0.0
circuit InvalidInOtherModule :
module InvalidInOtherModule :
public module InvalidInOtherModule :
input clock: Clock
input reset: UInt<1>
output b: SInt<8>

303
test/Dialect/FIRRTL/SFCTests/invalid-reg-pass.fir
View File

@ -13,8 +13,9 @@
; The FIRRTL circuits in this file were generated using:
; https://github.com/seldridge/firrtl-torture/blob/main/Invalid.scala
FIRRTL version 4.0.0
circuit add :
module add :
public module add :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -27,13 +28,13 @@ circuit add :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = add(in_1, in_0)
node _T_1 = tail(_T, 1)
r_0 <= _T_1
@ -59,8 +60,9 @@ circuit add :
; // -----
FIRRTL version 4.0.0
circuit and :
module and :
public module and :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<1>
@ -73,13 +75,13 @@ circuit and :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = and(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -101,8 +103,9 @@ circuit and :
; // -----
FIRRTL version 4.0.0
circuit asAsyncReset :
module asAsyncReset :
public module asAsyncReset :
input clock : Clock
input reset : UInt<1>
input in : UInt<1>
@ -112,9 +115,9 @@ circuit asAsyncReset :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : AsyncReset, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : AsyncReset, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = asAsyncReset(in)
r_0 <= _T
out_0 <= r_0
@ -128,8 +131,9 @@ circuit asAsyncReset :
; // -----
FIRRTL version 4.0.0
circuit asClock :
module asClock :
public module asClock :
input clock : Clock
input reset : UInt<1>
input in : UInt<1>
@ -139,9 +143,9 @@ circuit asClock :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : Clock, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : Clock, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = asClock(in)
r_0 <= _T
out_0 <= r_0
@ -157,8 +161,9 @@ circuit asClock :
; // -----
FIRRTL version 4.0.0
circuit cvt :
module cvt :
public module cvt :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -168,9 +173,9 @@ circuit cvt :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : SInt<5>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : SInt<5>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = cvt(in)
r_0 <= _T
out_0 <= r_0
@ -186,8 +191,9 @@ circuit cvt :
; // -----
FIRRTL version 4.0.0
circuit eq :
module eq :
public module eq :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -200,13 +206,13 @@ circuit eq :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = eq(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -228,8 +234,9 @@ circuit eq :
; // -----
FIRRTL version 4.0.0
circuit neg :
module neg :
public module neg :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -239,14 +246,14 @@ circuit neg :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_1)
node _T = sub(UInt<1>("h0"), in)
reset => (UInt<1>(0h0), r_1)
node _T = sub(UInt<1>(0h0), in)
node _T_1 = tail(_T, 1)
r_0 <= _T_1
out_0 <= r_0
node _T_2 = sub(UInt<1>("h0"), invalid)
node _T_2 = sub(UInt<1>(0h0), invalid)
node _T_3 = tail(_T_2, 1)
r_1 <= _T_3
out_1 <= r_1
@ -260,8 +267,9 @@ circuit neg :
; // -----
FIRRTL version 4.0.0
circuit neq :
module neq :
public module neq :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -274,13 +282,13 @@ circuit neq :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = neq(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -302,8 +310,9 @@ circuit neq :
; // -----
FIRRTL version 4.0.0
circuit or :
module or :
public module or :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<1>
@ -316,13 +325,13 @@ circuit or :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = or(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -344,8 +353,9 @@ circuit or :
; // -----
FIRRTL version 4.0.0
circuit pad :
module pad :
public module pad :
input clock : Clock
input reset : UInt<1>
input in : UInt<1>
@ -355,9 +365,9 @@ circuit pad :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = pad(in, 2)
r_0 <= _T
out_0 <= r_0
@ -373,8 +383,9 @@ circuit pad :
; // -----
FIRRTL version 4.0.0
circuit xor :
module xor :
public module xor :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<1>
@ -387,13 +398,13 @@ circuit xor :
wire invalid : UInt<1>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = xor(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -415,8 +426,9 @@ circuit xor :
; // -----
FIRRTL version 4.0.0
circuit andr :
module andr :
public module andr :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -426,9 +438,9 @@ circuit andr :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = andr(in)
r_0 <= _T
out_0 <= r_0
@ -444,8 +456,9 @@ circuit andr :
; // -----
FIRRTL version 4.0.0
circuit asSInt :
module asSInt :
public module asSInt :
input clock : Clock
input reset : UInt<1>
input in : UInt<2>
@ -455,9 +468,9 @@ circuit asSInt :
wire invalid : UInt<2>
invalid is invalid
reg r_0 : SInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : SInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = asSInt(in)
r_0 <= _T
out_0 <= r_0
@ -473,8 +486,9 @@ circuit asSInt :
; // -----
FIRRTL version 4.0.0
circuit asUInt :
module asUInt :
public module asUInt :
input clock : Clock
input reset : UInt<1>
input in : SInt<2>
@ -484,9 +498,9 @@ circuit asUInt :
wire invalid : SInt<2>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = asUInt(in)
r_0 <= _T
out_0 <= r_0
@ -502,8 +516,9 @@ circuit asUInt :
; // -----
FIRRTL version 4.0.0
circuit bits :
module bits :
public module bits :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -513,9 +528,9 @@ circuit bits :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = bits(in, 3, 2)
r_0 <= _T
out_0 <= r_0
@ -531,8 +546,9 @@ circuit bits :
; // -----
FIRRTL version 4.0.0
circuit cat :
module cat :
public module cat :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<2>
@ -545,13 +561,13 @@ circuit cat :
wire invalid : UInt<2>
invalid is invalid
reg r_0 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = cat(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -573,8 +589,9 @@ circuit cat :
; // -----
FIRRTL version 4.0.0
circuit dshl :
module dshl :
public module dshl :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<2>
@ -587,13 +604,13 @@ circuit dshl :
wire invalid : UInt<2>
invalid is invalid
reg r_0 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = dshl(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -615,8 +632,9 @@ circuit dshl :
; // -----
FIRRTL version 4.0.0
circuit dshr :
module dshr :
public module dshr :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<2>
@ -629,13 +647,13 @@ circuit dshr :
wire invalid : UInt<2>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = dshr(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -657,8 +675,9 @@ circuit dshr :
; // -----
FIRRTL version 4.0.0
circuit head :
module head :
public module head :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -668,9 +687,9 @@ circuit head :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = head(in, 2)
r_0 <= _T
out_0 <= r_0
@ -686,8 +705,9 @@ circuit head :
; // -----
FIRRTL version 4.0.0
circuit lt :
module lt :
public module lt :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -700,13 +720,13 @@ circuit lt :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = lt(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -728,8 +748,9 @@ circuit lt :
; // -----
FIRRTL version 4.0.0
circuit gt :
module gt :
public module gt :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -742,13 +763,13 @@ circuit gt :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = gt(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -770,8 +791,9 @@ circuit gt :
; // -----
FIRRTL version 4.0.0
circuit leq :
module leq :
public module leq :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -784,13 +806,13 @@ circuit leq :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = leq(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -812,8 +834,9 @@ circuit leq :
; // -----
FIRRTL version 4.0.0
circuit geq :
module geq :
public module geq :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -826,13 +849,13 @@ circuit geq :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = geq(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -854,8 +877,9 @@ circuit geq :
; // -----
FIRRTL version 4.0.0
circuit mul :
module mul :
public module mul :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -868,13 +892,13 @@ circuit mul :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<8>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<8>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<8>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<8>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = mul(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -896,8 +920,9 @@ circuit mul :
; // -----
FIRRTL version 4.0.0
circuit not :
module not :
public module not :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -907,9 +932,9 @@ circuit not :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = not(in)
r_0 <= _T
out_0 <= r_0
@ -925,8 +950,9 @@ circuit not :
; // -----
FIRRTL version 4.0.0
circuit orr :
module orr :
public module orr :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -936,9 +962,9 @@ circuit orr :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = orr(in)
r_0 <= _T
out_0 <= r_0
@ -954,8 +980,9 @@ circuit orr :
; // -----
FIRRTL version 4.0.0
circuit shl :
module shl :
public module shl :
input clock : Clock
input reset : UInt<1>
input in : UInt<2>
@ -965,9 +992,9 @@ circuit shl :
wire invalid : UInt<2>
invalid is invalid
reg r_0 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = shl(in, 2)
r_0 <= _T
out_0 <= r_0
@ -983,8 +1010,9 @@ circuit shl :
; // -----
FIRRTL version 4.0.0
circuit shr :
module shr :
public module shr :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -994,9 +1022,9 @@ circuit shr :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = shr(in, 2)
r_0 <= _T
out_0 <= r_0
@ -1012,8 +1040,9 @@ circuit shr :
; // -----
FIRRTL version 4.0.0
circuit sub :
module sub :
public module sub :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -1026,13 +1055,13 @@ circuit sub :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<5>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = sub(in_1, in_0)
node _T_1 = tail(_T, 1)
r_0 <= _T_1
@ -1058,8 +1087,9 @@ circuit sub :
; // -----
FIRRTL version 4.0.0
circuit tail :
module tail :
public module tail :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -1069,9 +1099,9 @@ circuit tail :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<2>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = tail(in, 2)
r_0 <= _T
out_0 <= r_0
@ -1087,8 +1117,9 @@ circuit tail :
; // -----
FIRRTL version 4.0.0
circuit div :
module div :
public module div :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -1101,13 +1132,13 @@ circuit div :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = div(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -1129,8 +1160,9 @@ circuit div :
; // -----
FIRRTL version 4.0.0
circuit rem :
module rem :
public module rem :
input clock : Clock
input reset : UInt<1>
input in_0 : UInt<4>
@ -1143,13 +1175,13 @@ circuit rem :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
reg r_2 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_2)
reset => (UInt<1>(0h0), r_2)
reg r_3 : UInt<4>, clock with :
reset => (UInt<1>("h0"), r_3)
reset => (UInt<1>(0h0), r_3)
node _T = rem(in_1, in_0)
r_0 <= _T
out_0 <= r_0
@ -1171,8 +1203,9 @@ circuit rem :
; // -----
FIRRTL version 4.0.0
circuit xorr :
module xorr :
public module xorr :
input clock : Clock
input reset : UInt<1>
input in : UInt<4>
@ -1182,9 +1215,9 @@ circuit xorr :
wire invalid : UInt<4>
invalid is invalid
reg r_0 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_0)
reset => (UInt<1>(0h0), r_0)
reg r_1 : UInt<1>, clock with :
reset => (UInt<1>("h0"), r_1)
reset => (UInt<1>(0h0), r_1)
node _T = xorr(in)
r_0 <= _T
out_0 <= r_0

3
test/Dialect/FIRRTL/SFCTests/load-memory-from-file.fir
View File

@ -2,8 +2,9 @@
; RUN: firtool %s -annotation-file %s.inline.anno.json -disable-all-randomization -lowering-options=emitBindComments | FileCheck %s --check-prefixes=CHECK,INIT_INLINE
; RUN: firtool %s -annotation-file %s.outline.anno.json -disable-all-randomization -lowering-options=emitBindComments | FileCheck %s --check-prefixes=CHECK,INIT_OUTLINE
FIRRTL version 4.0.0
circuit Foo :
module Foo :
public module Foo :
input clock : Clock
input reset : UInt<1>
output read : { flip en : UInt<1>, data : UInt<8>, flip addr : UInt<5>}

3
test/Dialect/FIRRTL/SFCTests/mem-taps-reg.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool --verilog --allow-adding-ports-on-public-modules %s | FileCheck %s
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
@ -37,7 +38,7 @@ circuit Top : %[[
infer mport write = rf[io.addr], clock
write <= io.dataIn
module Top :
public module Top :
input clock : Clock
input reset : UInt<1>
output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}

3
test/Dialect/FIRRTL/SFCTests/mem-taps.fir
View File

@ -2,6 +2,7 @@
; RUN: firtool --verilog -allow-adding-ports-on-public-modules -preserve-aggregate=1d-vec %s | FileCheck %s --check-prefix=AGGGREGATE
; RUN: firtool --verilog -allow-adding-ports-on-public-modules -lower-annotations-no-ref-type-ports %s | FileCheck %s --check-prefix=NOREFS
FIRRTL version 4.0.0
circuit Top : %[[
{
"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
@ -38,7 +39,7 @@ circuit Top : %[[
infer mport write = rf[io.addr], clock
write <= io.dataIn
module Top :
public module Top :
input clock : Clock
input reset : UInt<1>
output io : { flip addr : UInt<3>, flip dataIn : UInt<8>, flip wen : UInt<1>, dataOut : UInt<8>}

3
test/Dialect/FIRRTL/SFCTests/parameters.fir
View File

@ -3,11 +3,12 @@
; Test that a negative parameter prints out as a 32-bit parameter. It is fine
; to change this test to print as "-1" in the output Verilog, but not as a
; non-32-bit "-1" like "0xF".
FIRRTL version 4.0.0
circuit NegativeParameter:
extmodule Foo:
output a: UInt<1>
parameter x = -1
module NegativeParameter:
public module NegativeParameter:
output a: UInt<1>
inst foo of Foo

12
test/Dialect/FIRRTL/SFCTests/remove-reset.fir
View File

@ -4,8 +4,9 @@
; Should not generate a reset mux for an invalid init, given a 1-bit register
; 'foo' initialized to invalid, 1-bit wire 'bar'.
FIRRTL version 4.0.0
circuit Example :
module Example :
public module Example :
input clock : Clock
input arst : AsyncReset
input srst : UInt<1>
@ -28,8 +29,9 @@ circuit Example :
; is reset, given aggregate register 'foo' with 2-bit field 'a' and 1-bit field
; 'b', and aggregate, invalid wire 'bar' with the same fields, and 'foo' is
; initialized to 'bar', and 'bar.a[1]' connected to zero.
FIRRTL version 4.0.0
circuit Example1 :
module Example1 :
public module Example1 :
input clock : Clock
input arst : AsyncReset
input srst : UInt<1>
@ -59,8 +61,9 @@ circuit Example1 :
; with 1-bit field 'a' and 1-bit field 'b', and aggregate, invalid wires 'bar'
; and 'baz' with the same fields, and 'foo' is initialized to 'baz', and 'bar.a'
; is connected to zero, and 'baz' is connected to 'bar'.
FIRRTL version 4.0.0
circuit Example2 :
module Example2 :
public module Example2 :
input clock : Clock
input arst : AsyncReset
input srst : UInt<1>
@ -90,8 +93,9 @@ circuit Example2 :
; Should convert a reset wired to UInt<0> to a canonical non-reset, given foo's
; reset is connected to zero.
FIRRTL version 4.0.0
circuit Example3 :
module Example3 :
public module Example3 :
input clock : Clock
input in : UInt<2>
output out : UInt<2>[3]

3
test/Dialect/FIRRTL/SFCTests/trace-api.fir
View File

@ -1,6 +1,7 @@
; RUN: firtool --output-annotation-file=Baz.anno.json %s | FileCheck %s
; Test that a wire in an inlined instance get the proper Trace Annotation.
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class":"chisel3.experimental.Trace$TraceNameAnnotation",
@ -32,7 +33,7 @@ circuit Foo: %[[
baz.a <= a
b <= baz.b
module Foo:
public module Foo:
input a: UInt<1>
output b: UInt<1>

39
test/Dialect/FIRRTL/SFCTests/width-spec-errors.fir
View File

@ -3,30 +3,31 @@
; - test/scala/firrtlTests/WidthSpec.scala
; Dshl by more than 31 bits should result in an error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input x : UInt<3>
input y : UInt<32>
output z : UInt
; expected-error @+1 {{shift amount too large: second operand of dshl is wider than 31 bits}}
z <= dshl(x, y)
node z = dshl(x, y)
// -----
; Dshl by to more than 31 bits total width should result in an error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input x : UInt<1073741825>
input y : UInt<30>
output z : UInt
; expected-error @+1 {{shift amount too large: first operand shifted by maximum amount exceeds maximum width}}
z <= dshl(x, y)
node z = dshl(x, y)
// -----
; Casting a multi-bit signal to Clock should result in error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input i: UInt<2>
; expected-error @+1 {{must be 1-bit uint/sint/analog, reset, asyncreset, or clock}}
node x = asClock(i)
@ -34,8 +35,9 @@ circuit Unit :
// -----
; Casting a multi-bit signal to AsyncReset should result in error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input i: UInt<2>
; expected-error @+1 {{operand must be single bit scalar type}}
node x = asAsyncReset(i)
@ -43,16 +45,18 @@ circuit Unit :
// -----
; Width >= MaxWidth should result in an error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
; expected-error @+1 {{value is too big to handle}}
input x: UInt<2147483648>
// -----
; Circular reg depending on reg + 1 should error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input clock: Clock
input reset: UInt<1>
; expected-error @+1 {{'firrtl.regreset' op is constrained to be wider than itself}}
@ -66,31 +70,32 @@ circuit Unit :
// -----
; Add of UInt<2> and SInt<2> should error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input x: UInt<2>
input y: SInt<2>
output z: SInt
; expected-error @+1 {{operand signedness must match}}
z <= add(x, y)
node z = add(x, y)
// -----
; SInt<2> - UInt<3> should error
FIRRTL version 4.0.0
circuit Unit :
module Unit :
public module Unit :
input x: UInt<3>
input y: SInt<2>
output z: SInt
; expected-error @+1 {{operand signedness must match}}
z <= sub(y, x)
node z = sub(y, x)
// -----
; Should provide a good error message with a full target if a user forgets an
; assign.
FIRRTL version 4.0.0
circuit Foo :
module Foo :
public module Foo :
input clock : Clock
inst bar of Bar
module Bar :

1
test/Dialect/FIRRTL/SFCTests/width-spec.fir
View File

@ -3,6 +3,7 @@
; - test/scala/firrtlTests/WidthSpec.scala
; Literal width checks
FIRRTL version 3.0.0
circuit Foo :
; CHECK-LABEL: firrtl.module @Foo(
; CHECK-SAME: out %si0: !firrtl.sint<3>

9
test/Dialect/FIRRTL/annotations-errors.fir
View File

@ -2,28 +2,31 @@
; Annotations JSON is not an array.
FIRRTL version 4.0.0
; expected-error @+2 {{Invalid/unsupported annotation format}}
; expected-note @+1 {{/* error: Expected annotations to be an array, but found something else. */}}
circuit Foo: %[{"a":"a"}]
module Foo:
public module Foo:
skip
; // -----
; Annotations JSON is not an array of objects.
FIRRTL version 4.0.0
; expected-error @+2 {{Invalid/unsupported annotation format}}
; expected-note @+1 {{/* error: Expected annotations to be an array of objects, but found an array of something else. */}}
circuit Foo: %[[{"a":"a"},[{"b":"b"}]]]
module Foo:
public module Foo:
skip
; // -----
; Annotations JSON is invalid. (There's a trailing comma.)
FIRRTL version 4.0.0
; expected-error @+2 {{Failed to parse JSON Annotations}}
; expected-note @+1 {{}}
circuit Foo: %[[{"a":"a"},]]]
module Foo:
public module Foo:
skip

18
test/Dialect/FIRRTL/annotations.fir
View File

@ -1,5 +1,6 @@
; RUN: circt-translate -import-firrtl -split-input-file %s | FileCheck %s
FIRRTL version 4.0.0
; All types of JSON values should work
circuit Foo: %[[
{
@ -15,7 +16,7 @@ circuit Foo: %[[
"array": [1, 2, 3]
}
]]
module Foo:
public module Foo:
skip
; CHECK-LABEL: module {
@ -29,27 +30,30 @@ circuit Foo: %[[
; // -----
FIRRTL version 4.0.0
; JSON escapes should work.
circuit Foo: %[[{"class": "circt.testNT", "\"":"}]]"}]]
module Foo:
public module Foo:
skip
; CHECK-LABEL: module {
; CHECK: firrtl.circuit "Foo" attributes {rawAnnotations =
; // -----
FIRRTL version 4.0.0
; JSON with a JSON-quoted string should be expanded.
circuit Foo: %[[{"class":"circt.testNT","a":"{\"b\":null}"}]]
module Foo:
public module Foo:
skip
; CHECK-LABEL: module {
; CHECK: firrtl.circuit "Foo" attributes {rawAnnotations = [{a = {b}, class = "circt.testNT"}]}
; // -----
FIRRTL version 4.0.0
; JSON with a JSON-quoted number should stay as a number.
circuit Foo: %[[{"class":"circt.testNT","a":"0","b":0,"c":"\"0\""}]]
module Foo:
public module Foo:
skip
; CHECK-LABEL: module {
@ -62,13 +66,14 @@ circuit Foo: %[[{"class":"circt.testNT","a":"0","b":0,"c":"\"0\""}]]
;
; A numeric "class" shouldn't crash the parser.
FIRRTL version 4.0.0
circuit Top : %[[
{
"class":"0",
"target":"~Top|Top>a"
}
]]
module Top :
public module Top :
wire a: UInt<1>
a is invalid
@ -76,6 +81,7 @@ circuit Top : %[[
; // -----
FIRRTL version 4.0.0
; Test that a circuit with annotations that are supposed to be bypassed by
; parsing/scattering are properly moved onto the circuit under a
; "rawAnnotations" attribute.
@ -90,7 +96,7 @@ circuit RawAnnotations: %[[
"class":"circt.missing"
}
]]
module RawAnnotations:
public module RawAnnotations:
wire x: UInt<1>
; CHECK-LABEL: firrtl.circuit "RawAnnotations"

36
test/Dialect/FIRRTL/connect-errors.fir
View File

@ -1,7 +1,8 @@
; RUN: circt-translate -import-firrtl -verify-diagnostics --split-input-file %s
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
output a: { flip a: UInt<1> }
output b: { a: UInt<1> }
@ -10,38 +11,9 @@ circuit Foo:
;// -----
circuit PartialFoo:
module PartialFoo:
output a: { flip a: UInt<1> }
output b: { a: UInt<1> }
; expected-error @+1 {{cannot partially connect non-weakly-equivalent}}
b <- a
;// -----
circuit PartialConnectMismatch:
module PartialConnectMismatch:
output a: UInt
output b: SInt
; expected-error @+1 {{cannot partially connect non-weakly-equivalent}}
b <- a
;// -----
circuit PartialConnectResetFlipMismatch:
module PartialConnectResetFlipMismatch:
output a: { flip a: Reset }
output b: { a: Reset }
; expected-error @+1 {{cannot partially connect non-weakly-equivalent}}
b <- a
;// -----
FIRRTL version 4.0.0
circuit Bar:
module Bar:
public module Bar:
; expected-note @+1 {{destination}}
output a: { flip a: UInt<1> }
input b: { flip a: UInt<1> }

32
test/Dialect/FIRRTL/parse-basic.fir
View File

@ -1303,32 +1303,6 @@ circuit Foo_v3p0p0:
; CHECK-NEXT: %b = firrtl.node {{.+}}%a
node b = a
;// -----
FIRRTL version 1.2.0
circuit Foo_v1p9p9:
module Foo_v1p9p9:
input a: UInt<1>
output b: UInt<1>
output auto : UInt<1>
; CHECK: firrtl.matchingconnect %b, %a
b <- a
; CHECK: [[a0:%.+]] = firrtl.subfield %bundleWithAnalog[a]
; CHECK: [[a1:%.+]] = firrtl.subfield %bundleWithAnalog[a]
; CHECK: firrtl.attach [[a1]], [[a0]]
wire bundleWithAnalog : {a: Analog<1>}
bundleWithAnalog <- bundleWithAnalog
; CHECK: [[A:%.+]] = firrtl.subfield %out_0[member] : !firrtl.bundle<member: bundle<"0": bundle<clock: clock, reset: uint<1>>>>
; CHECK: [[B:%.+]] = firrtl.subfield [[A]]["0"] : !firrtl.bundle<"0": bundle<clock: clock, reset: uint<1>>>
; CHECK: [[C:%.+]] = firrtl.subfield [[B]][reset] : !firrtl.bundle<clock: clock, reset: uint<1>>
; CHECK: firrtl.matchingconnect %auto, [[C]] : !firrtl.uint<1>
wire out_0 : { member : { 0 : { clock : Clock, reset : UInt<1>}}}
auto <- out_0.member.0.reset @[Field 173:49]
;// -----
; Check reference expressions using literal identifiers or keywords.
@ -1437,6 +1411,7 @@ circuit RadixEncodedIntegerLiterals:
;// -----
; Tests for type alias
FIRRTL version 4.0.0
circuit Top:
type WordType = const UInt<32>
type ValidType = UInt<1>
@ -1455,7 +1430,7 @@ circuit Top:
; CHECK-NEXT: %[[RESULT:.+]] = firrtl.subfield %in_data[valid] : !firrtl.alias<Data, bundle<w: const.vector<const.alias<WordType, const.uint<32>>, 2>, valid: alias<ValidType, uint<1>>, ready flip: uint<1>>>
; CHECK-NEXT: %c = firrtl.wire interesting_name : !firrtl.alias<Complex_id, alias<Complex, bundle<real: sint<10>, imag: sint<10>>>>
; CHECK-NEXT: firrtl.matchingconnect %out_valid, %[[RESULT]] : !firrtl.alias<ValidType, uint<1>>
module Top:
public module Top:
input in_data: Data
input in_complex: Complex
output out: ProbeComplex
@ -1714,8 +1689,9 @@ circuit VecOfProps:
;// -----
; Test parsing of wires of probes, wires of agg of probes, and namekinds.
; CHECK-LABEL: circuit "WireOfProbesAndNames"
FIRRTL version 4.0.0
circuit WireOfProbesAndNames:
module WireOfProbesAndNames:
public module WireOfProbesAndNames:
; CHECK: %mixed = firrtl.wire interesting_name : !firrtl.openbundle
wire mixed : { a : UInt<3>, b : Probe<UInt<3>> }
; CHECK: %probe = firrtl.wire : !firrtl.probe

224
test/Dialect/FIRRTL/parse-errors.fir
View File

@ -1,5 +1,6 @@
; RUN: circt-translate -import-firrtl -verify-diagnostics --split-input-file %s
FIRRTL version 4.0.0
circuit test :
extmodule MyModule :
@ -45,18 +46,19 @@ circuit test :
;// -----
; expected-error @below {{'circuit' must be first token on its line}}
FIRRTL version 1.1.0 circuit test :
FIRRTL version 2.0.0 circuit test :
module test :
;// -----
; expected-error @below {{FIRRTL version must be >=0.2.0}}
; expected-error @below {{FIRRTL version must be >=2.0.0}}
FIRRTL version 0.1.0
circuit test :
module test :
;// -----
FIRRTL version 4.0.0
circuit test test : ; expected-error {{expected ':' in circuit definition}}
;// -----
@ -66,6 +68,7 @@ circuit test test : ; expected-error {{expected ':' in circuit definition}}
;// -----
FIRRTL version 4.0.0
circuit nameConflict :
module nameConflict :
input c: Clock ; expected-note {{previous definition here}}
@ -74,6 +77,7 @@ circuit nameConflict :
;// -----
FIRRTL version 4.0.0
circuit nameConflict :
extmodule nameConflict :
input c: Clock ; expected-note {{previous definition here}}
@ -82,22 +86,25 @@ circuit nameConflict :
;// -----
FIRRTL version 4.0.0
circuit invalid_name :
module invalid_name :
input c: UInt
public module invalid_name :
input c: UInt<4>
out <= c ; expected-error {{use of unknown declaration 'out'}}
;// -----
FIRRTL version 4.0.0
circuit invalid_name :
module invalid_name :
output out: UInt
public module invalid_name :
output out: UInt<4>
out <= c ; expected-error {{use of unknown declaration 'c'}}
;// -----
FIRRTL version 4.0.0
circuit subfield_of_ground_type :
module subfield_of_ground_type :
public module subfield_of_ground_type :
input a: UInt<1>
output b: UInt<1>
; expected-error @+1 {{subfield requires bundle or object operand}}
@ -105,26 +112,27 @@ circuit subfield_of_ground_type :
;// -----
FIRRTL version 1.2.0
FIRRTL version 2.0.0
circuit invalid_name :
module invalid_name :
input out_0 : { member : { 0 : { clock : Clock, reset : UInt<1>}}}
; expected-error @+1 {{unknown field 'xx' in type '!firrtl.bundle<member: bundle<"0": bundle<clock: clock, reset: uint<1>>>>'}}
out_0.xx <- out_0.yy
; expected-error @+1 {{unknown field 'xx' in type '!firrtl.bundle<member: bundle<"0": bundle<clock: clock, reset: uint<1>>>>}}
out_0.xx <= out_0.yy
;// -----
FIRRTL version 1.2.0
FIRRTL version 2.0.0
circuit invalid_name :
module invalid_name :
input out_0 : SInt<8>[5]
; expected-error @+1 {{out of range index '5' in vector type '!firrtl.vector<sint<8>, 5>'}}
out_0[4] <- out_0[5]
out_0[4] <= out_0[5]
;// -----
FIRRTL version 4.0.0
circuit invalid_add :
module invalid_add :
public module invalid_add :
input in : SInt<8>
input c : Clock
; expected-error @+1 {{second operand must be an integer type, not '!firrtl.clock'}}
@ -132,8 +140,9 @@ circuit invalid_add :
;// -----
FIRRTL version 4.0.0
circuit invalid_add :
module invalid_add :
public module invalid_add :
input in : SInt<8>
input c : Clock
; expected-error @+1 {{operation requires two operands}}
@ -141,25 +150,27 @@ circuit invalid_add :
;// -----
FIRRTL version 2.0.0
circuit invalid_int_literal :
module invalid_int_literal :
node n = add(UInt<8>("hAX"), UInt<10>(42)) ; expected-error {{invalid character in integer literal}}
;// -----
; When scopes are local to the body
FIRRTL version 1.2.0
FIRRTL version 2.0.0
circuit invalid_name :
module invalid_name :
input reset : UInt<1>
output out : UInt<1>
when reset :
node n4 = reset
out <- n4 ; expected-error {{use of unknown declaration 'n4'}}
out <= n4 ; expected-error {{use of unknown declaration 'n4'}}
;// -----
FIRRTL version 4.0.0
circuit invalid_inst :
module invalid_inst :
public module invalid_inst :
; expected-error @+1 {{use of undefined module name 'some_module' in instance}}
inst xyz of some_module
@ -175,6 +186,7 @@ circuit class_inst :
;// -----
FIRRTL version 4.0.0
circuit MyParameterizedExtModule :
extmodule MyParameterizedExtModule :
parameter DEFAULT = 0
@ -182,15 +194,17 @@ circuit MyParameterizedExtModule :
;// -----
FIRRTL version 4.0.0
circuit invalid_name :
module invalid_name :
public module invalid_name :
input bf: { flip int_1 : UInt<1>, int_out : UInt<2>}
node n4 = add(bf, bf) ; expected-error {{operands must be integer types, not '!firrtl.bundle<int_1 flip: uint<1>, int_out: uint<2>>' and '!firrtl.bundle<int_1 flip: uint<1>, int_out: uint<2>>'}}
;// -----
FIRRTL version 4.0.0
circuit invalid_bits :
module invalid_bits:
public module invalid_bits:
input a: UInt<8>
output b: UInt<4>
; expected-error @+1 {{high must be equal or greater than low, but got high = 4, low = 7}}
@ -198,25 +212,28 @@ circuit invalid_bits :
;// -----
FIRRTL version 4.0.0
circuit test :
module invalid_add :
input in1 : SInt
input in2 : UInt
public module invalid_add :
input in1 : SInt<5>
input in2 : UInt<5>
node n = add(in1, in2) ; expected-error {{operand signedness must match}}
;// -----
FIRRTL version 4.0.0
circuit invalid_node_not_passive :
module invalid_node_not_passive :
input a : { a: UInt, flip b: UInt}
output b : { a: UInt, flip b: UInt}
public module invalid_node_not_passive :
input a : { a: UInt<5>, flip b: UInt<5>}
output b : { a: UInt<5>, flip b: UInt<5>}
; expected-error @+1 {{Node cannot be analog and must be passive or passive under a flip}}
node n = a
;// -----
FIRRTL version 4.0.0
circuit invalid_node_analog :
module invalid_node_analog :
public module invalid_node_analog :
input a : Analog<1>
output b : Analog<1>
; expected-error @+1 {{Node cannot be analog and must be passive or passive under a flip}}
@ -224,8 +241,9 @@ circuit invalid_node_analog :
;// -----
FIRRTL version 4.0.0
circuit Issue418:
module Issue418:
public module Issue418:
input a: UInt<1>
output b: UInt<1>
@ -234,8 +252,9 @@ circuit Issue418:
;// -----
FIRRTL version 4.0.0
circuit Issue3799:
module Issue3799:
public module Issue3799:
output a: UInt<0>
a <= UInt<0>(0) ; ok
a <= UInt<0>(-0) ; ok
@ -244,8 +263,9 @@ circuit Issue3799:
;// -----
FIRRTL version 4.0.0
circuit Issue3799:
module Issue3799:
public module Issue3799:
output a: SInt<0>
a <= SInt<0>(0) ; ok
a <= SInt<0>(-0) ; ok
@ -255,16 +275,18 @@ circuit Issue3799:
;// -----
FIRRTL version 4.0.0
circuit Issue426:
module Issue426:
public module Issue426:
output a: UInt<1>
; expected-error @+1 {{initializer too wide for declared width}}
a <= UInt<1>(2)
;// -----
FIRRTL version 4.0.0
circuit Issue426:
module Issue426:
public module Issue426:
output a: SInt<1>
a <= SInt<1>(0) ; ok
a <= SInt<1>(-1) ; ok
@ -272,16 +294,18 @@ circuit Issue426:
a <= SInt<1>(1)
;// -----
FIRRTL version 4.0.0
circuit Issue426:
module Issue426:
public module Issue426:
output a: SInt<1>
; expected-error @+1 {{initializer too wide for declared width}}
a <= SInt<1>(-2)
;// -----
FIRRTL version 4.0.0
circuit circuit:
module circuit :
public module circuit :
input in: UInt<80>
inst xyz of circuit
node n = xyz
@ -289,32 +313,36 @@ circuit circuit:
;// -----
FIRRTL version 4.0.0
circuit circuit:
module circuit :
public module circuit :
input in: UInt<80>
inst xyz of circuit
node n = xyz.foo ; expected-error {{use of invalid field name 'foo' on bundle value}}
;// -----
FIRRTL version 4.0.0
circuit NonAscii:
module NonAscii:
public module NonAscii:
input clk: Clock
input enable: UInt<1>
printf(clk, enable, "’") ; expected-error {{string characters must be 7-bit ASCII}}
;// -----
FIRRTL version 4.0.0
circuit UnicodeEscape:
module UnicodeEscape:
public module UnicodeEscape:
input clk: Clock
input enable: UInt<1>
printf(clk, enable, "\u0065") ; expected-error {{unicode escape not supported in string}}
;// -----
FIRRTL version 4.0.0
circuit PrintfExpr:
module PrintfExpr:
public module PrintfExpr:
input clk: Clock
input enable: UInt<1>
output out : UInt<1>
@ -322,14 +350,16 @@ circuit PrintfExpr:
;// -----
FIRRTL version 4.0.0
circuit ProbeFlipType:
module ProbeFlipType:
public module ProbeFlipType:
output p : Probe<{a: UInt, flip b: UInt}> ; expected-error {{probe inner type must be passive}}
;// -----
FIRRTL version 4.0.0
circuit NestedProbes:
module NestedProbes:
public module NestedProbes:
output p : Probe<Probe<UInt>> ; expected-error {{invalid probe inner type, must be base-type}}
;// -----
@ -341,8 +371,9 @@ circuit ProbeOfProp:
;// -----
FIRRTL version 4.0.0
circuit RefSubaccess:
module RefSubaccess:
public module RefSubaccess:
input in : UInt<1>[3]
input sel : UInt<2>
output out : UInt<1>
@ -351,57 +382,63 @@ circuit RefSubaccess:
;// -----
FIRRTL version 4.0.0
circuit ProbeBase:
extmodule ProbeGen:
output p : Probe<UInt<2>>
ref p is "x.y"
module ProbeBase:
public module ProbeBase:
input in : UInt<1>
output out : UInt
output out : UInt<1>
inst pg of ProbeGen
out <= probe(pg.p) ; expected-error {{expected base-type expression in 'probe', got}}
;// -----
FIRRTL version 4.0.0
circuit ProbeProbe:
module ProbeProbe:
public module ProbeProbe:
input in : UInt<1>
output out : UInt
output out : UInt<1>
out <= probe(probe(in)) ; expected-error {{expected static reference expression in 'probe'}}
;// -----
FIRRTL version 4.0.0
circuit ReadBase:
module ReadBase:
public module ReadBase:
input in : UInt<1>
output out : UInt
output out : UInt<1>
out <= read(in) ; expected-error {{expected reference-type expression in 'read', got}}
;// -----
FIRRTL version 4.0.0
circuit DefineBaseLHS:
module DefineBaseLHS:
public module DefineBaseLHS:
input in : UInt<1>
output out : UInt
output out : UInt<1>
define out = probe(in) ; expected-error {{expected reference-type expression in 'define' target (LHS), got}}
;// -----
FIRRTL version 4.0.0
circuit DefineBaseRHS:
module DefineBaseRHS:
public module DefineBaseRHS:
input in : UInt<1>
output out : Probe<UInt>
output out : Probe<UInt<1>>
define out = in ; expected-error {{expected reference-type expression in 'define' source (RHS), got}}
;// -----
FIRRTL version 4.0.0
circuit RefSubaccess:
module RefSubaccess:
public module RefSubaccess:
input in : UInt<1>[3]
input sel : UInt<2>
output out : UInt<1>
@ -410,8 +447,9 @@ circuit RefSubaccess:
;// -----
FIRRTL version 4.0.0
circuit DefineTwice:
module DefineTwice:
public module DefineTwice:
input in: UInt<1>
output out : Probe<UInt<1>>
define out = probe(in) ; expected-error {{destination reference cannot be reused by multiple operations, it can only capture a unique dataflow}}
@ -419,8 +457,9 @@ circuit DefineTwice:
;// -----
FIRRTL version 4.0.0
circuit DefineIntoSubindex:
module DefineIntoSubindex:
public module DefineIntoSubindex:
input in : UInt<1>[3]
output out : Probe<UInt<1>[3]>
@ -428,8 +467,9 @@ circuit DefineIntoSubindex:
;// -----
FIRRTL version 4.0.0
circuit DefineIntoProbe:
module DefineIntoProbe:
public module DefineIntoProbe:
input in : UInt<1>
output out : UInt<1>
@ -437,12 +477,14 @@ circuit DefineIntoProbe:
;// -----
FIRRTL version 4.0.0
circuit InProbeTop:
module InProbeTop:
public module InProbeTop:
input p : Probe<UInt<1>> ; expected-error {{input probe not allowed}}
;// -----
FIRRTL version 4.0.0
circuit InProbeExt:
extmodule BadExtMod:
input p : Probe<UInt<1>> ; expected-error {{references in ports must be output on extmodule and intmodule}}
@ -452,6 +494,7 @@ circuit InProbeExt:
;// -----
FIRRTL version 3.0.0
circuit RefDupe:
extmodule RefDupe:
output p : Probe<UInt<2>>
@ -461,6 +504,7 @@ circuit RefDupe:
;// -----
; Either use ref statements or ABI, can't partially use ref statements.
FIRRTL version 3.0.0
circuit MissingRef:
extmodule MissingRef:
output p : Probe<UInt<2>> ; expected-error {{no ref statement found for ref port "p"}}
@ -469,12 +513,14 @@ circuit MissingRef:
;// -----
FIRRTL version 3.0.0
circuit UnusedRef:
extmodule UnusedRef:
ref p is "x.y" ; expected-error {{unused ref statement}}
;// -----
FIRRTL version 3.0.0
circuit RefNotString:
extmodule RefNotString:
output p : Probe<UInt<2>>
@ -482,6 +528,7 @@ circuit RefNotString:
;// -----
FIRRTL version 3.0.0
circuit RefForAggElement:
extmodule RefForAggElement:
output p : { x: Probe<UInt<2>> }
@ -489,8 +536,9 @@ circuit RefForAggElement:
;// -----
FIRRTL version 4.0.0
circuit ConnectWrongType:
module ConnectWrongType:
public module ConnectWrongType:
input a: UInt<1>
output b: SInt<1>
@ -516,8 +564,9 @@ circuit ConnectAlternateWrongType:
;// -----
FIRRTL version 4.0.0
circuit ProbeConnect:
module ProbeConnect:
public module ProbeConnect:
input in : UInt<1>
output p : Probe<UInt<1>>
@ -535,18 +584,9 @@ circuit ProbeConnectAlternate:
;// -----
FIRRTL version 1.2.0
circuit ProbePartialConnect:
module ProbePartialConnect:
input in : UInt<1>
output p : Probe<UInt<1>>
p <- probe(in) ; expected-error {{cannot connect reference or property types}}
;// -----
FIRRTL version 4.0.0
circuit ProbeMem:
module ProbeMem:
public module ProbeMem:
output out : Probe<UInt<3>> ; (wrong probe type, can't probe memories)
mem memory:
@ -565,6 +605,7 @@ circuit ProbeMem:
;// -----
FIRRTL version 3.0.0
circuit ProbeSMem:
module ProbeSMem:
input clock : Clock
@ -580,43 +621,49 @@ circuit ProbeSMem:
;// -----
FIRRTL version 4.0.0
circuit LeadingRead:
module LeadingRead:
public module LeadingRead:
input in : UInt<1>
read(probe(in)) ; expected-error {{unexpected read() as start of statement}}
;// -----
FIRRTL version 4.0.0
circuit LeadingProbe:
module LeadingProbe:
public module LeadingProbe:
input in : UInt<1>
probe(in) ; expected-error {{unexpected probe() as start of statement}}
;// -----
FIRRTL version 4.0.0
circuit ForceProbe:
module ForceProbe:
public module ForceProbe:
input in : UInt<1>
force_initial(probe(in), UInt<1>(1)) ; expected-error {{expected rwprobe-type expression for force_initial destination, got '!firrtl.probe<uint<1>>'}}
;// -----
FIRRTL version 4.0.0
circuit ForceWithLiteral:
module ForceWithLiteral:
public module ForceWithLiteral:
input in : UInt<1>
node n = in
force_initial(rwprobe(n), 1) ; expected-error {{expected source expression in force_initial}}
;// -----
FIRRTL version 4.0.0
circuit RWProbeConst:
extmodule RWProbeConst:
output p : RWProbe<{a: const UInt}> ; expected-error {{rwprobe cannot contain const}}
;// -----
FIRRTL version 4.0.0
circuit RWProbeConstPort:
module RWProbeConstPort:
public module RWProbeConstPort:
input in : const UInt<1>[2]
output p : RWProbe<UInt<1>>
define p = rwprobe(in[1]) ; expected-error {{cannot force target of type '!firrtl.const.uint<1>'}}
@ -629,7 +676,7 @@ circuit PartialConnect_v2p0p0:
input a: UInt<1>
output b: UInt<1>
b <- a ; expected-error {{partial connects were removed in FIRRTL 2.0.0, but the specified FIRRTL version was 2.0.0}}
b <- a ; expected-error {{unexpected character after sign}}
;// -----
@ -649,31 +696,35 @@ circuit IllegalLiteral:
;// -----
FIRRTL version 4.0.0
circuit NodeProbe:
extmodule Ref:
output x : Probe<UInt<1>>
module NodeProbe:
public module NodeProbe:
inst r of Ref
node n = r.x ; expected-error {{Node cannot be analog and must be passive or passive under a flip}}
;// -----
FIRRTL version 4.0.0
circuit ConstProbe:
module ConstProbe:
public module ConstProbe:
output x : const Probe<UInt<1>> ; expected-error {{only hardware types can be 'const'}}
;// -----
FIRRTL version 4.0.0
circuit MultiConst:
module MultiConst:
public module MultiConst:
output x : const const UInt<1> ; expected-error {{'const' can only be specified once on a type}}
;// -----
FIRRTL version 4.0.0
circuit DefinePromoteToRW:
extmodule Ref:
output ro : Probe<UInt<1>>
module DefinePromoteToRW:
public module DefinePromoteToRW:
output rw : RWProbe<UInt<1>>
inst r of Ref
; expected-error @below {{cannot define reference of type '!firrtl.rwprobe<uint<1>>' with incompatible reference of type '!firrtl.probe<uint<1>>'}}
@ -744,24 +795,28 @@ circuit UnsupportedStringEncodedIntegerLiterals:
;// -----
FIRRTL version 4.0.0
circuit UnknownTypeAlias:
module UnknownTypeAlias:
public module UnknownTypeAlias:
output x : Foo ; expected-error {{type identifier `Foo` is not declared}}
;// -----
FIRRTL version 4.0.0
circuit DuplicateAlias:
type Foo = UInt
type Foo = UInt; expected-error {{type alias `Foo` is already defined}}
module DuplicateAlias:
public module DuplicateAlias:
;// -----
FIRRTL version 4.0.0
circuit KeywordTypeName:
type Clock = UInt; expected-error {{cannot use keyword 'Clock' for type alias name}}
;// -----
FIRRTL version 4.0.0
circuit KeywordTypeName:
type module = UInt; expected-error {{cannot use keyword 'module' for type alias name}}
@ -1191,8 +1246,9 @@ circuit PublicNonModule:
public module PublicNonModule:
;// -----
FIRRTL version 4.0.0
circuit RWProbeExprOOB :
module RWProbeExprOOB :
public module RWProbeExprOOB :
output p : RWProbe<UInt<1>>
wire x : UInt<1>[2]
x is invalid
@ -1201,7 +1257,7 @@ circuit RWProbeExprOOB :
define p = rwprobe(x[100])
input out_0 : SInt<8>[5]
out_0[4] <- out_0[5]
out_0[4] <= out_0[5]
;// -----
@ -1384,12 +1440,14 @@ circuit PrivateMainModule:
module PrivateMainModule:
;// -----
FIRRTL version 3.0.0
circuit IntModuleNoIntrinsic:
intmodule test:
; expected-error @below {{expected 'intrinsic'}}
module IntModule:
;// -----
FIRRTL version 3.0.0
circuit IntModuleBadIntrinsic:
intmodule test:
; expected-error @below {{expected intrinsic name}}

13
test/Dialect/FIRRTL/parse-locations.fir
View File

@ -1,16 +1,17 @@
; RUN: circt-translate -import-firrtl --mlir-print-debuginfo -verify-diagnostics -mlir-print-local-scope %s | FileCheck %s
FIRRTL version 4.0.0
circuit MyModule : @[CIRCUIT.scala 127]
; CHECK-LABEL: firrtl.module @MyModule(
; CHECK-SAME: in %in: !firrtl.uint loc("InputPort.scala":0:0)
; CHECK-SAME: in %in: !firrtl.uint<8> loc("InputPort.scala":0:0)
; CHECK-SAME: out %out: !firrtl.uint<8> loc("OutputPort.scala":0:0)
; CHECK-SAME: ) {
module MyModule : @[FooBar.scala 369:27]
input in: UInt @[InputPort.scala 0:0]
public module MyModule : @[FooBar.scala 369:27]
input in: UInt<8> @[InputPort.scala 0:0]
output out: UInt<8> @[OutputPort.scala 0:0]
; CHECK: firrtl.connect {{.*}}loc("Somewhere.galaxy":42:1)
; CHECK: firrtl.matchingconnect {{.*}}loc("Somewhere.galaxy":42:1)
out <= in @[Somewhere.galaxy 42:1]
; CHECK: firrtl.node {{.*}}loc("Somewhere.galaxy":42:2)
@ -46,7 +47,7 @@ circuit MyModule : @[CIRCUIT.scala 127]
; CHECK: %2 = firrtl.subfield %1["0"] {{.*}} loc("Field":173:49)
; CHECK: %3 = firrtl.subfield %2[reset] : {{.*}} loc("Field":173:49)
; CHECK: firrtl.matchingconnect %0, %3 : {{.*}} loc("Field":173:49)
auto.out_0 <- out_0.member.0.reset @[Field 173:49]
auto.out_0 <= out_0.member.0.reset @[Field 173:49]
; Fused locators: https://github.com/llvm/circt/issues/224
@ -60,7 +61,7 @@ circuit MyModule : @[CIRCUIT.scala 127]
; https://github.com/llvm/circt/issues/1140
module issue1140:
input mask_bit_2 : UInt<1>
node mask_nbit_2 = eq(mask_bit_2, UInt<1>("h0")) @[Misc.scala 210:20]
node mask_nbit_2 = eq(mask_bit_2, UInt<1>(0h0)) @[Misc.scala 210:20]
; Make sure the locator is applied to all the subexpressions.
; CHECK: %c0_ui1 = firrtl.constant 0 : !firrtl.const.uint<1> loc("Misc.scala":210:20)

3
test/Dialect/FIRRTL/parse-name-preservation.fir
View File

@ -1,6 +1,7 @@
; RUN: firtool --parse-only %s | FileCheck %s
FIRRTL version 4.0.0
circuit Bar :
module Bar :
public module Bar :
input in: UInt<1>
; Should create a "tap" node with the same type and a symbol when the type

2
test/Dialect/FIRRTL/parse-version.fir
View File

@ -1,5 +1,5 @@
; RUN: circt-translate -import-firrtl -verify-diagnostics %s | circt-opt | FileCheck %s
FIRRTL version 1.1.0
FIRRTL version 2.0.0
circuit MyModule : ; CHECK: firrtl.circuit "MyModule" {
; CHECK-LABEL: firrtl.module @MyModule(in %in: !firrtl.uint, out %out: !firrtl.uint<8>) {

3
test/Dialect/FIRRTL/when-encoded-verif.fir
View File

@ -1,8 +1,9 @@
; RUN: circt-translate -import-firrtl -verify-diagnostics %s
FIRRTL version 4.0.0
circuit WhenEncodedVerification:
; expected-error @below {{module contains 23 printf-encoded verification operation(s), which are no longer supported.}}
; expected-note @below {{For more information, see https://github.com/llvm/circt/issues/6970}}
module WhenEncodedVerification:
public module WhenEncodedVerification:
input clock: Clock
input cond: UInt<1>
input enable: UInt<1>

3
test/circt-translate/parse_int64.fir
View File

@ -1,7 +1,8 @@
; RUN: circt-translate %s --import-firrtl | FileCheck %s --strict-whitespace
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
mem memory:
data-type => UInt<8>
depth => 2147483648

3
test/firtool/annotation-error.fir
View File

@ -5,10 +5,11 @@
; RUN: firtool %s --parse-only --annotation-file %t.json --verify-diagnostics
FIRRTL version 4.0.0
; expected-error @below {{Failed to parse JSON}}
; expected-note @below {{}}
circuit Test:
module Test:
public module Test:
output o : UInt<1>
o <= UInt<1>(0)

3
test/firtool/annotation-openaggs-error.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool -parse-only %s --verify-diagnostics
FIRRTL version 4.0.0
; expected-error @below {{Unable to resolve target of annotation: {class = "circt.test", target = "~OpenAgg|OpenAgg>out.p"}}
circuit OpenAgg : %[[
{ "class": "circt.test",
@ -7,7 +8,7 @@ circuit OpenAgg : %[[
}
]]
; expected-error @below {{cannot resolve field 'p'}}
module OpenAgg:
public module OpenAgg:
output out : {a : UInt<1>,
p : Probe<UInt<1>>
b : UInt<1>}

3
test/firtool/annotation-openaggs.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool -parse-only %s | FileCheck %s
FIRRTL version 4.0.0
circuit OpenAgg : %[[
{ "class": "circt.test",
"target": "~OpenAgg|OpenAgg>out.a"
@ -14,7 +15,7 @@ circuit OpenAgg : %[[
; CHECK-LABEL: module @OpenAgg
; CHECK-SAME: (out %out: !firrtl.bundle<a: uint<1>, b: uint<1>> [{circt.fieldID = 1 : i32, class = "circt.test"}, {circt.fieldID = 2 : i32, class = "circt.test"}, {class = "circt.test"}]
; CHECK-SAME: , out %out_p: !firrtl.probe<uint<1>>)
module OpenAgg:
public module OpenAgg:
output out : {a : UInt<1>,
p : Probe<UInt<1>>
b : UInt<1>}

11
test/firtool/btor2.fir
View File

@ -1,21 +1,22 @@
; RUN: firtool --btor2 %s | FileCheck %s
FIRRTL version 4.0.0
circuit Counter :
module Counter :
public module Counter :
input clock : Clock
input reset : UInt<1>
input en : UInt<1>
reg count : UInt<32>, clock with :
reset => (reset, UInt<32>("h0"))
reset => (reset, UInt<32>(0h0))
when and(eq(count, UInt<32>(22)), en) :
count <= UInt<1>("h0")
count <= UInt<1>(0h0)
when and(neq(count, UInt<32>(22)), en) :
count <= tail(add(count, UInt<1>("h1")), 1)
count <= tail(add(count, UInt<1>(0h1)), 1)
assert(clock, neq(count, UInt<4>("ha")), en, "Counter reached 10!")
assert(clock, neq(count, UInt<4>(0ha)), en, "Counter reached 10!")
; CHECK: 1 sort bitvec 1
; CHECK: 2 input 1 reset

3
test/firtool/chirrtl.fir
View File

@ -5,11 +5,12 @@
; be enabled. If they are accidentally removed before the lower-chirrtl pass,
; then they won't be enabled.
FIRRTL version 4.0.0
circuit test: %[[{
"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
"target":"~test|test"
}]]
module test:
public module test:
input p: UInt<1>
input addr1: UInt<4>
input addr2: UInt<4>

3
test/firtool/chisel-interface.fir
View File

@ -19,8 +19,9 @@
; CHECK-NEXT: val out = IO(Output(UInt(4.W)))
; CHECK-NEXT: }
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input in: UInt<4>
output out: UInt<4>
out <= in

3
test/firtool/connect-errors.fir
View File

@ -1,8 +1,9 @@
; RUN: firtool %s --format=fir --parse-only -verify-diagnostics
; CHECK-LABEL: outOfOrderFields
FIRRTL version 4.0.0
circuit outOfOrderFields :
module outOfOrderFields :
public module outOfOrderFields :
output a: { a: UInt<5>, b: UInt<3> }
input b: { b: UInt<1>, a: UInt<6> }
; expected-error@+1 {{cannot connect non-equivalent type '!firrtl.bundle<b: uint<1>, a: uint<6>>' to '!firrtl.bundle<a: uint<5>, b: uint<3>>'}}

20
test/firtool/connect.fir
View File

@ -1,25 +1,31 @@
; RUN: firtool %s --format=fir --parse-only | FileCheck %s
; RUN: firtool %s --format=fir --parse-only --split-input-file | FileCheck %s
; Ensure connect is demoted to partial connect in the presence of implicit truncation.
; CHECK-LABEL: @regularConnect
; CHECK: %0 = firrtl.pad %b, 5 : (!firrtl.uint<3>) -> !firrtl.uint<5>
; CHECK: firrtl.matchingconnect %a, %0 : !firrtl.uint<5>
FIRRTL version 4.0.0
circuit regularConnect :
module regularConnect :
public module regularConnect :
output a: UInt<5>
input b: UInt<3>
a <= b
; // -----
; CHECK-LABEL: @truncatingIntegerConnect
; CHECK: %0 = firrtl.tail %b, 2 : (!firrtl.uint<5>) -> !firrtl.uint<3>
; CHECK: firrtl.matchingconnect %a, %0 : !firrtl.uint<3>
FIRRTL version 4.0.0
circuit truncatingIntegerConnect :
module truncatingIntegerConnect :
public module truncatingIntegerConnect :
output a: UInt<3>
input b: UInt<5>
a <= b
; // -----
; CHECK-LABEL: @regularBundleConnect
; CHECK: %0 = firrtl.subfield %a[a] : !firrtl.bundle<a: uint<5>, b: uint<3>>
; CHECK: %1 = firrtl.subfield %b[a] : !firrtl.bundle<a: uint<3>, b: uint<2>>
@ -29,12 +35,15 @@ circuit truncatingIntegerConnect :
; CHECK: %4 = firrtl.subfield %b[b] : !firrtl.bundle<a: uint<3>, b: uint<2>>
; CHECK: %5 = firrtl.pad %4, 3 : (!firrtl.uint<2>) -> !firrtl.uint<3>
; CHECK: firrtl.matchingconnect %3, %5 : !firrtl.uint<3>
FIRRTL version 4.0.0
circuit regularBundleConnect :
module regularBundleConnect :
public module regularBundleConnect :
output a: { a: UInt<5>, b: UInt<3> }
input b: { a: UInt<3>, b: UInt<2> }
a <= b
; // -----
; CHECK-LABEL: @truncatingBundleConnect
; CHECK: %0 = firrtl.subfield %a[a] : !firrtl.bundle<a: uint<5>, b: uint<3>>
; CHECK: %1 = firrtl.subfield %b[a] : !firrtl.bundle<a: uint<6>, b: uint<1>>
@ -44,8 +53,9 @@ circuit regularBundleConnect :
; CHECK: %4 = firrtl.subfield %b[b] : !firrtl.bundle<a: uint<6>, b: uint<1>>
; CHECK: %5 = firrtl.pad %4, 3 : (!firrtl.uint<1>) -> !firrtl.uint<3>
; CHECK: firrtl.matchingconnect %3, %5 : !firrtl.uint<3>
FIRRTL version 4.0.0
circuit truncatingBundleConnect :
module truncatingBundleConnect :
public module truncatingBundleConnect :
output a: { a: UInt<5>, b: UInt<3> }
input b: { a: UInt<6>, b: UInt<1> }
a <= b

3
test/firtool/convention.fir
View File

@ -11,6 +11,7 @@
; Ensure that top module and ext modules are marked scalarized.
FIRRTL version 4.0.0
circuit Top :
; SCALARIZE_FFF-NOT: attributes {convention = #firrtl<convention scalarized>}
; SCALARIZE_TFF: attributes {convention = #firrtl<convention scalarized>}
@ -20,7 +21,7 @@ circuit Top :
; SCALARIZE_TFT: attributes {convention = #firrtl<convention scalarized>}
; SCALARIZE_FTT-NOT: attributes {convention = #firrtl<convention scalarized>}
; SCALARIZE_TTT: attributes {convention = #firrtl<convention scalarized>}
module Top :
public module Top :
output port: UInt<8>[2]
port[0] <= UInt<8>(0)
port[1] <= UInt<8>(0)

11
test/firtool/import-ref.fir
View File

@ -3,13 +3,14 @@
; CHECK: Generated by
; CHECK-LABEL: module TestHarness(
FIRRTL version 4.0.0
circuit TestHarness:
extmodule DUT:
input clock: Clock
output read: Probe<UInt<32>>
output write: RWProbe<UInt<32>>
module TestHarness:
public module TestHarness:
input clock: Clock
inst dut of DUT
@ -20,7 +21,7 @@ circuit TestHarness:
printf(clock, UInt<1>(1) "%x", read(dut.read))
; CHECK: initial
; CHECK: force TestHarness.dut.`ref_DUT_write = 32'hDEADBEEF;
force_initial(dut.write, UInt<32>("hdeadbeef"))
force_initial(dut.write, UInt<32>(0hdeadbeef))
; CHECK: endmodule
@ -30,6 +31,7 @@ circuit TestHarness:
; CHECK-LABEL: module DUT(
FIRRTL version 4.0.0
circuit DUT:
extmodule NotTheRealName:
input clock: Clock
@ -37,7 +39,7 @@ circuit DUT:
output write: RWProbe<UInt<32>>
defname = Inner
module DUT:
public module DUT:
input clock: Clock
output read: Probe<UInt<32>>
output write: RWProbe<UInt<32>>
@ -58,8 +60,9 @@ circuit DUT:
; CHECK: Generated by
; CHECK-LABEL: module Inner(
FIRRTL version 4.0.0
circuit Inner:
module Inner:
public module Inner:
input clock: Clock
output read: Probe<UInt<32>>
output write: RWProbe<UInt<32>>

3
test/firtool/include-dirs-annotations.fir
View File

@ -9,8 +9,9 @@
; Confirm annotation file is found.
; RUN: firtool %s --parse-only --annotation-file test.anno.json -I %t | grep circt.test
FIRRTL version 4.0.0
circuit Test:
module Test:
public module Test:
output o : UInt<1>
o <= UInt<1>(0)

13
test/firtool/locators-diagnostics.fir
View File

@ -5,21 +5,22 @@
; RUN: not firtool %s -fuse-info-locators 2>&1 | FileCheck %s --check-prefixes=DIAG
; DIAG: path/to/Foo.scala:273:69: error:
; DIAG: locators-diagnostics.fir:20:5: note: additional location here
; DIAG: locators-diagnostics.fir:23:5: error:
; DIAG: locators-diagnostics.fir:21:5: note: additional location here
; DIAG: locators-diagnostics.fir:24:5: error:
; DIAG-NOT: note
FIRRTL version 4.0.0
circuit Error:
module Error:
public module Error:
output xa: UInt<1>
output ya: UInt<1>
; COMMON: %x = firrtl.wire
; FUSE-SAME: loc(fused["path/to/Foo.scala":273:69, "{{.+}}.fir":20:5])
; FUSE-SAME: loc(fused["path/to/Foo.scala":273:69, "{{.+}}.fir":21:5])
; PREFER-SAME: loc("path/to/Foo.scala":273:69)
; IGNORE-SAME: loc("{{.+}}.fir":20:5)
; IGNORE-SAME: loc("{{.+}}.fir":21:5)
wire x : { boop: { foo: { a: UInt<1>, b: UInt<2>}, bar: { a: UInt<1> }}} @[path/to/Foo.scala 273:69]
; COMMON: %y = firrtl.wire
; COMMON-SAME: loc("{{.+}}.fir":23:5)
; COMMON-SAME: loc("{{.+}}.fir":24:5)
wire y : { boop: { foo: { a: UInt<1>, b: UInt<2>}, bar: { a: UInt<1> }}} ; (no locator)
; invalidate all but .boop.foo.a

5
test/firtool/lower-memories.fir
View File

@ -1,8 +1,9 @@
; RUN: firtool %s --format=fir | FileCheck %s --check-prefixes COMMON,NOLOWER
; RUN: firtool %s --format=fir -lower-memories | FileCheck %s --check-prefixes COMMON,LOWER
FIRRTL version 4.0.0
circuit ByteEnableMemory:
module ByteEnableMemory :
public module ByteEnableMemory :
input clock : Clock
input reset : UInt<1>
output io : { flip readAddr : UInt<16>, dataOut : UInt<8>[2], flip readEnable : UInt<1>, flip dataIn : UInt<8>[2], flip writeAddr : UInt<16>, flip writeMask : UInt<1>[2]}
@ -18,7 +19,7 @@ circuit ByteEnableMemory:
_WIRE is invalid
when io.readEnable :
_WIRE <= io.readAddr
node _T_1 = or(_WIRE, UInt<1>("h0"))
node _T_1 = or(_WIRE, UInt<1>(0h0))
node _T_2 = bits(_T_1, 0, 0)
read mport MPORT_1 = mem[_T_2], clock
io.dataOut <= MPORT_1

3
test/firtool/memory.fir
View File

@ -4,6 +4,7 @@
; RUN: firtool %s --format=fir --ir-sv -disable-mem-randomization --disable-reg-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM --implicit-check-not RANDOMIZE_REG
; RUN: firtool %s --format=fir --ir-sv -disable-all-randomization | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM --implicit-check-not RANDOMIZE_REG
FIRRTL version 4.0.0
circuit Qux: %[[{
"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
"target":"~Qux|Qux"
@ -11,7 +12,7 @@ circuit Qux: %[[{
{
"class": "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"
}]]
module Qux:
public module Qux:
input clock: Clock
input rAddr: UInt<2>
input rEn: UInt<1>

3
test/firtool/memoryLowering.fir
View File

@ -1,7 +1,8 @@
; RUN: firtool %s --annotation-file %s.anno.json -repl-seq-mem -repl-seq-mem-file="test.conf" | FileCheck %s
FIRRTL version 4.0.0
circuit test:
module test:
public module test:
input clock: Clock
input rAddr: UInt<4>
input rEn: UInt<1>

3
test/firtool/memoryMetadata.fir
View File

@ -1,6 +1,7 @@
; RUN: firtool %s --annotation-file %s.anno.json --repl-seq-mem --repl-seq-mem-file="dutModule.conf" | FileCheck %s
FIRRTL version 4.0.0
circuit test:
module tbMemModule1:
input clock: Clock
@ -111,7 +112,7 @@ circuit test:
m.wMask <= wMask
m.wData <= wData
module test:
public module test:
input clock: Clock
input rAddr: UInt<4>
input rEn: UInt<1>

3
test/firtool/memoryMetadataRenameFail.fir
View File

@ -1,6 +1,7 @@
; RUN: firtool %s --format=fir --annotation-file %s.anno.json --verilog | FileCheck %s
; XFAIL: true
FIRRTL version 4.0.0
circuit test:
module memoryTest1:
input clock: Clock
@ -63,7 +64,7 @@ circuit test:
memory.w.data <= wData
module test:
public module test:
input clock: Clock
input rAddr: UInt<4>
input rEn: UInt<1>

3
test/firtool/module-hier.fir
View File

@ -4,6 +4,7 @@
; HWExportModuleHierarchy pass and any renaming which may happen in the circuit.
;
; See: https://github.com/llvm/circt/issues/5478
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class": "sifive.enterprise.firrtl.ModuleHierarchyAnnotation",
@ -37,7 +38,7 @@ circuit Foo: %[[
a is invalid
module Bar:
inst baz of Baz
module Foo:
public module Foo:
inst bar of Bar
; CHECK-LABEL: module Baz()

3
test/firtool/name-preservation.fir
View File

@ -1,8 +1,9 @@
; RUN: firtool --preserve-values=named %s | FileCheck %s
FIRRTL version 4.0.0
circuit Foo:
; CHECK-LABEL: module Foo
module Foo:
public module Foo:
input a: {a: UInt<1>, flip b: UInt<1>}
output b: {a: UInt<1>, flip b: UInt<1>}

3
test/firtool/optimizations.fir
View File

@ -1,8 +1,9 @@
; RUN: firtool %s --format=fir --ir-fir | circt-opt | FileCheck %s --check-prefix=OPT
; RUN: firtool %s --format=fir --ir-fir -disable-opt | circt-opt | FileCheck %s --check-prefix=NOOPT
FIRRTL version 4.0.0
circuit test_cse :
module test_cse :
public module test_cse :
input a1: UInt<4>
input a2: UInt<4>
output b: UInt<5>

3
test/firtool/phase-ordering.fir
View File

@ -9,6 +9,7 @@
; CHECK: firrtl.mux(%[[v14:.+]], %wData_0, %[[memory_0]])
; CHECK: firrtl.mux(%[[v19:.+]], %wData_1, %[[v5:.+]])
; CHECK: firrtl.matchingconnect %[[memory_0]], %[[v22:.+]]
FIRRTL version 4.0.0
circuit Issue794: %[[{
"class": "sifive.enterprise.firrtl.MarkDUTAnnotation",
"target":"~Issue794|Issue794"
@ -16,7 +17,7 @@ circuit Issue794: %[[{
{
"class": "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"
}]]
module Issue794:
public module Issue794:
input clock: Clock
input rAddr: UInt<2>
input rEn: UInt<1>

23
test/firtool/prefixMemory.fir
View File

@ -3,6 +3,7 @@
; RUN: firtool --no-dedup %s --repl-seq-mem --repl-seq-mem-file=test.txt --ir-fir | FileCheck %s --check-prefix=REPL-FIR --check-prefix=CHECK-FIR
; RUN: firtool --no-dedup %s --repl-seq-mem --repl-seq-mem-file=test.txt --ir-sv | FileCheck %s --check-prefix=REPL-HW --check-prefix=CHECK-HW
FIRRTL version 4.0.0
circuit Foo : %[[
{
"class":"sifive.enterprise.firrtl.NestedPrefixModulesAnnotation",
@ -51,10 +52,10 @@ circuit Foo : %[[
writer => MPORT
mem.readData_MPORT.addr is invalid
mem.readData_MPORT.clk is invalid
mem.readData_MPORT.en <= UInt<1>("h0")
mem.readData_MPORT.en <= UInt<1>(0h0)
mem.MPORT.addr is invalid
mem.MPORT.clk is invalid
mem.MPORT.en <= UInt<1>("h0")
mem.MPORT.en <= UInt<1>(0h0)
mem.MPORT.data is invalid
mem.MPORT.mask is invalid
mem.readData_MPORT.addr <= readAddr
@ -63,10 +64,10 @@ circuit Foo : %[[
when writeEn :
mem.MPORT.addr <= writeAddr
mem.MPORT.clk <= clock
mem.MPORT.en <= UInt<1>("h1")
mem.MPORT.mask <= UInt<1>("h0")
mem.MPORT.en <= UInt<1>(0h1)
mem.MPORT.mask <= UInt<1>(0h0)
mem.MPORT.data <= writeData
mem.MPORT.mask <= UInt<1>("h1")
mem.MPORT.mask <= UInt<1>(0h1)
; CHECK-FIR-LABEL: firrtl.module private @prefix2_Baz
; CHECK-HW-LABEL: hw.module private @prefix2_Baz
@ -94,10 +95,10 @@ circuit Foo : %[[
writer => MPORT
mem.readData_MPORT.addr is invalid
mem.readData_MPORT.clk is invalid
mem.readData_MPORT.en <= UInt<1>("h0")
mem.readData_MPORT.en <= UInt<1>(0h0)
mem.MPORT.addr is invalid
mem.MPORT.clk is invalid
mem.MPORT.en <= UInt<1>("h0")
mem.MPORT.en <= UInt<1>(0h0)
mem.MPORT.data is invalid
mem.MPORT.mask is invalid
mem.readData_MPORT.addr <= readAddr
@ -106,12 +107,12 @@ circuit Foo : %[[
when writeEn :
mem.MPORT.addr <= writeAddr
mem.MPORT.clk <= clock
mem.MPORT.en <= UInt<1>("h1")
mem.MPORT.mask <= UInt<1>("h0")
mem.MPORT.en <= UInt<1>(0h1)
mem.MPORT.mask <= UInt<1>(0h0)
mem.MPORT.data <= writeData
mem.MPORT.mask <= UInt<1>("h1")
mem.MPORT.mask <= UInt<1>(0h1)
module Foo :
public module Foo :
input clock : Clock
input reset : UInt<1>
input readAddr : UInt<3>

3
test/firtool/print-before.fir
View File

@ -10,5 +10,6 @@
; RUN: firtool %s -mlir-print-ir-before=lower-firrtl-to-hw 2>&1 | FileCheck %s -Dpass=LowerFIRRTLToHW
; RUN: firtool %s -mlir-print-ir-before=prepare-for-emission 2>&1 | FileCheck %s -Dpass=PrepareForEmission
; CHECK: IR Dump Before [[pass]]
FIRRTL version 4.0.0
circuit Empty:
module Empty:
public module Empty:

5
test/firtool/print.fir
View File

@ -1,8 +1,9 @@
; RUN: firtool %s --format=fir --ir-sv | FileCheck %s
FIRRTL version 4.0.0
circuit PrintTest:
; CHECK-LABEL: @PrintTest
module PrintTest :
public module PrintTest :
input clock : Clock
input cond : UInt<1>
input var : UInt<32>
@ -17,4 +18,4 @@ circuit PrintTest:
; CHECK-NEXT: sv.fwrite %c-2147483646_i32, "test %d\0A"(%var) : i32
; CHECK-NEXT: }
; CHECK-NEXT: }
; CHECK-NEXT: }
; CHECK-NEXT: }

3
test/firtool/refs-in-aggs.fir
View File

@ -6,6 +6,7 @@
; RUN: circt-translate -import-firrtl -verify-diagnostics -split-input-file %s | circt-opt | FileCheck %s
; CHECK-LABEL: circuit "Bundle"
FIRRTL version 4.0.0
circuit Bundle :
; CHECK-LABEL: module private @Child
; CHECK-SAME: in %in: !firrtl.bundle
@ -54,7 +55,7 @@ circuit Bundle :
; CHECK-LABEL: module @Bundle
; CHECK: opensubfield
; CHECK: opensubindex
module Bundle:
public module Bundle:
input in : {a : UInt<1>, b : UInt<1>[2]}
output out1 : {a : UInt<1>, b : UInt<1>[2]}
output out2 : {a : UInt<1>, b : UInt<1>[2]}

3
test/firtool/register-optimization.fir
View File

@ -5,6 +5,7 @@
; CHECK-LABEL: module Example
; CHECK: assign out = 1'h0;
FIRRTL version 4.0.0
circuit Example :
module Passthrough:
input en: UInt<1>
@ -24,7 +25,7 @@ circuit Example :
p.en <= b
out <= p.out
module Example:
public module Example:
input clock: Clock
input unknown: UInt<1>
output out: UInt<1>

3
test/firtool/register-randomization.fir
View File

@ -3,8 +3,9 @@
; RUN: firtool -preserve-values=none -verilog %s | FileCheck %s --check-prefix=NONE
; RUN: firtool -preserve-values=all -verilog %s --lowering-options=disallowLocalVariables| FileCheck %s --check-prefix=LOCAL
FIRRTL version 4.0.0
circuit Foo:
module Foo:
public module Foo:
input clock: Clock
input d: UInt<33>
input d0: UInt<60000>

1
test/firtool/spec/refs/ext.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool %s
; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
FIRRTL version 3.0.0
circuit MyExternalModuleWithRefs :
; SPEC EXAMPLE BEGIN
extmodule MyExternalModuleWithRefs :

5
test/firtool/spec/refs/forwarding_refs_upwards.fir
View File

@ -1,13 +1,14 @@
; RUN: firtool %s
; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
FIRRTL version 4.0.0
circuit Forward:
; SPEC EXAMPLE BEGIN
extmodule Foo : ; XXX: module -> extmodule
output p : Probe<UInt<3>> ; XXX: added width
; ...
module Forward :
output p : Probe<UInt>
public module Forward :
output p : Probe<UInt<3>>
inst f of Foo
define p = f.p

5
test/firtool/spec/refs/forwarding_refs_upwards_narrow.fir
View File

@ -1,13 +1,14 @@
; RUN: firtool %s
; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
FIRRTL version 4.0.0
circuit Forward :
; SPEC EXAMPLE BEGIN
extmodule Foo :
output p : Probe<UInt<3>[2]>[2]
; ...
module Forward :
output p : Probe<UInt>
public module Forward :
output p : Probe<UInt<3>>
inst f of Foo
define p = f.p[0][1]

5
test/firtool/spec/refs/nosubaccess.fir
View File

@ -1,15 +1,16 @@
; RUN: firtool %s
; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
FIRRTL version 4.0.0
circuit NoSubAccessesWithProbes :
extmodule Ext :
output x : {a : Probe<UInt<2>[2]>, b : UInt<2>}[3]
; XXX: Modified to not use input probes, get probe from ext, widths.
; SPEC EXAMPLE BEGIN:
module NoSubAccessesWithProbes :
public module NoSubAccessesWithProbes :
input i : UInt<5>
input c : const UInt<5>
output p : Probe<UInt>
output p : Probe<UInt<2>>
inst e of Ext

5
test/firtool/spec/refs/probe_export_simple.fir
View File

@ -1,10 +1,11 @@
; RUN: firtool %s
; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
FIRRTL version 4.0.0
circuit MyModule :
; SPEC EXAMPLE BEGIN
module MyModule :
public module MyModule :
input in: UInt<5> ; XXX: Added width.
output r : Probe<UInt>
output r : Probe<UInt<5>>
define r = probe(in)
; SPEC EXAMPLE END

3
test/firtool/stop.fir
View File

@ -9,8 +9,9 @@
; CHECK: }
; CHECK: }
FIRRTL version 4.0.0
circuit StopAndFinishTest:
module StopAndFinishTest :
public module StopAndFinishTest :
input clock : Clock
input cond : UInt<1>

3
test/firtool/style.fir
View File

@ -2,8 +2,9 @@
; RUN: not firtool --ir-fir --lowering-options=bad-option %s 2>&1 | FileCheck %s --check-prefix=BADOPTION
; RUN: firtool --ir-fir --lowering-options=noAlwaysComb %s | FileCheck %s --check-prefix=OPTIONS
FIRRTL version 4.0.0
circuit test :
module test :
public module test :
; DEFAULT: module {
; BADOPTION: lowering-options option: unknown style option 'bad-option'

3
test/firtool/sv-attr.fir
View File

@ -1,5 +1,6 @@
; RUN: firtool %s | FileCheck %s
FIRRTL version 4.0.0
circuit Foo: %[[{"class": "firrtl.AttributeAnnotation",
"description": "keep_hierarchy = \"true\"",
"target": "~Foo|Foo"},
@ -18,7 +19,7 @@ circuit Foo: %[[{"class": "firrtl.AttributeAnnotation",
"target": "~Foo|Foo>r"}]]
; CHECK: (* keep_hierarchy = "true" *)
; CHECK-NEXT: module Foo
module Foo:
public module Foo:
input a: UInt<1>
input clock: Clock
output b1: UInt<1>

3
test/firtool/verbose-pass-executions.fir
View File

@ -2,5 +2,6 @@
;
; CHECK: [firtool] Running
FIRRTL version 4.0.0
circuit Empty:
module Empty:
public module Empty: