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[FVInt] Fix printing when bit width is less than one full digit 

Printing of `FVInt`s would continuously shift the value right by the
log2 of the radix. This triggers an assertion in `APInt` in the case
where the bit width is less than the number of bits being shifted.
This commit is contained in:
Fabian Schuiki 2024-08-07 17:22:34 -07:00
parent fcdefe5a1a
commit aae791b1e9
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GPG Key ID: C42F5825FC5275E6
2 changed files with 6 additions and 2 deletions
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5
lib/Support/FVInt.cpp
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@ -102,8 +102,9 @@ bool FVInt::tryToString(SmallVectorImpl<char> &str, unsigned radix,
while (!value.isZero() || !unknown.isZero()) {
unsigned digitValue = value.getRawData()[0] & radixMask;
unsigned digitUnknown = unknown.getRawData()[0] & radixMask;
value.lshrInPlace(radixLog2);
unknown.lshrInPlace(radixLog2);
unsigned shiftAmount = std::min(radixLog2, getBitWidth());
value.lshrInPlace(shiftAmount);
unknown.lshrInPlace(shiftAmount);
// Handle unknown bits. Since we only get to print a single X or Z character
// to the string, either all bits in the digit have to be X, or all have to

3
unittests/Support/FVIntTest.cpp
View File

@ -94,6 +94,9 @@ TEST(FVIntTest, StringConversion) {
StringRef("12345XZ67890ABCDEF"));
ASSERT_EQ(FVInt::fromString("12345xz67890abcdef", 16).toString(16, false),
StringRef("12345xz67890abcdef"));
// Narrow <4 bit integers printed as hex.
ASSERT_EQ(FVInt::fromString("10", 2).toString(16), StringRef("2"));
}
TEST(FVIntTest, LogicOps) {