[ImportVerilog] Add debug info switch

Add an option to ImportVerilog to enable debug info generation. If set,
the Verilog importer should generate additional `dbg.*` ops in the IR to
track variables and constants defined by the user in the Verilog source
text. No such ops are generated yet.

Also add a corresponding `-g` option to `circt-verilog`.

include/circt/Conversion/ImportVerilog.h

@@ -46,6 +46,9 @@ struct ImportVerilogOptions {
   };
   Mode mode = Mode::Full;
 
+  /// Generate debug information in the form of debug dialect ops in the IR.
+  bool debugInfo = false;
+
   //===--------------------------------------------------------------------===//
   // Include paths
   //===--------------------------------------------------------------------===//

lib/Conversion/ImportVerilog/ImportVerilog.cpp

@@ -267,7 +267,8 @@ LogicalResult ImportDriver::importVerilog(ModuleOp module) {
   mlirContext->loadDialect<moore::MooreDialect, hw::HWDialect,
                            cf::ControlFlowDialect, func::FuncDialect>();
   auto conversionTimer = ts.nest("Verilog to dialect mapping");
-  Context context(*compilation, module, driver.sourceManager, bufferFilePaths);
+  Context context(options, *compilation, module, driver.sourceManager,
+                  bufferFilePaths);
   if (failed(context.convertCompilation()))
     return failure();
   conversionTimer.stop();

lib/Conversion/ImportVerilog/ImportVerilogInternals.h

@@ -61,10 +61,11 @@ struct LoopFrame {
 /// operations. Keeps track of the destination MLIR module, builders, and
 /// various worklists and utilities needed for conversion.
 struct Context {
-  Context(slang::ast::Compilation &compilation, mlir::ModuleOp intoModuleOp,
+  Context(const ImportVerilogOptions &options,
+          slang::ast::Compilation &compilation, mlir::ModuleOp intoModuleOp,
           const slang::SourceManager &sourceManager,
           SmallDenseMap<slang::BufferID, StringRef> &bufferFilePaths)
-      : compilation(compilation), intoModuleOp(intoModuleOp),
+      : options(options), compilation(compilation), intoModuleOp(intoModuleOp),
         sourceManager(sourceManager), bufferFilePaths(bufferFilePaths),
         builder(OpBuilder::atBlockEnd(intoModuleOp.getBody())),
         symbolTable(intoModuleOp) {}
@@ -123,6 +124,7 @@ struct Context {
   Value materializeConstant(const slang::ConstantValue &constant,
                             const slang::ast::Type &type, Location loc);
 
+  const ImportVerilogOptions &options;
   slang::ast::Compilation &compilation;
   mlir::ModuleOp intoModuleOp;
   const slang::SourceManager &sourceManager;

tools/circt-verilog/circt-verilog.cpp

@@ -81,6 +81,9 @@ struct CLOptions {
                      "core dialect IR")),
       cl::init(LoweringMode::Full), cl::cat(cat)};
 
+  cl::opt<bool> debugInfo{"g", cl::desc("Generate debug information"),
+                          cl::cat(cat)};
+
   //===--------------------------------------------------------------------===//
   // Include paths
   //===--------------------------------------------------------------------===//
@@ -293,6 +296,7 @@ static LogicalResult executeWithSources(MLIRContext *context,
     options.mode = ImportVerilogOptions::Mode::OnlyLint;
   else if (opts.loweringMode == LoweringMode::OnlyParse)
     options.mode = ImportVerilogOptions::Mode::OnlyParse;
+  options.debugInfo = opts.debugInfo;
 
   options.includeDirs = opts.includeDirs;
   options.includeSystemDirs = opts.includeSystemDirs;