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[FIRRTL] Make FModuleLike op interface friendly with properties

This commit is contained in:
Andrew Young 2024-10-25 14:16:13 -07:00
parent 70df0eced7
commit 542d7e5f37
17 changed files with 93 additions and 196 deletions
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168
include/circt/Dialect/FIRRTL/FIRRTLOpInterfaces.td
View File

@ -25,9 +25,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
// Parameters
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the parameters",
"ArrayAttr", "getParameters", (ins),
/*methodBody=*/[{ return $_op.getParameters(); }]>,
InterfaceMethod<"Get the parameters", "ArrayAttr", "getParameters">,
//===------------------------------------------------------------------===//
// Instantiation Convention
@ -54,17 +52,10 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the port directions attribute",
"mlir::DenseBoolArrayAttr", "getPortDirectionsAttr", (ins), [{}],
/*defaultImplementation=*/[{
return $_op->template
getAttrOfType<mlir::DenseBoolArrayAttr>(FModuleLike::getPortDirectionsAttrName());
}]>,
"mlir::DenseBoolArrayAttr", "getPortDirectionsAttr">,
InterfaceMethod<"Get the port directions",
"ArrayRef<bool>", "getPortDirections", (ins), [{}],
/*defaultImplementation=*/[{
return $_op.getPortDirectionsAttr().getValue();
}]>,
"ArrayRef<bool>", "getPortDirections">,
InterfaceMethod<"Get a port direction",
"Direction", "getPortDirection", (ins "size_t":$portIndex), [{}],
@ -77,17 +68,10 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the port names attribute",
"ArrayAttr", "getPortNamesAttr", (ins), [{}],
/*defaultImplementation=*/[{
return $_op->template
getAttrOfType<ArrayAttr>(FModuleLike::getPortNamesAttrName());
}]>,
"ArrayAttr", "getPortNamesAttr">,
InterfaceMethod<"Get the port names",
"ArrayRef<Attribute>", "getPortNames", (ins), [{}],
/*defaultImplementation=*/[{
return $_op.getPortNamesAttr().getValue();
}]>,
"ArrayRef<Attribute>", "getPortNames">,
InterfaceMethod<"Get a port name",
"StringAttr", "getPortNameAttr", (ins "size_t":$portIndex), [{}],
@ -106,17 +90,13 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the port types attribute",
"ArrayAttr", "getPortTypesAttr", (ins), [{}],
/*defaultImplementation=*/[{
return $_op->template
getAttrOfType<ArrayAttr>(FModuleLike::getPortTypesAttrName());
}]>,
"ArrayAttr", "getPortTypesAttr">,
InterfaceMethod<"Get the port types",
"ArrayRef<Attribute>", "getPortTypes", (ins), [{}],
/*defaultImplementation=*/[{
return $_op.getPortTypesAttr().getValue();
}]>,
"ArrayRef<Attribute>", "getPortTypes">,
InterfaceMethod<"Set the types of all ports", "void",
"setPortTypesAttr", (ins "::mlir::ArrayAttr":$portTypes)>,
InterfaceMethod<"Get a port type",
"TypeAttr", "getPortTypeAttr", (ins "size_t":$portIndex), [{}],
@ -127,8 +107,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
InterfaceMethod<"Get a port type",
"Type", "getPortType", (ins "size_t":$portIndex), [{}],
/*defaultImplementation=*/[{
auto typeAttr = $_op.getPortTypeAttr(portIndex);
return typeAttr.getValue();
return $_op.getPortTypeAttr(portIndex).getValue();
}]>,
//===------------------------------------------------------------------===//
@ -136,23 +115,13 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the port annotations attribute",
"ArrayAttr", "getPortAnnotationsAttr", (ins), [{}],
/*defaultImplementation=*/[{
return $_op->template
getAttrOfType<ArrayAttr>(FModuleLike::getPortAnnotationsAttrName());
}]>,
"ArrayAttr", "getPortAnnotationsAttr">,
InterfaceMethod<"Get the port annotations attribute",
"ArrayRef<Attribute>", "getPortAnnotations">,
InterfaceMethod<"Set the port annotations attribute",
"void", "setPortAnnotationsAttr", (ins "ArrayAttr":$annotations), [{}],
/*defaultImplementation=*/[{
return $_op->setAttr(FModuleLike::getPortAnnotationsAttrName(), annotations);
}]>,
"void", "setPortAnnotationsAttr", (ins "::mlir::ArrayAttr":$annotations)>,
InterfaceMethod<"Get the port annotations attribute",
"ArrayRef<Attribute>", "getPortAnnotations", (ins), [{}],
/*defaultImplementation=*/[{
return $_op.getPortAnnotationsAttr().getValue();
}]>,
InterfaceMethod<"Get a port's annotations attribute",
"ArrayAttr", "getAnnotationsAttrForPort", (ins "size_t":$portIndex), [{}],
@ -174,32 +143,16 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
// Port Symbols
//===------------------------------------------------------------------===//
// Symbol conventions:
// 1. Every element of the ArrayAttr(portSyms) must be NON-NULL.
// 1. Every element of the ArrayAttr(portSymbols) must be NON-NULL.
// 2. An empty array represents no symbol.
// a. TODO: Update the representation to avoid storing it.
// 3. The Getters return null if a port sym is invalid.
// 4. The fixupPortSymsArray, is a utility to update a portSyms
// Vector, by replacing each null entry with empty array and
// clearing the array if all the elements are empty.
// Getters
InterfaceMethod<"Get the port symbols attribute",
"ArrayAttr", "getPortSymbolsAttr", (ins), [{}], [{
return $_op->template
getAttrOfType<ArrayAttr>(FModuleLike::getPortSymbolsAttrName());
}]>,
"ArrayAttr", "getPortSymbolsAttr">,
InterfaceMethod<"Get the port symbols",
"ArrayRef<Attribute>", "getPortSymbols", (ins), [{}], [{
return $_op.getPortSymbolsAttr().getValue();
}]>,
InterfaceMethod<"Check if port has symbol attribute",
"bool", "hasPortSymbolAttr", (ins "size_t":$portIndex), [{}], [{
auto syms = $_op.getPortSymbols();
return (!syms.empty() &&
!llvm::cast<hw::InnerSymAttr>(syms[portIndex]).empty());
}]>,
"ArrayRef<Attribute>", "getPortSymbols">,
InterfaceMethod<"Get the port symbol attribute",
"circt::hw::InnerSymAttr", "getPortSymbolAttr", (ins "size_t":$portIndex), [{}], [{
@ -212,35 +165,13 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
// Setters
InterfaceMethod<"Set the symbols of all ports and their fields", "void",
"setPortSymbols", (ins "ArrayRef<Attribute>":$symbols), [{}], [{
assert(symbols.empty() || symbols.size() == $_op.getNumPorts());
SmallVector<Attribute> newSyms(symbols.begin(), symbols.end());
FModuleLike::fixupPortSymsArray(newSyms, $_op.getContext());
assert(newSyms.empty() || newSyms.size() == $_op.getNumPorts());
$_op->setAttr(FModuleLike::getPortSymbolsAttrName(),
ArrayAttr::get($_op.getContext(), newSyms));
}]>,
"setPortSymbolsAttr", (ins "::mlir::ArrayAttr":$symbols)>,
InterfaceMethod<"Set a port's top-level symbol to the specified string, dropping any symbols on its fields", "void",
"setPortSymbolAttr", (ins "size_t":$portIndex, "StringAttr":$symbol), [{}],
[{
SmallVector<Attribute> symbols($_op.getPortSymbols().begin(),
$_op.getPortSymbols().end());
if (symbols.empty()) {
symbols.resize($_op.getNumPorts(),
hw::InnerSymAttr::get($_op.getContext()));
}
assert(symbols.size() == $_op.getNumPorts());
symbols[portIndex] = hw::InnerSymAttr::get(symbol);
FModuleLike::fixupPortSymsArray(symbols, $_op.getContext());
assert(symbols.empty() || symbols.size() == $_op.getNumPorts());
$_op->setAttr(FModuleLike::getPortSymbolsAttrName(),
ArrayAttr::get($_op.getContext(), symbols));
}]>,
InterfaceMethod<"Set the symbols of all ports and their fields", "void",
"setPortSymbols", (ins "::llvm::ArrayRef<Attribute>":$symbols)>,
InterfaceMethod<"Set the symbols for a port including its fields", "void",
"setPortSymbolsAttr", (ins "size_t":$portIndex, "circt::hw::InnerSymAttr":$symbol), [{}],
"setPortSymbolAttr", (ins "size_t":$portIndex, "circt::hw::InnerSymAttr":$symbol), [{}],
[{
SmallVector<Attribute> symbols($_op.getPortSymbols().begin(),
$_op.getPortSymbols().end());
@ -255,14 +186,7 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
FModuleLike::fixupPortSymsArray(symbols, $_op.getContext());
assert(symbols.empty() || symbols.size() == $_op.getNumPorts());
$_op->setAttr(FModuleLike::getPortSymbolsAttrName(),
ArrayAttr::get($_op.getContext(), symbols));
}]>,
InterfaceMethod<"Set a port's top-level symbol to the specified string, dropping any symbols on its fields", "void",
"setPortSymbol", (ins "size_t":$portIndex, "StringRef":$symbol), [{}], [{
$_op.setPortSymbolAttr(portIndex, StringAttr::get($_op.getContext(),
symbol));
$_op.setPortSymbolsAttr(ArrayAttr::get($_op.getContext(), symbols));
}]>,
//===------------------------------------------------------------------===//
@ -270,17 +194,10 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
//===------------------------------------------------------------------===//
InterfaceMethod<"Get the port locations attribute",
"ArrayAttr", "getPortLocationsAttr", (ins), [{}],
/*defaultImplementation=*/[{
return $_op->template
getAttrOfType<ArrayAttr>(FModuleLike::getPortLocationsAttrName());
}]>,
"ArrayAttr", "getPortLocationsAttr">,
InterfaceMethod<"Get the port locations attribute",
"ArrayRef<Attribute>", "getPortLocations", (ins), [{}],
/*defaultImplementation=*/[{
return $_op.getPortLocationsAttr().getValue();
}]>,
"ArrayRef<Attribute>", "getPortLocations">,
InterfaceMethod<"Get a port's location attribute",
"LocationAttr", "getPortLocationAttr", (ins "size_t":$portIndex), [{}],
@ -311,41 +228,12 @@ def FModuleLike : OpInterface<"FModuleLike", [Symbol, PortList, InstanceGraphMod
];
let extraClassDeclaration = [{
/// Get the attribute name for port directions.
static StringRef getPortDirectionsAttrName() {
return "portDirections";
}
/// Get the attribute name for port names",
static StringRef getPortNamesAttrName() {
return "portNames";
}
/// Get the attribute name for port types.
static StringRef getPortTypesAttrName() {
return "portTypes";
}
/// Get the attribute name for port annotations.
static StringRef getPortAnnotationsAttrName() {
return "portAnnotations";
}
/// Get the attribute name for port symbols.
static StringRef getPortSymbolsAttrName() {
return "portSyms";
}
/// Get the attribute name for port locations.
static StringRef getPortLocationsAttrName() {
return "portLocations";
}
/// Replace NULL entries with invalid sym and clear array if all elements
/// are invalid.
/// Replace NULL entries with an empty InnerSymbol. If all elements of the
/// array are empty, then it will clear the array.
static void fixupPortSymsArray(SmallVectorImpl<Attribute> &syms,
MLIRContext *context) {
// The lack of *any* port symbol is represented by an empty `portSyms`
// The lack of *any* port symbol is represented by an empty `portSymbols`
// array as a shorthand.
if (llvm::none_of(syms, [&](auto &sym) {
return sym && !cast<hw::InnerSymAttr>(sym).empty();

16
include/circt/Dialect/FIRRTL/FIRRTLStructure.td
View File

@ -138,7 +138,7 @@ def FModuleOp : FIRRTLModuleLike<"module", [SingleBlock, NoTerminator]> {
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portLocations,
ArrayRefAttr:$portAnnotations,
ArrayRefAttr:$portSyms,
ArrayRefAttr:$portSymbols,
ArrayRefAttr:$portNames,
ArrayRefAttr:$portTypes,
DefaultValuedAttr<AnnotationArrayAttr, "{}">:$annotations,
@ -180,7 +180,6 @@ def FModuleOp : FIRRTLModuleLike<"module", [SingleBlock, NoTerminator]> {
void getAsmBlockArgumentNames(mlir::Region &region,
mlir::OpAsmSetValueNameFn setNameFn);
ArrayAttr getParameters();
}];
}
@ -203,7 +202,7 @@ def FExtModuleOp : FIRRTLModuleLike<"extmodule"> {
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portLocations,
ArrayRefAttr:$portAnnotations,
ArrayRefAttr:$portSyms,
ArrayRefAttr:$portSymbols,
ArrayRefAttr:$portNames,
ArrayRefAttr:$portTypes,
DefaultValuedAttr<AnnotationArrayAttr, "{}">:$annotations,
@ -245,7 +244,7 @@ def FIntModuleOp : FIRRTLModuleLike<"intmodule"> {
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portLocations,
ArrayRefAttr:$portAnnotations,
ArrayRefAttr:$portSyms,
ArrayRefAttr:$portSymbols,
ArrayRefAttr:$portNames,
ArrayRefAttr:$portTypes,
DefaultValuedAttr<AnnotationArrayAttr, "ArrayAttr()">:$annotations,
@ -293,7 +292,7 @@ def FMemModuleOp : FIRRTLModuleLike<"memmodule"> {
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portLocations,
ArrayRefAttr:$portAnnotations,
ArrayRefAttr:$portSyms,
ArrayRefAttr:$portSymbols,
ArrayRefAttr:$portNames,
ArrayRefAttr:$portTypes,
AnnotationArrayAttr:$annotations,
@ -319,7 +318,6 @@ def FMemModuleOp : FIRRTLModuleLike<"memmodule"> {
bool isMasked() { return getMaskBits() > 1; }
void getAsmBlockArgumentNames(mlir::Region &region,
mlir::OpAsmSetValueNameFn setNameFn);
ArrayAttr getParameters();
}];
let hasCustomAssemblyFormat = 1;
@ -346,7 +344,7 @@ def ClassOp : FIRRTLModuleLike<"class", [
let arguments = (ins SymbolNameAttr:$sym_name,
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portNames, ArrayRefAttr:$portTypes,
ArrayRefAttr:$portSyms, ArrayRefAttr:$portLocations);
ArrayRefAttr:$portSymbols, ArrayRefAttr:$portLocations);
let results = (outs);
let regions = (region SizedRegion<1>:$body);
@ -392,7 +390,6 @@ def ClassOp : FIRRTLModuleLike<"class", [
void getAsmBlockArgumentNames(mlir::Region &region,
mlir::OpAsmSetValueNameFn setNameFn);
ArrayAttr getParameters();
}];
}
@ -419,7 +416,7 @@ def ExtClassOp : FIRRTLModuleLike<"extclass", [
let arguments = (ins SymbolNameAttr:$sym_name,
DenseBoolArrayAttr:$portDirections,
ArrayRefAttr:$portNames, ArrayRefAttr:$portTypes,
ArrayRefAttr:$portSyms, ArrayRefAttr:$portLocations);
ArrayRefAttr:$portSymbols, ArrayRefAttr:$portLocations);
let results = (outs);
let regions = (region AnyRegion:$body);
let skipDefaultBuilders = 1;
@ -433,7 +430,6 @@ def ExtClassOp : FIRRTLModuleLike<"extclass", [
void getAsmBlockArgumentNames(mlir::Region &region,
mlir::OpAsmSetValueNameFn setNameFn);
ArrayAttr getParameters();
}];
let hasCustomAssemblyFormat = 1;
}

2
lib/Conversion/FIRRTLToHW/LowerToHW.cpp
View File

@ -1098,7 +1098,7 @@ FIRRTLModuleLowering::lowerModule(FModuleOp oldModule, Block *topLevelModule,
SmallVector<StringRef, 12> attrNames = {
"annotations", "convention", "layers",
"portNames", "sym_name", "portDirections",
"portTypes", "portAnnotations", "portSyms",
"portTypes", "portAnnotations", "portSymbols",
"portLocations", "parameters", SymbolTable::getVisibilityAttrName()};
DenseSet<StringRef> attrSet(attrNames.begin(), attrNames.end());

33
lib/Dialect/FIRRTL/FIRRTLOps.cpp
View File

@ -847,6 +847,7 @@ static void insertPorts(FModuleLike op,
op->setAttr("portNames", ArrayAttr::get(op.getContext(), newNames));
op->setAttr("portTypes", ArrayAttr::get(op.getContext(), newTypes));
op->setAttr("portAnnotations", ArrayAttr::get(op.getContext(), newAnnos));
FModuleLike::fixupPortSymsArray(newSyms, op.getContext());
op.setPortSymbols(newSyms);
op->setAttr("portLocations", ArrayAttr::get(op.getContext(), newLocs));
if (supportsInternalPaths) {
@ -898,7 +899,7 @@ static void erasePorts(FModuleLike op, const llvm::BitVector &portIndices) {
op->setAttr("portAnnotations", ArrayAttr::get(op.getContext(), newPortAnnos));
op->setAttr("portTypes", ArrayAttr::get(op.getContext(), newPortTypes));
FModuleLike::fixupPortSymsArray(newPortSyms, op.getContext());
op->setAttr("portSyms", ArrayAttr::get(op.getContext(), newPortSyms));
op->setAttr("portSymbols", ArrayAttr::get(op.getContext(), newPortSyms));
op->setAttr("portLocations", ArrayAttr::get(op.getContext(), newPortLocs));
}
@ -1011,7 +1012,7 @@ static void buildModuleLike(OpBuilder &builder, OperationState &result,
direction::packAttribute(builder.getContext(), portDirections));
result.addAttribute("portNames", builder.getArrayAttr(portNames));
result.addAttribute("portTypes", builder.getArrayAttr(portTypes));
result.addAttribute("portSyms", builder.getArrayAttr(portSyms));
result.addAttribute("portSymbols", builder.getArrayAttr(portSyms));
result.addAttribute("portLocations", builder.getArrayAttr(portLocs));
if (withAnnotations) {
@ -1347,8 +1348,8 @@ static void printFModuleLikeOp(OpAsmPrinter &p, FModuleLike op) {
op.getPortAnnotations(), op.getPortSymbols(), op.getPortLocations());
SmallVector<StringRef, 12> omittedAttrs = {
"sym_name", "portDirections", "portTypes", "portAnnotations",
"portSyms", "portLocations", "parameters", visibilityAttrName};
"sym_name", "portDirections", "portTypes", "portAnnotations",
"portSymbols", "portLocations", "parameters", visibilityAttrName};
if (op.getConvention() == Convention::Internal)
omittedAttrs.push_back("convention");
@ -1500,9 +1501,9 @@ static ParseResult parseFModuleLikeOp(OpAsmParser &parser,
}
// Add port symbols.
if (!result.attributes.get("portSyms")) {
if (!result.attributes.get("portSymbols")) {
FModuleLike::fixupPortSymsArray(portSyms, builder.getContext());
result.addAttribute("portSyms", builder.getArrayAttr(portSyms));
result.addAttribute("portSymbols", builder.getArrayAttr(portSyms));
}
// Add port locations.
@ -1896,9 +1897,9 @@ static ParseResult parseClassLike(OpAsmParser &parser, OperationState &result,
result.addAttribute("portTypes", builder.getArrayAttr(portTypes));
// Add the port symbols.
if (!result.attributes.get("portSyms")) {
if (!result.attributes.get("portSymbols")) {
FModuleLike::fixupPortSymsArray(portSyms, builder.getContext());
result.addAttribute("portSyms", builder.getArrayAttr(portSyms));
result.addAttribute("portSymbols", builder.getArrayAttr(portSyms));
}
// Add port locations.
@ -1945,8 +1946,8 @@ static void printClassLike(OpAsmPrinter &p, ClassLike op) {
// Print the attr-dict.
SmallVector<StringRef, 8> omittedAttrs = {
"sym_name", "portNames", "portTypes", "portDirections",
"portSyms", "portLocations", visibilityAttrName};
"sym_name", "portNames", "portTypes", "portDirections",
"portSymbols", "portLocations", visibilityAttrName};
// We can omit the portNames if they were able to be printed as properly as
// block arguments.
@ -2067,6 +2068,12 @@ ArrayAttr ClassOp::getPortAnnotationsAttr() {
return ArrayAttr::get(getContext(), {});
}
ArrayRef<Attribute> ClassOp::getPortAnnotations() { return {}; }
void ClassOp::setPortAnnotationsAttr(ArrayAttr annotations) {
llvm_unreachable("classes do not support annotations");
}
ArrayAttr ClassOp::getLayersAttr() { return ArrayAttr::get(getContext(), {}); }
ArrayRef<Attribute> ClassOp::getLayers() { return getLayersAttr(); }
@ -2153,6 +2160,12 @@ ArrayAttr ExtClassOp::getPortAnnotationsAttr() {
return ArrayAttr::get(getContext(), {});
}
ArrayRef<Attribute> ExtClassOp::getPortAnnotations() { return {}; }
void ExtClassOp::setPortAnnotationsAttr(ArrayAttr annotations) {
llvm_unreachable("classes do not support annotations");
}
SmallVector<::circt::hw::PortInfo> ExtClassOp::getPortList() {
return ::getPortListImpl(*this);
}

2
lib/Dialect/FIRRTL/FIRRTLUtils.cpp
View File

@ -822,7 +822,7 @@ StringAttr circt::firrtl::getOrAddInnerSym(
auto [attr, sym] =
getOrAddInnerSym(mod.getContext(), mod.getPortSymbolAttr(portIdx),
target.getField(), getNamespace);
mod.setPortSymbolsAttr(portIdx, attr);
mod.setPortSymbolAttr(portIdx, attr);
return sym;
}
} else {

15
lib/Dialect/FIRRTL/Transforms/Dedup.cpp
View File

@ -113,7 +113,7 @@ struct StructuralHasherSharedConstants {
portTypesAttr = StringAttr::get(context, "portTypes");
moduleNameAttr = StringAttr::get(context, "moduleName");
innerSymAttr = StringAttr::get(context, "inner_sym");
portSymsAttr = StringAttr::get(context, "portSyms");
portSymbolsAttr = StringAttr::get(context, "portSymbols");
portNamesAttr = StringAttr::get(context, "portNames");
nonessentialAttributes.insert(StringAttr::get(context, "annotations"));
nonessentialAttributes.insert(StringAttr::get(context, "name"));
@ -132,8 +132,8 @@ struct StructuralHasherSharedConstants {
// This is a cached "inner_sym" string attr.
StringAttr innerSymAttr;
// This is a cached "portSyms" string attr.
StringAttr portSymsAttr;
// This is a cached "portSymbols" string attr.
StringAttr portSymbolsAttr;
// This is a cached "portNames" string attr.
StringAttr portNamesAttr;
@ -263,7 +263,7 @@ private:
}
// Special case the InnerSymbols to ignore the symbol names.
if (name == constants.portSymsAttr) {
if (name == constants.portSymbolsAttr) {
if (op->getNumRegions() != 1)
continue;
auto &region = op->getRegion(0);
@ -386,7 +386,7 @@ struct Equivalence {
nonessentialAttributes.insert(StringAttr::get(context, "portAnnotations"));
nonessentialAttributes.insert(StringAttr::get(context, "portNames"));
nonessentialAttributes.insert(StringAttr::get(context, "portTypes"));
nonessentialAttributes.insert(StringAttr::get(context, "portSyms"));
nonessentialAttributes.insert(StringAttr::get(context, "portSymbols"));
nonessentialAttributes.insert(StringAttr::get(context, "portLocations"));
nonessentialAttributes.insert(StringAttr::get(context, "sym_name"));
nonessentialAttributes.insert(StringAttr::get(context, "inner_sym"));
@ -1324,14 +1324,14 @@ private:
}
// If there are no port symbols on the "from" operation, we are done here.
auto fromPortSyms = from->getAttrOfType<ArrayAttr>("portSyms");
auto fromPortSyms = from->getAttrOfType<ArrayAttr>("portSymbols");
if (!fromPortSyms || fromPortSyms.empty())
return;
// We have to map each "fromPort" to each "toPort".
auto &moduleNamespace = getNamespace(toModule);
auto portCount = fromPortSyms.size();
auto portNames = to->getAttrOfType<ArrayAttr>("portNames");
auto toPortSyms = to->getAttrOfType<ArrayAttr>("portSyms");
auto toPortSyms = to->getAttrOfType<ArrayAttr>("portSymbols");
// Create an array of new port symbols for the "to" operation, copy in the
// old symbols if it has any, create an empty symbol array if it doesn't.
@ -1366,6 +1366,7 @@ private:
}
// Commit the new symbol attribute.
FModuleLike::fixupPortSymsArray(newPortSyms, toModule.getContext());
cast<FModuleLike>(to).setPortSymbols(newPortSyms);
}

3
lib/Dialect/FIRRTL/Transforms/DropConst.cpp
View File

@ -70,8 +70,7 @@ class DropConstPass : public circt::firrtl::impl::DropConstBase<DropConstPass> {
return type;
});
if (convertedAny)
mod->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(mod.getContext(), portTypes));
mod.setPortTypesAttr(ArrayAttr::get(mod.getContext(), portTypes));
};
// Rewrite module bodies in parallel.

6
lib/Dialect/FIRRTL/Transforms/InferResets.cpp
View File

@ -1190,8 +1190,7 @@ LogicalResult InferResetsPass::updateReset(ResetNetwork net, ResetKind kind) {
for (auto arg : module.getArguments())
argTypes.push_back(TypeAttr::get(arg.getType()));
module->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(op->getContext(), argTypes));
module.setPortTypesAttr(ArrayAttr::get(op->getContext(), argTypes));
LLVM_DEBUG(llvm::dbgs()
<< "- Updated type of module '" << module.getName() << "'\n");
}
@ -1205,8 +1204,7 @@ LogicalResult InferResetsPass::updateReset(ResetNetwork net, ResetKind kind) {
for (auto type : instOp.getResultTypes())
types.push_back(TypeAttr::get(type));
module->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(module->getContext(), types));
module.setPortTypesAttr(ArrayAttr::get(module->getContext(), types));
LLVM_DEBUG(llvm::dbgs()
<< "- Updated type of extmodule '" << module.getName() << "'\n");
}

3
lib/Dialect/FIRRTL/Transforms/InferWidths.cpp
View File

@ -2131,8 +2131,7 @@ FailureOr<bool> InferenceTypeUpdate::updateOperation(Operation *op) {
// Update the module function type if needed.
if (argsChanged) {
module->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(module.getContext(), argTypes));
module.setPortTypesAttr(ArrayAttr::get(module.getContext(), argTypes));
anyChanged = true;
}
}

2
lib/Dialect/FIRRTL/Transforms/InnerSymbolDCE.cpp
View File

@ -44,7 +44,7 @@ static void dropSymbol(const InnerSymTarget &target) {
auto mod = cast<FModuleLike>(target.getOp());
assert(target.getPort() < mod.getNumPorts());
auto base = mod.getPortSymbolAttr(target.getPort());
cast<firrtl::FModuleLike>(*mod).setPortSymbolsAttr(
cast<firrtl::FModuleLike>(*mod).setPortSymbolAttr(
target.getPort(), base.erase(target.getField()));
return;
}

5
lib/Dialect/FIRRTL/Transforms/LowerClasses.cpp
View File

@ -429,8 +429,6 @@ PathTracker::run(CircuitOp circuit, InstanceGraph &instanceGraph,
HierPathCache &cache, PathInfoTable &pathInfoTable,
const SymbolTable &symbolTable,
const DenseMap<DistinctAttr, FModuleOp> &owningModules) {
SmallVector<PathTracker> trackers;
// First allocate module namespaces. Don't capture a namespace reference at
// this point since they could be invalidated when DenseMap grows.
for (auto *node : instanceGraph)
@ -439,6 +437,9 @@ PathTracker::run(CircuitOp circuit, InstanceGraph &instanceGraph,
for (auto *node : instanceGraph)
if (auto module = node->getModule<FModuleLike>()) {
// Classes do not have path trackers on them.
if (isa<firrtl::ClassOp, firrtl::ExtClassOp>(module))
continue;
PathTracker tracker(module, namespaces, instanceGraph, symbolTable,
owningModules);
if (failed(tracker.runOnModule()))

4
lib/Dialect/FIRRTL/Transforms/LowerLayers.cpp
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@ -261,8 +261,8 @@ void LowerLayersPass::removeLayersFromPorts(FModuleLike moduleLike) {
if (!changed)
return;
moduleLike->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(moduleLike.getContext(), newTypeAttrs));
moduleLike.setPortTypesAttr(
ArrayAttr::get(moduleLike.getContext(), newTypeAttrs));
if (auto moduleOp = dyn_cast<FModuleOp>(moduleLike.getOperation())) {
for (auto arg : moduleOp.getBodyBlock()->getArguments())

3
lib/Dialect/FIRRTL/Transforms/LowerSignatures.cpp
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@ -340,7 +340,7 @@ static LogicalResult lowerModuleSignature(FModuleLike module, Convention conv,
// handled differently below.
if (attr.getName() != "portNames" && attr.getName() != "portDirections" &&
attr.getName() != "portTypes" && attr.getName() != "portAnnotations" &&
attr.getName() != "portSyms" && attr.getName() != "portLocations" &&
attr.getName() != "portSymbols" && attr.getName() != "portLocations" &&
attr.getName() != "internalPaths")
newModuleAttrs.push_back(attr);
@ -394,6 +394,7 @@ static LogicalResult lowerModuleSignature(FModuleLike module, Convention conv,
// Update the module's attributes.
module->setAttrs(newModuleAttrs);
FModuleLike::fixupPortSymsArray(newPortSyms, theBuilder.getContext());
module.setPortSymbols(newPortSyms);
return success();
}

10
lib/Dialect/FIRRTL/Transforms/LowerTypes.cpp
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@ -321,7 +321,7 @@ struct AttrCache {
sPortDirections = StringAttr::get(context, "portDirections");
sPortNames = StringAttr::get(context, "portNames");
sPortTypes = StringAttr::get(context, "portTypes");
sPortSyms = StringAttr::get(context, "portSyms");
sPortSymbols = StringAttr::get(context, "portSymbols");
sPortLocations = StringAttr::get(context, "portLocations");
sPortAnnotations = StringAttr::get(context, "portAnnotations");
sEmpty = StringAttr::get(context, "");
@ -330,7 +330,7 @@ struct AttrCache {
Type i64ty;
StringAttr nameAttr, nameKindAttr, sPortDirections, sPortNames, sPortTypes,
sPortSyms, sPortLocations, sPortAnnotations, sEmpty;
sPortSymbols, sPortLocations, sPortAnnotations, sEmpty;
};
// The visitors all return true if the operation should be deleted, false if
@ -1083,7 +1083,7 @@ bool TypeLoweringVisitor::visitDecl(FExtModuleOp extModule) {
// handled differently below.
if (attr.getName() != "portDirections" && attr.getName() != "portNames" &&
attr.getName() != "portTypes" && attr.getName() != "portAnnotations" &&
attr.getName() != "portSyms" && attr.getName() != "portLocations")
attr.getName() != "portSymbols" && attr.getName() != "portLocations")
newModuleAttrs.push_back(attr);
SmallVector<Direction> newArgDirections;
@ -1124,6 +1124,7 @@ bool TypeLoweringVisitor::visitDecl(FExtModuleOp extModule) {
// Update the module's attributes.
extModule->setAttrs(newModuleAttrs);
FModuleLike::fixupPortSymsArray(newArgSyms, context);
extModule.setPortSymbols(newArgSyms);
if (internalPaths)
extModule.setInternalPathsAttr(builder.getArrayAttr(newInternalPaths));
@ -1172,7 +1173,7 @@ bool TypeLoweringVisitor::visitDecl(FModuleOp module) {
// handled differently below.
if (attr.getName() != "portNames" && attr.getName() != "portDirections" &&
attr.getName() != "portTypes" && attr.getName() != "portAnnotations" &&
attr.getName() != "portSyms" && attr.getName() != "portLocations")
attr.getName() != "portSymbols" && attr.getName() != "portLocations")
newModuleAttrs.push_back(attr);
SmallVector<Direction> newArgDirections;
@ -1208,6 +1209,7 @@ bool TypeLoweringVisitor::visitDecl(FModuleOp module) {
// Update the module's attributes.
module->setAttrs(newModuleAttrs);
FModuleLike::fixupPortSymsArray(newArgSyms, context);
module.setPortSymbols(newArgSyms);
return false;
}

3
lib/Dialect/FIRRTL/Transforms/ProbesToSignals.cpp
View File

@ -254,8 +254,7 @@ LogicalResult ProbeVisitor::visit(FModuleLike mod) {
// Update signature and argument types.
if (portsToChange) {
mod->setAttr(mod.getPortTypesAttrName(),
ArrayAttr::get(mod->getContext(), newPortTypes));
mod.setPortTypesAttr(ArrayAttr::get(mod->getContext(), newPortTypes));
if (block) {
// We may also need to update the types on the block arguments.

4
lib/Dialect/FIRRTL/Transforms/SpecializeLayers.cpp
View File

@ -527,8 +527,8 @@ struct SpecializeLayers {
moduleLike.erasePorts(disabledPorts);
// Update the rest of the port types.
moduleLike->setAttr(FModuleLike::getPortTypesAttrName(),
ArrayAttr::get(moduleLike.getContext(), newTypeAttrs));
moduleLike.setPortTypesAttr(
ArrayAttr::get(moduleLike.getContext(), newTypeAttrs));
// We may also need to update the types on the block arguments.
if (auto moduleOp = dyn_cast<FModuleOp>(moduleLike.getOperation()))

10
test/Dialect/FIRRTL/errors.mlir
View File

@ -73,7 +73,7 @@ firrtl.circuit "foo" {
"firrtl.module"() ( { }, { })
{sym_name = "foo", convention = #firrtl<convention internal>,
portTypes = [!firrtl.uint], portDirections = array<i1: true>,
portNames = ["in0"], portAnnotations = [], portSyms = []} : () -> ()
portNames = ["in0"], portAnnotations = [], portSymbols = []} : () -> ()
}
// -----
@ -84,7 +84,7 @@ firrtl.circuit "foo" {
^entry:
}) { sym_name = "foo", convention = #firrtl<convention internal>,
portTypes = [!firrtl.uint], portDirections = array<i1: true>,
portNames = ["in0"], portAnnotations = [], portSyms = []} : () -> ()
portNames = ["in0"], portAnnotations = [], portSymbols = []} : () -> ()
}
// -----
@ -95,7 +95,7 @@ firrtl.circuit "foo" {
^entry:
}) {sym_name = "foo", convention = #firrtl<convention internal>,
portTypes = [!firrtl.uint], portDirections = array<i1: true>,
portNames = ["in0"], portAnnotations = [], portSyms = [],
portNames = ["in0"], portAnnotations = [], portSymbols = [],
portLocations = []} : () -> ()
}
@ -110,7 +110,7 @@ firrtl.circuit "foo" {
^entry:
}) {sym_name = "foo", convention = #firrtl<convention internal>,
portTypes = [!firrtl.uint], portDirections = array<i1: true>,
portNames = ["in0"], portAnnotations = [], portSyms = [],
portNames = ["in0"], portAnnotations = [], portSymbols = [],
portLocations = [loc("loc")]} : () -> ()
}
@ -122,7 +122,7 @@ firrtl.circuit "foo" {
^entry(%a: i1):
}) {sym_name = "foo", convention = #firrtl<convention internal>,
portTypes = [!firrtl.uint], portDirections = array<i1: true>,
portNames = ["in0"], portAnnotations = [], portSyms = [],
portNames = ["in0"], portAnnotations = [], portSymbols = [],
portLocations = [loc("foo")]} : () -> ()
}