rm48x50: cleanup sys_startup.c
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Grissiom
parent
81ab083ae5
commit
d3648dbc9f
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@ -59,9 +59,6 @@ extern uint32 * __binit__;
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extern void main(void);
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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/* Startup Routine */
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/** @fn void memoryInit(uint32 ram)
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@ -71,9 +68,6 @@ extern void main(void);
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*/
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void memoryInit(uint32 ram)
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{
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/* USER CODE BEGIN (11) */
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/* USER CODE END */
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/* Enable Memory Hardware Initialization */
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systemREG1->MINITGCR = 0xAU;
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@ -87,14 +81,8 @@ void memoryInit(uint32 ram)
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/* Disable Memory Hardware Initialization */
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systemREG1->MINITGCR = 0x5U;
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/* USER CODE BEGIN (12) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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void _c_int00(void)
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{
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/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
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@ -108,44 +96,21 @@ void _c_int00(void)
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_esmCcmErrorsClear_();
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}
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/* USER CODE BEGIN (8) */
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/* USER CODE END */
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/* USER CODE BEGIN (11) */
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/* USER CODE END */
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_errata_CORTEXR4_66_();
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_errata_CORTEXR4_57_();
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/* Reset handler: the following instructions read from the system exception status register
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* to identify the cause of the CPU reset. */
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/* check for power-on reset condition */
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if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
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{
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/* USER CODE BEGIN (12) */
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/* USER CODE END */
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/* clear all reset status flags */
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SYS_EXCEPTION = 0xFFFFU;
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/* USER CODE BEGIN (13) */
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/* USER CODE END */
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_errata_CORTEXR4_66_();
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/* USER CODE BEGIN (14) */
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/* USER CODE END */
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_errata_CORTEXR4_57_();
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/* USER CODE BEGIN (15) */
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/* USER CODE END */
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/* continue with normal start-up sequence */
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}
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else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
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{
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/* Reset caused due to oscillator failure.
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Add user code here to handle oscillator failure */
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/* USER CODE BEGIN (16) */
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/* USER CODE END */
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}
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else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
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{
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@ -157,21 +122,13 @@ void _c_int00(void)
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if(WATCHDOG_STATUS != 0U)
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{
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/* Add user code here to handle watchdog violation. */
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/* USER CODE BEGIN (17) */
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/* USER CODE END */
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/* Clear the Watchdog reset flag in Exception Status register */
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SYS_EXCEPTION = WATCHDOG_RESET;
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/* USER CODE BEGIN (18) */
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/* USER CODE END */
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}
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else
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{
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/* Clear the ICEPICK reset flag in Exception Status register */
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SYS_EXCEPTION = ICEPICK_RESET;
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/* USER CODE BEGIN (19) */
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/* USER CODE END */
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}
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}
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else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
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@ -179,49 +136,23 @@ void _c_int00(void)
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/* Reset caused due to CPU reset.
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CPU reset can be caused by CPU self-test completion, or
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by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
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/* USER CODE BEGIN (20) */
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/* USER CODE END */
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/* clear all reset status flags */
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SYS_EXCEPTION = CPU_RESET;
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/* USER CODE BEGIN (21) */
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/* USER CODE END */
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}
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else if ((SYS_EXCEPTION & SW_RESET) != 0U)
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{
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/* Reset caused due to software reset.
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Add user code to handle software reset. */
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/* USER CODE BEGIN (22) */
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/* USER CODE END */
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}
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else
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{
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/* Reset caused by nRST being driven low externally.
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Add user code to handle external reset. */
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/* USER CODE BEGIN (23) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (26) */
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/* USER CODE END */
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/* Initialize System - Clock, Flash settings with Efuse self check */
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systemInit();
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/* USER CODE BEGIN (29) */
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/* USER CODE END */
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/* USER CODE BEGIN (31) */
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/* USER CODE END */
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/* USER CODE BEGIN (33) */
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/* USER CODE END */
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/* USER CODE BEGIN (36) */
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/* USER CODE END */
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/* USER CODE BEGIN (37) */
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/* USER CODE END */
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/* Initialize CPU RAM.
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* This function uses the system module's hardware for auto-initialization of memories and their
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* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
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@ -230,32 +161,7 @@ void _c_int00(void)
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*/
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memoryInit(0x1U);
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/* USER CODE BEGIN (38) */
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/* USER CODE END */
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_coreEnableRamEcc_();
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/* USER CODE BEGIN (39) */
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/* USER CODE END */
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/* USER CODE BEGIN (40) */
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/* USER CODE END */
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tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
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tcram2REG->RAMCTRL &= ~(0x00000100U);
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tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
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tcram2REG->RAMCTRL &= ~(0x00000100U);
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/* USER CODE BEGIN (41) */
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/* USER CODE END */
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/* USER CODE BEGIN (43) */
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/* USER CODE END */
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/* USER CODE BEGIN (44) */
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/* USER CODE END */
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/* USER CODE BEGIN (48) */
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/* USER CODE END */
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/* USER CODE BEGIN (56) */
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/* USER CODE END */
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/* Release the MibSPI1 modules from local reset.
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* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
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*/
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@ -271,54 +177,17 @@ void _c_int00(void)
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*/
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mibspiREG5->GCR0 = 0x1U;
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/* USER CODE BEGIN (57) */
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/* USER CODE END */
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/* Initialize all on-chip SRAMs except for MibSPIx RAMs
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* The MibSPIx modules have their own auto-initialization mechanism which is triggered
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* as soon as the modules are brought out of local reset.
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*/
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/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
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*/
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/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
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Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
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*/
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memoryInit( (1U << 1U)
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| (1U << 2U)
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| (1U << 5U)
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| (1U << 6U)
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| (1U << 10U)
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| (1U << 8U)
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| (1U << 14U)
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| (1U << 3U)
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| (1U << 4U)
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| (1U << 15U)
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| (1U << 16U)
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| (0U << 13U) );
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/* USER CODE BEGIN (58) */
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/* USER CODE END */
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/* USER CODE BEGIN (59) */
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/* USER CODE END */
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/* USER CODE BEGIN (60) */
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/* USER CODE END */
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/* USER CODE BEGIN (61) */
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/* USER CODE END */
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/* USER CODE BEGIN (62) */
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/* USER CODE END */
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/* USER CODE BEGIN (63) */
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/* USER CODE END */
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/* USER CODE BEGIN (64) */
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/* USER CODE END */
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/* USER CODE BEGIN (65) */
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/* USER CODE END */
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/* USER CODE BEGIN (66) */
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/* USER CODE END */
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/* USER CODE BEGIN (67) */
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/* USER CODE END */
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/* USER CODE BEGIN (68) */
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/* USER CODE END */
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/* USER CODE BEGIN (69) */
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/* USER CODE END */
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/* Initialize all on-chip SRAMs except for MibSPIx RAMs The MibSPIx modules
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* have their own auto-initialization mechanism which is triggered as soon
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* as the modules are brought out of local reset. */
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/* The system module auto-init will hang on the MibSPI RAM if the module is
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* still in local reset. */
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/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories
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* and their channel numbers. Memory Initialization is perfomed only on
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* the user selected memories in HALCoGen's GUI SAFETY INIT tab. */
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memoryInit((1U << 1U) | (1U << 2U) | (1U << 5U) | (1U << 6U)
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| (1U << 10U) | (1U << 8U) | (1U << 14U) | (1U << 3U)
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| (1U << 4U) | (1U << 15U) | (1U << 16U) | (0U << 13U) );
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while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
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{
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@ -333,24 +202,9 @@ void _c_int00(void)
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}/* Wait */
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/* wait for MibSPI5 RAM to complete initialization */
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/* USER CODE BEGIN (70) */
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/* USER CODE END */
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/* USER CODE BEGIN (71) */
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/* USER CODE END */
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/* USER CODE BEGIN (72) */
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/* USER CODE END */
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/* USER CODE BEGIN (73) */
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/* USER CODE END */
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/* USER CODE BEGIN (74) */
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/* USER CODE END */
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/* Initialize VIM table */
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vimInit();
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/* USER CODE BEGIN (75) */
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/* USER CODE END */
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#ifdef __GNUC__
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data_init();
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#elif defined(__TI_COMPILER_VERSION__)
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@ -390,17 +244,6 @@ void _c_int00(void)
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}
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}
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#endif
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/* USER CODE BEGIN (76) */
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/* USER CODE END */
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/* call the application */
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main();
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/* USER CODE BEGIN (77) */
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/* USER CODE END */
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/* USER CODE BEGIN (78) */
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/* USER CODE END */
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}
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/* USER CODE BEGIN (79) */
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/* USER CODE END */
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