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Merge pull request #225 from nongxiaoming/master 

add the bsp for lpc407x/408x
This commit is contained in:
Bernard Xiong 2014-01-02 02:53:58 -08:00
parent b924104129 a043a74c7b
commit c1550361fa
105 changed files with 50936 additions and 0 deletions
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/* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* $Date: 11. November 2010
* $Revision: V1.0.2
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern uint16_t armBitRevTable[256];
extern q15_t armRecipTableQ15[64];
extern q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
#endif /* ARM_COMMON_TABLES_H */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \mainpage CMSIS Cortex-M0
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
*/
/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
CMSIS violates following MISRA-C2004 Rules:
- Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
- Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
- Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core
- Cortex-M core Revision Number
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
/* add preprocessor checks */
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_cmInstr.h" /*!< Core Instruction Access */
#include "core_cmFunc.h" /*!< Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*@} end of group CMSIS_core_definitions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
and not via processor. Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
This function enables a device specific interrupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
This function disables a device specific interrupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
\return 1 Interrupt status is pending
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
This function sets the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
\param [in] IRQn Number of the interrupt for set priority
\param [in] priority Priority to set
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
This function reads the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
priority bits of the microcontroller.
\param [in] IRQn Number of the interrupt for get priority
\return Interrupt Priority
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
This function initiate a system reset request to reset the MCU.
*/
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
This function initialises the system tick timer and its interrupt and start the system tick timer.
Counter is in free running mode to generate periodical interrupts.
\param [in] ticks Number of ticks between two interrupts
\return 0 Function succeeded
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
/* intrinsic __SADD8 see intrinsics.h */
/* intrinsic __QADD8 see intrinsics.h */
/* intrinsic __SHADD8 see intrinsics.h */
/* intrinsic __UADD8 see intrinsics.h */
/* intrinsic __UQADD8 see intrinsics.h */
/* intrinsic __UHADD8 see intrinsics.h */
/* intrinsic __SSUB8 see intrinsics.h */
/* intrinsic __QSUB8 see intrinsics.h */
/* intrinsic __SHSUB8 see intrinsics.h */
/* intrinsic __USUB8 see intrinsics.h */
/* intrinsic __UQSUB8 see intrinsics.h */
/* intrinsic __UHSUB8 see intrinsics.h */
/* intrinsic __SADD16 see intrinsics.h */
/* intrinsic __QADD16 see intrinsics.h */
/* intrinsic __SHADD16 see intrinsics.h */
/* intrinsic __UADD16 see intrinsics.h */
/* intrinsic __UQADD16 see intrinsics.h */
/* intrinsic __UHADD16 see intrinsics.h */
/* intrinsic __SSUB16 see intrinsics.h */
/* intrinsic __QSUB16 see intrinsics.h */
/* intrinsic __SHSUB16 see intrinsics.h */
/* intrinsic __USUB16 see intrinsics.h */
/* intrinsic __UQSUB16 see intrinsics.h */
/* intrinsic __UHSUB16 see intrinsics.h */
/* intrinsic __SASX see intrinsics.h */
/* intrinsic __QASX see intrinsics.h */
/* intrinsic __SHASX see intrinsics.h */
/* intrinsic __UASX see intrinsics.h */
/* intrinsic __UQASX see intrinsics.h */
/* intrinsic __UHASX see intrinsics.h */
/* intrinsic __SSAX see intrinsics.h */
/* intrinsic __QSAX see intrinsics.h */
/* intrinsic __SHSAX see intrinsics.h */
/* intrinsic __USAX see intrinsics.h */
/* intrinsic __UQSAX see intrinsics.h */
/* intrinsic __UHSAX see intrinsics.h */
/* intrinsic __USAD8 see intrinsics.h */
/* intrinsic __USADA8 see intrinsics.h */
/* intrinsic __SSAT16 see intrinsics.h */
/* intrinsic __USAT16 see intrinsics.h */
/* intrinsic __UXTB16 see intrinsics.h */
/* intrinsic __SXTB16 see intrinsics.h */
/* intrinsic __UXTAB16 see intrinsics.h */
/* intrinsic __SXTAB16 see intrinsics.h */
/* intrinsic __SMUAD see intrinsics.h */
/* intrinsic __SMUADX see intrinsics.h */
/* intrinsic __SMLAD see intrinsics.h */
/* intrinsic __SMLADX see intrinsics.h */
/* intrinsic __SMLALD see intrinsics.h */
/* intrinsic __SMLALDX see intrinsics.h */
/* intrinsic __SMUSD see intrinsics.h */
/* intrinsic __SMUSDX see intrinsics.h */
/* intrinsic __SMLSD see intrinsics.h */
/* intrinsic __SMLSDX see intrinsics.h */
/* intrinsic __SMLSLD see intrinsics.h */
/* intrinsic __SMLSLDX see intrinsics.h */
/* intrinsic __SEL see intrinsics.h */
/* intrinsic __QADD see intrinsics.h */
/* intrinsic __QSUB see intrinsics.h */
/* intrinsic __PKHBT see intrinsics.h */
/* intrinsic __PKHTB see intrinsics.h */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
* @ingroup CMSIS_Core
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**********************************************************************
* $Id$ system_LPC177x_8x.h 2011-06-02
*//**
* @file system_LPC177x_8x.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC177x_8x Device Series
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef __SYSTEM_LPC177x_8x_H
#define __SYSTEM_LPC177x_8x_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock */
extern uint32_t USBClock; /*!< USB Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (12000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC177x_8x_H */

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/**********************************************************************
* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
*//**
* @file system_LPC407x_8x_177x_8x.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC Device Series
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
#define __SYSTEM_LPC407x_8x_177x_8x_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock */
extern uint32_t USBClock; /*!< USB Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (12000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */

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;/*****************************************************************************
; * @file: startup_LPC177x_8x.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC177x_8x Device Series
; * @version: V1.20
; * @date: 07. October 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD 0 ; 29: reserved, not for SPIFI anymore
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD MCI_IRQHandler ; 45: SD/MMC card I/F
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
DCD UART4_IRQHandler ; 51: UART4
DCD SSP2_IRQHandler ; 52: SSP2
DCD LCD_IRQHandler ; 53: LCD
DCD GPIO_IRQHandler ; 54: GPIO
DCD PWM0_IRQHandler ; 55: PWM0
DCD EEPROM_IRQHandler ; 56: EEPROM
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
;EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT PLL0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT MCI_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT PLL1_IRQHandler [WEAK]
EXPORT USBActivity_IRQHandler [WEAK]
EXPORT CANActivity_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT SSP2_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT EEPROM_IRQHandler [WEAK]
WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
;SPIFI_IRQHandler ;not used
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
MCI_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler
UART4_IRQHandler
SSP2_IRQHandler
LCD_IRQHandler
GPIO_IRQHandler
PWM0_IRQHandler
EEPROM_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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;/*****************************************************************************
; * @file: startup_LPC407x_8x.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * for the NXP LPC407x_8x Device Series
; * @version: V1.20
; * @date: 16. January 2012
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
; DCD 0xEFFFF5D6 ; Reserved- vector sum
DCD 0xEFFFF39E ; Reserved- vector sum
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD 0 ; 29: reserved, not for SPIFI anymore
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD MCI_IRQHandler ; 45: SD/MMC card I/F
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
DCD UART4_IRQHandler ; 51: UART4
DCD SSP2_IRQHandler ; 52: SSP2
DCD LCD_IRQHandler ; 53: LCD
DCD GPIO_IRQHandler ; 54: GPIO
DCD PWM0_IRQHandler ; 55: PWM0
DCD EEPROM_IRQHandler ; 56: EEPROM
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
;EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT PLL0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT MCI_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT PLL1_IRQHandler [WEAK]
EXPORT USBActivity_IRQHandler [WEAK]
EXPORT CANActivity_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT SSP2_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT EEPROM_IRQHandler [WEAK]
WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
;SPIFI_IRQHandler ;not used
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
MCI_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler
UART4_IRQHandler
SSP2_IRQHandler
LCD_IRQHandler
GPIO_IRQHandler
PWM0_IRQHandler
EEPROM_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

279
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/*****************************************************************************/
/* startup_LPC17xx.s: Startup file for LPC17xx device series */
/*****************************************************************************/
/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
/*****************************************************************************/
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Stack_Size, 0x00000100
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Heap_Size, 0x00001000
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
/* Vector Table */
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack /* Top of Stack */
.long __cs3_reset /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long WDT_IRQHandler /* 16: Watchdog Timer */
.long TIMER0_IRQHandler /* 17: Timer0 */
.long TIMER1_IRQHandler /* 18: Timer1 */
.long TIMER2_IRQHandler /* 19: Timer2 */
.long TIMER3_IRQHandler /* 20: Timer3 */
.long UART0_IRQHandler /* 21: UART0 */
.long UART1_IRQHandler /* 22: UART1 */
.long UART2_IRQHandler /* 23: UART2 */
.long UART3_IRQHandler /* 24: UART3 */
.long PWM1_IRQHandler /* 25: PWM1 */
.long I2C0_IRQHandler /* 26: I2C0 */
.long I2C1_IRQHandler /* 27: I2C1 */
.long I2C2_IRQHandler /* 28: I2C2 */
.long 0 /* 29: Reserved, not for SPIFI anymore */
.long SSP0_IRQHandler /* 30: SSP0 */
.long SSP1_IRQHandler /* 31: SSP1 */
.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
.long RTC_IRQHandler /* 33: Real Time Clock */
.long EINT0_IRQHandler /* 34: External Interrupt 0 */
.long EINT1_IRQHandler /* 35: External Interrupt 1 */
.long EINT2_IRQHandler /* 36: External Interrupt 2 */
.long EINT3_IRQHandler /* 37: External Interrupt 3 */
.long ADC_IRQHandler /* 38: A/D Converter */
.long BOD_IRQHandler /* 39: Brown-Out Detect */
.long USB_IRQHandler /* 40: USB */
.long CAN_IRQHandler /* 41: CAN */
.long DMA_IRQHandler /* 42: General Purpose DMA */
.long I2S_IRQHandler /* 43: I2S */
.long ENET_IRQHandler /* 44: Ethernet */
.long MCI_IRQHandler /* 45: SD/MMC Card */
.long MCPWM_IRQHandler /* 46: Motor Control PWM */
.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
.long USBActivity_IRQHandler /* 49: USB Activity */
.long CANActivity_IRQHandler /* 50: CAN Activity */
.long UART4_IRQHandler /* 51: UART4 */
.long SSP2_IRQHandler /* 52: SSP2 */
.long LCD_IRQHandler /* 53: LCD */
.long GPIO_IRQHandler /* 54: GPIO */
.long PWM0_IRQHandler /* 55: PWM0 */
.long EEPROM_IRQHandler /* 56: EEPROM */
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
.section ".crp"
.globl CRP_Value
CRP_Value:
.long 0xFFFFFFFF
/* Reset Handler */
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
.if (RAM_MODE)
/* Clear .bss section (Zero init) */
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
CMP R1,R2
BEQ BSSIsEmpty
LoopZI:
CMP R1, R2
BHS BSSIsEmpty
STR R0, [R1]
ADD R1, #4
BLO LoopZI
BSSIsEmpty:
LDR R0, =SystemInit
BLX R0
LDR R0,=main
BX R0
.else
LDR R0, =SystemInit
BLX R0
LDR R0,=_start
BX R0
.endif
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
B .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
B .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WDT_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ UART0_IRQHandler
IRQ UART1_IRQHandler
IRQ UART2_IRQHandler
IRQ UART3_IRQHandler
IRQ PWM1_IRQHandler
IRQ I2C0_IRQHandler
IRQ I2C1_IRQHandler
IRQ I2C2_IRQHandler
/* IRQ SPIFI_IRQHandler */
IRQ SSP0_IRQHandler
IRQ SSP1_IRQHandler
IRQ PLL0_IRQHandler
IRQ RTC_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ ADC_IRQHandler
IRQ BOD_IRQHandler
IRQ USB_IRQHandler
IRQ CAN_IRQHandler
IRQ DMA_IRQHandler
IRQ I2S_IRQHandler
IRQ ENET_IRQHandler
IRQ MCI_IRQHandler
IRQ MCPWM_IRQHandler
IRQ QEI_IRQHandler
IRQ PLL1_IRQHandler
IRQ USBActivity_IRQHandler
IRQ CANActivity_IRQHandler
IRQ UART4_IRQHandler
IRQ SSP2_IRQHandler
IRQ LCD_IRQHandler
IRQ GPIO_IRQHandler
IRQ PWM0_IRQHandler
IRQ EEPROM_IRQHandler
.end

279
bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s Normal file
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/*****************************************************************************/
/* startup_LPC17xx.s: Startup file for LPC17xx device series */
/*****************************************************************************/
/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
/*****************************************************************************/
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Stack_Size, 0x00000100
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Heap_Size, 0x00001000
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
/* Vector Table */
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack /* Top of Stack */
.long __cs3_reset /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long WDT_IRQHandler /* 16: Watchdog Timer */
.long TIMER0_IRQHandler /* 17: Timer0 */
.long TIMER1_IRQHandler /* 18: Timer1 */
.long TIMER2_IRQHandler /* 19: Timer2 */
.long TIMER3_IRQHandler /* 20: Timer3 */
.long UART0_IRQHandler /* 21: UART0 */
.long UART1_IRQHandler /* 22: UART1 */
.long UART2_IRQHandler /* 23: UART2 */
.long UART3_IRQHandler /* 24: UART3 */
.long PWM1_IRQHandler /* 25: PWM1 */
.long I2C0_IRQHandler /* 26: I2C0 */
.long I2C1_IRQHandler /* 27: I2C1 */
.long I2C2_IRQHandler /* 28: I2C2 */
.long 0 /* 29: Reserved, not for SPIFI anymore */
.long SSP0_IRQHandler /* 30: SSP0 */
.long SSP1_IRQHandler /* 31: SSP1 */
.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
.long RTC_IRQHandler /* 33: Real Time Clock */
.long EINT0_IRQHandler /* 34: External Interrupt 0 */
.long EINT1_IRQHandler /* 35: External Interrupt 1 */
.long EINT2_IRQHandler /* 36: External Interrupt 2 */
.long EINT3_IRQHandler /* 37: External Interrupt 3 */
.long ADC_IRQHandler /* 38: A/D Converter */
.long BOD_IRQHandler /* 39: Brown-Out Detect */
.long USB_IRQHandler /* 40: USB */
.long CAN_IRQHandler /* 41: CAN */
.long DMA_IRQHandler /* 42: General Purpose DMA */
.long I2S_IRQHandler /* 43: I2S */
.long ENET_IRQHandler /* 44: Ethernet */
.long MCI_IRQHandler /* 45: SD/MMC Card */
.long MCPWM_IRQHandler /* 46: Motor Control PWM */
.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
.long USBActivity_IRQHandler /* 49: USB Activity */
.long CANActivity_IRQHandler /* 50: CAN Activity */
.long UART4_IRQHandler /* 51: UART4 */
.long SSP2_IRQHandler /* 52: SSP2 */
.long LCD_IRQHandler /* 53: LCD */
.long GPIO_IRQHandler /* 54: GPIO */
.long PWM0_IRQHandler /* 55: PWM0 */
.long EEPROM_IRQHandler /* 56: EEPROM */
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
.section ".crp"
.globl CRP_Value
CRP_Value:
.long 0xFFFFFFFF
/* Reset Handler */
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
.ifdef RAM_MODE
/* Clear .bss section (Zero init) */
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
CMP R1,R2
BEQ BSSIsEmpty
LoopZI:
CMP R1, R2
BHS BSSIsEmpty
STR R0, [R1]
ADD R1, #4
BLO LoopZI
BSSIsEmpty:
LDR R0, =SystemInit
BLX R0
LDR R0,=main
BX R0
.else
LDR R0, =SystemInit
BLX R0
LDR R0,=_start
BX R0
.endif
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
B .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
B .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WDT_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ UART0_IRQHandler
IRQ UART1_IRQHandler
IRQ UART2_IRQHandler
IRQ UART3_IRQHandler
IRQ PWM1_IRQHandler
IRQ I2C0_IRQHandler
IRQ I2C1_IRQHandler
IRQ I2C2_IRQHandler
/* IRQ SPIFI_IRQHandler */
IRQ SSP0_IRQHandler
IRQ SSP1_IRQHandler
IRQ PLL0_IRQHandler
IRQ RTC_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ ADC_IRQHandler
IRQ BOD_IRQHandler
IRQ USB_IRQHandler
IRQ CAN_IRQHandler
IRQ DMA_IRQHandler
IRQ I2S_IRQHandler
IRQ ENET_IRQHandler
IRQ MCI_IRQHandler
IRQ MCPWM_IRQHandler
IRQ QEI_IRQHandler
IRQ PLL1_IRQHandler
IRQ USBActivity_IRQHandler
IRQ CANActivity_IRQHandler
IRQ UART4_IRQHandler
IRQ SSP2_IRQHandler
IRQ LCD_IRQHandler
IRQ GPIO_IRQHandler
IRQ PWM0_IRQHandler
IRQ EEPROM_IRQHandler
.end

396
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;/*****************************************************************************
; * @file: startup_LPC177x_8x.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC17xx Device Series
; * @version: V1.03
; * @date: 09. February 2010
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD 0 ; 29: reserved; not for SPIFI anymore
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD MCI_IRQHandler ; 45: MCI Card
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
DCD UART4_IRQHandler ; 51: UART4
DCD SSP2_IRQHandler ; 52: SSP2
DCD LCD_IRQHandler ; 53: LCD
DCD GPIO_IRQHandler ; 54: GPIO
DCD PWM0_IRQHandler ; 55: PWM0
DCD EEPROM_IRQHandler ; 56: EEPROM
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
PUBLIC CRP_Value
RSEG CRPKEY : CODE(2)
CRP_Value
DCD 0xFFFFFFFF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER(1)
WDT_IRQHandler
B WDT_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK PWM1_IRQHandler
SECTION .text:CODE:REORDER(1)
PWM1_IRQHandler
B PWM1_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
;PUBWEAK SPIFI_IRQHandler
;SECTION .text:CODE:REORDER(1)
;SPIFI_IRQHandler
;B SPIFI_IRQHandler
PUBWEAK SSP0_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP0_IRQHandler
B SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP1_IRQHandler
B SSP1_IRQHandler
PUBWEAK PLL0_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL0_IRQHandler
B PLL0_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK BOD_IRQHandler
SECTION .text:CODE:REORDER(1)
BOD_IRQHandler
B BOD_IRQHandler
PUBWEAK USB_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_IRQHandler
B USB_IRQHandler
PUBWEAK CAN_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN_IRQHandler
B CAN_IRQHandler
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK I2S_IRQHandler
SECTION .text:CODE:REORDER(1)
I2S_IRQHandler
B I2S_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK MCI_IRQHandler
SECTION .text:CODE:REORDER(1)
MCI_IRQHandler
B MCI_IRQHandler
PUBWEAK MCPWM_IRQHandler
SECTION .text:CODE:REORDER(1)
MCPWM_IRQHandler
B MCPWM_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
QEI_IRQHandler
B QEI_IRQHandler
PUBWEAK PLL1_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL1_IRQHandler
B PLL1_IRQHandler
PUBWEAK USBActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
USBActivity_IRQHandler
B USBActivity_IRQHandler
PUBWEAK CANActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
CANActivity_IRQHandler
B CANActivity_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK SSP2_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP2_IRQHandler
B SSP2_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK GPIO_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_IRQHandler
B GPIO_IRQHandler
PUBWEAK PWM0_IRQHandler
SECTION .text:CODE:REORDER(1)
PWM0_IRQHandler
B PWM0_IRQHandler
PUBWEAK EEPROM_IRQHandler
SECTION .text:CODE:REORDER(1)
EEPROM_IRQHandler
B EEPROM_IRQHandler
END

396
bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s Normal file
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@ -0,0 +1,396 @@
;/*****************************************************************************
; * @file: startup_LPC177x_8x.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC17xx Device Series
; * @version: V1.03
; * @date: 09. February 2010
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD 0 ; 29: reserved; not for SPIFI anymore
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD MCI_IRQHandler ; 45: MCI Card
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
DCD UART4_IRQHandler ; 51: UART4
DCD SSP2_IRQHandler ; 52: SSP2
DCD LCD_IRQHandler ; 53: LCD
DCD GPIO_IRQHandler ; 54: GPIO
DCD PWM0_IRQHandler ; 55: PWM0
DCD EEPROM_IRQHandler ; 56: EEPROM
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
PUBLIC CRP_Value
RSEG CRPKEY : CODE(2)
CRP_Value
DCD 0xFFFFFFFF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WDT_IRQHandler
SECTION .text:CODE:REORDER(1)
WDT_IRQHandler
B WDT_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK UART2_IRQHandler
SECTION .text:CODE:REORDER(1)
UART2_IRQHandler
B UART2_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK PWM1_IRQHandler
SECTION .text:CODE:REORDER(1)
PWM1_IRQHandler
B PWM1_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
;PUBWEAK SPIFI_IRQHandler
;SECTION .text:CODE:REORDER(1)
;SPIFI_IRQHandler
;B SPIFI_IRQHandler
PUBWEAK SSP0_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP0_IRQHandler
B SSP0_IRQHandler
PUBWEAK SSP1_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP1_IRQHandler
B SSP1_IRQHandler
PUBWEAK PLL0_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL0_IRQHandler
B PLL0_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK EINT0_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT0_IRQHandler
B EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT1_IRQHandler
B EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT2_IRQHandler
B EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
SECTION .text:CODE:REORDER(1)
EINT3_IRQHandler
B EINT3_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK BOD_IRQHandler
SECTION .text:CODE:REORDER(1)
BOD_IRQHandler
B BOD_IRQHandler
PUBWEAK USB_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_IRQHandler
B USB_IRQHandler
PUBWEAK CAN_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN_IRQHandler
B CAN_IRQHandler
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK I2S_IRQHandler
SECTION .text:CODE:REORDER(1)
I2S_IRQHandler
B I2S_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK MCI_IRQHandler
SECTION .text:CODE:REORDER(1)
MCI_IRQHandler
B MCI_IRQHandler
PUBWEAK MCPWM_IRQHandler
SECTION .text:CODE:REORDER(1)
MCPWM_IRQHandler
B MCPWM_IRQHandler
PUBWEAK QEI_IRQHandler
SECTION .text:CODE:REORDER(1)
QEI_IRQHandler
B QEI_IRQHandler
PUBWEAK PLL1_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL1_IRQHandler
B PLL1_IRQHandler
PUBWEAK USBActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
USBActivity_IRQHandler
B USBActivity_IRQHandler
PUBWEAK CANActivity_IRQHandler
SECTION .text:CODE:REORDER(1)
CANActivity_IRQHandler
B CANActivity_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK SSP2_IRQHandler
SECTION .text:CODE:REORDER(1)
SSP2_IRQHandler
B SSP2_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK GPIO_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO_IRQHandler
B GPIO_IRQHandler
PUBWEAK PWM0_IRQHandler
SECTION .text:CODE:REORDER(1)
PWM0_IRQHandler
B PWM0_IRQHandler
PUBWEAK EEPROM_IRQHandler
SECTION .text:CODE:REORDER(1)
EEPROM_IRQHandler
B EEPROM_IRQHandler
END

507
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/**********************************************************************
* $Id$ system_LPC177x_8x.c 2011-06-02
*//**
* @file system_LPC177x_8x.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC177x_8x Device Series
*
* ARM Limited (ARM) is supplying this software for use with
* Cortex-M processor based microcontrollers. This file can be
* freely distributed within development tools that are supporting
* such ARM based processors.
*
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#include <stdint.h>
#include "LPC177x_8x.h"
#include "system_LPC177x_8x.h"
#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Controls and Status Register (SCS - address 0x400F C1A0)
// <o1.0> EMC Shift Control Bit
// <i> Controls how addresses are output on the EMC address pins for static memories
// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
//
// <o1.1> EMC Reset Disable Bit
// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
// <i> If 1, EMC is still retained its state through a warm reset
// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
//
// <o1.2> EMC Burst Control
// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
// <0=> Burst enabled (Bit 2 is 0)
// <1=> Bust disbled (Bit 2 is 1)
//
// <o1.3> MCIPWR Active Level
// <i> Selects the active level for the SD card interface signal SD_PWR
// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
//
// <o1.4> Main Oscillator Range Select
// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
//
// <o1.5> Main Oscillator enable
// <i> 0 (zero) means disabled, 1 means enable
//
// <o1.6> Main Oscillator status (Read-Only)
// </h>
//
// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
// <0=> Internal RC oscillator (Bit 0 is 0)
// <1=> Main oscillator (Bit 0 is 1)
// </h>
//
// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
// <i> F_in is in the range of 1 MHz to 25 MHz
// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
//
// <o4.0..4> MSEL: PLL Multiplier Value
// <i> M Value
// <1-32><#-1>
//
// <o4.5..6> PSEL: PLL Divider Value
// <i> P Value
// <0=> 1
// <1=> 2
// <2=> 4
// <3=> 8
// </e>
//
// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
// <i> F_in is in the range of 1 MHz to 25 MHz
// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
//
// <o6.0..4> MSEL: PLL Multiplier Value
// <i> M Value
// <1-32><#-1>
//
// <o6.5..6> PSEL: PLL Divider Value
// <i> P Value
// <0=> 1
// <1=> 2
// <2=> 4
// <3=> 8
// </e>
//
// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
// <i> 0: The divider is turned off. No clock will be provided to the CPU
// <i> n: The input clock is divided by n to produce the CPU clock
// <0-31>
//
// <o7.8> CCLKSEL: Select the input to the divider of CPU clock
// <0=> sysclk clock is used
// <1=> Main PLL0 clock is used
// </h>
//
// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
// <0=> Divider is off and no clock provides to USB subsystem
// <4=> Divider value is 4 (The source clock is divided by 4)
// <6=> Divider value is 6 (The source clock is divided by 6)
//
// <o8.8..9> USBSEL: Select the source for USB clock divider
// <i> When CPU clock is selected, the USB can be accessed
// <i> by software but cannot perform USB functions
// <0=> sysclk clock (the clock input to PLL0)
// <1=> The clock output from PLL0
// <2=> The clock output from PLL1
// </h>
//
// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
// <o9.0> EMCDIV: Set the divider for EMC clock
// <0=> Divider value is 1
// <1=> Divider value is 2 (EMC clock is equal a half of input clock)
// </h>
//
// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
// <o10.0..4> PCLKDIV: APB Peripheral clock divider
// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
// <i> n: The input clock is divided by n to produce the APB peripheral clock
// <0-31>
// </h>
//
// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
// <o11.0> PCLCD: LCD controller power/clock enable (bit 0)
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
// <o11.3> PCUART0: UART 0 power/clock enable (bit 3)
// <o11.4> PCUART1: UART 1 power/clock enable (bit 4)
// <o11.5> PCPWM0: PWM0 power/clock enable (bit 5)
// <o11.6> PCPWM1: PWM1 power/clock enable (bit 6)
// <o11.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
// <o11.8> PCUART4: UART 4 power/clock enable (bit 8)
// <o11.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
// <o11.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
// <o11.11> PCEMC: External Memory Controller power/clock enable (bit 11)
// <o11.12> PCADC: A/D converter power/clock enable (bit 12)
// <o11.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
// <o11.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
// <o11.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
// <o11.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
// <o11.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
// <o11.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
// <o11.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
// <o11.22> PCTIM2: Timer 2 power/clock enable (bit 22)
// <o11.23> PCTIM3: Timer 3 power/clock enable (bit 23)
// <o11.24> PCUART2: UART 2 power/clock enable (bit 24)
// <o11.25> PCUART3: UART 3 power/clock enable (bit 25)
// <o11.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
// <o11.27> PCI2S: I2S interface power/clock enable (bit 27)
// <o11.28> PCSDC: SD Card interface power/clock enable (bit 28)
// <o11.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
// <o11.30> PCENET: Ethernet block power/clock enable (bit 30)
// <o11.31> PCUSB: USB interface power/clock enable (bit 31)
// </h>
//
// <h> Clock Output Configuration Register (CLKOUTCFG)
// <o12.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
// <0=> CPU clock
// <1=> Main Oscillator
// <2=> Internal RC Oscillator
// <3=> USB clock
// <4=> RTC Oscillator
// <5=> unused
// <6=> Watchdog Oscillator
//
// <o12.4..7> CLKOUTDIV: Output Clock Divider
// <1-16><#-1>
//
// <o12.8> CLKOUT_EN: CLKOUT enable
// </h>
//
// </e>
*/
#define CLOCK_SETUP 1
#define SCS_Val 0x00000021
#define CLKSRCSEL_Val 0x00000001
#define PLL0_SETUP 1
#define PLL0CFG_Val 0x00000009
#define PLL1_SETUP 1
#define PLL1CFG_Val 0x00000023
#define CCLKSEL_Val 0x00000101
#define USBCLKSEL_Val 0x00000201
#define EMCCLKSEL_Val 0x00000001
#define PCLKSEL_Val 0x00000002
#define PCONP_Val 0x042887DE
#define CLKOUTCFG_Val 0x00000100
/*--------------------- Flash Accelerator Configuration ----------------------
//
// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
// <o1.12..15> FLASHTIM: Flash Access Time
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
// <5=> 6 CPU clocks (for any CPU clock)
// </e>
*/
#define FLASH_SETUP 1
#define FLASHCFG_Val 0x00005000
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
#error "SCS: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
#error "CLKSRCSEL: Value out of range!"
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
#error "PLL0CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
#error "PLL1CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
#error "CCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
#error "USBCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
#error "EMCCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
#error "PCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
#error "PCONP: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
#error "CLKOUTCFG: Invalid values of reserved bits!"
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
#warning "FLASHCFG: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/* pll_out_clk = F_cco / (2 × P)
F_cco = pll_in_clk × M × 2 × P */
#define __M ((PLL0CFG_Val & 0x1F) + 1)
#define __PLL0_CLK(__F_IN) (__F_IN * __M)
#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
/* Determine core clock frequency according to settings */
#if (CLOCK_SETUP) /* Clock Setup */
#if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
#error "Main Oscillator is selected as clock source but is not enabled!"
#endif
#if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
#error "Main PLL is selected as clock source but is not enabled!"
#endif
#if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
#define __PER_CLK (IRC_OSC/ __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
#define __PER_CLK (OSC_CLK/ __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
#endif
#else /* cclk = pll_clk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
#endif
#endif
#else
#define __CORE_CLK (IRC_OSC)
#define __PER_CLK (IRC_OSC)
#define __EMC_CLK (__CORE_CLK)
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
be updated after call SystemCoreClockUpdate, should be 48MHz*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
}
else { /* sysclk = osc_clk */
if ((LPC_SC->SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
}
}
}
else { /* cclk = pll_clk */
if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
EMCClock = SystemCoreClock / emc_div;
}
else { /* sysclk = osc_clk */
if ((LPC_SC->SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
EMCClock = SystemCoreClock / emc_div;
}
}
}
}
/* ---update USBClock------------------*/
if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
{
switch (LPC_SC->USBCLKSEL & 0x1F)
{
case 0:
USBClock = 0; //no clock will be provided to the USB subsystem
break;
case 4:
case 6:
{
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
USBClock = OSC_CLK * mul / usb_div;
else //pll_clk_in = irc_clk
USBClock = IRC_OSC * mul / usb_div;
}
break;
default:
USBClock = 0; /* this should never happen! */
}
}
else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
{
if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
else //pll1_clk_in = irc_clk
USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
}
else
USBClock = 0; /* this should never happen! */
}
/* Determine clock frequency according to clock register values */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (CLOCK_SETUP) /* Clock Setup */
LPC_SC->SCS = SCS_Val;
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
}
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
#if (PLL0_SETUP)
LPC_SC->PLL0CFG = PLL0CFG_Val;
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
#endif
#if (PLL1_SETUP)
LPC_SC->PLL1CFG = PLL1CFG_Val;
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
#endif
LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
LPC_SC->PBOOST |= 0x03; /* Power Boost control */
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
#endif
#ifdef __RAM_MODE__
SCB->VTOR = 0x10000000 & 0x3FFFFF80;
#else
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
#endif
SystemCoreClockUpdate();
}

571
bsp/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c Normal file
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@ -0,0 +1,571 @@
/**********************************************************************
* $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
*//**
* @file system_LPC407x_8x_177x_8x.c
* @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
* for the NXP LPC407x_8x_177x_8x Device Series
*
* ARM Limited (ARM) is supplying this software for use with
* Cortex-M processor based microcontrollers. This file can be
* freely distributed within development tools that are supporting
* such ARM based processors.
*
* @version 1.2
* @date 20. June. 2012
* @author NXP MCU SW Application Team
*
* Copyright(C) 2012, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include <stdint.h>
#include "LPC407x_8x_177x_8x.h"
#include "system_LPC407x_8x_177x_8x.h"
#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> System Controls and Status Register (SCS - address 0x400F C1A0)
// <o1.0> EMC Shift Control Bit
// <i> Controls how addresses are output on the EMC address pins for static memories
// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
// <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
//
// <o1.1> EMC Reset Disable Bit
// <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
// <i> If 1, EMC is still retained its state through a warm reset
// <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
// <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
//
// <o1.2> EMC Burst Control
// <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
// <0=> Burst enabled (Bit 2 is 0)
// <1=> Bust disbled (Bit 2 is 1)
//
// <o1.3> MCIPWR Active Level
// <i> Selects the active level for the SD card interface signal SD_PWR
// <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
// <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
//
// <o1.4> Main Oscillator Range Select
// <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
// <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
//
// <o1.5> Main Oscillator enable
// <i> 0 (zero) means disabled, 1 means enable
//
// <o1.6> Main Oscillator status (Read-Only)
// </h>
//
// <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
// <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
// <0=> Internal RC oscillator (Bit 0 is 0)
// <1=> Main oscillator (Bit 0 is 1)
// </h>
//
// <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
// <i> F_in is in the range of 1 MHz to 25 MHz
// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
//
// <o4.0..4> MSEL: PLL Multiplier Value
// <i> M Value
// <1-32><#-1>
//
// <o4.5..6> PSEL: PLL Divider Value
// <i> P Value
// <0=> 1
// <1=> 2
// <2=> 4
// <3=> 8
// </e>
//
// <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
// <i> F_in is in the range of 1 MHz to 25 MHz
// <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
// <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
//
// <o6.0..4> MSEL: PLL Multiplier Value
// <i> M Value
// <1-32><#-1>
//
// <o6.5..6> PSEL: PLL Divider Value
// <i> P Value
// <0=> 1
// <1=> 2
// <2=> 4
// <3=> 8
// </e>
//
// <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
// <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
// <i> 0: The divider is turned off. No clock will be provided to the CPU
// <i> n: The input clock is divided by n to produce the CPU clock
// <0-31>
//
// <o7.8> CCLKSEL: Select the input to the divider of CPU clock
// <0=> sysclk clock is used
// <1=> Main PLL0 clock is used
// </h>
//
// <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
// <0=> Divider is off and no clock provides to USB subsystem
// <4=> Divider value is 4 (The source clock is divided by 4)
// <6=> Divider value is 6 (The source clock is divided by 6)
//
// <o8.8..9> USBSEL: Select the source for USB clock divider
// <i> When CPU clock is selected, the USB can be accessed
// <i> by software but cannot perform USB functions
// <0=> sysclk clock (the clock input to PLL0)
// <1=> The clock output from PLL0
// <2=> The clock output from PLL1
// </h>
//
// <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
// <o9.0> EMCDIV: Set the divider for EMC clock
// <0=> Divider value is 1
// <1=> Divider value is 2 (EMC clock is equal a half of input clock)
// </h>
//
// <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
// <o10.0..4> PCLKDIV: APB Peripheral clock divider
// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
// <i> n: The input clock is divided by n to produce the APB peripheral clock
// <0-31>
// </h>
//
// <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
// <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
// <i> 0: The divider is turned off. No clock will be provided to the SPIFI
// <i> n: The input clock is divided by n to produce the SPIFI clock
// <0-31>
//
// <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
// <0=> sysclk clock (the clock input to PLL0)
// <1=> The clock output from PLL0
// <2=> The clock output from PLL1
// </h>
//
// <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
// <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
// <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
// <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
// <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
// <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
// <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
// <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
// <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
// <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
// <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
// <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
// <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
// <o12.12> PCADC: A/D converter power/clock enable (bit 12)
// <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
// <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
// <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
// <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
// <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
// <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
// <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
// <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
// <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
// <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
// <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
// <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
// <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
// <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
// <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
// <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
// <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
// <o12.31> PCUSB: USB interface power/clock enable (bit 31)
// </h>
//
// <h> Clock Output Configuration Register (CLKOUTCFG)
// <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
// <0=> CPU clock
// <1=> Main Oscillator
// <2=> Internal RC Oscillator
// <3=> USB clock
// <4=> RTC Oscillator
// <5=> unused
// <6=> Watchdog Oscillator
//
// <o13.4..7> CLKOUTDIV: Output Clock Divider
// <1-16><#-1>
//
// <o13.8> CLKOUT_EN: CLKOUT enable
// </h>
//
// </e>
*/
#define CLOCK_SETUP 1
#define SCS_Val 0x00000020
#define CLKSRCSEL_Val 0x00000001
#define PLL0_SETUP 1
#define PLL0CFG_Val 0x0000000a
#define PLL1_SETUP 1
#define PLL1CFG_Val 0x00000023
#define CCLKSEL_Val 0x00000101
#define USBCLKSEL_Val 0x00000201
#define EMCCLKSEL_Val 0x00000001
#define PCLKSEL_Val 0x00000002
#define SPIFICLKSEL_Val 0x00000002
#define PCONP_Val 0x042887DE
#define CLKOUTCFG_Val 0x00000100
#ifdef CORE_M4
#define LPC_CPACR 0xE000ED88
#define SCB_MVFR0 0xE000EF40
#define SCB_MVFR0_RESET 0x10110021
#define SCB_MVFR1 0xE000EF44
#define SCB_MVFR1_RESET 0x11000011
#endif
/*--------------------- Flash Accelerator Configuration ----------------------
//
// <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
// <o1.12..15> FLASHTIM: Flash Access Time
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
// <5=> 6 CPU clocks (for any CPU clock)
// </e>
*/
#define FLASH_SETUP 1
#define FLASHCFG_Val 0x00005000
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
#error "SCS: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
#error "CLKSRCSEL: Value out of range!"
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
#error "PLL0CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
#error "PLL1CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
#error "CCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
#error "USBCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
#error "EMCCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
#error "PCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
#error "PCONP: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
#error "CLKOUTCFG: Invalid values of reserved bits!"
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
#error "FLASHCFG: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/* pll_out_clk = F_cco / (2 ?P)
F_cco = pll_in_clk ?M ?2 ?P */
#define __M ((PLL0CFG_Val & 0x1F) + 1)
#define __PLL0_CLK(__F_IN) (__F_IN * __M)
#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
/* Determine core clock frequency according to settings */
#if (CLOCK_SETUP) /* Clock Setup */
#if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
#error "Main Oscillator is selected as clock source but is not enabled!"
#endif
#if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
#error "Main PLL is selected as clock source but is not enabled!"
#endif
#if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
#define __PER_CLK (IRC_OSC/ __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
#define __PER_CLK (OSC_CLK/ __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
#endif
#else /* cclk = pll_clk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
#define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
#endif
#endif
#else
#define __CORE_CLK (IRC_OSC)
#define __PER_CLK (IRC_OSC)
#define __EMC_CLK (__CORE_CLK)
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
be updated after call SystemCoreClockUpdate, should be 48MHz*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
}
else { /* sysclk = osc_clk */
if ((LPC_SC->SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
}
}
}
else { /* cclk = pll_clk */
if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
EMCClock = SystemCoreClock / emc_div;
}
else { /* sysclk = osc_clk */
if ((LPC_SC->SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
EMCClock = SystemCoreClock / emc_div;
}
}
}
}
/* ---update USBClock------------------*/
if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
{
switch (LPC_SC->USBCLKSEL & 0x1F)
{
case 0:
USBClock = 0; //no clock will be provided to the USB subsystem
break;
case 4:
case 6:
{
uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
USBClock = OSC_CLK * mul / usb_div;
else //pll_clk_in = irc_clk
USBClock = IRC_OSC * mul / usb_div;
}
break;
default:
USBClock = 0; /* this should never happen! */
}
}
else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
{
if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
else //pll1_clk_in = irc_clk
USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
}
else
USBClock = 0; /* this should never happen! */
}
/* Determine clock frequency according to clock register values */
#ifdef CORE_M4
void fpu_init(void)
{
// from arm trm manual:
// ; CPACR is located at address 0xE000ED88
// LDR.W R0, =0xE000ED88
// ; Read CPACR
// LDR R1, [R0]
// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
// ORR R1, R1, #(0xF << 20)
// ; Write back the modified value to the CPACR
// STR R1, [R0]
volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
volatile uint32_t Cpacr;
volatile uint32_t Mvfr0;
volatile uint32_t Mvfr1;
char vfpPresent = 0;
Mvfr0 = *regMvfr0;
Mvfr1 = *regMvfr1;
vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
if(vfpPresent)
{
Cpacr = *regCpacr;
Cpacr |= (0xF << 20);
*regCpacr = Cpacr; // enable CP10 and CP11 for full access
}
}
#endif
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifndef __CODE_RED
#ifdef CORE_M4
fpu_init();
#endif
#endif
#if (CLOCK_SETUP) /* Clock Setup */
LPC_SC->SCS = SCS_Val;
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
}
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
#if (PLL0_SETUP)
LPC_SC->PLL0CFG = PLL0CFG_Val;
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
#endif
#if (PLL1_SETUP)
LPC_SC->PLL1CFG = PLL1CFG_Val;
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
#endif
LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
LPC_SC->PBOOST |= 0x03; /* Power Boost control */
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
#endif
#ifndef __CODE_RED
#ifdef __RAM_MODE__
SCB->VTOR = 0x10000000 & 0x3FFFFF80;
#else
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
#endif
#endif
SystemCoreClockUpdate();
}

23
bsp/lpc408x/Libraries/Device/SConscript Normal file
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@ -0,0 +1,23 @@
# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Split('''
NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c
''')
CPPPATH = [cwd + '/NXP/LPC407x_8x_177x_8x/Include', cwd + '/../CMSIS/Include']
CPPDEFINES = ['CORE_M4']
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s']
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')

39
bsp/lpc408x/Libraries/Drivers/SConscript Normal file
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# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Split('''
source/lpc_adc.c
source/lpc_bod.c
source/lpc_can.c
source/lpc_clkpwr.c
source/lpc_crc.c
source/lpc_dac.c
source/lpc_eeprom.c
source/lpc_emc.c
source/lpc_exti.c
source/lpc_gpdma.c
source/lpc_gpio.c
source/lpc_i2c.c
source/lpc_i2s.c
source/lpc_iap.c
source/lpc_lcd.c
source/lpc_mcpwm.c
source/lpc_nvic.c
source/lpc_pinsel.c
source/lpc_pwm.c
source/lpc_qei.c
source/lpc_rtc.c
source/lpc_ssp.c
source/lpc_systick.c
source/lpc_timer.c
source/lpc_uart.c
source/lpc_wwdt.c
''')
CPPPATH = [cwd + '/include']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

114
bsp/lpc408x/Libraries/Drivers/include/debug_frmwrk.h Normal file
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/**********************************************************************
* $Id$ debug_frmwrk.h 2011-06-02
*//**
* @file debug_frmwrk.h
* @brief Contains some utilities that used for debugging through UART
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef __DEBUG_FRMWRK_H_
#define __DEBUG_FRMWRK_H_
#include "lpc_uart.h"
#define USED_UART_DEBUG_PORT 0
#define NUM_SKIPPED_ALLOWED (10)
#define DBG_GETVAL_IN_DEC (0)
#define DBG_GETVAL_IN_HEX (1)
//#define DBG_GETVAL_IN_CHARS (2)
#if (USED_UART_DEBUG_PORT == 0)
#define DEBUG_UART_PORT (UART_0)
#elif (USED_UART_DEBUG_PORT == 1)
#define DEBUG_UART_PORT (UART_1)
#elif (USED_UART_DEBUG_PORT == 2)
#define DEBUG_UART_PORT (UART_2)
#elif (USED_UART_DEBUG_PORT == 3)
#define DEBUG_UART_PORT (UART_3)
#elif (USED_UART_DEBUG_PORT == 4)
#define DEBUG_UART_PORT (UART_4)
#else
#error "Invalid UART port selection!"
#endif
#define _DBG(x) _db_msg(DEBUG_UART_PORT, x)
#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x)
#define _DBC(x) _db_char(DEBUG_UART_PORT, x)
#define _DBD(x) _db_dec(DEBUG_UART_PORT, x)
#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x)
#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x)
#define _DBH(x) _db_hex(DEBUG_UART_PORT, x)
#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x)
#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x)
#define _DBH_(x) _db_hex_(DEBUG_UART_PORT, x)
#define _DBH16_(x) _db_hex_16_(DEBUG_UART_PORT, x)
#define _DBH32_(x) _db_hex_32_(DEBUG_UART_PORT, x)
#define _DG _db_get_char(DEBUG_UART_PORT)
#define _DG_NONBLOCK(c) _db_get_char_nonblocking(DEBUG_UART_PORT,c)
#define _DGV(option, numCh, val) _db_get_val(DEBUG_UART_PORT, option, numCh, val)
//void _printf (const char *format, ...);
extern void (*_db_msg)(UART_ID_Type UartID, const void *s);
extern void (*_db_msg_)(UART_ID_Type UartID, const void *s);
extern void (*_db_char)(UART_ID_Type UartID, uint8_t ch);
extern void (*_db_dec)(UART_ID_Type UartID, uint8_t decn);
extern void (*_db_dec_16)(UART_ID_Type UartID, uint16_t decn);
extern void (*_db_dec_32)(UART_ID_Type UartID, uint32_t decn);
extern void (*_db_hex)(UART_ID_Type UartID, uint8_t hexn);
extern void (*_db_hex_16)(UART_ID_Type UartID, uint16_t hexn);
extern void (*_db_hex_32)(UART_ID_Type UartID, uint32_t hexn);
extern void (*_db_hex_)(UART_ID_Type UartID, uint8_t hexn);
extern void (*_db_hex_16_)(UART_ID_Type UartID, uint16_t hexn);
extern void (*_db_hex_32_)(UART_ID_Type UartID, uint32_t hexn);
extern uint8_t (*_db_get_char)(UART_ID_Type UartID);
extern Bool (*_db_get_char_nonblocking)(UART_ID_Type UartID, uint8_t* c);
extern uint8_t (*_db_get_val)(UART_ID_Type UartID, uint8_t option, uint8_t numCh, uint32_t * val);
uint8_t UARTGetValue (UART_ID_Type UartID, uint8_t option,
uint8_t numCh, uint32_t* val);
void UARTPutChar (UART_ID_Type UartID, uint8_t ch);
void UARTPuts(UART_ID_Type UartID, const void *str);
void UARTPuts_(UART_ID_Type UartID, const void *str);
void UARTPutDec(UART_ID_Type UartID, uint8_t decnum);
void UARTPutDec16(UART_ID_Type UartID, uint16_t decnum);
void UARTPutDec32(UART_ID_Type UartID, uint32_t decnum);
void UARTPutHex (UART_ID_Type UartID, uint8_t hexnum);
void UARTPutHex16 (UART_ID_Type UartID, uint16_t hexnum);
void UARTPutHex32 (UART_ID_Type UartID, uint32_t hexnum);
uint8_t UARTGetChar (UART_ID_Type UartID);
Bool UARTGetCharInNonBlock(UART_ID_Type UartID, uint8_t* c);
void debug_frmwrk_init(void);
#endif /* __DEBUG_FRMWRK_H_ */

156
bsp/lpc408x/Libraries/Drivers/include/lpc177x_8x_libcfg_default.h Normal file
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/**********************************************************************
* $Id$ lpc17xx_libcfg.h 2010-05-21
***
* @file lpc17xx_libcfg.h
* @brief Library configuration file
* @version 2.0
* @date 21. May. 2010
* @author NXP MCU SW Application Team
*
* Copyright(C) 2010, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef _LPC177x_8x_LIBCFG_H_
#define _LPC177x_8x_LIBCFG_H_
#include "lpc_types.h"
/************************** DEBUG MODE DEFINITIONS *********************************/
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
the "CHECK_PARAM" macro in the FW library code */
#define DEBUG
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
/* Comment the line below to disable the specific peripheral inclusion */
/* DEBUG_FRAMWORK -------------------- */
#define _DBGFWK
/* Clock & Power -------------------- */
#define _CLKPWR
/* CRC -------------------- */
#define _CRC
/* GPIO ------------------------------- */
#define _GPIO
/* NVIC ------------------------------- */
#define _NVIC
/* PINSEL ------------------------------- */
#define _PINSEL
/* EXTI ------------------------------- */
#define _EXTI
/* EMC ------------------------------- */
#define _EMC
/* UART ------------------------------- */
#define _UART
/* SPI ------------------------------- */
#define _SPI
/* SYSTICK --------------------------- */
#define _SYSTICK
/* SSP ------------------------------- */
#define _SSP
/* I2C ------------------------------- */
#define _I2C
/* TIMER ------------------------------- */
#define _TIM
/* WDT ------------------------------- */
#define _WDT
/* GPDMA ------------------------------- */
#define _GPDMA
/* DAC ------------------------------- */
#define _DAC
/* ADC ------------------------------- */
#define _ADC
/* EEPROM ------------------------------- */
#define _EEPROM
/* PWM ------------------------------- */
#define _PWM
/* RTC ------------------------------- */
#define _RTC
/* I2S ------------------------------- */
#define _I2S
/* USB device ------------------------------- */
#define _USBDEV
#ifdef _USBDEV
#define _USB_DEV_AUDIO
#define _USB_DEV_MASS_STORAGE
#define _USB_DEV_HID
#define _USB_DEV_VIRTUAL_COM
#endif /*_USBDEV*/
/* USB Host ------------------------------- */
#define _USBHost
/* QEI ------------------------------- */
#define _QEI
/* MCPWM ------------------------------- */
#define _MCPWM
/* CAN--------------------------------*/
#define _CAN
/* EMAC ------------------------------ */
#define _EMAC
/* LCD ------------------------------ */
#define _LCD
/* MCI ------------------------------ */
#define _MCI
/* IAP------------------------------ */
#define _IAP
/* BOD------------------------------ */
#define _BOD
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
#endif /* _LPC177x_8x_LIBCFG_H_ */

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/**********************************************************************
* $Id$ lpc_adc.h 2011-06-02
*//**
* @file lpc_adc.h
* @brief Contains all macro definitions and function prototypes
* support for ADC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup ADC ADC (Analog-to-Digital Converter)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_ADC_H_
#define __LPC_ADC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for ADC control register
**********************************************************************/
/** Selects which of the AD0.0:7 pins (channels) is (are) to be sampled and converted */
#define ADC_CR_CH_SEL(n) ((1UL << n))
/** The APB clock (PCLK) is divided by (this value plus one)
* to produce the clock for the A/D */
#define ADC_CR_CLKDIV(n) ((n<<8))
/** Repeated conversions A/D enable bit */
#define ADC_CR_BURST ((1UL<<16))
/** ADC convert in power down mode; if 0, it's in power down mode; if 1, it's in normal
* operation mode */
#define ADC_CR_PDN ((1UL<<21))
/** Start mask bits */
#define ADC_CR_START_MASK ((7UL<<24))
/** Select Start Mode controll the AD Converter in case the Burst bit is 0 (zero) */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
/** Start conversion now */
#define ADC_CR_START_NOW ((1UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
#define ADC_CR_START_EINT0 ((2UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
#define ADC_CR_START_CAP01 ((3UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
#define ADC_CR_START_MAT01 ((4UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
#define ADC_CR_START_MAT03 ((5UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
#define ADC_CR_START_MAT10 ((6UL<<24))
/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
#define ADC_CR_START_MAT11 ((7UL<<24))
/** Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_CR_EDGE ((1UL<<27))
/*********************************************************************//**
* Macro defines for ADC Global Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion
* (in 12-bit value) */
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
/** These bits contain the channel from which the LS bits were converted */
#define ADC_GDR_CH(n) (((n>>24)&0x7))
/** This bits is used to mask for Channel */
#define ADC_GDR_CH_MASK ((7UL<<24))
/** This bit is 1 in burst mode if the results of one or
* more conversions was (were) lost */
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes */
#define ADC_GDR_DONE_FLAG ((1UL<<31))
/*********************************************************************//**
* Macro defines for ADC Interrupt register
**********************************************************************/
/** These bits allow control over which A/D channels generate
* interrupts for conversion completion */
#define ADC_INTEN_CH(n) ((1UL<<n))
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
#define ADC_INTEN_GLOBAL ((1UL<<8))
/*********************************************************************//**
* Macro defines for ADC Data register
**********************************************************************/
/** When DONE is 1, this field contains result value of ADC conversion */
#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
/** This bit is set to 1 when an A/D conversion completes. It is cleared
* when this register is read */
#define ADC_DR_DONE_FLAG ((1UL<<31))
/*********************************************************************//**
* Macro defines for ADC Status register
**********************************************************************/
/** These bits mirror the DONE status flags that appear in the result
* register for each A/D channel */
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
/** These bits mirror the OVERRRUN status flags that appear in the
* result register for each A/D channel */
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
/** This bit is the A/D interrupt flag */
#define ADC_STAT_INT_FLAG ((1UL<<16))
/*********************************************************************//**
* Macro defines for ADC Trim register
**********************************************************************/
/** Offset trim bits for ADC operation */
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
/** Written to boot code*/
#define ADC_TRIM(n) (((n&0xF)<<8))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup ADC_Public_Types ADC Public Types
* @{
*/
/*********************************************************************//**
* @brief ADC enumeration
**********************************************************************/
/** @brief Channel Selection */
typedef enum
{
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
ADC_CHANNEL_1, /*!< Channel 1 */
ADC_CHANNEL_2, /*!< Channel 2 */
ADC_CHANNEL_3, /*!< Channel 3 */
ADC_CHANNEL_4, /*!< Channel 4 */
ADC_CHANNEL_5, /*!< Channel 5 */
ADC_CHANNEL_6, /*!< Channel 6 */
ADC_CHANNEL_7 /*!< Channel 7 */
}ADC_CHANNEL_SELECTION;
/** @brief Type of start option */
typedef enum
{
ADC_START_CONTINUOUS = 0, /*!< Continuous mode */
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
* by bit 27 occurs on P2.10/EINT0 */
ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
* by bit 27 occurs on P1.27/CAP0.1 */
ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
* by bit 27 occurs on MAT0.1 */
ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
* by bit 27 occurs on MAT0.3 */
ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
* by bit 27 occurs on MAT1.0 */
ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
* by bit 27 occurs on MAT1.1 */
} ADC_START_OPT;
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
typedef enum
{
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
*on the selected CAP/MAT signal */
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
*on the selected CAP/MAT signal */
} ADC_START_ON_EDGE_OPT;
/** @brief* ADC type interrupt enum */
typedef enum
{
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
ADC_ADINTEN1, /*!< Interrupt channel 1 */
ADC_ADINTEN2, /*!< Interrupt channel 2 */
ADC_ADINTEN3, /*!< Interrupt channel 3 */
ADC_ADINTEN4, /*!< Interrupt channel 4 */
ADC_ADINTEN5, /*!< Interrupt channel 5 */
ADC_ADINTEN6, /*!< Interrupt channel 6 */
ADC_ADINTEN7, /*!< Interrupt channel 7 */
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
}ADC_TYPE_INT_OPT;
/** @brief ADC Data status */
typedef enum
{
ADC_DATA_BURST = 0, /*Burst bit*/
ADC_DATA_DONE /*Done bit*/
}ADC_DATA_STATUS;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup ADC_Public_Functions ADC Public Functions
* @{
*/
/* Init/DeInit ADC peripheral ----------------*/
void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
/* Enable/Disable ADC functions --------------*/
void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
/* Configure ADC functions -------------------*/
void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
/* Get ADC information functions -------------------*/
uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC_ADC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_bod.h 2011-12-09
*//**
* @file lpc_bod.h
* @brief Contain definitions & functions related to BOD.
* @version 1.0
* @date 09 December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup BOD BOD (Brown-Out Detector)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/#ifndef __LPC_BOD_H
#define __LPC_BOD_H
#include "lpc_types.h"
/** @defgroup BOD_Private_Macros BOD Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/**********************************************************************
** Power Mode Control register definitions
**********************************************************************/
#define BOD_PCON_BODRPM (0x01 << 2)
#define BOD_PCON_BOGD (0x01 << 3)
#define BOD_PCON_BORD (0x01 << 4)
/**********************************************************************
** Reset Source Identification Register definitions
**********************************************************************/
#define BOD_RSID_POR (0x01 << 0)
#define BOD_RSID_BODR (0x01 << 3)
/**
* @}
*/
/** @defgroup BOD_Public_Types BOD Public Types
* @{
*/
/**
* @brief The field to configurate BOD
*/
typedef struct
{
uint8_t Enabled; /**< Enable BOD Circuit */
uint8_t PowerReduced; /**< if ENABLE, BOD will be turned off in Power-down mode or Deep Sleep mode */
/**< So, BOD can't be used to wake-up from these mode. */
uint8_t ResetOnVoltageDown; /**< if ENABLE, reset the device when the VDD(REG)(3V3) voltage < the BOD reset trip level */
}BOD_Config_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup BOD_Public_Functions BOD Public Functions
* @{
*/
void BOD_Init( BOD_Config_Type* pConfig );
int32_t BOD_ResetSourceStatus(void);
void BOD_ResetSourceClr(void);
/**
* @}
*/
#endif /* end __LPC_BOD_H */
/**
* @}
*/
/*****************************************************************************
** End Of File
******************************************************************************/

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/**********************************************************************
* $Id$ lpc_clkpwr.h 2011-06-02
*//**
* @file lpc_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on
* LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR CLKPWR (Clock Power)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_CLKPWR_H_
#define __LPC_CLKPWR_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#include "system_LPC407x_8x_177x_8x.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
* @{
*/
/********************************************************************
* Clock Source Selection Definitions
**********************************************************************/
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
/********************************************************************
* Clock type/domain Definitions (calculated from input and pre-configuration
* parameter(s)
**********************************************************************/
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
/** LCD controller power/clock control bit */
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
/** Timer/Counter 0 power/clock control bit */
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
/* Timer/Counter 1 power/clock control bit */
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
/** UART0 power/clock control bit */
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
/** UART1 power/clock control bit */
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
/** PWM0 power/clock control bit */
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
/** PWM1 power/clock control bit */
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
/** The I2C0 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
/** UART4 power/clock control bit */
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
/** The RTC power/clock control bit */
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
/** The SSP1 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
/** External Memory controller power/clock control bit */
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
/** A/D converter 0 (ADC0) power/clock control bit */
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
/** CAN Controller 1 power/clock control bit */
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
/** CAN Controller 2 power/clock control bit */
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
/** GPIO power/clock control bit */
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
/** Motor Control PWM */
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
/** Quadrature Encoder Interface power/clock control bit */
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
/** The I2C1 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
/** The SSP2 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
/** The SSP0 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
/** Timer 2 power/clock control bit */
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
/** Timer 3 power/clock control bit */
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
/** UART 2 power/clock control bit */
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
/** UART 3 power/clock control bit */
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
/** I2C interface 2 power/clock control bit */
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
/** I2S interface power/clock control bit*/
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
/** SD card interface power/clock control bit */
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
/** GP DMA function power/clock control bit*/
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
/** Ethernet block power/clock control bit*/
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
/** USB interface power/clock control bit*/
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
/**
* @}
*/
/* External clock variable from system_LPC407x_8x_177x_8x.h */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
/* External clock variable from lpc_clkpwr.h */
extern uint32_t USBClock; /*!< USB Frequency */
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
* @{
*/
void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal);
uint32_t CLKPWR_GetCLK(uint8_t ClkType);
void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState);
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState);
void CLKPWR_Sleep(void);
void CLKPWR_DeepSleep(void);
void CLKPWR_PowerDown(void);
void CLKPWR_DeepPowerDown(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_CLKPWR_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_crc.h 2011-06-02
*//**
* @file lpc_crc.h
* @brief Contains all macro definitions and function prototypes
* support for CRC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CRC CRC (Cyclic Redundancy Check)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC__CRC_H_
#define __LPC__CRC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
/*********************************************************************//**
* Macro defines for CRC mode register
**********************************************************************/
#define CRC_BIT_RVS_WR (1<<2)
#define CRC_CMPL_WR (1<<3)
#define CRC_BIT_RVS_SUM (1<<4)
#define CRC_CMPL_SUM (1<<5)
/**
* @}
*/
/* Private types ------------------------------------------------------------- */
typedef enum
{
CRC_POLY_CRCCCITT = 0, /** CRC CCITT polynomial */
CRC_POLY_CRC16, /** CRC-16 polynomial */
CRC_POLY_CRC32 /** CRC-32 polynomial */
}CRC_Type;
typedef enum
{
CRC_WR_8BIT = 1, /** 8-bit write: 1-cycle operation */
CRC_WR_16BIT = 2, /** 16-bit write: 2-cycle operation */
CRC_WR_32BIT = 4, /** 32-bit write: 4-cycle operation */
}CRC_WR_SIZE;
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CRC_Public_Functions CRC Public Functions
* @{
*/
void CRC_Init(CRC_Type CRCType);
void CRC_Reset(void);
uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType);
uint32_t CRC_CalcBlockChecksum(void *blockdata, uint32_t blocksize, CRC_WR_SIZE SizeType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_CRC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_dac.h 2011-06-02
*//**
* @file lpc_dac.h
* @brief Contains all macro definitions and function prototypes
* support for DAC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup DAC DAC (Digital-to-Analog Converter)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_DAC_H_
#define __LPC_DAC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
/** After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 × VREF */
#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
* and the maximum current is 700 microAmpere
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
* and the maximum current is 350 microAmpere */
#define DAC_BIAS_EN ((uint32_t)(1<<16))
/** Value to reload interrupt DMA counter */
#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
/** DCAR double buffering */
#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
/** DCAR Time out count enable */
#define DAC_CNT_ENA ((uint32_t)(1<<2))
/** DCAR DMA access */
#define DAC_DMA_ENA ((uint32_t)(1<<3))
/** DCAR DACCTRL mask bit */
#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
/** Macro to determine if it is valid DAC peripheral */
#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
/** Macro to check DAC current optional parameter */
#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
||(OPTION == DAC_MAX_CURRENT_350uA))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup DAC_Public_Types DAC Public Types
* @{
*/
/**
* @brief Current option in DAC configuration option */
typedef enum
{
DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
and the maximum current is 700 uA */
DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
and the maximum current is 350 uA */
} DAC_CURRENT_OPT;
/**
* @brief Configuration for DAC converter control register */
typedef struct
{
uint8_t DBLBUF_ENA; /**<
- If 0: Disable DACR double buffering
- If 1: when bit CNT_ENA, enable DACR double buffering feature
*/
uint8_t CNT_ENA; /*!<
- If 0: Time out counter is disable
-1: Time out conter is enable
*/
uint8_t DMA_ENA; /*!<
- If 0: DMA access is disable
- If 1: DMA burst request
*/
uint8_t RESERVED;
} DAC_CONVERTER_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup DAC_Public_Functions DAC Public Functions
* @{
*/
void DAC_Init(uint8_t DAC_Id);
void DAC_UpdateValue (uint8_t DAC_Id, uint32_t dac_value);
void DAC_SetBias (uint8_t DAC_Id,uint32_t bias);
void DAC_ConfigDAConverterControl (uint8_t DAC_Id,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
void DAC_SetDMATimeOut(uint8_t DAC_Id,uint32_t time_out);
uint8_t DAC_IsIntRequested(uint8_t DAC_Id);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_DAC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_eeprom.h 2011-06-02
*//**
* @file lpc_eeprom.h
* @brief Contains all macro definitions and function prototypes
* support for EEPROM firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EEPROM EEPROM (Electrically Erasable Programmable Read-Only Memory)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_EEPROM_H_
#define __LPC_EEPROM_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup EEPROM_Private_Macros EEPROM Private Macros
* @{
*/
/* -------------------------- BIT DEFINITIONS --------------------------------- */
/*********************************************************************//**
* Macro defines for EEPROM command register
**********************************************************************/
#define EEPROM_CMD_8_BIT_READ (0)
#define EEPROM_CMD_16_BIT_READ (1)
#define EEPROM_CMD_32_BIT_READ (2)
#define EEPROM_CMD_8_BIT_WRITE (3)
#define EEPROM_CMD_16_BIT_WRITE (4)
#define EEPROM_CMD_32_BIT_WRITE (5)
#define EEPROM_CMD_ERASE_PRG_PAGE (6)
#define EEPROM_CMD_RDPREFETCH (1<<3)
#define EEPROM_PAGE_SIZE 64
#define EEPROM_PAGE_NUM 63
/*********************************************************************//**
* Macro defines for EEPROM address register
**********************************************************************/
#define EEPROM_PAGE_OFFSET(n) (n&0x3F)
#define EEPROM_PAGE_ADRESS(n) ((n&0x3F)<<6)
/*********************************************************************//**
* Macro defines for EEPROM write data register
**********************************************************************/
#define EEPROM_WDATA_8_BIT(n) (n&0x000000FF)
#define EEPROM_WDATA_16_BIT(n) (n&0x0000FFFF)
#define EEPROM_WDATA_32_BIT(n) (n&0xFFFFFFFF)
/*********************************************************************//**
* Macro defines for EEPROM read data register
**********************************************************************/
#define EEPROM_RDATA_8_BIT(n) (n&0x000000FF)
#define EEPROM_RDATA_16_BIT(n) (n&0x0000FFFF)
#define EEPROM_RDATA_32_BIT(n) (n&0xFFFFFFFF)
/*********************************************************************//**
* Macro defines for EEPROM power down register
**********************************************************************/
#define EEPROM_PWRDWN (1<<0)
#define EEPROM_ENDOF_RW (26)
#define EEPROM_ENDOF_PROG (28)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup EEPROM_Public_Types EEPROM Public Types
* @{
*/
typedef enum
{
MODE_8_BIT = 0,
MODE_16_BIT,
MODE_32_BIT
}EEPROM_Mode_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup EEPROM_Public_Functions EEPROM Public Functions
* @{
*/
void EEPROM_Init(void);
void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
void EEPROM_Erase(uint16_t address);
void EEPROM_PowerDown(FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_EEPROM_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_emac.h 2011-06-02
*//**
* @file lpc_emac.h
* @brief Contains all macro definitions and function prototypes
* support for Ethernet MAC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMAC EMAC (Ethernet Media Access Controller)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_EMAC_H_
#define __LPC_EMAC_H_
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @defgroup EMAC_Private_Macros EMAC Private Macros
* @{
*/
/* Ethernet MAC register definitions --------------------------------------------------------------------- */
/* MAC Configuration Register 1 */
#define EMAC_MAC1_MASK 0xcf1f /*MAC1 register mask*/
#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
/* MAC Configuration Register 2 */
#define EMAC_MAC2_MASK 0x73ff /*MAC2 register mask*/
#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
/* Back-to-Back Inter-Packet-Gap Register */
/** Programmable field representing the nibble time offset of the minimum possible period
* between the end of any transmitted packet to the beginning of the next */
#define EMAC_IPGT_BBIPG(n) (n&0x7F)
/** Recommended value for Full Duplex of Programmable field representing the nibble time
* offset of the minimum possible period between the end of any transmitted packet to the
* beginning of the next */
#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
/** Recommended value for Half Duplex of Programmable field representing the nibble time
* offset of the minimum possible period between the end of any transmitted packet to the
* beginning of the next */
#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
/* Non Back-to-Back Inter-Packet-Gap Register */
/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
/** Programmable field representing the optional carrierSense window referenced in
* IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
/* Collision Window/Retry Register */
/** Programmable field specifying the number of retransmission attempts following a collision before
* aborting the packet due to excessive collisions */
#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
/** Programmable field representing the slot time or collision window during which collisions occur
* in properly configured networks */
#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
/** Default value for Collision Window / Retry register */
#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
/* Maximum Frame Register */
/** Represents a maximum receive frame of 1536 octets */
#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
#define EMAC_MAXF_MAXFRMLEN_DEF (0x6000)
/* PHY Support Register */
#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
//#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
/* Test Register */
#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
/* MII Management Configuration Register */
#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
/* MII Management Command Register */
#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
/* MII Management Address Register */
#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
/* MII Management Write Data Register */
#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
/* MII Management Read Data Register */
#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
/* MII Management Indicators Register */
#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
/* Station Address 0 Register */
/* Station Address 1 Register */
/* Station Address 2 Register */
/* Control register definitions --------------------------------------------------------------------------- */
/* Command Register */
#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
/* Status Register */
#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
/* Receive Descriptor Base Address Register */
//
/* Receive Status Base Address Register */
//
/* Receive Number of Descriptors Register */
//
/* Receive Produce Index Register */
//
/* Receive Consume Index Register */
//
/* Transmit Descriptor Base Address Register */
//
/* Transmit Status Base Address Register */
//
/* Transmit Number of Descriptors Register */
//
/* Transmit Produce Index Register */
//
/* Transmit Consume Index Register */
//
/* Transmit Status Vector 0 Register */
#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
/* Transmit Status Vector 1 Register */
#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
/* Receive Status Vector Register */
#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
/* Flow Control Counter Register */
#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
/* Flow Control Status Register */
#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
/* Receive filter register definitions -------------------------------------------------------- */
/* Receive Filter Control Register */
#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
/* Receive Filter WoL Status/Clear Registers */
#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
/* Hash Filter Table LSBs Register */
//
/* Hash Filter Table MSBs Register */
//
/* Module control register definitions ---------------------------------------------------- */
/* Interrupt Status/Enable/Clear/Set Registers */
#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
/* Power Down Register */
#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
/* Descriptor and status formats ------------------------------------------------------ */
/* RX and TX descriptor and status definitions. */
/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE LPC_PERI_RAM_BASE
#define RX_STAT_BASE (RX_DESC_BASE + EMAC_NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + EMAC_NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + EMAC_NUM_TX_FRAG*8)
#define RX_BUF_BASE (TX_STAT_BASE + EMAC_NUM_TX_FRAG*4)
#define TX_BUF_BASE (RX_BUF_BASE + EMAC_NUM_RX_FRAG*EMAC_ETH_MAX_FLEN)
/**
* @brief RX Descriptor structure type definition
*/
#define RX_DESC_PACKET(i) (*(uint32_t *)(RX_DESC_BASE + 8*i))
#define RX_DESC_CTRL(i) (*(uint32_t *)(RX_DESC_BASE+4 + 8*i))
/**
* @brief RX Status structure type definition
*/
#define RX_STAT_INFO(i) (*(uint32_t *)(RX_STAT_BASE + 8*i))
#define RX_STAT_HASHCRC(i) (*(uint32_t *)(RX_STAT_BASE+4 + 8*i))
/**
* @brief TX Descriptor structure type definition
*/
#define TX_DESC_PACKET(i) (*(uint32_t *)(TX_DESC_BASE + 8*i))
#define TX_DESC_CTRL(i) (*(uint32_t *)(TX_DESC_BASE+4 + 8*i))
/**
* @brief TX Status structure type definition
*/
#define TX_STAT_INFO(i) (*(uint32_t *)(TX_STAT_BASE + 4*i))
/**
* @brief TX Data Buffer structure definition
*/
#define RX_BUF(i) (RX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
#define TX_BUF(i) (TX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
/* RX Descriptor Control Word */
#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
/* RX Status Hash CRC Word */
#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
/* RX Status Information Word */
#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
/** RX Status Information word mask */
#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
/* TX Descriptor Control Word */
#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
/* TX Status Information Word */
#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
/* DP83848C PHY definition ------------------------------------------------------------ */
/** PHY device reset time out definition */
#define EMAC_PHY_RESP_TOUT 0x100000UL
/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
/* PHY Basic Mode Control Register (BMCR) bitmap definitions */
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
//#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
#define EMAC_PHY_FULLD_100M (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 100Mbit
#define EMAC_PHY_HALFD_100M (EMAC_PHY_BMCR_SPEED_SEL | (~ EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 100Mbit
#define EMAC_PHY_FULLD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 10Mbit
#define EMAC_PHY_HALFD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | (~EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 10MBit
#define EMAC_PHY_AUTO_NEG (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_AN) // Select Auto Negotiation
/* EMAC PHY status type definitions */
#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
/* EMAC PHY device Speed definitions */
#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
/* EMAC User Buffers*/
#define EMAC_MAX_FRAME_SIZE (0x600) /* 1536 */
#define EMAC_MAX_FRAME_NUM (2)
/* EMAC Error Codes */
#define EMAC_ALIGN_ERR ( 1 << 0)
#define EMAC_RANGE_ERR ( 1 << 1)
#define EMAC_LENGTH_ERR ( 1 << 2)
#define EMAC_SYMBOL_ERR ( 1 << 3)
#define EMAC_CRC_ERR ( 1 << 4)
#define EMAC_RX_NO_DESC_ERR ( 1 << 5)
#define EMAC_OVERRUN_ERR ( 1 << 6)
#define EMAC_LATE_COLLISION_ERR ( 1 << 7)
#define EMAC_EXCESSIVE_COLLISION_ERR ( 1 << 8)
#define EMAC_EXCESSIVE_DEFER_ERR ( 1 << 9)
#define EMAC_UNDERRUN_ERR ( 1 << 10)
#define EMAC_TX_NO_DESC_ERR ( 1 << 11)
#define EMAC_FILTER_FAILED_ERR ( 1 << 12)
/**
* @}
*/
/**************************** GLOBAL/PUBLIC TYPES ***************************/
/** @defgroup EMAC_Public_Types EMAC Public Types
* @{
*/
/**
* @brief TX Data Buffer structure definition
*/
typedef struct {
uint32_t ulDataLen; /**< Data length */
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
} EMAC_PACKETBUF_Type;
/**
* @brief PHY Configuration structure definition
*/
typedef struct {
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
- EMAC_MODE_AUTO
- EMAC_MODE_10M_FULL
- EMAC_MODE_10M_HALF
- EMAC_MODE_100M_FULL
- EMAC_MODE_100M_HALF
*/
} EMAC_PHY_CFG_Type;
/** EMAC Call back function type definition */
typedef int32_t (PHY_INIT_FUNC)(EMAC_PHY_CFG_Type* pPhyCfg);
typedef int32_t (PHY_RESET_FUNC)(void);
typedef void (EMAC_FRAME_RECV_FUNC)(uint16_t* pData, uint32_t size);
typedef void (EMAC_TRANSMIT_FINISH_FUNC)(void);
typedef void (EMAC_ERR_RECV_FUNC)(int32_t ulErrCode);
typedef void (EMAC_WAKEUP_FUNC)(void);
typedef void (SOFT_INT_FUNC)(void);
/**
* @brief EMAC configuration structure definition
*/
typedef struct {
EMAC_PHY_CFG_Type PhyCfg; /* PHY Configuration */
uint8_t bPhyAddr; /* 5-bit PHY Address field */
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
*/
uint16_t nMaxFrameSize; /* maximum frame length */
PHY_INIT_FUNC *pfnPHYInit; /* point to the funtion which will be called to initialize PHY */
PHY_RESET_FUNC *pfnPHYReset; /* point to the function which will be called to reset PHY */
EMAC_FRAME_RECV_FUNC *pfnFrameReceive; /* point to the function which will be called when a frame is received*/
EMAC_TRANSMIT_FINISH_FUNC* pfnTransmitFinish; /*point to the function which will be called when transmit finished*/
EMAC_ERR_RECV_FUNC *pfnErrorReceive; /* point to an array of functions which will be called error occur. */
/* Errors:
EMAC_ALIGN_ERR
EMAC_RANGE_ERR
EMAC_LENGTH_ERR
EMAC_SYMBOL_ERR
EMAC_CRC_ERR
EMAC_RX_NO_DESC_ERR
EMAC_OVERRUN_ERR
EMAC_LATE_COLLISION_ERR
EMAC_EXCESSIVE_COLLISION_ERR
EMAC_EXCESSIVE_DEFER_ERR
EMAC_UNDERRUN_ERR
EMAC_TX_NO_DESC_ERR
*/
EMAC_WAKEUP_FUNC *pfnWakeup; /* point to the function which will be called when receiving wakeup interrupt */
SOFT_INT_FUNC *pfnSoftInt; /* point to the function which will be called when the interrupt caused by software occurs */
} EMAC_CFG_Type;
/**
* @brief EMAC Buffer status definition
*/
typedef enum {
EMAC_BUFF_EMPTY, /* buffer is empty */
EMAC_BUFF_PARTIAL_FULL, /* buffer contains some packets */
EMAC_BUFF_FULL, /* buffer is full */
} EMAC_BUFF_STATUS;
/**
* @brief EMAC Buffer Index definition
*/
typedef enum {
EMAC_TX_BUFF, /* transmit buffer */
EMAC_RX_BUFF, /* receive buffer */
} EMAC_BUFF_IDX;
/**
* @}
*/
/** @defgroup EMAC_Public_Functions EMAC Public Functions
* @{
*/
/** Init/DeInit */
int32_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
void EMAC_DeInit(void);
/** Send/Receive data */
void EMAC_TxEnable( void );
void EMAC_RxEnable( void );
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
/** PHY Setup */
void EMAC_Write_PHY (uint8_t PhyReg, uint16_t Value);
uint16_t EMAC_Read_PHY (uint8_t PhyReg);
void EMAC_SetFullDuplexMode(uint8_t full_duplex);
void EMAC_SetPHYSpeed(uint8_t mode_100Mbps);
/** Filter */
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
EMAC_BUFF_STATUS EMAC_GetBufferSts(EMAC_BUFF_IDX idx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_EMAC_DRIVER_H_ */
/**
* @}
*/

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/**********************************************************************
* $Id$ lpc_emc.h 2011-06-02
*//**
* @file lpc_emc.h
* @brief Contains all macro definitions and function prototypes
* support for EMC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMC EMC (External Memory Controller)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_EMC_H_
#define __LPC_EMC_H_
#include "lpc_types.h"
#include "LPC407x_8x_177x_8x.h"
/** @defgroup EMC_Private_Macros EMC Private Macros
* @{
*/
/***********************************************************************
* EMC Control Register (EMCControl)
**********************************************************************/
/* Control register mask */
#define EMC_Control_MASK ((uint32_t )0x07)
/* Control register EMC: Enable control. */
#define EMC_Control_E ((uint32_t )(1<<0))
/* Control register EMC: Address mirror control. */
#define EMC_Control_M ((uint32_t )(1<<1))
/* Control register EMC: Low-power mode control. */
#define EMC_Control_L ((uint32_t )(1<<2))
/***********************************************************************
* EMC Status Register (EMCStatus)
**********************************************************************/
/* Status register mask */
#define EMC_Status_MASK ((uint32_t )0x07)
/* Status register EMC: Busy. */
#define EMC_Status_B ((uint32_t )(1<<0))
/* Status register EMC: Write buffer status. */
#define EMC_Status_S ((uint32_t )(1<<1))
/* Status register EMC: Self-refresh acknowledge.. */
#define EMC_Status_SA ((uint32_t )(1<<2))
/***********************************************************************
* EMC Configuration register (EMCConfig)
**********************************************************************/
/* EMC Configuration register : Little Endian. */
#define EMC_Config_Little_Endian_Mode ((uint32_t )(0<<0))
/* EMC Configuration register : Big Endian. */
#define EMC_Config_Big_Endian_Mode ((uint32_t )(1<<0))
/* EMC Configuration: Endian Mask */
#define EMC_Config_Endian_Mask (0x01<<0)
/* EMC Configuration register: CLKOUT ratio 1:1. */
#define EMC_Config_CCLK_1_1 ((uinr32_t)(0<<8))
/* EMC Configuration register: CLKOUT ratio 1:1. */
#define EMC_Config_CCLK_1_2 ((uinr32_t)(1<<8))
/* EMC Configuration register mask */
#define EMC_Config_MASK ((uint32_t)(0x101))
/***********************************************************************
* Dynamic Memory Control register (EMCDynamicControl)
**********************************************************************/
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
#define EMC_DYNAMIC_CTRL_MEMCLK_EN_POS (0)
#define EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK (1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
#define EMC_DYNAMIC_CTRL_CE_SAVEPWR (0<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
#define EMC_DYNAMIC_CTRL_CE_ALLCLK_HI (1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
/* Dynamic Memory Control register EMC: Dynamic memory clock control */
#define EMC_DYNAMIC_CTRL_CLKCTRL_POS (1)
#define EMC_DYNAMIC_CTRL_CLKCTRL_BMASK (1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
#define EMC_DYNAMIC_CTRL_CS_CLKOUT_STOP (0<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
#define EMC_DYNAMIC_CTRL_CE_CLKOUT_CONT (1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS (2)
#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK (1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
#define EMC_DYNAMIC_CTRL_SR_NORMALMODE (0<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
#define EMC_DYNAMIC_CTRL_SR_SELFREFRESH (1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS (5)
#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK (1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED (0<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_DISABLED (1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
/* Dynamic Memory Control register EMC: SDRAM initialization*/
#define EMC_DYNAMIC_CTRL_SDRAM_INIT_POS (7)
#define EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK (0x03<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_NORMAL (0<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_MODE (1<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_PALL (2<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_NOP (3<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS (13)
#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK (0x01<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
#define EMC_DYNAMIC_CTRL_DP_NORMAL (0<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
#define EMC_DYNAMIC_CTRL_DP_DEEPSLEEP (1<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
/***********************************************************************
* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
**********************************************************************/
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
/***********************************************************************
* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
**********************************************************************/
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
/***********************************************************************
* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
**********************************************************************/
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
**********************************************************************/
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX)
**********************************************************************/
/* EMCDynamictSREX register EMC: self-refresh exit time (tSREX)) */
#define EMC_DynamictRP_tSREX(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
**********************************************************************/
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
**********************************************************************/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
**********************************************************************/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
/***********************************************************************
* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
**********************************************************************/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
/***********************************************************************
* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
**********************************************************************/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
**********************************************************************/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
**********************************************************************/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
**********************************************************************/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Extended Wait Register (EMCStaticExtendedWait)
**********************************************************************/
/* StaticExtendedWait register EMC: External wait time out. */
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
/***********************************************************************
* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
**********************************************************************/
/* DynamicConfig register EMC: Memory device (MD). */
#define EMC_DYNAMIC_CFG_MEMDEV_POS (3)
#define EMC_DYNAMIC_CFG_MEMDEV_BMASK (0x03 << EMC_DYNAMIC_CFG_MEMDEV_POS)
#define EMC_DYNAMIC_CFG_MEMDEV_SDRAM (0 << EMC_DYNAMIC_CFG_MEMDEV_POS)
#define EMC_DYNAMIC_CFG_MEMDEV_LOWPWR_SDRAM (1 << EMC_DYNAMIC_CFG_MEMDEV_POS)
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DYNAMIC_CFG_ADD_MAP_P1_POS (7)
#define EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK (0x3F<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2_POS (12)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK (0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3_POS (14)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK (0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)
#define EMC_DYNAMIC_CFG_ADD_MAP_P1(n) ( (n<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2(n) ( (n<<EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3(n) ( (n<<EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK)
#define EMC_ADD_MAP_ROW_BANK_COL (0)
#define EMC_ADD_MAP_BANK_ROW_COL (1)
/* DynamicConfig register EMC: Buffer enable */
#define EMC_DYNAMIC_CFG_BUFFENABLE_POS (19)
#define EMC_DYNAMIC_CFG_BUFFENABLE_BMASK (0x01<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
#define EMC_DYNAMIC_CFG_BUFF_DISABLED (0<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
#define EMC_DYNAMIC_CFG_BUFF_ENABLED (1<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
/* DynamicConfig register EMC: Write protect (P) */
#define EMC_DYNAMIC_CFG_WRPROTECT_POS (20)
#define EMC_DYNAMIC_CFG_WRPROTECT_BMASK (0x01<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
#define EMC_DYNAMIC_CFG_WR_UNPROTECTED (0<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
#define EMC_DYNAMIC_CFG_WR_PROTECTED (1<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
/***********************************************************************
* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
**********************************************************************/
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
#define EMC_DYNAMIC_RASCAS_RASCFG_POS (0)
#define EMC_DYNAMIC_RASCAS_RASCFG_BMASK (0x03<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_RESVD (0<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_1CLK (1<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_2CLK (2<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_3CLK (3<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
/* DynamicRASCAS register EMC: CAS latency (CAS)*/
#define EMC_DYNAMIC_RASCAS_CASCFG_POS (8)
#define EMC_DYNAMIC_RASCAS_CASCFG_BMASK (0x03<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_RESVD (0<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_1CLK (1<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_2CLK (2<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_3CLK (3<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
/***********************************************************************
* Static Memory Configuration registers (EMCStaticConfig0-3)
**********************************************************************/
/* StaticConfig register EMC: Memory width (MW). */
#define EMC_STATIC_CFG_MEMWIDTH_POS (0)
#define EMC_STATIC_CFG_MEMWIDTH_BMASK (0x03<<EMC_STATIC_CFG_MEMWIDTH_POS)
#define EMC_StaticConfig_MW(n) ((uint32_t )((n<<EMC_STATIC_CFG_MEMWIDTH_POS) & EMC_STATIC_CFG_MEMWIDTH_BMASK))
/* StaticConfig register EMC: Memory width 8bit . */
#define EMC_STATIC_CFG_MW_8BITS (EMC_StaticConfig_MW(0))
/* StaticConfig register EMC: Memory width 16bit . */
#define EMC_STATIC_CFG_MW_16BITS (EMC_StaticConfig_MW(1))
/* StaticConfig register EMC: Memory width 32bit . */
#define EMC_STATIC_CFG_MW_32BITS (EMC_StaticConfig_MW(2))
/* StaticConfig register EMC: Page mode (PM) */
#define EMC_STATIC_CFG_PAGEMODE_POS (3)
#define EMC_STATIC_CFG_PAGEMODE_MASK (1<<EMC_STATIC_CFG_PAGEMODE_POS)
#define EMC_CFG_PM_DISABLE (0<<EMC_STATIC_CFG_PAGEMODE_POS)
#define EMC_CFG_PM_ASYNC_ENABLE (1<<EMC_STATIC_CFG_PAGEMODE_POS)
/* StaticConfig register EMC: Chip select polarity (PC) */
#define EMC_STATIC_CFG_CHIPPOLARITY_POS (6)
#define EMC_STATIC_CFG_CHIPPOLARITY_MASK (1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
#define EMC_CFG_BYTELAND_PC_ACTIVE_LO (0<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
#define EMC_CFG_BYTELAND_PC_ACTIVE_HI (1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
/* StaticConfig register EMC: Byte lane state (PB) */
#define EMC_STATIC_CFG_BYTELAND_POS (7)
#define EMC_STATIC_CFG_BYTELAND_MASK (1<<EMC_STATIC_CFG_BYTELAND_POS)
#define EMC_CFG_BYTELAND_READ_BITSHIGH (0<<EMC_STATIC_CFG_BYTELAND_POS)
#define EMC_CFG_BYTELAND_READ_BITSLOW (1<<EMC_STATIC_CFG_BYTELAND_POS)
/* StaticConfig register EMC: Extended wait (EW) */
#define EMC_STATIC_CFG_EXTWAIT_POS (8)
#define EMC_STATIC_CFG_EXTWAIT_MASK (1<<EMC_STATIC_CFG_EXTWAIT_POS)
#define EMC_CFG_EW_DISABLED (0<<EMC_STATIC_CFG_EXTWAIT_POS)
#define EMC_CFG_EW_ENABLED (1<<EMC_STATIC_CFG_EXTWAIT_POS)
/* StaticConfig register EMC: Buffer enable (B) */
#define EMC_STATIC_CFG_BUFENABLE_POS (19)
#define EMC_STATIC_CFG_BUFENABLE_MASK (1<<EMC_STATIC_CFG_BUFENABLE_POS)
#define EMC_CFG_BUF_DISABLED (0<<EMC_STATIC_CFG_BUFENABLE_POS)
#define EMC_CFG_BUF_ENABLED (1<<EMC_STATIC_CFG_BUFENABLE_POS)
/* StaticConfig register EMC: Write protect (P) */
#define EMC_STATIC_CFG_WRIEPROTECT_POS (20)
#define EMC_STATIC_CFG_WRIEPROTECT_MASK (1<<EMC_STATIC_CFG_WRIEPROTECT_POS)
#define EMC_CFG_WRITEPROTECT_DISABLED (0<<EMC_STATIC_CFG_WRIEPROTECT_POS)
#define EMC_CFG_WRITEPROTECT_ENABLED (1<<EMC_STATIC_CFG_WRIEPROTECT_POS)
/***********************************************************************
* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
**********************************************************************/
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
**********************************************************************/
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
**********************************************************************/
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
read first access wait state (WAITRD) */
#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
**********************************************************************/
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
read wait states (WAITPAGE). */
#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
**********************************************************************/
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
**********************************************************************/
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Delay Control register (EMCDLYCTL)
**********************************************************************/
#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
/***********************************************************************
* EMC Calibration register (EMCCAL)
**********************************************************************/
#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
#define EMC_CAL_START ((uint32_t)(1<<14))
#define EMC_CAL_DONE ((uint32_t)(1<<15))
/***********************************************************************
* EMC Function Return codes
**********************************************************************/
typedef int32_t EMC_FUNC_CODE;
#define EMC_FUNC_OK (0)
#define EMC_FUNC_ERR (0x01)
#define EMC_FUNC_INVALID_PARAM (0x02)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup EMC_Public_Types EMC Public Types
* @{
*/
/*EMC dynamic memory registers enum*/
typedef enum
{
EMC_DYN_MEM_REFRESH_TIMER,
EMC_DYN_MEM_READ_CONFIG,
EMC_DYN_MEM_TRP,
EMC_DYN_MEM_TRAS,
EMC_DYN_MEM_TSREX,
EMC_DYN_MEM_TAPR,
EMC_DYN_MEM_TDAL,
EMC_DYN_MEM_TWR,
EMC_DYN_MEM_TRC,
EMC_DYN_MEM_TRFC,
EMC_DYN_MEM_TXSR,
EMC_DYN_MEM_TRRD,
EMC_DYN_MEM_TMRD
} EMC_DYN_MEM_PAR;
/*EMC static memory registers enum*/
typedef enum
{
EMC_STA_MEM_WAITWEN,
EMC_STA_MEM_WAITOEN,
EMC_STA_MEM_WAITRD,
EMC_STA_MEM_WAITPAGE,
EMC_STA_MEM_WAITWR,
EMC_STA_MEM_WAITTURN,
} EMC_STA_MEM_PAR;
/* SDRAM Config Struct */
typedef struct
{
uint8_t CSn; // 0/1/2/3
uint32_t TotalSize; // SDRAM TotalSize
uint16_t ChipSize; // chip size(Mb): 16Mb, 64Mb, 128Mb, 256Mb, 512Mb
uint8_t DataWidth; // 8bit, 16 bit, 32bit
uint8_t AddrBusWidth; // 16bit, 32bit
uint8_t AddrMap; // EMC_ADD_MAP_BANK_ROW_COL/ EMC_ADD_MAP_ROW_BANK_COL
/* timming */
uint16_t RefreshTime; // Dynamic Refresh Time
uint8_t ReadConfig; // Read Config Strategy
uint8_t PrechargeCmdPeriod; // Precharge Command Period (tRP)
uint8_t SeftRefreshExitTime; // Self-Refresh Exit Time (tSREX)
uint8_t DataOut2ActiveTime; // the last-data-out to active command time (tAPR)
uint8_t DataIn2ActiveTime; // the data-in to active command time (tDAL, or tAPW)
uint8_t WriteRecoveryTime; // the write recovery time (tWR, tDPL, tRWL, or tRDL)
uint8_t Active2ActivePeriod; // the active to active command period (tRC)
uint8_t AutoRefrehPeriod; // the auto-refresh period and auto-refresh to active command period (tRFC/tRC)
uint8_t ExitSelfRefreshTime; // the exit self-refresh to active command time (tXSR)
uint8_t ActiveBankLatency; // the active bank A to active bank B latency (tRRD)
uint8_t LoadModeReg2Active; // the load mode register to active command time (tMRD)
uint8_t Active2PreChargeTime; // Active to precharge command period (tRAS)
uint8_t RASLatency; // RAS Delay
uint8_t CASLatency; // CAS Delay
} EMC_DYN_MEM_Config_Type;
typedef struct
{
uint8_t CSn; // 0/1/2/3
uint8_t DataWidth; // 8bit, 16bit, 32bit
uint8_t PageMode; // 1: asynchronous page mode enabled
uint8_t ByteLane; // 1: Read when active bits are low, 0: read when acrive bits are High
uint8_t ExtendedWait; //1: enabled
uint8_t AddressMirror; // 1: reset memory map, 0: normal memory map
uint8_t WaitWEn; // Delay from the chip select to the write enable (CCLK cycles)
uint8_t WaitOEn; // Delay from the chip select or address change to output enable (CCLK cycles)
uint8_t WaitRd; // Delay from the chip select to the read access (CCLK cycles)
uint8_t WaitPage; // Delay for asynchronous page mode sequential accesses (CCLK cycles)
uint8_t WaitWr; // Delay from the chip select to the write access (CCLK cycles)
uint8_t WaitTurn; // The number of bus turnaround cycles
} EMC_STATIC_MEM_Config_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup EMC_Public_Functions EMC Public Functions
* @{
*/
uint32_t EMC_SDRAM_REFRESH(uint32_t time);
uint32_t EMC_NS2CLK(uint32_t time);
EMC_FUNC_CODE DynMem_Init(EMC_DYN_MEM_Config_Type* pConfig);
EMC_FUNC_CODE StaticMem_Init(EMC_STATIC_MEM_Config_Type* pConfig);
EMC_FUNC_CODE EMC_Init(void);
EMC_FUNC_CODE EMC_ConfigEndianMode(uint32_t endian_mode);
EMC_FUNC_CODE EMC_DynCtrlClockEnable(uint32_t clock_enable);
EMC_FUNC_CODE EMC_DynCtrlClockControl(int32_t clock_control);
EMC_FUNC_CODE EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
EMC_FUNC_CODE EMC_DynCtrlMMC(uint32_t MMC_val);
EMC_FUNC_CODE EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
EMC_FUNC_CODE EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
EMC_FUNC_CODE EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
EMC_FUNC_CODE EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
EMC_FUNC_CODE EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index , uint8_t addr_bus_width, uint8_t addr_map,uint8_t data_bus_width,uint16_t chip_size);
EMC_FUNC_CODE EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
EMC_FUNC_CODE EMC_DynMemConfigP(uint32_t index , uint32_t permission);
EMC_FUNC_CODE EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
EMC_FUNC_CODE EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
EMC_FUNC_CODE EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
EMC_FUNC_CODE EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
EMC_FUNC_CODE EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
EMC_FUNC_CODE EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
EMC_FUNC_CODE EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
EMC_FUNC_CODE EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
EMC_FUNC_CODE EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
EMC_FUNC_CODE EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);
/**
* @}
*/
#endif /* __LPC_EMC_H_ */
/**
* @}
*/

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/**********************************************************************
* $Id$ lpc_exti.h 2011-06-02
*//**
* @file lpc_exti.h
* @brief Contains all macro definitions and function prototypes
* support for External Interrupt firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EXTI EXTI (External Interrupt)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_EXTI_H_
#define __LPC_EXTI_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
/*********************************************************************//**
* Macro defines for EXTI control register
**********************************************************************/
#define EXTI_EINT0_BIT_MARK 0x01
#define EXTI_EINT1_BIT_MARK 0x02
#define EXTI_EINT2_BIT_MARK 0x04
#define EXTI_EINT3_BIT_MARK 0x08
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup EXTI_Public_Types EXTI Public Types
* @{
*/
/**
* @brief EXTI external interrupt line option
*/
typedef enum
{
EXTI_EINT0, /*!< External interrupt 0, P2.10 */
EXTI_EINT1, /*!< External interrupt 0, P2.11 */
EXTI_EINT2, /*!< External interrupt 0, P2.12 */
EXTI_EINT3 /*!< External interrupt 0, P2.13 */
} EXTI_LINE_ENUM;
/**
* @brief EXTI mode option
*/
typedef enum
{
EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */
EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */
} EXTI_MODE_ENUM;
/**
* @brief EXTI polarity option
*/
typedef enum
{
EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive
depending on pin mode */
EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive
depending on pin mode */
} EXTI_POLARITY_ENUM;
/**
* @brief EXTI Initialize structure
*/
typedef struct
{
/** Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
EXTI_LINE_ENUM EXTI_Line;
/** Choose between Level-sensitivity or Edge sensitivity */
EXTI_MODE_ENUM EXTI_Mode;
/** If EXTI mode is level-sensitive: this element use to select low or high active level
if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
EXTI_POLARITY_ENUM EXTI_polarity;
}EXTI_InitTypeDef;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup EXTI_Public_Functions EXTI Public Functions
* @{
*/
void EXTI_Init(void);
void EXTI_DeInit(void);
void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_EXTI_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_gpdma.h 2011-06-02
*//**
* @file lpc_gpdma.h
* @brief Contains all macro definitions and function prototypes
* support for GPDMA firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_GPDMA_H_
#define __LPC_GPDMA_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
* @{
*/
/** DMA Connection number definitions */
#define GPDMA_CONN_MCI ((1UL)) /** SD card */
#define GPDMA_CONN_SSP0_Tx ((2UL)) /**< SSP0 Tx */
#define GPDMA_CONN_SSP0_Rx ((3UL)) /**< SSP0 Rx */
#define GPDMA_CONN_SSP1_Tx ((4UL)) /**< SSP1 Tx */
#define GPDMA_CONN_SSP1_Rx ((5UL)) /**< SSP1 Rx */
#define GPDMA_CONN_SSP2_Tx ((6UL)) /**< SSP2 Tx */
#define GPDMA_CONN_SSP2_Rx ((7UL)) /**< SSP2 Rx */
#define GPDMA_CONN_ADC ((8UL)) /**< ADC */
#define GPDMA_CONN_DAC ((9UL)) /**< DAC */
#define GPDMA_CONN_UART0_Tx ((10UL)) /**< UART0 Tx */
#define GPDMA_CONN_UART0_Rx ((11UL)) /**< UART0 Rx */
#define GPDMA_CONN_UART1_Tx ((12UL)) /**< UART1 Tx */
#define GPDMA_CONN_UART1_Rx ((13UL)) /**< UART1 Rx */
#define GPDMA_CONN_UART2_Tx ((14UL)) /**< UART2 Tx */
#define GPDMA_CONN_UART2_Rx ((15UL)) /**< UART2 Rx */
#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
#define GPDMA_CONN_I2S_Channel_0 ((22UL)) /**< I2S channel 0 */
#define GPDMA_CONN_I2S_Channel_1 ((23UL)) /**< I2S channel 1 */
#define GPDMA_CONN_UART3_Tx ((26UL)) /**< UART3 Tx */
#define GPDMA_CONN_UART3_Rx ((27UL)) /**< UART3 Rx */
#define GPDMA_CONN_UART4_Tx ((28UL)) /**< UART3 Tx */
#define GPDMA_CONN_UART4_Rx ((29UL)) /**< UART3 Rx */
#define GPDMA_CONN_MAT3_0 ((30UL)) /**< MAT3.0 */
#define GPDMA_CONN_MAT3_1 ((31UL)) /**< MAT3.1 */
/** GPDMA Transfer type definitions: Memory to memory - DMA control */
#define GPDMA_TRANSFERTYPE_M2M ((0UL))
/** GPDMA Transfer type definitions: Memory to peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_M2P ((1UL))
/** GPDMA Transfer type definitions: Peripheral to memory - DMA control */
#define GPDMA_TRANSFERTYPE_P2M ((2UL))
/** Source peripheral to destination peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2P ((3UL))
/** Memory to peripheral - Destination peripheral control */
#define GPDMA_TRANSFERTYPE_M2P_DEST_CTRL ((5UL))
/** Peripheral to memory - Source peripheral control */
#define GPDMA_TRANSFERTYPE_P2M_SRC_CTRL ((6UL))
/** Burst size in Source and Destination definitions */
#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
/** Width in Source transfer width and Destination transfer width definitions */
#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
/** DMA Request Select Mode definitions */
#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for DMA Interrupt Status register
**********************************************************************/
#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Status register
**********************************************************************/
#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Terminal Count Request Clear register
**********************************************************************/
#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Status register
**********************************************************************/
#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Interrupt Error Clear register
**********************************************************************/
#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Interrupt Terminal Count Status register
**********************************************************************/
#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Raw Error Interrupt Status register
**********************************************************************/
#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Enabled Channel register
**********************************************************************/
#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Software Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Single Request register
**********************************************************************/
#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Burst Request register
**********************************************************************/
#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Software Last Single Request register
**********************************************************************/
#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Configuration register
**********************************************************************/
#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
#define GPDMA_DMACConfig_BITMASK ((0x03))
/*********************************************************************//**
* Macro defines for DMA Synchronization register
**********************************************************************/
#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
#define GPDMA_DMACSync_BITMASK ((0xFFFF))
/*********************************************************************//**
* Macro defines for DMA Request Select register
**********************************************************************/
#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
#define GPDMA_DMAReqSel_BITMASK ((0xFF))
/*********************************************************************//**
* Macro defines for DMA Channel Linked List Item registers
**********************************************************************/
/** DMA Channel Linked List Item registers bit mask*/
#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
/*********************************************************************//**
* Macro defines for DMA channel control registers
**********************************************************************/
/** Transfer size*/
#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))
/** Source burst size*/
#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12))
/** Destination burst size*/
#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15))
/** Source transfer width*/
#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18))
/** Destination transfer width*/
#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21))
/** Source increment*/
#define GPDMA_DMACCxControl_SI ((1UL<<26))
/** Destination increment*/
#define GPDMA_DMACCxControl_DI ((1UL<<27))
/** Indicates that the access is in user mode or privileged mode*/
#define GPDMA_DMACCxControl_Prot1 ((1UL<<28))
/** Indicates that the access is bufferable or not bufferable*/
#define GPDMA_DMACCxControl_Prot2 ((1UL<<29))
/** Indicates that the access is cacheable or not cacheable*/
#define GPDMA_DMACCxControl_Prot3 ((1UL<<30))
/** Terminal count interrupt enable bit */
#define GPDMA_DMACCxControl_I ((1UL<<31))
/** DMA channel control registers bit mask */
#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
/*********************************************************************//**
* Macro defines for DMA Channel Configuration registers
**********************************************************************/
/** DMA control enable*/
#define GPDMA_DMACCxConfig_E ((1UL<<0))
/** Source peripheral*/
#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1))
/** Destination peripheral*/
#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6))
/** This value indicates the type of transfer*/
#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11))
/** Interrupt error mask*/
#define GPDMA_DMACCxConfig_IE ((1UL<<14))
/** Terminal count interrupt mask*/
#define GPDMA_DMACCxConfig_ITC ((1UL<<15))
/** Lock*/
#define GPDMA_DMACCxConfig_L ((1UL<<16))
/** Active*/
#define GPDMA_DMACCxConfig_A ((1UL<<17))
/** Halt*/
#define GPDMA_DMACCxConfig_H ((1UL<<18))
/** DMA Channel Configuration registers bit mask */
#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Types GPDMA Public Types
* @{
*/
/**
* @brief GPDMA Status enumeration
*/
typedef enum {
GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
} GPDMA_Status_Type;
/**
* @brief GPDMA Interrupt clear status enumeration
*/
typedef enum{
GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
}GPDMA_StateClear_Type;
/**
* @brief GPDMA Channel configuration structure type definition
*/
typedef struct {
uint32_t ChannelNum; /**< DMA channel number, should be in
range from 0 to 7.
Note: DMA channel 0 has the highest priority
and DMA channel 7 the lowest priority.
*/
uint32_t TransferSize; /**< Length/Size of transfer */
uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
uint32_t TransferType; /**< Transfer Type, should be one of the following:
- GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
- GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
- GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
- GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
*/
uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC: ADC
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
following:
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
- GPDMA_CONN_ADC: ADC
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
- GPDMA_CONN_DAC: DAC
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
*/
uint32_t DMALLI; /**< Linker List Item structure data address
if there's no Linker List, set as '0'
*/
} GPDMA_Channel_CFG_Type;
/**
* @brief GPDMA Linker List Item structure type definition
*/
typedef struct {
uint32_t SrcAddr; /**< Source Address */
uint32_t DstAddr; /**< Destination address */
uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
uint32_t Control; /**< GPDMA Control of this LLI */
} GPDMA_LLI_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
* @{
*/
void GPDMA_Init(void);
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
//void GPDMA_IntHandler(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_GPDMA_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_gpio.h 2011-06-02
*//**
* @file lpc_gpio.h
* @brief Contains all macro definitions and function prototypes
* support for GPIO firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPIO GPIO (General Purpose Input/Output)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_GPIO_H_
#define __LPC_GPIO_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPIO_Public_Macros GPIO Public Macros
* @{
*/
#define GPIO_DIRECTION_INPUT (0)
#define GPIO_DIRECTION_OUTPUT (1)
/** Fast GPIO port 0 byte accessible definition */
#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO0_BASE))
/** Fast GPIO port 1 byte accessible definition */
#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO1_BASE))
/** Fast GPIO port 2 byte accessible definition */
#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO2_BASE))
/** Fast GPIO port 3 byte accessible definition */
#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO3_BASE))
/** Fast GPIO port 4 byte accessible definition */
#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO4_BASE))
/** Fast GPIO port 4 byte accessible definition */
#define GPIO5_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO5_BASE))
/** Fast GPIO port 0 half-word accessible definition */
#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO0_BASE))
/** Fast GPIO port 1 half-word accessible definition */
#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO1_BASE))
/** Fast GPIO port 2 half-word accessible definition */
#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO2_BASE))
/** Fast GPIO port 3 half-word accessible definition */
#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO3_BASE))
/** Fast GPIO port 4 half-word accessible definition */
#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO4_BASE))
/** Fast GPIO port 4 half-word accessible definition */
#define GPIO5_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO5_BASE))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup GPIO_Public_Types GPIO Public Types
* @{
*/
/**
* @brief Fast GPIO port byte type definition
*/
typedef struct {
__IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */
uint32_t RESERVED0[3]; /**< Reserved */
__IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */
__IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */
__IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */
__O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */
} GPIO_Byte_TypeDef;
/**
* @brief Fast GPIO port half-word type definition
*/
typedef struct {
__IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */
__IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */
uint32_t RESERVED0[3]; /**< Reserved */
__IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */
__IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */
__IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */
__IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */
__IO uint16_t FIOSETL; /**< FIO set register lower halfword part */
__IO uint16_t FIOSETU; /**< FIO set register upper halfword part */
__O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */
__O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */
} GPIO_HalfWord_TypeDef;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup GPIO_Public_Functions GPIO Public Functions
* @{
*/
/* GPIO style ------------------------------- */
void GPIO_Init(void);
void GPIO_Deinit(void);
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
void GPIO_OutputValue(uint8_t portNum, uint32_t bitMask, uint8_t value);
uint32_t GPIO_ReadValue(uint8_t portNum);
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
/* FIO (word-accessible) style ------------------------------- */
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t FIO_ReadValue(uint8_t portNum);
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
/* FIO (halfword-accessible) style ------------------------------- */
void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
/* FIO (byte-accessible) style ------------------------------- */
void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_GPIO_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_i2c.h 2011-06-02
*//**
* @file lpc_i2c.h
* @brief Contains all macro definitions and function prototypes
* support for I2C firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2C I2C (Inter-IC Control bus)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_I2C_H_
#define __LPC_I2C_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*******************************************************************//**
* I2C Control Set register description
*********************************************************************/
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
/*******************************************************************//**
* I2C Control Clear register description
*********************************************************************/
/** Assert acknowledge Clear bit */
#define I2C_I2CONCLR_AAC ((1<<2))
/** I2C interrupt Clear bit */
#define I2C_I2CONCLR_SIC ((1<<3))
/** I2C STOP Clear bit */
#define I2C_I2CONCLR_STOC ((1<<4))
/** START flag Clear bit */
#define I2C_I2CONCLR_STAC ((1<<5))
/** I2C interface Disable bit */
#define I2C_I2CONCLR_I2ENC ((1<<6))
/********************************************************************//**
* I2C Status Code definition (I2C Status register)
*********************************************************************/
/* Return Code in I2C status register */
#define I2C_STAT_CODE_BITMASK ((0xF8))
/* I2C return status code definitions ----------------------------- */
/** No relevant information */
#define I2C_I2STAT_NO_INF ((0xF8))
/** Bus Error */
#define I2C_I2STAT_BUS_ERROR ((0x00))
/* Master transmit mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_TX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))
/** SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
/** SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
/** Arbitration lost in SLA+R/W or Data bytes */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
/* Master receive mode -------------------------------------------- */
/** A start condition has been transmitted */
#define I2C_I2STAT_M_RX_START ((0x08))
/** A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))
/** Arbitration lost */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
/** SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
/** SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
/** Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
/** Data has been received, NACK has been return */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
/* Slave receive mode -------------------------------------------- */
/** Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
/** General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
/** Previously addressed with own SLV address;
* Data has been received, ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
/** Previously addressed with own SLA;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
/** Previously addressed with General Call;
* Data has been received and ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
/** Previously addressed with General Call;
* Data has been received and NOT ACK has been return */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
/** A STOP condition or repeated START condition has
* been received while still addressed as SLV/REC
* (Slave Receive) or SLV/TRX (Slave Transmit) */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
/** Slave transmit mode */
/** Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
/** Arbitration lost in SLA+R/W as master */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
/** Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
/** Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
/** Last data byte in I2DAT has been transmitted (AA = 0);
ACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
/** Time out in case of using I2C slave mode */
#define I2C_SLAVE_TIME_OUT 0x10000UL
/********************************************************************//**
* I2C Data register definition
*********************************************************************/
/** Mask for I2DAT register*/
#define I2C_I2DAT_BITMASK ((0xFF))
/** Idle data value will be send out in slave mode in case of the actual
* expecting data requested from the master is greater than its sending data
* length that can be supported */
#define I2C_I2DAT_IDLE_CHAR (0xFF)
/********************************************************************//**
* I2C Monitor mode control register description
*********************************************************************/
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/********************************************************************//**
* I2C Data buffer register description
*********************************************************************/
/** I2C Data buffer register bit mask */
#define I2DATA_BUFFER_BITMASK ((0xFF))
/********************************************************************//**
* I2C Slave Address registers definition
*********************************************************************/
/** General Call enable bit */
#define I2C_I2ADR_GC ((1<<0))
/** I2C Slave Address registers bit mask */
#define I2C_I2ADR_BITMASK ((0xFF))
/********************************************************************//**
* I2C Mask Register definition
*********************************************************************/
/** I2C Mask Register mask field */
#define I2C_I2MASK_MASK(n) ((n&0xFE))
/********************************************************************//**
* I2C SCL HIGH duty cycle Register definition
*********************************************************************/
/** I2C SCL HIGH duty cycle Register bit mask */
#define I2C_I2SCLH_BITMASK ((0xFFFF))
/********************************************************************//**
* I2C SCL LOW duty cycle Register definition
*********************************************************************/
/** I2C SCL LOW duty cycle Register bit mask */
#define I2C_I2SCLL_BITMASK ((0xFFFF))
/* I2C status values */
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
/* I2C state handle return values */
#define I2C_OK 0x00
#define I2C_BYTE_SENT 0x01
#define I2C_BYTE_RECV 0x02
#define I2C_LAST_BYTE_RECV 0x04
#define I2C_SEND_END 0x08
#define I2C_RECV_END 0x10
#define I2C_STA_STO_RECV 0x20
#define I2C_ERR (0x10000000)
#define I2C_NAK_RECV (0x10000000 |0x01)
#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2C_Public_Types I2C Public Types
* @{
*/
typedef enum
{
I2C_0 = 0,
I2C_1,
I2C_2
} en_I2C_unitId;
typedef enum
{
I2C_MASTER_MODE,
I2C_SLAVE_MODE,
I2C_GENERAL_MODE,
} en_I2C_Mode;
/**
* @brief I2C Own slave address setting structure
*/
typedef struct
{
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
should be in range from 0..3
*/
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
when I2C control being in Slave mode, should be:
- ENABLE: Enable General Call function.
- DISABLE: Disable General Call function.
*/
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
which is set to '1' will cause an automatic compare on
the corresponding bit of the received address when it
is compared to the SlaveAddr_7bit value associated with this
mask register. In other words, bits in SlaveAddr_7bit value
which are masked are not taken into account in determining
an address match
*/
} I2C_OWNSLAVEADDR_CFG_Type;
/**
* @brief Master transfer setup data structure definitions
*/
typedef struct
{
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
__IO uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
is not used */
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
is not used*/
__IO uint32_t tx_count; /**< Current Transmit data counter */
__IO uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
is not used */
uint32_t rx_length; /**< Receive data length - 0 if data receive is
not used */
__IO uint32_t rx_count; /**< Current Receive data counter */
uint32_t retransmissions_max; /**< Max Re-Transmission value */
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
__IO uint32_t status; /**< Current status of I2C activity */
void (*callback)(void); /**< Pointer to Call back function when transmission complete
used in interrupt transfer mode */
} I2C_M_SETUP_Type;
/**
* @brief Slave transfer setup data structure definitions
*/
typedef struct
{
__IO uint8_t* tx_data;
uint32_t tx_length;
__IO uint32_t tx_count;
__IO uint8_t* rx_data;
uint32_t rx_length;
__IO uint32_t rx_count;
__IO uint32_t status;
void (*callback)(void);
} I2C_S_SETUP_Type;
/**
* @brief Transfer option type definitions
*/
typedef enum
{
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
} I2C_TRANSFER_OPT_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2C_Public_Functions I2C Public Functions
* @{
*/
/* I2C Init/DeInit functions ---------- */
void I2C_Init(en_I2C_unitId i2cId, uint32_t clockrate);
void I2C_DeInit(en_I2C_unitId i2cId);
void I2C_Cmd(en_I2C_unitId i2cId, en_I2C_Mode Mode, FunctionalState NewState);
/* I2C transfer data functions -------- */
Status I2C_MasterTransferData(en_I2C_unitId i2cId,
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
Status I2C_SlaveTransferData(en_I2C_unitId i2cId,
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
uint32_t I2C_MasterTransferComplete(en_I2C_unitId i2cId);
uint32_t I2C_SlaveTransferComplete(en_I2C_unitId i2cId);
void I2C_SetOwnSlaveAddr(en_I2C_unitId i2cId, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
uint8_t I2C_GetLastStatusCode(en_I2C_unitId i2cId);
/* I2C Monitor functions ---------------*/
void I2C_MonitorModeConfig(en_I2C_unitId i2cId, uint32_t MonitorCfgType, FunctionalState NewState);
void I2C_MonitorModeCmd(en_I2C_unitId i2cId, FunctionalState NewState);
uint8_t I2C_MonitorGetDatabuffer(en_I2C_unitId i2cId);
BOOL_8 I2C_MonitorHandler(en_I2C_unitId i2cId, uint8_t *buffer, uint32_t size);
/* I2C Interrupt handler functions ------*/
void I2C_IntCmd (en_I2C_unitId i2cId, Bool NewState);
void I2C_MasterHandler (en_I2C_unitId i2cId);
void I2C_SlaveHandler (en_I2C_unitId i2cId);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_I2C_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_i2s.h 2011-06-02
*//**
* @file lpc_i2s.h
* @brief Contains all macro definitions and function prototypes
* support for I2S firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup I2S I2S (Inter-IC Sound bus)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_I2S_H_
#define __LPC_I2S_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup I2S_Public_Macros I2S Public Macros
* @{
*/
/*********************************************************************//**
* I2S configuration parameter defines
**********************************************************************/
/** I2S Wordwidth bit */
#define I2S_WORDWIDTH_8 ((uint32_t)(0))
#define I2S_WORDWIDTH_16 ((uint32_t)(1))
#define I2S_WORDWIDTH_32 ((uint32_t)(3))
/** I2S Channel bit */
#define I2S_STEREO ((uint32_t)(0))
#define I2S_MONO ((uint32_t)(1))
/** I2S Master/Slave mode bit */
#define I2S_MASTER_MODE ((uint8_t)(0))
#define I2S_SLAVE_MODE ((uint8_t)(1))
/** I2S Stop bit */
#define I2S_STOP_ENABLE ((uint8_t)(1))
#define I2S_STOP_DISABLE ((uint8_t)(0))
/** I2S Reset bit */
#define I2S_RESET_ENABLE ((uint8_t)(1))
#define I2S_RESET_DISABLE ((uint8_t)(0))
/** I2S Mute bit */
#define I2S_MUTE_ENABLE ((uint8_t)(1))
#define I2S_MUTE_DISABLE ((uint8_t)(0))
/** I2S Transmit/Receive bit */
#define I2S_TX_MODE ((uint8_t)(0))
#define I2S_RX_MODE ((uint8_t)(1))
/** I2S Clock Select bit */
#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
#define I2S_CLKSEL_MCLK ((uint8_t)(2))
/** I2S 4-pin Mode bit */
#define I2S_4PIN_ENABLE ((uint8_t)(1))
#define I2S_4PIN_DISABLE ((uint8_t)(0))
/** I2S MCLK Enable bit */
#define I2S_MCLK_ENABLE ((uint8_t)(1))
#define I2S_MCLK_DISABLE ((uint8_t)(0))
/** I2S select DMA bit */
#define I2S_DMA_1 ((uint8_t)(0))
#define I2S_DMA_2 ((uint8_t)(1))
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/*********************************************************************//**
* Macro defines for DAO-Digital Audio Output register
**********************************************************************/
/** I2S wordwide - the number of bytes in data output - 8 bits*/
#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0))
/** I2S wordwide - the number of bytes in data output - 16 bits*/
#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1))
/** I2S wordwide - the number of bytes in data output - 32 bits*/
#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3))
/** I2S control mono or stereo format */
#define I2S_DAO_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAO_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAO_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one */
#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
/** I2S control mute mode */
#define I2S_DAO_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for DAI-Digital Audio Input register
**********************************************************************/
/** I2S wordwide - the number of bytes in data input - 8 bit*/
#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0))
/** I2S wordwide - the number of bytes in data input - 16 bit*/
#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1))
/** I2S wordwide - the number of bytes in data input - 32 bit*/
#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3))
/** I2S control mono or stereo format */
#define I2S_DAI_MONO ((uint32_t)(1<<2))
/** I2S control stop mode */
#define I2S_DAI_STOP ((uint32_t)(1<<3))
/** I2S control reset mode */
#define I2S_DAI_RESET ((uint32_t)(1<<4))
/** I2S control master/slave mode */
#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
/** I2S word select half period minus one (9 bits)*/
#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
/** I2S control mute mode */
#define I2S_DAI_MUTE ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for STAT register (Status Feedback register)
**********************************************************************/
/** I2S Status Receive or Transmit Interrupt */
#define I2S_STATE_IRQ ((uint32_t)(1))
/** I2S Status Receive or Transmit DMA1 */
#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
/** I2S Status Receive or Transmit DMA2 */
#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
/** I2S Status Current level of the Receive FIFO (5 bits)*/
#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
/** I2S Status Current level of the Transmit FIFO (5 bits)*/
#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
/*********************************************************************//**
* Macro defines for DMA1 register (DMA1 Configuration register)
**********************************************************************/
/** I2S control DMA1 for I2S receive */
#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for DMA2 register (DMA2 Configuration register)
**********************************************************************/
/** I2S control DMA2 for I2S receive */
#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
/** I2S control DMA1 for I2S transmit */
#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/*********************************************************************//**
* Macro defines for IRQ register (Interrupt Request Control register)
**********************************************************************/
/** I2S control I2S receive interrupt */
#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
/** I2S control I2S transmit interrupt */
#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
/** I2S set the FIFO level on which to create an irq request */
#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
/********************************************************************************//**
* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
*********************************************************************************/
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Transmit MCLK rate denominator */
#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
/** I2S Receive MCLK rate denominator */
#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
/*************************************************************************************//**
* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
**************************************************************************************/
#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
/**********************************************************************************//**
* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
************************************************************************************/
/** I2S Transmit select clock source (2 bits)*/
#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Transmit control 4-pin mode */
#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Transmit control the TX_MCLK output */
#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
/** I2S Receive select clock source */
#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
/** I2S Receive control 4-pin mode */
#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
/** I2S Receive control the TX_MCLK output */
#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup I2S_Public_Types I2S Public Types
* @{
*/
/**
* @brief I2S configuration structure definition
*/
typedef struct {
uint8_t wordwidth; /** the number of bytes in data as follow:
-I2S_WORDWIDTH_8: 8 bit data
-I2S_WORDWIDTH_16: 16 bit data
-I2S_WORDWIDTH_32: 32 bit data */
uint8_t mono; /** Set mono/stereo mode, should be:
- I2S_STEREO: stereo mode
- I2S_MONO: mono mode */
uint8_t stop; /** Disables accesses on FIFOs, should be:
- I2S_STOP_ENABLE: enable stop mode
- I2S_STOP_DISABLE: disable stop mode */
uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
- I2S_RESET_ENABLE: enable reset mode
- I2S_RESET_DISABLE: disable reset mode */
uint8_t ws_sel; /** Set Master/Slave mode, should be:
- I2S_MASTER_MODE: I2S master mode
- I2S_SLAVE_MODE: I2S slave mode */
uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
- I2S_MUTE_ENABLE: enable mute mode
- I2S_MUTE_DISABLE: disable mute mode */
uint8_t Reserved0[2];
} I2S_CFG_Type;
/**
* @brief I2S DMA configuration structure definition
*/
typedef struct {
uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
- I2S_DMA_1: DMA1
- I2S_DMA_2: DMA2 */
uint8_t depth; /** FIFO level that triggers a DMA request */
uint8_t Reserved0[2];
}I2S_DMAConf_Type;
/**
* @brief I2S mode configuration structure definition
*/
typedef struct{
uint8_t clksel; /** Clock source selection, should be:
- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
uint8_t fpin; /** Select four pin mode, should be:
- I2S_4PIN_ENABLE: 4-pin enable
- I2S_4PIN_DISABLE: 4-pin disable */
uint8_t mcena; /** Select MCLK mode, should be:
- I2S_MCLK_ENABLE: MCLK enable for output
- I2S_MCLK_DISABLE: MCLK disable for output */
uint8_t Reserved;
}I2S_MODEConf_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup I2S_Public_Functions I2S Public Functions
* @{
*/
/* I2S Init/DeInit functions ---------*/
void I2S_Init(LPC_I2S_TypeDef *I2Sx);
void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
/* I2S configuration functions --------*/
void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
/* I2S operate functions -------------*/
void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
void I2S_Start(LPC_I2S_TypeDef *I2Sx);
void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
/* I2S DMA functions ----------------*/
void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
/* I2S IRQ functions ----------------*/
void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_SSP_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_iap.h 2011-11-21
*//**
* @file lpc_iap.h
* @brief Contains all functions support for IAP
* on LPC
* @version 1.0
* @date 21. November. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef _LPC_IAP_H
#define _LPC_IAP_H
#include "lpc_types.h"
/** @defgroup IAP IAP (In Application Programming)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
/** @defgroup IAP_Public_Macros IAP Public Macros
* @{
*/
/** IAP entry location */
#define IAP_LOCATION (0x1FFF1FF1UL)
/**
* @}
*/
/** @defgroup IAP_Public_Types IAP Public Types
* @{
*/
/**
* @brief IAP command code definitions
*/
typedef enum
{
IAP_PREPARE = 50, // Prepare sector(s) for write operation
IAP_COPY_RAM2FLASH = 51, // Copy RAM to Flash
IAP_ERASE = 52, // Erase sector(s)
IAP_BLANK_CHECK = 53, // Blank check sector(s)
IAP_READ_PART_ID = 54, // Read chip part ID
IAP_READ_BOOT_VER = 55, // Read chip boot code version
IAP_COMPARE = 56, // Compare memory areas
IAP_REINVOKE_ISP = 57, // Reinvoke ISP
IAP_READ_SERIAL_NUMBER = 58, // Read serial number
} IAP_COMMAND_CODE;
/**
* @brief IAP status code definitions
*/
typedef enum
{
CMD_SUCCESS, // Command is executed successfully.
INVALID_COMMAND, // Invalid command.
SRC_ADDR_ERROR, // Source address is not on a word boundary.
DST_ADDR_ERROR, // Destination address is not on a correct boundary.
SRC_ADDR_NOT_MAPPED, // Source address is not mapped in the memory map.
DST_ADDR_NOT_MAPPED, // Destination address is not mapped in the memory map.
COUNT_ERROR, // Byte count is not multiple of 4 or is not a permitted value.
INVALID_SECTOR, // Sector number is invalid.
SECTOR_NOT_BLANK, // Sector is not blank.
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, // Command to prepare sector for write operation was not executed.
COMPARE_ERROR, // Source and destination data is not same.
BUSY, // Flash programming hardware interface is busy.
} IAP_STATUS_CODE;
/**
* @brief IAP write length definitions
*/
typedef enum {
IAP_WRITE_256 = 256,
IAP_WRITE_512 = 512,
IAP_WRITE_1024 = 1024,
IAP_WRITE_4096 = 4096,
} IAP_WRITE_SIZE;
/**
* @brief IAP command structure
*/
typedef struct {
uint32_t cmd; // Command
uint32_t param[4]; // Parameters
uint32_t status; // status code
uint32_t result[4]; // Result
} IAP_COMMAND_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup IAP_Public_Functions IAP Public Functions
* @{
*/
/** Get sector number of an address */
uint32_t GetSecNum (uint32_t adr);
/** Prepare sector(s) for write operation */
IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec);
/** Copy RAM to Flash */
IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size);
/** Prepare sector(s) for write operation */
IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec);
/** Blank check sectors */
IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
uint32_t *first_nblank_loc,
uint32_t *first_nblank_val);
/** Read part identification number */
IAP_STATUS_CODE ReadPartID(uint32_t *partID);
/** Read boot code version */
IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor);
/** Read Device serial number */
IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid);
/** Compare memory */
IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size);
/** Invoke ISP */
void InvokeISP(void);
/**
* @}
*/
/**
* @}
*/
#endif /*_LPC_IAP_H*/

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/**********************************************************************
* $Id$ lpc_lcd.h 2011-10-14
*//**
* @file lpc_lcd.h
* @brief Contains all functions support for LCD firmware library
* on LPC
* @version 1.0
* @date 14. October. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#include "lpc_types.h"
#ifndef __LPC_LCD_H_
#define __LPC_LCD_H_
/** @defgroup LCD LCD (Liquid Crystal Display)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
/** @defgroup LCD_Public_Macros LCD Public Macros
* @{
*/
#define LCD_PWR_ENA_DIS_DLY 10000
#define LCD_FUNC_OK 0
#define LCD_FUNC_ERR -1
#define GET_CURSOR_IMG_SIZE(size) ((size == 32) ? 64:256)
/**
* @}
*/
/** @defgroup LCD_Public_Types LCD Public Types
* @{
*/
typedef enum __LCD_TYPES
{
LCD_STN_MONOCHROME,
LCD_STN_COLOR,
LCD_TFT,
LCD_TYPE_UNKNOWN,
} LCD_TYPES;
typedef enum __LCD_BPP
{
LCD_BPP_1 = 0x00,
LCD_BPP_2 = 0x01,
LCD_BPP_4 = 0x02,
LCD_BPP_8 = 0x03,
LCD_BPP_16 = 0x04,
LCD_BPP_24 = 0x05,
LCD_BPP_16_565Mode = 0x06,
LCD_BPP_12_444Mode = 0x07,
} LCD_BPP;
typedef enum __LCD_PANEL
{
LCD_PANEL_UPPER,
LCD_PANEL_LOWER,
}LCD_PANEL;
/**
* @brief A struct for Bitmap on LCD screen
*/
typedef struct _Bmp_t
{
uint32_t H_Size;
uint32_t V_Size;
uint32_t BitsPP;
uint32_t BytesPP;
uint8_t *pPalette;
uint8_t *pPicStream;
uint8_t *pPicDesc;
} Bmp_t, *pBmp_t;
/**
* @brief A struct for Font Type on LCD screen
*/
typedef struct _FontType_t
{
uint32_t H_Size;
uint32_t V_Size;
uint32_t CharacterOffset;
uint32_t CharactersNuber;
uint8_t *pFontStream;
uint8_t *pFontDesc;
} FontType_t, *pFontType_t;
/**
* @brief A struct for LCD Palette
*/
typedef struct __LCD_PALETTE_Type
{
uint8_t Red;
uint8_t Green;
uint8_t Blue;
}LCD_PALETTE_Type, *pLCD_PALETTE_Type;
/**
* @brief A struct for Horizontal configuration
*/
typedef struct __LCD_HConfig_Type
{
uint8_t hfp; // Horizontal front porch
uint8_t hbp; // Horizontal back porch
uint8_t hsw; // Horizontal synchronization pulse width
uint16_t ppl; // Number of pixels per line
}LCD_HConfig_Type;
/**
* @brief A struct for Vertical configuration
*/
typedef struct __LCD_VConfig_Type
{
uint8_t vfp; // Vertical front and back porch
uint8_t vbp; // Vertical back porch
uint8_t vsw; // Vertical synchronization pulse width
uint16_t lpp; // Number of lines per panel
}LCD_VConfig_Type;
/**
* @brief A struct for Polarity configuration
*/
typedef struct __LCD_POLARITY_Type
{
uint16_t cpl; // Number of pixel clocks per line
uint8_t active_high; // Signal polarity, active HIGH or LOW
uint8_t acb; // AC bias pin frequency
uint8_t invert_panel_clock; // Invert Panel clock;
uint8_t invert_hsync; // Invert HSYNC
uint8_t invert_vsync; // Invert VSYSNC
}LCD_POLARITY_Type;
/**
* @brief A struct for LCD Configuration
*/
typedef struct __LCD_Config_Type
{
LCD_HConfig_Type hConfig; // Horizontal config
LCD_VConfig_Type vConfig; // Vertical config
LCD_POLARITY_Type polarity; // Polarity config
uint32_t panel_clk; // Panel clock frequency
LCD_BPP lcd_bpp; // Bits-per-pixel
LCD_TYPES lcd_type; // Display type: STN monochrome, STN color, or TFT
uint8_t lcd_mono8; // STN 4 or 8-bit interface mode
uint8_t lcd_dual; // STN dual or single panel mode
uint8_t big_endian_byte; // byte ordering in memory
uint8_t big_endian_pixel; // pixel ordering within a byte
uint32_t lcd_panel_upper; // base address of frame buffer
uint32_t lcd_panel_lower; // base address of frame buffer
uint8_t* lcd_palette; // point to palette buffer
Bool lcd_bgr; // False: RGB , TRUE: BGR
} LCD_Config_Type;
/**
* @brief A struct for Cursor configuration
*/
typedef struct __LCD_Cursor_Config_Type
{
uint8_t size32; // 32x32 or 64x64
uint8_t framesync;
LCD_PALETTE_Type palette[2];
uint32_t baseaddress;
} LCD_Cursor_Config_Type;
typedef uint32_t LcdPixel_t, *pLcdPixel_t;
typedef int32_t LCD_RET_CODE;
/**
* @}
*/
/** @defgroup LCD_Public_Functions LCD Public Functions
* @{
*/
LCD_RET_CODE LCD_Init (LCD_Config_Type* pConfig);
void LCD_SetBaseAddress(LCD_PANEL panel, uint32_t pAddress);
void LCD_SetPalette (const uint8_t* pPallete);
void LCD_Enable (Bool bEna);
void LCD_Cursor_Cfg(LCD_Cursor_Config_Type* pConfig);
void LCD_Cursor_Enable(int enable, int cursor);
void LCD_Move_Cursor(int x, int y);
void LCD_Cursor_SetImage (const uint32_t *pCursor, int cursor, int size);
void LCD_SetImage(LCD_PANEL panel,const uint8_t *pPain);
void LCD_FillRect (LCD_PANEL panel, uint32_t startx,uint32_t endx,
uint32_t starty, uint32_t endy,
LcdPixel_t color);
void LCD_PutPixel (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, LcdPixel_t color);
void LCD_LoadPic (LCD_PANEL panel,uint32_t X_Left, uint32_t Y_Up, Bmp_t * pBmp, uint32_t Mask);
/**
* @}
*/
#endif // __LPC_LCD_H_
/**
* @}
*/

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/**********************************************************************
* $Id$ lpc_libcfg.h 2010-05-21
***
* @file lpc_libcfg.h
* @brief Library configuration file
* @version 3.0
* @date 20. June. 2010
* @author NXP MCU SW Application Team
*
* Copyright(C) 2010, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef _LPC_LIBCFG_DEFAULT_H_
#define _LPC_LIBCFG_DEFAULT_H_
#include "lpc_types.h"
/************************** DEBUG MODE DEFINITIONS *********************************/
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
the "CHECK_PARAM" macro in the FW library code */
#ifndef __CODE_RED
#define DEBUG
#endif
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
/* Comment the line below to disable the specific peripheral inclusion */
/* DEBUG_FRAMWORK -------------------- */
#define _DBGFWK
/* Clock & Power -------------------- */
#define _CLKPWR
/* CRC -------------------- */
#define _CRC
/* GPIO ------------------------------- */
#define _GPIO
/* NVIC ------------------------------- */
#define _NVIC
/* PINSEL ------------------------------- */
#define _PINSEL
/* EXTI ------------------------------- */
#define _EXTI
/* EMC ------------------------------- */
#define _EMC
/* UART ------------------------------- */
#define _UART
/* SPI ------------------------------- */
#define _SPI
/* SYSTICK --------------------------- */
#define _SYSTICK
/* SSP ------------------------------- */
#define _SSP
/* I2C ------------------------------- */
#define _I2C
/* TIMER ------------------------------- */
#define _TIM
/* WDT ------------------------------- */
#define _WDT
/* GPDMA ------------------------------- */
#define _GPDMA
/* DAC ------------------------------- */
#define _DAC
/* ADC ------------------------------- */
#define _ADC
/* EEPROM ------------------------------- */
#define _EEPROM
/* PWM ------------------------------- */
#define _PWM
/* RTC ------------------------------- */
#define _RTC
/* I2S ------------------------------- */
#define _I2S
/* USB device ------------------------------- */
#define _USBDEV
#ifdef _USBDEV
#define _USB_DEV_AUDIO
#define _USB_DEV_MASS_STORAGE
#define _USB_DEV_HID
#define _USB_DEV_VIRTUAL_COM
#endif /*_USBDEV*/
/* USB Host ------------------------------- */
#define _USBHost
/* QEI ------------------------------- */
#define _QEI
/* MCPWM ------------------------------- */
#define _MCPWM
/* CAN--------------------------------*/
#define _CAN
/* EMAC ------------------------------ */
#define _EMAC
/* LCD ------------------------------ */
#define _LCD
/* MCI ------------------------------ */
#define _MCI
/* IAP------------------------------ */
#define _IAP
/* BOD------------------------------ */
#define _BOD
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
#endif /* _LPC_LIBCFG_DEFAULT_H_ */

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/**********************************************************************
* $Id$ lpc_mci.h 2011-06-02
*//**
* @file lpc_mci.h
* @brief Contains all macro definitions and function prototypes
* support for MCI firmware library on LPC
* @version 2.0
* @date 29. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup MCI MCI (Multimedia Card Interface)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_MCI_H_
#define __LPC_MCI_H_
/** @defgroup MCI_Public_Macros MCI Public Macros
* @{
*/
#define MCI_DMA_ENABLED (1)
#define HIGH_LVL (1)
#define LOW_LVL (0)
/* SD/MMC Command list, per MMC spec. SD Memory Card Spec. Simplified version */
/* GO_IDLE_STATE(MMC) or RESET(SD) */
#define CMD0_GO_IDLE_STATE (0)
/* SEND_OP_COND(MMC) or ACMD41(SD) */
#define CMD1_SEND_OP_COND (1)
/* ALL_SEND_CID */
#define CMD2_ALL_SEND_CID (2)
/* SET_RELATE_ADDR */
#define CMD3_SET_RELATIVE_ADDR (3)
/* Set Bus-Width 1 bit or 4 bits */
#define ACMD6_SET_BUS_WIDTH (6)
/* SELECT/DESELECT_CARD */
#define CMD7_SELECT_CARD (7)
/**Sending interface condition cmd */
#define CMD8_SEND_IF_COND (8)
/* SEND_CSD */
#define CMD9_SEND_CSD (9)
/* Stop either READ or WRITE operation */
#define CMD12_STOP_TRANSMISSION 12
/* SEND_STATUS */
#define CMD13_SEND_STATUS (13)
/* SET_BLOCK_LEN */
#define CMD16_SET_BLOCK_LEN (16)
/* READ_SINGLE_BLOCK */
#define CMD17_READ_SINGLE_BLOCK (17)
/* READ_MULTIPLE_BLOCK */
#define CMD18_READ_MULTIPLE_BLOCK (18)
/* WRITE_BLOCK */
#define CMD24_WRITE_BLOCK (24)
/* WRITE_MULTIPLE_BLOCK */
#define CMD25_WRITE_MULTIPLE_BLOCK (25)
/* Start erase block number*/
#define CMD32_ERASE_WR_BLK_START (32)
/* End erase block number*/
#define CMD33_ERASE_WR_BLK_END (33)
/* Start erase*/
#define CMD38_ERASE (38)
/* ACMD41 for SD card */
#define ACMD41_SEND_APP_OP_COND (41)
/* APP_CMD, the following will a ACMD */
#define CMD55_APP_CMD (55)
#define OCR_INDEX (0x00FF8000)
#define RCA_ARGUMENT_POS (16)
#define RCA_ARGUMENT_MASK (0xFFFF)
/* Card Status (coded in 32 bits) in R1 & R1b Response */
#define CARD_STATUS_OUT_OF_RANGE ( 1 << 31)
#define CARD_STATUS_ADDRESS_ERROR ( 1 << 30)
#define CARD_STATUS_BLOCK_LEN_ERROR ( 1 << 29)
#define CARD_STATUS_ERASE_SEQ_ERROR ( 1 << 28)
#define CARD_STATUS_ERASE_PARAM_ERROR ( 1 << 27)
#define CARD_STATUS_WP_VIOLATION ( 1 << 26)
#define CARD_STATUS_CARD_IS_LOCKED ( 1 << 25)
#define CARD_STATUS_COM_CRC_ERROR ( 1 << 23)
#define CARD_STATUS_ILLEGAL_COMMAND ( 1 << 22)
#define CARD_STATUS_CARD_ECC_FAILED ( 1 << 21)
#define CARD_STATUS_CC_ERROR ( 1 << 20)
#define CARD_STATUS_GEN_ERROR ( 1 << 19)
#define CARD_STATUS_CSD_OVERWRITE ( 1 << 16)
#define CARD_STATUS_WP_ERASE_SKIP ( 1 << 15)
#define CARD_STATUS_CARD_ECC_DISABLED ( 1 << 14)
#define CARD_STATUS_ERASE_RESET ( 1 << 13)
#define CARD_STATUS_READY_FOR_DATA ( 1 << 8)
#define CARD_STATUS_ACMD_ENABLE ( 1 << 5)
#define CARD_STATUS_ERR_MASK (0xFDF88008)
#define CARDSTATEOF(x) ((x>>9) & 0x0F)
#define CARD_STATE_IDLE (0)
#define CARD_STATE_READY (1)
#define CARD_STATE_IDENT (2)
#define CARD_STATE_STBY (3)
#define CARD_STATE_TRAN (4)
#define CARD_STATE_DATA (5)
#define CARD_STATE_RCV (6)
#define CARD_STATE_PRG (7)
#define CARD_STATE_DIS (8)
/* CID in R2 reponse (Code length is 136 bits) */
#define MCI_CID_MANUFACTURER_ID_WPOS (24) //pos in word 0
#define MCI_CID_MANUFACTURER_ID_WBMASK (0xFF)
#define MCI_CID_OEMAPPLICATION_ID_WPOS (8) //pos in word 0
#define MCI_CID_OEMAPPLICATION_ID_WBMASK (0xFFFF)
#define MCI_CID_PRODUCTNAME_ID_H_WPOS (0) //pos in word 0
#define MCI_CID_PRODUCTNAME_ID_H_WBMASK (0xFF)
#define MCI_CID_PRODUCTNAME_ID_L_WPOS (0) //pos in word 1
#define MCI_CID_PRODUCTNAME_ID_L_WBMASK (0xFFFFFFFF)
#define MCI_CID_PRODUCTREVISION_ID_WPOS (24) //pos in word 2
#define MCI_CID_PRODUCTREVISION_ID_WBMASK (0xFF)
#define MCI_CID_PRODUCTSERIALNUM_ID_H_WPOS (0) //pos in word 2
#define MCI_CID_PRODUCTSERIALNUM_ID_H_WBMASK (0x00FFFFFF)
#define MCI_CID_PRODUCTSERIALNUM_ID_L_WPOS (24) //pos in word 3
#define MCI_CID_PRODUCTSERIALNUM_ID_L_WBMASK (0xFF)
#define MCI_CID_PRODUCTSERIALNUM_ID_WBMASK (0xFFFFFFFF)
#define MCI_CID_RESERVED_ID_WPOS (20) //pos in word 3
#define MCI_CID_RESERVED_ID_WBMASK (0x1F)
#define MCI_CID_MANUFACTURINGDATE_ID_WPOS (8) //in word 3
#define MCI_CID_MANUFACTURINGDATE_ID_WBMASK (0x0FFF)
#define MCI_CID_CHECKSUM_ID_WPOS (1) //in word 3
#define MCI_CID_CHECKSUM_ID_WBMASK (0x7F)
#define MCI_CID_UNUSED_ID_WPOS (0) //in word 3
#define MCI_CID_UNUSED_ID_WBMASK (0x01)
/* R6 (Published RCA response) */
#define RCA_RES_CARD_STATUS_POS (0)
#define RCA_RES_CARD_STATUS_MASK (0xFFFF)
#define RCA_RES_NEW_PUBLISHED_RCA_POS (16)
#define RCA_RES_NEW_PUBLISHED_RCA_MASK (0xFFFF)
/* R7 (Card interface condition) */
#define MCI_CMD8_VOLTAGESUPPLIED_POS (8)
#define MCI_CMD8_VOLTAGESUPPLIED_BMASK (0x0F)
#define MCI_CMD8_VOLATAGESUPPLIED_NOT_DEFINED (0)
#define MCI_CMD8_VOLATAGESUPPLIED_27_36 (1) /*2.7 - 3.6V*/
#define MCI_CMD8_CHECKPATTERN_POS (0)
#define MCI_CMD8_CHECKPATTERN_BMASK (0xFF)
#define MCI_SLOW_RATE (400000) /* 400KHz */
#define MCI_NORMAL_RATE (20000000) /* 20MHz */
#define SD_1_BIT (0)
#define SD_4_BIT (1)
#define DATA_TIMER_VALUE_R (MCI_NORMAL_RATE/4) // 250ms
#define DATA_TIMER_VALUE_W (MCI_NORMAL_RATE) // 1000ms
#define DATA_RW_MAX_LEN (0xFFFF)
#define EXPECT_NO_RESP (0)
#define EXPECT_SHORT_RESP (1)
#define EXPECT_LONG_RESP (2)
#define MCI_OUTPUT_MODE_PUSHPULL (0)
#define MCI_OUTPUT_MODE_OPENDRAIN (1)
#define NOT_ALLOW_CMD_TIMER (0)
#define ALLOW_CMD_TIMER (1)
#define MCI_DISABLE_CMD_TIMER (1<<8)
/* For the SD card I tested, the minimum block length is 512 */
/* For MMC, the restriction is loose, due to the variety of SD and MMC
card support, ideally, the driver should read CSD register to find the
speed and block length for the card, and set them accordingly. */
/* In this driver example, it will support both MMC and SD cards, it
does read the information by send SEND_CSD to poll the card status,
but, it doesn't configure them accordingly. this is not intended to
support all the SD and MMC card. */
/* DATA_BLOCK_LEN table
DATA_BLOCK_LEN Actual Size( BLOCK_LENGTH )
11 2048
10 1024
9 512
8 256
7 128
6 64
5 32
4 16
3 8
2 4
1 2
*/
/* This is the size of the buffer of origin data */
#define MCI_DMA_SIZE (1000UL)
/* This is the area original data is stored or data to be written to the SD/MMC card. */
#define MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE
/* This is the area, after reading from the SD/MMC*/
#define MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE)
/* To simplify the programming, please note that, BLOCK_LENGTH is a multiple
of FIFO_SIZE */
#define DATA_BLOCK_LEN (9) /* Block size field in DATA_CTRL */
#define BLOCK_LENGTH (1 << DATA_BLOCK_LEN)
/* for SD card, 128, the size of the flash */
/* card is 512 * 128 = 64K */
#define BLOCK_NUM 0x80
#define FIFO_SIZE 16
#define BUS_WIDTH_1BIT 0
#define BUS_WIDTH_4BITS 10
/* MCI Status register bit information */
#define MCI_CMD_CRC_FAIL (1 << 0)
#define MCI_DATA_CRC_FAIL (1 << 1)
#define MCI_CMD_TIMEOUT (1 << 2)
#define MCI_DATA_TIMEOUT (1 << 3)
#define MCI_TX_UNDERRUN (1 << 4)
#define MCI_RX_OVERRUN (1 << 5)
#define MCI_CMD_RESP_END (1 << 6)
#define MCI_CMD_SENT (1 << 7)
#define MCI_DATA_END (1 << 8)
#define MCI_START_BIT_ERR (1 << 9)
#define MCI_DATA_BLK_END (1 << 10)
#define MCI_CMD_ACTIVE (1 << 11)
#define MCI_TX_ACTIVE (1 << 12)
#define MCI_RX_ACTIVE (1 << 13)
#define MCI_TX_HALF_EMPTY (1 << 14)
#define MCI_RX_HALF_FULL (1 << 15)
#define MCI_TX_FIFO_FULL (1 << 16)
#define MCI_RX_FIFO_FULL (1 << 17)
#define MCI_TX_FIFO_EMPTY (1 << 18)
#define MCI_RX_FIFO_EMPTY (1 << 19)
#define MCI_TX_DATA_AVAIL (1 << 20)
#define MCI_RX_DATA_AVAIL (1 << 21)
/***********************************************************************
* MCI Data control register definitions
**********************************************************************/
/** Data transfer enable */
#define MCI_DATACTRL_ENABLE_POS (0)
#define MCI_DATACTRL_ENABLE_MASK (0x01)
#define MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS)
#define MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS)
/** Data transfer direction */
#define MCI_DATACTRL_DIR_POS (1)
#define MCI_DATACTRL_DIR_MASK (0x01)
#define MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS)
#define MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS)
/** Data transfer mode */
#define MCI_DATACTRL_XFER_MODE_POS (2)
#define MCI_DATACTRL_XFER_MODE_MASK (0x01)
#define MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS)
#define MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS)
/** Enable DMA */
#define MCI_DATACTRL_DMA_ENABLE_POS (3)
#define MCI_DATACTRL_DMA_ENABLE_MASK (0x01)
#define MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS)
#define MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS)
/** Data block length macro */
#define MCI_DTATCTRL_BLOCKSIZE(n) _SBF(4, (n & 0xF))
#define CMD_INT_MASK (MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END \
| MCI_CMD_SENT | MCI_CMD_ACTIVE)
#define DATA_ERR_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN \
| MCI_RX_OVERRUN | MCI_START_BIT_ERR)
#define ACTIVE_INT_MASK ( MCI_TX_ACTIVE | MCI_RX_ACTIVE)
#define FIFO_INT_MASK (MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL \
| MCI_TX_FIFO_FULL | MCI_RX_FIFO_FULL \
| MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY \
| MCI_DATA_BLK_END )
#define FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY )
#define FIFO_RX_INT_MASK (MCI_RX_HALF_FULL )
#define DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END)
#define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR)
#define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR)
/* Error code on the command response. */
#define INVALID_RESPONSE 0xFFFFFFFF
/**
* @}
*/
/** @defgroup MCI_Public_Types MCI Public Types
* @{
*/
typedef enum mci_card_state
{
MCI_CARDSTATE_IDLE = 0,
MCI_CARDSTATE_READY,
MCI_CARDSTATE_IDENDTIFIED,
MCI_CARDSTATE_STBY,
MCI_CARDSTATE_TRAN,
MCI_CARDSTATE_DATA,
MCI_CARDSTATE_RCV,
MCI_CARDSTATE_PRG,
MCI_CARDSTATE_DIS,
}en_Mci_CardState;
typedef enum mci_func_error
{
MCI_FUNC_OK = 0,
MCI_FUNC_FAILED = -1,
MCI_FUNC_BAD_PARAMETERS = -2,
MCI_FUNC_BUS_NOT_IDLE = -3,
MCI_FUNC_TIMEOUT = -3,
MCI_FUNC_ERR_STATE = -4,
MCI_FUNC_NOT_READY = -5,
}en_Mci_Func_Error;
typedef enum mci_card_type
{
MCI_SDHC_SDXC_CARD = 3,
MCI_SDSC_V2_CARD = 2,
MCI_MMC_CARD = 1,
MCI_SDSC_V1_CARD = 0,
MCI_CARD_UNKNOWN = -1,
}en_Mci_CardType;
typedef struct mci_cid
{
/** Manufacturer ID */
uint8_t MID;
/** OEM/Application ID */
uint16_t OID;
/** Product name 8-bits higher */
uint8_t PNM_H;
/** Product name 32-bits Lower */
uint32_t PNM_L;
/** Product revision */
uint8_t PRV;
/** Product serial number */
uint32_t PSN;
/** reserved: 4 bit */
uint8_t reserved;
/** Manufacturing date: 12 bit */
uint16_t MDT;
/** CRC7 checksum: 7 bit */
uint8_t CRC;
/** not used, always: 1 bit always 1 */
uint8_t unused;
} st_Mci_CardId;
typedef struct cmd_info{
/** Command ID*/
uint32_t CmdIndex;
/** Command Argument*/
uint32_t Argument;
/** Expected response: no response, short response or long response */
uint32_t ExpectResp;
/** Allow timeout */
uint32_t AllowTimeout;
/** Command Response Info */
uint32_t *CmdResp;
} st_Mci_CmdInfo;
/**
* @}
*/
/** @defgroup MCI_Public_Functions MCI Public Functions
* @{
*/
int32_t MCI_Init(uint8_t powerActiveLevel );
void MCI_SendCmd( st_Mci_CmdInfo* pCmdIf );
int32_t MCI_GetCmdResp( uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus );
int32_t MCI_CmdResp(st_Mci_CmdInfo *pCmdIf);
void MCI_Set_MCIClock( uint32_t clockrate );
int32_t MCI_SetBusWidth( uint32_t width );
int32_t MCI_Acmd_SendOpCond(uint8_t hcsVal);
int32_t MCI_CardInit( void );
en_Mci_CardType MCI_GetCardType(void);
int32_t MCI_CardReset( void );
int32_t MCI_Cmd_SendIfCond(void);
int32_t MCI_GetCID(st_Mci_CardId* cidValue);
int32_t MCI_SetCardAddress( void );
uint32_t MCI_GetCardAddress(void);
int32_t MCI_GetCSD(uint32_t* csdVal);
int32_t MCI_Cmd_SelectCard( void );
int32_t MCI_GetCardStatus(int32_t* cardStatus);
uint32_t MCI_GetDataXferEndState(void);
uint32_t MCI_GetXferErrState(void);
int32_t MCI_SetBlockLen( uint32_t blockLength );
int32_t MCI_Acmd_SendBusWidth( uint32_t buswidth );
int32_t MCI_Cmd_StopTransmission( void );
int32_t MCI_Cmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock);
int32_t MCI_Cmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock);
int32_t MCI_WriteBlock(volatile uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock);
int32_t MCI_ReadBlock(volatile uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock);
#if MCI_DMA_ENABLED
void MCI_DMA_IRQHandler (void);
#endif
/**
* @}
*/
#endif /* end __LPC_MCI_H_ */
/**
* @}
*/
/****************************************************************************
** End Of File
****************************************************************************/

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/**********************************************************************
* $Id$ lpc_mcpwm.h 2011-06-02
*//**
* @file lpc_mcpwm.h
* @brief Contains all macro definitions and function prototypes
* support for Motor Control PWM firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup MCPWM MCPWM (Motor Control PWM)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_MCPWM_H_
#define __LPC_MCPWM_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup MCPWM_Public_Macros MCPWM Public Macros
* @{
*/
/** Edge aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
/** Center aligned mode for channel in MCPWM */
#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
* the six output pins under the control of the bits in this register */
#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/* Interrupt type in MCPWM */
/** Limit interrupt for channel (0) */
#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
/** Match interrupt for channel (0) */
#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
/** Capture interrupt for channel (0) */
#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
/** Limit interrupt for channel (1) */
#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
/** Match interrupt for channel (1) */
#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
/** Capture interrupt for channel (1) */
#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
/** Limit interrupt for channel (2) */
#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
/** Match interrupt for channel (2) */
#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
/** Capture interrupt for channel (2) */
#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
/** Fast abort interrupt */
#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
* @{
*/
/*********************************************************************//**
* Macro defines for MCPWM Control register
**********************************************************************/
/* MCPWM Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Control read address
* - MCPWM Control set address
* - MCPWM Control clear address
*/
/** Stops/starts timer channel n */
#define MCPWM_CON_RUN(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+0))) : (0))
/** Edge/center aligned operation for channel n */
#define MCPWM_CON_CENTER(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+1))) : (0))
/** Select polarity of the MCOAn and MCOBn pin */
#define MCPWM_CON_POLAR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+2))) : (0))
/** Control the dead-time feature for channel n */
#define MCPWM_CON_DTE(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+3))) : (0))
/** Enable/Disable update of functional register for channel n */
#define MCPWM_CON_DISUP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+4))) : (0))
/** Control the polarity for all 3 channels */
#define MCPWM_CON_INVBDC ((uint32_t)((uint32_t)1<<29))
/** 3-phase AC mode select */
#define MCPWM_CON_ACMODE ((uint32_t)((uint32_t)1<<30))
/** 3-phase DC mode select */
#define MCPWM_CON_DCMODE ((uint32_t)((uint32_t)1<<31))
/*********************************************************************//**
* Macro defines for MCPWM Capture Control register
**********************************************************************/
/* Capture Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Capture Control read address
* - MCPWM Capture Control set address
* - MCPWM Capture control clear address
*/
/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
/** TC(n) is reset by channel (n) capture event */
#define MCPWM_CAPCON_RT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(18+(n)))) : (0))
/** Hardware noise filter: channel (n) capture events are delayed */
#define MCPWM_CAPCON_HNFCAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(21+(n)))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Interrupt register
**********************************************************************/
/* Interrupt registers, these macro definitions below can be applied for these
* register type:
* - MCPWM Interrupt Enable read address
* - MCPWM Interrupt Enable set address
* - MCPWM Interrupt Enable clear address
* - MCPWM Interrupt Flags read address
* - MCPWM Interrupt Flags set address
* - MCPWM Interrupt Flags clear address
*/
/** Limit interrupt for channel (n) */
#define MCPWM_INT_ILIM(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+0))) : (0))
/** Match interrupt for channel (n) */
#define MCPWM_INT_IMAT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+1))) : (0))
/** Capture interrupt for channel (n) */
#define MCPWM_INT_ICAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+2))) : (0))
/** Fast abort interrupt */
#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
/*********************************************************************//**
* Macro defines for MCPWM Count Control register
**********************************************************************/
/* MCPWM Count Control register, these macro definitions below can be applied for these
* register type:
* - MCPWM Count Control read address
* - MCPWM Count Control set address
* - MCPWM Count Control clear address
*/
/** Counter(tc) advances on a rising edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
/** Channel (n) is in counter mode */
#define MCPWM_CNTCON_CNTR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(29+n))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Dead-time register
**********************************************************************/
/** Dead time value x for channel n */
#define MCPWM_DT(n,x) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
/*********************************************************************//**
* Macro defines for MCPWM Communication Pattern register
**********************************************************************/
#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
/*********************************************************************//**
* Macro defines for MCPWM Capture clear address register
**********************************************************************/
/** Clear the MCCAP (n) register */
#define MCPWM_CAPCLR_CAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<n)) : (0))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup MCPWM_Public_Types MCPWM Public Types
* @{
*/
typedef enum
{
MCPWM_CHANNEL_0 = 0,
MCPWM_CHANNEL_1,
MCPWM_CHANNEL_2,
MCPWM_MAX_CHANNEL,
} en_MCPWM_Channel_Id;
/**
* @brief Motor Control PWM Channel Configuration structure type definition
*/
typedef struct {
uint32_t channelType; /**< Edge/center aligned mode for this channel,
should be:
- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
*/
uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
*/
uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
should be:
- ENABLE.
- DISABLE.
*/
uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
uint32_t channelPeriodValue; /**< MCPWM Period value */
uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
} MCPWM_CHANNEL_CFG_Type;
/**
* @brief MCPWM Capture Configuration type definition
*/
typedef struct {
uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
- ENABLE.
- DISABLE.
*/
uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_CAPTURE_CFG_Type;
/**
* @brief MCPWM Count Control Configuration type definition
*/
typedef struct {
uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
- ENABLE.
- DISABLE.
*/
uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
- ENABLE.
- DISABLE.
*/
} MCPWM_COUNT_CFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
* @{
*/
void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type * channelSetup);
void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type *channelSetup);
void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CAPTURE_CFG_Type *captureConfig);
void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
uint32_t outputInvered, uint32_t outputPattern);
void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_MCPWM_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_nvic.h 2011-06-02
*//**
* @file lpc_nvic.h
* @brief Contains all macro definitions and function prototypes
* support for Nesting Vectored Interrupt firmware library
* on LPC. The main NVIC functions are defined in
* core_cm3.h
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup NVIC NVIC (Nested Vectored Interrupt Controller)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_NVIC_H_
#define __LPC_NVIC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Functions ----------------------------------------------------------- */
/** @defgroup NVIC_Public_Functions NVIC Public Functions
* @{
*/
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_SetVTOR(uint32_t offset);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_NVIC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_pinsel.h 2011-06-02
*//**
* @file lpc_pinsel.h
* @brief Contains all macro definitions and function prototypes
* support for Pin-connection block firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PINSEL PINSEL (Pin Selection)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_PINSEL_H
#define __LPC_PINSEL_H
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
/* Public Macros -------------------------------------------------------------- */
/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
* @{
*/
/* Macros define IOCON bits*/
/** Selects pin functions */
#define IOCON_FUNC_POS (0)
#define IOCON_FUNC_MASK (0x07<<IOCON_FUNC_POS)
/** Selects output function mode (on-chip pull-up/pull-down resistor control */
#define IOCON_MODE_POS (3)
#define IOCON_MODE_MASK (0x03<<IOCON_MODE_POS)
#define IOCON_MODE_PLAIN ((0<<IOCON_MODE_POS))
#define IOCON_MODE_PULLDOWN ((1<<IOCON_MODE_POS))
#define IOCON_MODE_PULLUP ((2<<IOCON_MODE_POS))
#define IOCON_MODE_REPEATER ((3<<IOCON_MODE_POS))
/** Hysteresis */
#define IOCON_HYS_POS (5)
#define IOCON_HYS_MASK (0x01<<IOCON_HYS_POS)
#define IOCON_HYS_ENABLE ((1<<IOCON_HYS_POS))
/** Input polarity */
#define IOCON_INVERT_POS (6)
#define IOCON_INVERT_MASK (0x01<<IOCON_INVERT_POS)
#define IOCON_INVERT_INPUT (1<<IOCON_INVERT_POS)
/** Selects Analog/Digital mode */
#define IOCON_ADMODE_POS (7)
#define IOCON_ADMODE_MASK (0x01<<IOCON_ADMODE_POS)
#define IOCON_ANALOG_MODE (0<<IOCON_ADMODE_POS)
#define IOCON_DIGITIAL_MODE (1<<IOCON_ADMODE_POS)
/* Controls Glitch Filter */
#define IOCON_FILTER_POS (8)
#define IOCON_FILTER_MASK (0x01<<IOCON_FILTER_POS)
#define IOCON_10ns_FILTER_ENABLE (0<<IOCON_FILTER_POS)
#define IOCON_10ns_FILTER_DISABLE (1<<IOCON_FILTER_POS)
/** I2C 50ns glitch filter and slew rate control */
#define IOCON_HS_POS (8)
#define IOCON_HS_MASK (0x01<<IOCON_HS_POS)
#define IOCON_I2C_FILTER_ENABLE (0<<IOCON_HS_POS)
#define IOCON_I2C_FILTER_DISABLE (1<<IOCON_HS_POS)
/** Driver Output Slew Rate Control*/
#define IOCON_SLEW_POS (9)
#define IOCON_SLEW_MASK (0x01<<IOCON_SLEW_POS)
#define IOCON_SLEW_ENABLE ((1<<IOCON_SLEW_POS))
/** Controls sink current capability of the pin*/
#define IOCON_HIDRIVE_POS (9)
#define IOCON_HIDRIVE_MASK (0x01<<IOCON_HIDRIVE_POS)
#define IOCON_I2CMODE_FASTPLUS (1<<IOCON_HIDRIVE_POS)
/** Controls open-drain mode */
#define IOCON_OD_POS (10)
#define IOCON_OD_MASK (0x01<<IOCON_OD_POS)
#define IOCON_OPENDRAIN_MODE (1<<IOCON_OD_POS)
/** DAC enable control */
#define IOCON_DACEN_POS (16)
#define IOCON_DACEN_MASK (0x01<<IOCON_DACEN_POS)
#define IOCON_DAC_ENABLE (1<<IOCON_DACEN_POS)
/* Macros define for Return Code */
typedef int32_t PINSEL_RET_CODE;
#define PINSEL_RET_OK (0)
#define PINSEL_RET_INVALID_PIN (0x10000001)
#define PINSEL_RET_NOT_SUPPORT (0x10000002)
#define PINSEL_RET_ERR (-1)
/**
* @}
*/
/** @defgroup PINSEL_Public_Types PINSEL Public Types
* @{
*/
typedef enum
{
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
}PinSel_BasicMode;
typedef enum
{
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
PINSEL_I2CMODE_FAST_STANDARD = 0,
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
PINSEL_I2CMODE_OPENDRAINIO,
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
PINSEL_I2CMODE_FASTMODEPLUS,
}PinSel_I2cMode;
typedef enum
{
/** Type D IOCON registers */
PINSEL_PIN_TYPE_D,
/** Type A IOCON registers */
PINSEL_PIN_TYPE_A,
/** Type U IOCON registers */
PINSEL_PIN_TYPE_U,
/** Type I IOCON registers */
PINSEL_PIN_TYPE_I,
/** Type W IOCON registers */
PINSEL_PIN_TYPE_W,
/** Unknown type */
PINSEL_PIN_TYPE_UNKNOWN,
}PinSel_PinType;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
* @{
*/
PinSel_PinType PINSEL_GetPinType(uint8_t portnum, uint8_t pinnum);
PINSEL_RET_CODE PINSEL_ConfigPin(uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
PINSEL_RET_CODE PINSEL_SetPinMode(uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum);
PINSEL_RET_CODE PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
PINSEL_RET_CODE PINSEL_SetInvertInput(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
PINSEL_RET_CODE PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
PINSEL_RET_CODE PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode);
PINSEL_RET_CODE PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
PINSEL_RET_CODE PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable);
PINSEL_RET_CODE PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable);
PINSEL_RET_CODE PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
PINSEL_RET_CODE PINSEL_SetI2CFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
/**
* @}
*/
#endif /* LPC_PINSEL_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_pwm.h 2011-06-02
*//**
* @file lpc_pwm.h
* @brief Contains all macro definitions and function prototypes
* support for PWM firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PWM PWM (Pulse Width Modulator)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_PWM_H_
#define __LPC_PWM_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup PWM_Private_Macros PWM Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/**********************************************************************
* IR register definitions
**********************************************************************/
/** Interrupt flag for PWM match channel for 6 channel */
#define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
/** Interrupt flag for capture input */
#define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))
/** IR register mask */
#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))
/**********************************************************************
* TCR register definitions
**********************************************************************/
/** TCR register mask */
#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))
/** PWM Counter Enable */
#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0))
/** PWM Counter Reset */
#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1))
/** PWM Enable */
#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3))
/**********************************************************************
* CTCR register definitions
**********************************************************************/
/** CTCR register mask */
#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))
/** PWM Counter-Timer Mode */
#define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))
/** PWM Capture input select */
#define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))
/**********************************************************************
* MCR register definitions
**********************************************************************/
/** MCR register mask */
#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))
/** generate a PWM interrupt when a MATCHn occurs */
#define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
/** reset the PWM when a MATCHn occurs */
#define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
/** stop the PWM when a MATCHn occurs */
#define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
/**********************************************************************
* CCR register definitions
**********************************************************************/
/** CCR register mask */
#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))
/** PCAPn is rising edge sensitive */
#define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
/** PCAPn is falling edge sensitive */
#define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
/** PWM interrupt is generated on a PCAP event */
#define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
/**********************************************************************
* PCR register definitions
**********************************************************************/
/** PCR register mask */
#define PWM_PCR_BITMASK (uint32_t)0x00007E7C
/** PWM output n is a single edge controlled output */
#define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
/** enable PWM output n */
#define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
/**********************************************************************
* LER register definitions
**********************************************************************/
/** LER register mask*/
#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))
/** PWM MATCHn register update control */
#define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup PWM_Public_Types PWM Public Types
* @{
*/
typedef enum
{
PWM_0 = 0,
PWM_1 = 1
} en_PWM_unitId;
/** @brief Configuration structure in PWM TIMER mode */
typedef struct
{
uint8_t PrescaleOption; /**< Prescale option, should be:
- PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
- PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
*/
uint8_t Reserved[3];
uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched
with PrescaleOption
*/
} PWM_TIMERCFG_Type;
/** @brief Configuration structure in PWM COUNTER mode */
typedef struct
{
uint8_t CounterOption; /**< Counter Option, should be:
- PWM_COUNTER_RISING: Rising Edge
- PWM_COUNTER_FALLING: Falling Edge
- PWM_COUNTER_ANY: Both rising and falling mode
*/
uint8_t CountInputSelect; /**< Counter input select, should be:
- PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
- PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
*/
uint8_t Reserved[2];
} PWM_COUNTERCFG_Type;
/** @brief PWM Match channel configuration structure */
typedef struct
{
uint8_t MatchChannel; /**< Match channel, should be in range
from 0..6 */
uint8_t IntOnMatch; /**< Interrupt On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t StopOnMatch; /**< Stop On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ResetOnMatch; /**< Reset On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
} PWM_MATCHCFG_Type;
/** @brief PWM Capture Input configuration structure */
typedef struct
{
uint8_t CaptureChannel; /**< Capture channel, should be in range
from 0..1 */
uint8_t RisingEdge; /**< caption rising edge, should be:
- ENABLE: Enable rising edge.
- DISABLE: Disable this function.
*/
uint8_t FallingEdge; /**< caption falling edge, should be:
- ENABLE: Enable falling edge.
- DISABLE: Disable this function.
*/
uint8_t IntOnCaption; /**< Interrupt On caption, should be:
- ENABLE: Enable interrupt function.
- DISABLE: Disable this function.
*/
} PWM_CAPTURECFG_Type;
/* Timer/Counter in PWM configuration type definition -----------------------------------*/
/** @brief PMW TC mode select option */
typedef enum
{
PWM_MODE_TIMER = 0, /*!< PWM using Timer mode */
PWM_MODE_COUNTER, /*!< PWM using Counter mode */
} PWM_TC_MODE_OPT;
#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER))
/** @brief PWM Timer/Counter prescale option */
typedef enum
{
PWM_TIMER_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
PWM_TIMER_PRESCALE_USVAL /*!< Prescale in microsecond value */
} PWM_TIMER_PRESCALE_OPT;
#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL))
/** @brief PWM Input Select in counter mode */
typedef enum
{
PWM_COUNTER_PCAP1_0 = 0, /*!< PWM Counter input selected is PCAP1.0 pin */
PWM_COUNTER_PCAP1_1 /*!< PWM counter input selected is CAP1.1 pin */
} PWM_COUNTER_INPUTSEL_OPT;
#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1))
/** @brief PWM Input Edge Option in counter mode */
typedef enum
{
PWM_COUNTER_RISING = 1, /*!< Rising edge mode */
PWM_COUNTER_FALLING = 2, /*!< Falling edge mode */
PWM_COUNTER_ANY = 3 /*!< Both rising and falling mode */
} PWM_COUNTER_EDGE_OPT;
#define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \
|| (n==PWM_COUNTER_ANY))
/* PWM configuration type definition ----------------------------------------------------- */
/** @brief PWM operating mode options */
typedef enum
{
PWM_CHANNEL_SINGLE_EDGE, /*!< PWM Channel Single edge mode */
PWM_CHANNEL_DUAL_EDGE /*!< PWM Channel Dual edge mode */
} PWM_CHANNEL_EDGE_OPT;
#define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE))
/** @brief PWM update type */
typedef enum
{
PWM_MATCH_UPDATE_NOW = 0, /**< PWM Match Channel Update Now */
PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next
PWM Counter resetting */
} PWM_MATCH_UPDATE_OPT;
#define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST))
/** @brief PWM interrupt status type definition ----------------------------------------------------- */
/** @brief PWM Interrupt status type */
typedef enum
{
PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /**< Interrupt flag for PWM match channel 0 */
PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /**< Interrupt flag for PWM match channel 1 */
PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /**< Interrupt flag for PWM match channel 2 */
PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /**< Interrupt flag for PWM match channel 3 */
PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /**< Interrupt flag for capture input 0 */
PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /**< Interrupt flag for capture input 1 */
PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /**< Interrupt flag for PWM match channel 4 */
PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /**< Interrupt flag for PWM match channel 5 */
PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6), /**< Interrupt flag for PWM match channel 6 */
}PWM_INTSTAT_TYPE;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PWM_Public_Functions PWM Public Functions
* @{
*/
void PWM_PinConfig(uint8_t pwmId, uint8_t PWM_Channel, uint8_t PinselOption);
IntStatus PWM_GetIntStatus(uint8_t pwmId, uint32_t IntFlag);
void PWM_ClearIntPending(uint8_t pwmId, uint32_t IntFlag);
void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
void PWM_Init(uint8_t pwmId, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct);
void PWM_DeInit (uint8_t pwmId);
void PWM_Cmd(uint8_t pwmId, FunctionalState NewState);
void PWM_CounterCmd(uint8_t pwmId, FunctionalState NewState);
void PWM_ResetCounter(uint8_t pwmId);
void PWM_ConfigMatch(uint8_t pwmId, PWM_MATCHCFG_Type *PWM_MatchConfigStruct);
void PWM_ConfigCapture(uint8_t pwmId, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct);
uint32_t PWM_GetCaptureValue(uint8_t pwmId, uint8_t CaptureChannel);
void PWM_MatchUpdate(uint8_t pwmId, uint8_t MatchChannel, \
uint32_t MatchValue, uint8_t UpdateType);
void PWM_ChannelConfig(uint8_t pwmId, uint8_t PWMChannel, uint8_t ModeOption);
void PWM_ChannelCmd(uint8_t pwmId, uint8_t PWMChannel, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_PWM_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_qei.h 2011-06-02
*//**
* @file lpc_qei.h
* @brief Contains all macro definitions and function prototypes
* support for QEI firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup QEI QEI (Quadrature Encoder Interface)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC17X_8X_QEI_H_
#define __LPC17X_8X_QEI_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup QEI_Public_Macros QEI Public Macros
* @{
*/
#define QEI_0 (0)
/* QEI Reset types */
/** QEI Reset types - Reset position counter */
#define QEI_RESET_POS QEI_CON_RESP
/** QEI Reset types - Reset Posistion Counter on Index */
#define QEI_RESET_POSOnIDX QEI_CON_RESPI
/** QEI Reset types - Reset Velocity */
#define QEI_RESET_VEL QEI_CON_RESV
/** QEI Reset types - Reset Index Counter */
#define QEI_RESET_IDX QEI_CON_RESI
/* QEI Direction Invert Type Option */
/** QEI Direction Invert Type Option - Direction is not inverted */
#define QEI_DIRINV_NONE ((uint32_t)(0))
/** QEI Direction Invert Type Option - Direction is complemented */
#define QEI_DIRINV_CMPL ((uint32_t)(1))
/* QEI Signal Mode Option */
/** Signal operation: Quadrature phase mode */
#define QEI_SIGNALMODE_QUAD ((uint32_t)(0))
/** Signal operation: Clock/Direction mode */
#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1))
/* QEI Capture Mode Option */
/** Capture mode: Only Phase-A edges are counted (2X) */
#define QEI_CAPMODE_2X ((uint32_t)(0))
/** Capture mode: BOTH PhA and PhB edges are counted (4X)*/
#define QEI_CAPMODE_4X ((uint32_t)(1))
/* QEI Invert Index Signal Option */
/** Invert Index signal option: None */
#define QEI_INVINX_NONE ((uint32_t)(0))
/** Invert Index signal option: Enable */
#define QEI_INVINX_EN ((uint32_t)(1))
/* QEI timer reload option */
/** Reload value in absolute value */
#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0))
/** Reload value in microsecond value */
#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1))
/* QEI Flag Status type */
/** Direction status */
#define QEI_STATUS_DIR ((uint32_t)(1<<0))
/* QEI Compare Position channel option */
/** QEI compare position channel 0 */
#define QEI_COMPPOS_CH_0 ((uint8_t)(0))
/** QEI compare position channel 1 */
#define QEI_COMPPOS_CH_1 ((uint8_t)(1))
/** QEI compare position channel 2 */
#define QEI_COMPPOS_CH_2 ((uint8_t)(2))
/* QEI interrupt flag type */
/** index pulse was detected interrupt */
#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0))
/** Velocity timer over flow interrupt */
#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1))
/** Capture velocity is less than compare interrupt */
#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2))
/** Change of direction interrupt */
#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3))
/** An encoder phase error interrupt */
#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4))
/** An encoder clock pulse was detected interrupt */
#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5))
/** position 0 compare value is equal to the current position interrupt */
#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6))
/** position 1 compare value is equal to the current position interrupt */
#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7))
/** position 2 compare value is equal to the current position interrupt */
#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8))
/** Index compare value is equal to the current index count interrupt */
#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9))
/** Combined position 0 and revolution count interrupt */
#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10))
/** Combined position 1 and revolution count interrupt */
#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11))
/** Combined position 2 and revolution count interrupt */
#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12))
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup QEI_Private_Macros QEI Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* Quadrature Encoder Interface Control Register Definition --------------------- */
/*********************************************************************//**
* Macro defines for QEI Control register
**********************************************************************/
/** Reset position counter */
#define QEI_CON_RESP ((uint32_t)(1<<0))
/** Reset Posistion Counter on Index */
#define QEI_CON_RESPI ((uint32_t)(1<<1))
/** Reset Velocity */
#define QEI_CON_RESV ((uint32_t)(1<<2))
/** Reset Index Counter */
#define QEI_CON_RESI ((uint32_t)(1<<3))
/** QEI Control register bit-mask */
#define QEI_CON_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro defines for QEI Configuration register
**********************************************************************/
/** Direction Invert */
#define QEI_CONF_DIRINV ((uint32_t)(1<<0))
/** Signal mode */
#define QEI_CONF_SIGMODE ((uint32_t)(1<<1))
/** Capture mode */
#define QEI_CONF_CAPMODE ((uint32_t)(1<<2))
/** Invert index */
#define QEI_CONF_INVINX ((uint32_t)(1<<3))
/** QEI Configuration register bit-mask */
#define QEI_CONF_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro defines for QEI Status register
**********************************************************************/
/** Direction bit */
#define QEI_STAT_DIR ((uint32_t)(1<<0))
/** QEI status register bit-mask */
#define QEI_STAT_BITMASK ((uint32_t)(1<<0))
/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
/*********************************************************************//**
* Macro defines for QEI Interrupt Status register
**********************************************************************/
/** Indicates that an index pulse was detected */
#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0))
/** Indicates that a velocity timer overflow occurred */
#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1))
/** Indicates that capture velocity is less than compare velocity */
#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2))
/** Indicates that a change of direction was detected */
#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3))
/** Indicates that an encoder phase error was detected */
#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4))
/** Indicates that and encoder clock pulse was detected */
#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5))
/** Indicates that the position 0 compare value is equal to the current position */
#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6))
/** Indicates that the position 1compare value is equal to the current position */
#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7))
/** Indicates that the position 2 compare value is equal to the current position */
#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8))
/** Indicates that the index compare value is equal to the current index count */
#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9))
/** Combined position 0 and revolution count interrupt. Set when
* both the POS0_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10))
/** Combined position 1 and revolution count interrupt. Set when
both the POS1_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11))
/** Combined position 2 and revolution count interrupt. Set when
both the POS2_Int bit is set and the REV_Int is set */
#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Status register bit-mask */
#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF))
/*********************************************************************//**
* Macro defines for QEI Interrupt Set register
**********************************************************************/
/** Set Bit Indicates that an index pulse was detected */
#define QEI_INTSET_INX_Int ((uint32_t)(1<<0))
/** Set Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1))
/** Set Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2))
/** Set Bit Indicates that a change of direction was detected */
#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3))
/** Set Bit Indicates that an encoder phase error was detected */
#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4))
/** Set Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5))
/** Set Bit Indicates that the position 0 compare value is equal to the current position */
#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6))
/** Set Bit Indicates that the position 1compare value is equal to the current position */
#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7))
/** Set Bit Indicates that the position 2 compare value is equal to the current position */
#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8))
/** Set Bit Indicates that the index compare value is equal to the current index count */
#define QEI_INTSET_REV_Int ((uint32_t)(1<<9))
/** Set Bit that combined position 0 and revolution count interrupt */
#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10))
/** Set Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11))
/** Set Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Set register bit-mask */
#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF))
/*********************************************************************//**
* Macro defines for QEI Interrupt Clear register
**********************************************************************/
/** Clear Bit Indicates that an index pulse was detected */
#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0))
/** Clear Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1))
/** Clear Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2))
/** Clear Bit Indicates that a change of direction was detected */
#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3))
/** Clear Bit Indicates that an encoder phase error was detected */
#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4))
/** Clear Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5))
/** Clear Bit Indicates that the position 0 compare value is equal to the current position */
#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6))
/** Clear Bit Indicates that the position 1compare value is equal to the current position */
#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7))
/** Clear Bit Indicates that the position 2 compare value is equal to the current position */
#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8))
/** Clear Bit Indicates that the index compare value is equal to the current index count */
#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9))
/** Clear Bit that combined position 0 and revolution count interrupt */
#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10))
/** Clear Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11))
/** Clear Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Clear register bit-mask */
#define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF))
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable register
**********************************************************************/
/** Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_INTEN_INX_Int ((uint32_t)(1<<0))
/** Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1))
/** Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2))
/** Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3))
/** Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4))
/** Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5))
/** Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the current position */
#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6))
/** Enabled Interrupt Bit Indicates that the position 1compare value is equal to the current position */
#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7))
/** Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the current position */
#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8))
/** Enabled Interrupt Bit Indicates that the index compare value is equal to the current index count */
#define QEI_INTEN_REV_Int ((uint32_t)(1<<9))
/** Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10))
/** Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11))
/** Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Enable register bit-mask */
#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF))
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Set register
**********************************************************************/
/** Set Enable Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IESET_INX_Int ((uint32_t)(1<<0))
/** Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IESET_TIM_Int ((uint32_t)(1<<1))
/** Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IESET_VELC_Int ((uint32_t)(1<<2))
/** Set Enable Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IESET_DIR_Int ((uint32_t)(1<<3))
/** Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IESET_ERR_Int ((uint32_t)(1<<4))
/** Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5))
/** Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to
* the current position */
#define QEI_IESET_POS0_Int ((uint32_t)(1<<6))
/** Set Enable Interrupt Bit Indicates that the position 1compare value is equal to
* the current position */
#define QEI_IESET_POS1_Int ((uint32_t)(1<<7))
/** Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to
* the current position */
#define QEI_IESET_POS2_Int ((uint32_t)(1<<8))
/** Set Enable Interrupt Bit Indicates that the index compare value is equal to the
* current index count */
#define QEI_IESET_REV_Int ((uint32_t)(1<<9))
/** Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10))
/** Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11))
/** Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Enable Set register bit-mask */
#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF))
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Clear register
**********************************************************************/
/** Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IECLR_INX_Int ((uint32_t)(1<<0))
/** Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1))
/** Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2))
/** Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3))
/** Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4))
/** Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5))
/** Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
* current position */
#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6))
/** Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
* current position */
#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7))
/** Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
* current position */
#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8))
/** Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
* index count */
#define QEI_IECLR_REV_Int ((uint32_t)(1<<9))
/** Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10))
/** Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11))
/** Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12))
/** QEI Interrupt Enable Clear register bit-mask */
#define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF))
/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macro check QEI peripheral */
#define PARAM_QEIx(n) ((n==LPC_QEI))
/* Macro check QEI reset type */
#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
|| (n==QEI_RESET_POSOnIDX) \
|| (n==QEI_RESET_VEL) \
|| (n==QEI_RESET_IDX))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
/* Macro check QEI signal mode */
#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
/* Macro check QEI Capture mode */
#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
/* Macro check QEI Invert index mode */
#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
/* Macro check QEI Direction invert mode */
#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
/* Macro check QEI status type */
#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
/* Macro check QEI combine position type */
#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
/* Macro check QEI interrupt flag type */
#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
|| (n==QEI_INTFLAG_TIM_Int) \
|| (n==QEI_INTFLAG_VELC_Int) \
|| (n==QEI_INTFLAG_DIR_Int) \
|| (n==QEI_INTFLAG_ERR_Int) \
|| (n==QEI_INTFLAG_ENCLK_Int) \
|| (n==QEI_INTFLAG_POS0_Int) \
|| (n==QEI_INTFLAG_POS1_Int) \
|| (n==QEI_INTFLAG_POS2_Int) \
|| (n==QEI_INTFLAG_REV_Int) \
|| (n==QEI_INTFLAG_POS0REV_Int) \
|| (n==QEI_INTFLAG_POS1REV_Int) \
|| (n==QEI_INTFLAG_POS2REV_Int))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup QEI_Public_Types QEI Public Types
* @{
*/
/**
* @brief QEI Configuration structure type definition
*/
typedef struct
{
uint32_t DirectionInvert :1; /**< Direction invert option:
- QEI_DIRINV_NONE: QEI Direction is normal
- QEI_DIRINV_CMPL: QEI Direction is complemented
*/
uint32_t SignalMode :1; /**< Signal mode Option:
- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
*/
uint32_t CaptureMode :1; /**< Capture Mode Option:
- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
*/
uint32_t InvertIndex :1; /**< Invert Index Option:
- QEI_INVINX_NONE: the sense of the index input is normal
- QEI_INVINX_EN: inverts the sense of the index input
*/
} QEI_CFG_Type;
/**
* @brief Timer Reload Configuration structure type definition
*/
typedef struct
{
uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
*/
uint8_t Reserved[3];
uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
with Velocity Timer Reload Option
*/
} QEI_RELOADCFG_Type;
/**
* @brief Filter Settings for QEI registers on PHA, PHB and IDX
*/
typedef struct
{
uint32_t PHA_FilterVal;/**< Digital Filter Register on PHA input */
uint32_t PHB_FilterVal;/**< Digital Filter Register on PHB input */
uint32_t INX_FilterVal;/**< Digital Filter Register on IDX input */
} st_Qei_FilterCfg;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup QEI_Public_Functions QEI Public Functions
* @{
*/
void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
void QEI_DeInit(uint8_t qeiId);
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
uint32_t QEI_GetPosition(uint8_t qeiId);
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
uint32_t QEI_GetIndex(uint8_t qeiId);
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
uint32_t QEI_GetTimer(uint8_t qeiId);
uint32_t QEI_GetVelocity(uint8_t qeiId);
uint32_t QEI_GetVelocityCap(uint8_t qeiId);
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_QEI_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_rtc.h 2011-06-02
*//**
* @file lpc_rtc.h
* @brief Contains all macro definitions and function prototypes
* support for RTC firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup RTC RTC (Real Time Clock)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_RTC_H_
#define __LPC_RTC_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/* ----------------------- BIT DEFINITIONS ----------------------------------- */
/* Miscellaneous register group --------------------------------------------- */
/**********************************************************************
* ILR register definitions
**********************************************************************/
/** ILR register mask */
#define RTC_ILR_BITMASK ((0x00000003))
/** Bit inform the source interrupt is counter increment*/
#define RTC_IRL_RTCCIF ((1<<0))
/** Bit inform the source interrupt is alarm match*/
#define RTC_IRL_RTCALF ((1<<1))
/**********************************************************************
* CCR register definitions
**********************************************************************/
/** CCR register mask */
#define RTC_CCR_BITMASK ((0x00000013))
/** Clock enable */
#define RTC_CCR_CLKEN ((1<<0))
/** Clock reset */
#define RTC_CCR_CTCRST ((1<<1))
/** Calibration counter enable */
#define RTC_CCR_CCALEN ((1<<4))
/**********************************************************************
* CIIR register definitions
**********************************************************************/
/** Counter Increment Interrupt bit for second */
#define RTC_CIIR_IMSEC ((1<<0))
/** Counter Increment Interrupt bit for minute */
#define RTC_CIIR_IMMIN ((1<<1))
/** Counter Increment Interrupt bit for hour */
#define RTC_CIIR_IMHOUR ((1<<2))
/** Counter Increment Interrupt bit for day of month */
#define RTC_CIIR_IMDOM ((1<<3))
/** Counter Increment Interrupt bit for day of week */
#define RTC_CIIR_IMDOW ((1<<4))
/** Counter Increment Interrupt bit for day of year */
#define RTC_CIIR_IMDOY ((1<<5))
/** Counter Increment Interrupt bit for month */
#define RTC_CIIR_IMMON ((1<<6))
/** Counter Increment Interrupt bit for year */
#define RTC_CIIR_IMYEAR ((1<<7))
/** CIIR bit mask */
#define RTC_CIIR_BITMASK ((0xFF))
/**********************************************************************
* AMR register definitions
**********************************************************************/
/** Counter Increment Select Mask bit for second */
#define RTC_AMR_AMRSEC ((1<<0))
/** Counter Increment Select Mask bit for minute */
#define RTC_AMR_AMRMIN ((1<<1))
/** Counter Increment Select Mask bit for hour */
#define RTC_AMR_AMRHOUR ((1<<2))
/** Counter Increment Select Mask bit for day of month */
#define RTC_AMR_AMRDOM ((1<<3))
/** Counter Increment Select Mask bit for day of week */
#define RTC_AMR_AMRDOW ((1<<4))
/** Counter Increment Select Mask bit for day of year */
#define RTC_AMR_AMRDOY ((1<<5))
/** Counter Increment Select Mask bit for month */
#define RTC_AMR_AMRMON ((1<<6))
/** Counter Increment Select Mask bit for year */
#define RTC_AMR_AMRYEAR ((1<<7))
/** AMR bit mask */
#define RTC_AMR_BITMASK ((0xFF))
/**********************************************************************
* RTC_AUX register definitions
**********************************************************************/
/** RTC Oscillator Fail detect flag */
#define RTC_AUX_RTC_OSCF ((1<<4))
/**********************************************************************
* RTC_AUXEN register definitions
**********************************************************************/
/** Oscillator Fail Detect interrupt enable*/
#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
/* Consolidated time register group ----------------------------------- */
/**********************************************************************
* Consolidated Time Register 0 definitions
**********************************************************************/
#define RTC_CTIME0_SECONDS_MASK ((0x3F))
#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
#define RTC_CTIME0_DOW_MASK ((0x7000000))
/**********************************************************************
* Consolidated Time Register 1 definitions
**********************************************************************/
#define RTC_CTIME1_DOM_MASK ((0x1F))
#define RTC_CTIME1_MONTH_MASK ((0xF00))
#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
/**********************************************************************
* Consolidated Time Register 2 definitions
**********************************************************************/
#define RTC_CTIME2_DOY_MASK ((0xFFF))
/**********************************************************************
* Time Counter Group and Alarm register group
**********************************************************************/
/** SEC register mask */
#define RTC_SEC_MASK (0x0000003F)
/** MIN register mask */
#define RTC_MIN_MASK (0x0000003F)
/** HOUR register mask */
#define RTC_HOUR_MASK (0x0000001F)
/** DOM register mask */
#define RTC_DOM_MASK (0x0000001F)
/** DOW register mask */
#define RTC_DOW_MASK (0x00000007)
/** DOY register mask */
#define RTC_DOY_MASK (0x000001FF)
/** MONTH register mask */
#define RTC_MONTH_MASK (0x0000000F)
/** YEAR register mask */
#define RTC_YEAR_MASK (0x00000FFF)
/** Maximum value of second */
#define RTC_SECOND_MAX 59
/** Maximum value of minute*/
#define RTC_MINUTE_MAX 59
/** Maximum value of hour*/
#define RTC_HOUR_MAX 23
/** Minimum value of month*/
#define RTC_MONTH_MIN 1
/** Maximum value of month*/
#define RTC_MONTH_MAX 12
/** Minimum value of day of month*/
#define RTC_DAYOFMONTH_MIN 1
/** Maximum value of day of month*/
#define RTC_DAYOFMONTH_MAX 31
/** Maximum value of day of week*/
#define RTC_DAYOFWEEK_MAX 6
/** Minimum value of day of year*/
#define RTC_DAYOFYEAR_MIN 1
/** Maximum value of day of year*/
#define RTC_DAYOFYEAR_MAX 366
/** Maximum value of year*/
#define RTC_YEAR_MAX 4095
/**********************************************************************
* Calibration register
**********************************************************************/
/** Calibration value */
#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
/** Calibration direction */
#define RTC_CALIBRATION_LIBDIR ((1<<17))
/** Calibration max value */
#define RTC_CALIBRATION_MAX ((0x20000))
/** Calibration definitions */
#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
/**********************************************************************
* Event Monitor/Recorder Control register
**********************************************************************/
#define RTC_ERCTRL_EV0_INTWAKE_ENABLE (1<<0)
#define RTC_ERCTRL_EV0_GPCLEAR_ENABLE (1<<1)
#define RTC_ERCTRL_EV0_POS_EDGE (1<<2)
#define RTC_ERCTRL_EV0_NEG_EDGE (0<<2)
#define RTC_ERCTRL_EV0_INPUT_ENABLE (1<<3)
#define RTC_ERCTRL_EV1_INTWAKE_ENABLE (1<<10)
#define RTC_ERCTRL_EV1_GPCLEAR_ENABLE (1<<11)
#define RTC_ERCTRL_EV1_POS_EDGE (1<<12)
#define RTC_ERCTRL_EV1_NEG_EDGE (0<<12)
#define RTC_ERCTRL_EV1_INPUT_ENABLE (1<<13)
#define RTC_ERCTRL_EV2_INTWAKE_ENABLE (1<<20)
#define RTC_ERCTRL_EV2_GPCLEAR_ENABLE (1<<21)
#define RTC_ERCTRL_EV2_POS_EDGE (1<<22)
#define RTC_ERCTRL_EV2_NEG_EDGE (0<<22)
#define RTC_ERCTRL_EV2_INPUT_ENABLE (1<<23)
#define RTC_ERCTRL_MODE_MASK (((uint32_t)3)<<30)
#define RTC_ERCTRL_MODE_CLK_DISABLE (((uint32_t)0)<<30)
#define RTC_ERCTRL_MODE_16HZ (((uint32_t)1)<<30)
#define RTC_ERCTRL_MODE_64HZ (((uint32_t)2)<<30)
#define RTC_ERCTRL_MODE_1KHZ (((uint32_t)3)<<30)
#define RTC_ER_INPUT_CHANNEL_NUM (3)
/**********************************************************************
* Event Monitor/Recorder Status register
**********************************************************************/
#define RTC_ER_STATUS_EV0_BIT (0)
#define RTC_ER_STATUS_EV1_BIT (1)
#define RTC_ER_STATUS_EV2_BIT (2)
#define RTC_ER_STATUS_GPCLEARED_BIT (3)
#define RTC_ER_STATUS_WAKEUP_BIT (31)
#define RTC_ER_EVENTS_ON_EV0_FLG (1<<RTC_ER_STATUS_EV0_BIT)
#define RTC_ER_EVENTS_ON_EV1_FLG (1<<RTC_ER_STATUS_EV1_BIT)
#define RTC_ER_EVENTS_ON_EV2_FLG (1<<RTC_ER_STATUS_EV2_BIT)
#define RTC_ER_STATUS_GP_CLEARED_FLG (1<<RTC_ER_STATUS_GPCLEARED_BIT)
#define RTC_ER_STATUS_WAKEUP_REQ_PENDING (((uint32_t)1)<<RTC_ER_STATUS_WAKEUP_BIT)
/**********************************************************************
* Event Monitor/Recorder Counter register
**********************************************************************/
#define RTC_ER_EV0_COUNTER(n) (n&0x07)
#define RTC_ER_EV1_COUNTER(n) ((n>>8)&0x07)
#define RTC_ER_EV2_COUNTER(n) ((n>>16)&0x07)
/**********************************************************************
* Event Monitor/Recorder TimeStamp register
**********************************************************************/
#define RTC_ER_TIMESTAMP_SEC(n) (n&0x3F)
#define RTC_ER_TIMESTAMP_MIN(n) ((n>>6)&0x3F)
#define RTC_ER_TIMESTAMP_HOUR(n) ((n>>12)&0x1F)
#define RTC_ER_TIMESTAMP_DOY(n) ((n>>17)&0x1FF)
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup RTC_Public_Types RTC Public Types
* @{
*/
/** @brief Time structure definitions for easy manipulate the data */
typedef struct
{
/** Seconds Register */
uint32_t SEC;
/** Minutes Register */
uint32_t MIN;
/** Hours Register */
uint32_t HOUR;
/** Day of Month Register */
uint32_t DOM;
/** Day of Week Register */
uint32_t DOW;
/** Day of Year Register */
uint32_t DOY;
/** Months Register */
uint32_t MONTH;
/** Years Register */
uint32_t YEAR;
} RTC_TIME_Type;
/** @brief RTC interrupt source */
typedef enum
{
/** Counter Increment Interrupt */
RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,
/** The alarm interrupt */
RTC_INT_ALARM = RTC_IRL_RTCALF,
} RTC_INT_OPT;
/** @brief RTC time type option */
typedef enum
{
/** Second */
RTC_TIMETYPE_SECOND = 0,
/** Month */
RTC_TIMETYPE_MINUTE = 1,
/** Hour */
RTC_TIMETYPE_HOUR = 2,
/** Day of week */
RTC_TIMETYPE_DAYOFWEEK = 3,
/** Day of month */
RTC_TIMETYPE_DAYOFMONTH = 4,
/** Day of year */
RTC_TIMETYPE_DAYOFYEAR = 5,
/** Month */
RTC_TIMETYPE_MONTH = 6,
/** Year */
RTC_TIMETYPE_YEAR = 7,
} RTC_TIMETYPE_Num;
/** @brief Event Monitor/Recording Input Channel configuration */
typedef struct
{
Bool EventOnPosEdge; // Event occurs on positive edge on the channel
Bool IntWake; // Create interrupt and wake-up request if there is an event
Bool GPClear; // Clear GP registers of RTC if there is an event.
} RTC_ER_CHANNEL_Init_Type;
/** @brief Event Monitor/Recording configuration */
typedef struct
{
RTC_ER_CHANNEL_Init_Type InputChannel[RTC_ER_INPUT_CHANNEL_NUM];
uint32_t Clk; // Sample clock on input channel. (Hz)
} RTC_ER_CONFIG_Type;
/** @brief Event Monitor/Recording TimeStamp Type */
typedef struct
{
/** Seconds Register */
uint32_t SEC;
/** Minutes Register */
uint32_t MIN;
/** Hours Register */
uint32_t HOUR;
/** Day of Year Register */
uint32_t DOY;
} RTC_ER_TIMESTAMP_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup RTC_Public_Functions RTC Public Functions
* @{
*/
void RTC_Init (LPC_RTC_TypeDef *RTCx);
void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
FunctionalState NewState);
void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
FunctionalState NewState);
void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
void RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig);
Status RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig);
Status RTC_ER_Cmd(uint8_t channel, FunctionalState state);
uint8_t RTC_ER_GetEventCount(uint8_t channel);
uint32_t RTC_ER_GetStatus(void);
Bool RTC_ER_WakupReqPending(void);
Bool RTC_ER_GPCleared(void);
Status RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
Status RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
void RTC_ER_ClearStatus(uint32_t status);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_RTC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/***********************************************************************
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef SPIFI_ROM_API_H
#define SPIFI_ROM_API_H
#include <stdint.h>
/* define the symbol TESTING in the environment if test output desired */
/* maintain LONGEST_PROT >= the length (in bytes) of the largest
protection block of any serial flash that this driver handles */
#define LONGEST_PROT 68
typedef uint8_t uc;
#ifndef NULL
#define NULL ((void *)0)
#endif
/* protection/sector descriptors */
typedef struct {
uint32_t base;
uc flags;
int8_t log2;
uint16_t rept;
} protEnt;
/* bits in the flags byte */
enum {RWPROT=1};
/* overall data structure includes # sectors, length of protection reg,
array of descriptors
typedef struct {
uint16_t sectors;
uint16_t protBytes;
protEnt *entries;
} protDesc; */
typedef union {
uint16_t hw;
uc byte[2];
}stat_t;
/* the object that init returns, and other routines use as an operand */
typedef struct {
uint32_t base, regbase, devSize, memSize;
uc mfger, devType, devID, busy;
stat_t stat;
uint16_t reserved;
uint16_t set_prot, write_prot;
uint32_t mem_cmd, prog_cmd;
uint16_t sectors, protBytes;
uint32_t opts, errCheck;
uc erase_shifts[4], erase_ops[4];
protEnt *protEnts;
char prot[LONGEST_PROT];
} SPIFIobj;
/* operands of program and erase */
typedef struct {
char *dest;
uint32_t length;
char *scratch;
int32_t protect;
uint32_t options;
} SPIFIopers;
/* instruction classes for wait_busy */
typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
/* bits in options operands (MODE3, RCVCLK, and FULLCLK
have the same relationship as in the Control register) */
#define S_MODE3 1
#define S_MODE0 0
#define S_MINIMAL 2
#define S_MAXIMAL 0
#define S_FORCE_ERASE 4
#define S_ERASE_NOT_REQD 8
#define S_CALLER_ERASE 8
#define S_ERASE_AS_REQD 0
#define S_VERIFY_PROG 0x10
#define S_VERIFY_ERASE 0x20
#define S_NO_VERIFY 0
#define S_RCVCLK 0x80
#define S_INTCLK 0
#define S_FULLCLK 0x40
#define S_HALFCLK 0
#define S_DUAL 0x100
#define S_CALLER_PROT 0x200
#define S_DRIVER_PROT 0
/* the following values in the first post-address memory command byte work
for all known quad devices that support "no opcode" operation */
#define NO_OPCODE_FOLLOWS 0xA5
#define OPCODE_FOLLOWS 0xFF
/* basic SPI commands for serial flash */
#define BASE_READ_CMD (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
#define BASE_PROG_CMD (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
/* the length of a standard program command is 256 on all devices */
#define PROG_SIZE 256
/* options in obj->opts (mostly for setMulti) */
/* used by Winbond: send 0xA3 command so hardware can read faster */
#define OPT_SEND_A3 1
/* used by SST: send 0x38 command to enable quad and allow full command set */
#define OPT_SEND_38 2
/* used by Winbond and others: read status reg 2, check it,
if necessary write it back with Quad Enable set */
#define OPT_35_OR02_01 4
/* used by Atmel: read Configuration register, if necessary set Quad Enable */
#define OPT_3F_OR80_3E 8
/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
#define OPT_65_CLR_C0_61 0x10
/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
to set # dummy bytes and allow XIP mode */
#define OPT_81 0x20
/* set for devices without full device erase command (Numonyx type 0x40) */
#define OPT_NO_DEV_ERASE 0x40
/* used by Macronix: status reg 2 includes selection between write-protect
in status reg and command-based */
#define OPT_WPSEL 0x80
/* set when protection data has been read into the SPIFI object */
#define OPT_PROT_READ 0x100
/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
#define OPT_4BAD 0x200
/* set if setMulti should set the Dual bit in Control reg */
#define OPT_DUAL 0x400
/* send "# dummy bits" in C0 command to Winbond */
#define OPT_C0 0x800
/* set QE for Chingis */
#define OPT_05_OR40_01 0x1000
/* write status does not go busy */
#define OPT_01_NO_BUSY 0x2000
/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */
#define OPT_PROT_STAT 0x4000
#define OPT_PROT_REG 0x8000
#define OPT_PROT_CMD3 0x10000
#define OPT_PROT_CMDE 0x20000
#define OPT_PROT_MASK 0x3C000
#define OPT_ALL_QUAD 0x40000
#ifndef OMIT_ROM_TABLE
/* interface to ROM API */
typedef struct {
int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options,
uint32_t mhz);
int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers);
/* mode switching */
void (*cancel_mem_mode)(SPIFIobj *obj);
void (*set_mem_mode) (SPIFIobj *obj);
/* mid level functions */
int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers);
int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change,
char *saveProt);
int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t check_program);
int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr);
uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length);
int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
uint32_t *left_in_page);
uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length);
/* low level functions */
void(*setSize) (SPIFIobj *obj, int32_t value);
int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
uint32_t prog_cmd);
uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len);
uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value);
void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value);
int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase);
} SPIFI_RTNS;
#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
#endif /* OMIT_ROM_TABLE */
#ifdef USE_SPIFI_LIB
extern SPIFI_RTNS spifi_table;
#endif /* USE_SPIFI_LIB */
/* example of using this interface:
#include "spifi_rom_api.h"
#define CSHIGH 4
#define SPIFI_MHZ 80
#define source_data_ad (char *)1234
int32_t rc;
SPIFIopers opers;
define_spifi_romPtr(spifi);
SPIFIobj *obj = malloc(sizeof(SPIFIobj));
if (!obj) { can't allocate memory }
rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
if (rc) { investigate init error rc }
printf ("the serial flash contains %d bytes\n", obj->devSize);
opers.dest = where_to_program;
opers.length = how_many_bytes;
opers.scratch = NULL; // unprogrammed data is not saved/restored
opers.protect = -1; // save & restore protection
opers.options = S_VERIFY_PROG;
rc = spifi->spifi_program (obj, source_data_ad, &opers);
if (rc) { investigate program error rc }
*/
/* these are for normal users, including boot code */
int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
/* these are used by the manufacturer-specific init functions */
void setSize (SPIFIobj *obj, int32_t value);
int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
uint32_t read04(SPIFIobj *obj, uc op, uc len);
int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
/* needs to be defined for each platform */
void pullMISO(int high);
#ifdef TESTING
/* used by testing code */
unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
/* predeclare a debug routine */
void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
#endif
#endif /* SPIFI_ROM_API_H */

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/**********************************************************************
* $Id$ lpc_ssp.h 2011-06-02
*//**
* @file lpc_ssp.h
* @brief Contains all macro definitions and function prototypes
* support for SSP firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SSP SSP (Synchronous Serial Port)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_SSP_H_
#define __LPC_SSP_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup SSP_Public_Macros SSP Public Macros
* @{
*/
/*********************************************************************//**
* SSP configuration parameter defines
**********************************************************************/
/** Clock phase control bit */
#define SSP_CPHA_FIRST ((uint32_t)(0))
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI ((uint32_t)(0))
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE ((uint32_t)(0))
/** SSP data bit number defines */
#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
/** SSP Frame Format definition */
/** Motorola SPI mode */
#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
/** TI synchronous serial mode */
#define SSP_FRAME_TI SSP_CR0_FRF_TI
/** National Micro-wire mode */
#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
/*********************************************************************//**
* SSP Status defines
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
/** SSP status TX FIFO not full bit */
#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
/** SSP status RX FIFO not empty bit */
#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
/** SSP status RX FIFO full bit */
#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
/** SSP status SSP Busy bit */
#define SSP_STAT_BUSY SSP_SR_BSY
/*********************************************************************//**
* SSP Interrupt Configuration defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTCFG_ROR SSP_IMSC_ROR
/** Receive TimeOut */
#define SSP_INTCFG_RT SSP_IMSC_RT
/** Rx FIFO is at least half full */
#define SSP_INTCFG_RX SSP_IMSC_RX
/** Tx FIFO is at least half empty */
#define SSP_INTCFG_TX SSP_IMSC_TX
/*********************************************************************//**
* SSP Configured Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_ROR SSP_MIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RT SSP_MIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RX SSP_MIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_TX SSP_MIS_TX
/*********************************************************************//**
* SSP Raw Interrupt Status defines
**********************************************************************/
/** Receive Overrun */
#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
/** Receive TimeOut */
#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
/** Rx FIFO is at least half full */
#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
/** Tx FIFO is at least half empty */
#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
/*********************************************************************//**
* SSP Interrupt Clear defines
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_INTCLR_ROR SSP_ICR_ROR
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_INTCLR_RT SSP_ICR_RT
/*********************************************************************//**
* SSP DMA defines
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_RX SSP_DMA_RXDMA_EN
/** SSP bit for enabling TX DMA */
#define SSP_DMA_TX SSP_DMA_TXDMA_EN
/* SSP Status Implementation definitions */
#define SSP_STAT_DONE (1UL<<8) /**< Done */
#define SSP_STAT_ERROR (1UL<<9) /**< Error */
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup SSP_Private_Macros SSP Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for CR0 register
**********************************************************************/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
/*********************************************************************//**
* Macro defines for CR1 register
**********************************************************************/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro defines for DR register
**********************************************************************/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
/*********************************************************************//**
* Macro defines for SR register
**********************************************************************/
/** SSP status TX FIFO Empty bit */
#define SSP_SR_TFE ((uint32_t)(1<<0))
/** SSP status TX FIFO not full bit */
#define SSP_SR_TNF ((uint32_t)(1<<1))
/** SSP status RX FIFO not empty bit */
#define SSP_SR_RNE ((uint32_t)(1<<2))
/** SSP status RX FIFO full bit */
#define SSP_SR_RFF ((uint32_t)(1<<3))
/** SSP status SSP Busy bit */
#define SSP_SR_BSY ((uint32_t)(1<<4))
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t)(0x1F))
/*********************************************************************//**
* Macro defines for CPSR register
**********************************************************************/
/** SSP clock prescaler */
#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************//**
* Macro define for (IMSC) Interrupt Mask Set/Clear registers
**********************************************************************/
/** Receive Overrun */
#define SSP_IMSC_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_IMSC_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_IMSC_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_IMSC_TX ((uint32_t)(1<<3))
/** IMSC bit mask */
#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (RIS) Raw Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_RIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_RIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_RIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_RIS_TX ((uint32_t)(1<<3))
/** RIS bit mask */
#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (MIS) Masked Interrupt Status registers
**********************************************************************/
/** Receive Overrun */
#define SSP_MIS_ROR ((uint32_t)(1<<0))
/** Receive TimeOut */
#define SSP_MIS_RT ((uint32_t)(1<<1))
/** Rx FIFO is at least half full */
#define SSP_MIS_RX ((uint32_t)(1<<2))
/** Tx FIFO is at least half empty */
#define SSP_MIS_TX ((uint32_t)(1<<3))
/** MIS bit mask */
#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
/*********************************************************************//**
* Macro define for (ICR) Interrupt Clear registers
**********************************************************************/
/** Writing a 1 to this bit clears the "frame was received when
* RxFIFO was full" interrupt */
#define SSP_ICR_ROR ((uint32_t)(1<<0))
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt */
#define SSP_ICR_RT ((uint32_t)(1<<1))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t)(0x03))
/*********************************************************************//**
* Macro defines for DMACR register
**********************************************************************/
/** SSP bit for enabling RX DMA */
#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
/** SSP bit for enabling TX DMA */
#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
/** DMACR bit mask */
#define SSP_DMA_BITMASK ((uint32_t)(0x03))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup SSP_Public_Types SSP Public Types
* @{
*/
/** @brief SSP configuration structure */
typedef struct {
uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
where x is in range from 4 - 16 */
uint32_t CPHA; /** Clock phase, should be:
- SSP_CPHA_FIRST: first clock edge
- SSP_CPHA_SECOND: second clock edge */
uint32_t CPOL; /** Clock polarity, should be:
- SSP_CPOL_HI: high level
- SSP_CPOL_LO: low level */
uint32_t Mode; /** SSP mode, should be:
- SSP_MASTER_MODE: Master mode
- SSP_SLAVE_MODE: Slave mode */
uint32_t FrameFormat; /** Frame Format:
- SSP_FRAME_SPI: Motorola SPI frame format
- SSP_FRAME_TI: TI frame format
- SSP_FRAME_MICROWIRE: National Microwire frame format */
uint32_t ClockRate; /** Clock rate,in Hz */
} SSP_CFG_Type;
/**
* @brief SSP Transfer Type definitions
*/
typedef enum {
SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
} SSP_TRANSFER_Type;
/**
* @brief SPI Data configuration structure definitions
*/
typedef struct {
void *tx_data; /**< Pointer to transmit data */
uint32_t tx_cnt; /**< Transmit counter */
void *rx_data; /**< Pointer to transmit data */
uint32_t rx_cnt; /**< Receive counter */
uint32_t length; /**< Length of transfer data */
uint32_t status; /**< Current status of SSP activity */
} SSP_DATA_SETUP_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SSP_Public_Functions SSP Public Functions
* @{
*/
/* SSP Init/DeInit functions --------------------------------------------------*/
void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
/* SSP configure functions ----------------------------------------------------*/
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
/* SSP enable/disable functions -----------------------------------------------*/
void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
/* SSP get information functions ----------------------------------------------*/
FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
/* SSP transfer data functions ------------------------------------------------*/
void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
SSP_TRANSFER_Type xfType);
/* SSP IRQ function ------------------------------------------------------------*/
void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_SSP_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_systick.h 2011-06-02
*//**
* @file lpc_systick.h
* @brief Contains all macro definitions and function prototypes
* support for SYSTICK firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SYSTICK SysTick (System tick timer)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_SYSTICK_H_
#define __LPC_SYSTICK_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup SYSTICK_Private_Macros SysTick Private Macros
* @{
*/
/*********************************************************************//**
* Macro defines for System Timer Control and status (STCTRL) register
**********************************************************************/
#define ST_CTRL_ENABLE ((uint32_t)(1<<0))
#define ST_CTRL_TICKINT ((uint32_t)(1<<1))
#define ST_CTRL_CLKSOURCE ((uint32_t)(1<<2))
#define ST_CTRL_COUNTFLAG ((uint32_t)(1<<16))
/*********************************************************************//**
* Macro defines for System Timer Reload value (STRELOAD) register
**********************************************************************/
#define ST_RELOAD_RELOAD(n) ((uint32_t)(n & 0x00FFFFFF))
/*********************************************************************//**
* Macro defines for System Timer Current value (STCURRENT) register
**********************************************************************/
#define ST_RELOAD_CURRENT(n) ((uint32_t)(n & 0x00FFFFFF))
/*********************************************************************//**
* Macro defines for System Timer Calibration value (STCALIB) register
**********************************************************************/
#define ST_CALIB_TENMS(n) ((uint32_t)(n & 0x00FFFFFF))
#define ST_CALIB_SKEW ((uint32_t)(1<<30))
#define ST_CALIB_NOREF ((uint32_t)(1<<31))
#define CLKSOURCE_EXT ((uint32_t)(0))
#define CLKSOURCE_CPU ((uint32_t)(1))
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SYSTICK_Public_Functions Systick Public Functions
* @{
*/
void SYSTICK_InternalInit(uint32_t time);
void SYSTICK_ExternalInit(uint32_t freq, uint32_t time);
void SYSTICK_Cmd(FunctionalState NewState);
void SYSTICK_IntCmd(FunctionalState NewState);
uint32_t SYSTICK_GetCurrentValue(void);
void SYSTICK_ClearCounterFlag(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_SYSTICK_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_timer.h 2011-06-02
*//**
* @file lpc_timer.h
* @brief Contains all macro definitions and function prototypes
* support for Timer firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup TIMER TIM (Timer)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_TIMER_H_
#define __LPC_TIMER_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Private Macros ------------------------------------------------------------- */
/** @defgroup TIM_Private_Macros Timer Private Macros
* @{
*/
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/**********************************************************************
** Interrupt information
**********************************************************************/
/** Macro to clean interrupt pending */
#define TIM_IR_CLR(n) _BIT(n)
/**********************************************************************
** Timer interrupt register definitions
**********************************************************************/
/** Macro for getting a timer match interrupt bit */
#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
/**********************************************************************
* Timer control register definitions
**********************************************************************/
/** Timer/counter enable bit */
#define TIM_ENABLE ((uint32_t)(1<<0))
/** Timer/counter reset bit */
#define TIM_RESET ((uint32_t)(1<<1))
/** Timer control bit mask */
#define TIM_TCR_MASKBIT ((uint32_t)(3))
/**********************************************************************
* Timer match control register definitions
**********************************************************************/
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
/** Timer Match control bit mask */
#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
/** Timer Match control bit mask for specific channel*/
#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer capture control register definitions
**********************************************************************/
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIM_CAP_RISING(n) (_BIT((n * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
/** Mask bit for rising and falling edge bit */
#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
/** Timer capture control bit mask */
#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
/** Timer Capture control bit mask for specific channel*/
#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
/**********************************************************************
* Timer external match register definitions
**********************************************************************/
/** Bit location for output state change of MAT.n when external match
happens, n = 0 to 3 */
#define TIM_EM(n) _BIT(n)
/** Output state change of MAT.n when external match happens: no change */
#define TIM_EM_NOTHING ((uint8_t)(0x0))
/** Output state change of MAT.n when external match happens: low */
#define TIM_EM_LOW ((uint8_t)(0x1))
/** Output state change of MAT.n when external match happens: high */
#define TIM_EM_HIGH ((uint8_t)(0x2))
/** Output state change of MAT.n when external match happens: toggle */
#define TIM_EM_TOGGLE ((uint8_t)(0x3))
/** Macro for setting for the MAT.n change state bits */
#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
/** Mask for the MAT.n change state bits */
#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
/** Timer external match bit mask */
#define TIM_EMR_MASKBIT 0x0FFF
/**********************************************************************
* Timer Count Control Register definitions
**********************************************************************/
/** Mask to get the Counter/timer mode bits */
#define TIM_CTCR_MODE_MASK 0x3
/** Mask to get the count input select bits */
#define TIM_CTCR_INPUT_MASK 0xC
/** Timer Count control bit mask */
#define TIM_CTCR_MASKBIT 0xF
#define TIM_COUNTER_MODE ((uint8_t)(1))
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup TIM_Public_Types Timer Public Types
* @{
*/
/***********************************************************************
* Timer device enumeration
**********************************************************************/
/** @brief interrupt type */
typedef enum
{
TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
}TIM_INT_TYPE;
/** @brief Timer/counter operating mode */
typedef enum
{
TIM_TIMER_MODE = 0, /*!< Timer mode */
TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */
TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */
TIM_COUNTER_ANY_MODE /*!< Counter on both edges */
} TIM_MODE_OPT;
/** @brief Timer/Counter prescale option */
typedef enum
{
TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */
} TIM_PRESCALE_OPT;
/** @brief Counter input option */
typedef enum
{
TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */
TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */
} TIM_COUNTER_INPUT_OPT;
/** @brief Timer/Counter external match option */
typedef enum
{
TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */
TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */
TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */
TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */
}TIM_EXTMATCH_OPT;
/** @brief Timer/counter capture mode options */
typedef enum {
TIM_CAPTURE_NONE = 0, /*!< No Capture */
TIM_CAPTURE_RISING, /*!< Rising capture mode */
TIM_CAPTURE_FALLING, /*!< Falling capture mode */
TIM_CAPTURE_ANY /*!< On both edges */
} TIM_CAP_MODE_OPT;
/** @brief Configuration structure in TIMER mode */
typedef struct
{
uint8_t PrescaleOption; /**< Timer Prescale option, should be:
- TIM_PRESCALE_TICKVAL: Prescale in absolute value
- TIM_PRESCALE_USVAL: Prescale in microsecond value
*/
uint8_t Reserved[3]; /**< Reserved */
uint32_t PrescaleValue; /**< Prescale value */
} TIM_TIMERCFG_Type;
/** @brief Configuration structure in COUNTER mode */
typedef struct {
uint8_t CounterOption; /**< Counter Option, should be:
- TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
- TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
*/
uint8_t CountInputSelect;
uint8_t Reserved[2];
} TIM_COUNTERCFG_Type;
/** @brief Match channel configuration structure */
typedef struct {
uint8_t MatchChannel; /**< Match channel, should be in range
from 0..3 */
uint8_t IntOnMatch; /**< Interrupt On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t StopOnMatch; /**< Stop On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ResetOnMatch; /**< Reset On match, should be:
- ENABLE: Enable this function.
- DISABLE: Disable this function.
*/
uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
- TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match
- TIM_EXTMATCH_LOW: Force external output pin to low if match
- TIM_EXTMATCH_HIGH: Force external output pin to high if match
- TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
*/
uint8_t Reserved[3]; /** Reserved */
uint32_t MatchValue; /** Match value */
} TIM_MATCHCFG_Type;
/** @brief Capture Input configuration structure */
typedef struct {
uint8_t CaptureChannel; /**< Capture channel, should be in range
from 0..1 */
uint8_t RisingEdge; /**< caption rising edge, should be:
- ENABLE: Enable rising edge.
- DISABLE: Disable this function.
*/
uint8_t FallingEdge; /**< caption falling edge, should be:
- ENABLE: Enable falling edge.
- DISABLE: Disable this function.
*/
uint8_t IntOnCaption; /**< Interrupt On caption, should be:
- ENABLE: Enable interrupt function.
- DISABLE: Disable this function.
*/
} TIM_CAPTURECFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup TIM_Public_Functions Timer Public Functions
* @{
*/
/* Init/DeInit TIM functions -----------*/
void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_DeInit(LPC_TIM_TypeDef *TIMx);
/* TIM interrupt functions -------------*/
void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
/* TIM configuration functions --------*/
void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState);
uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx);
void TIM_Waitus(uint32_t time);
void TIM_Waitms(uint32_t time);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_TIMER_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Type group ----------------------------------------------------------- */
#ifndef __LPC_TYPES_H
#define __LPC_TYPES_H
/* Includes ------------------------------------------------------------------- */
#include <stdint.h>
/** @defgroup LPC_Type_Def Data Types Definitions
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types Basic Public Data Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t(*PFI)();
/**
* @}
*/
/* Public Macros -------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Macros Basic Public Macros
* @{
*/
/** _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/** Set bit macro */
#define _BIT(n) (1<<n)
/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f,v) (v<<f)
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void*) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility ------------------------------------------ */
/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
* @{
*/
/** SMA type for character type */
typedef char CHAR;
/** SMA type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** SMA type for 8 bit signed value */
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;
/** SMA type for 64 bit unsigned value */
typedef uint64_t UNS_64;
/** 32 bit boolean type */
typedef Bool BOOL_32;
/** 16 bit boolean type */
typedef Bool BOOL_16;
/** 8 bit boolean type */
typedef Bool BOOL_8;
/**
* @}
*/
#endif /* __LPC_TYPES_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_uart.h 2011-06-02
*//**
* @file lpc_uart.h
* @brief Contains all macro definitions and function prototypes
* support for UART firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_UART_H_
#define __LPC_UART_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/* Public Macros -------------------------------------------------------------- */
/** @defgroup UART_Public_Macros UART Public Macros
* @{
*/
/** UART time-out definitions in case of using Read() and Write function
* with Blocking Flag mode
*/
#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
*/
/* Private Macros ------------------------------------------------------------- */
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
/* Accepted Error baud rate value (in percent unit) */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
/** UART Received Buffer mask bit (8 bits) */
#define UART_RBR_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
/** UART Transmit Holding mask bit (8 bits) */
#define UART_THR_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
/** Macro for loading least significant halfs of divisors */
#define UART_LOAD_DLL(div) ((div) & 0xFF)
/** Divisor latch LSB bit mask */
#define UART_DLL_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
/** Divisor latch MSB bit mask */
#define UART_DLM_MASKBIT ((uint8_t)0xFF)
/** Macro for loading most significant halfs of divisors */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
/** RBR Interrupt enable*/
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0))
/** THR Interrupt enable*/
#define UART_IER_THREINT_EN ((uint32_t)(1<<1))
/** RX line status interrupt enable*/
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2))
/** Modem status interrupt enable */
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3))
/** CTS1 signal transition interrupt enable */
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7))
/** Enables the end of auto-baud interrupt */
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8))
/** Enables the auto-baud time-out interrupt */
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9))
/** UART interrupt enable register bit mask */
#define UART_IER_BITMASK ((uint32_t)(0x307))
/** UART1 interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F))
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
/** Interrupt Status - Active low */
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0))
/** Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1))
/** Interrupt identification: Receive data available*/
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1))
/** Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1))
/** Interrupt identification: THRE interrupt*/
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1))
/** Interrupt identification: Modem interrupt*/
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1))
/** Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1))
/** These bits are equivalent to UnFCR[0] */
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6))
/** End of auto-baud interrupt */
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8))
/** Auto-baud time-out interrupt */
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9))
/** UART interrupt identification register bit mask */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
/** UART FIFO enable */
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0))
/** UART FIFO RX reset */
#define UART_FCR_RX_RS ((uint8_t)(1<<1))
/** UART FIFO TX reset */
#define UART_FCR_TX_RS ((uint8_t)(1<<2))
/** UART DMA mode selection */
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3))
/** UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV0 ((uint8_t)(0))
/** UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6))
/** UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6))
/** UART FIFO trigger level 3: 14 character */
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6))
/** UART FIFO control bit mask */
#define UART_FCR_BITMASK ((uint8_t)(0xCF))
#define UART_TX_FIFO_SIZE (16)
/*********************************************************************//**
* Macro defines for Macro defines for UART line control register
**********************************************************************/
/** UART 5 bit data mode */
#define UART_LCR_WLEN5 ((uint8_t)(0))
/** UART 6 bit data mode */
#define UART_LCR_WLEN6 ((uint8_t)(1<<0))
/** UART 7 bit data mode */
#define UART_LCR_WLEN7 ((uint8_t)(2<<0))
/** UART 8 bit data mode */
#define UART_LCR_WLEN8 ((uint8_t)(3<<0))
/** UART Two Stop Bits Select */
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2))
/** UART Parity Enable */
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3))
/** UART Odd Parity Select */
#define UART_LCR_PARITY_ODD ((uint8_t)(0))
/** UART Even Parity Select */
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4))
/** UART force 1 stick parity */
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4))
/** UART force 0 stick parity */
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4))
/** UART Transmission Break enable */
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6))
/** UART Divisor Latches Access bit enable */
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7))
/** UART line control bit mask */
#define UART_LCR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART1 Modem Control Register
**********************************************************************/
/** Source for modem output pin DTR */
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0))
/** Source for modem output pin RTS */
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1))
/** Loop back mode select */
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4))
/** Enable Auto RTS flow-control */
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6))
/** Enable Auto CTS flow-control */
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7))
/** UART1 bit mask value */
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3))
/*********************************************************************//**
* Macro defines for Macro defines for UART line status register
**********************************************************************/
/** Line status register: Receive data ready*/
#define UART_LSR_RDR ((uint8_t)(1<<0))
/** Line status register: Overrun error*/
#define UART_LSR_OE ((uint8_t)(1<<1))
/** Line status register: Parity error*/
#define UART_LSR_PE ((uint8_t)(1<<2))
/** Line status register: Framing error*/
#define UART_LSR_FE ((uint8_t)(1<<3))
/** Line status register: Break interrupt*/
#define UART_LSR_BI ((uint8_t)(1<<4))
/** Line status register: Transmit holding register empty*/
#define UART_LSR_THRE ((uint8_t)(1<<5))
/** Line status register: Transmitter empty*/
#define UART_LSR_TEMT ((uint8_t)(1<<6))
/** Error in RX FIFO*/
#define UART_LSR_RXFE ((uint8_t)(1<<7))
/** UART Line status bit mask */
#define UART_LSR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Modem (UART1 only) status register
**********************************************************************/
/** Set upon state change of input CTS */
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0))
/** Set upon state change of input DSR */
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1))
/** Set upon low to high transition of input RI */
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2))
/** Set upon state change of input DCD */
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3))
/** Clear To Send State */
#define UART1_MSR_CTS ((uint8_t)(1<<4))
/** Data Set Ready State */
#define UART1_MSR_DSR ((uint8_t)(1<<5))
/** Ring Indicator State */
#define UART1_MSR_RI ((uint8_t)(1<<6))
/** Data Carrier Detect State */
#define UART1_MSR_DCD ((uint8_t)(1<<7))
/** MSR register bit-mask value */
#define UART1_MSR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
/** UART Scratch Pad bit mask */
#define UART_SCR_BIMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
/** UART Auto-baud start */
#define UART_ACR_START ((uint32_t)(1<<0))
/** UART Auto baudrate Mode 1 */
#define UART_ACR_MODE ((uint32_t)(1<<1))
/** UART Auto baudrate restart */
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2))
/** UART End of auto-baud interrupt clear */
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8))
/** UART Auto-baud time-out interrupt clear */
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9))
/** UART Auto Baudrate register bit mask */
#define UART_ACR_BITMASK ((uint32_t)(0x307))
/*********************************************************************//**
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
/** IrDA mode enable */
#define UART_ICR_IRDAEN ((uint32_t)(1<<0))
/** IrDA serial input inverted */
#define UART_ICR_IRDAINV ((uint32_t)(1<<1))
/** IrDA fixed pulse width mode */
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2))
/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
/** UART IRDA bit mask */
#define UART_ICR_BITMASK ((uint32_t)(0x3F))
/*********************************************************************//**
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
/** Baud-rate generation pre-scaler divisor */
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
/** Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
/** UART Fractional Divider register bit mask */
#define UART_FDR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
/** Transmit enable bit */
#define UART_TER_TXEN ((uint8_t)(1<<7))
/** UART Transmit Enable Register bit mask */
#define UART_TER_BITMASK ((uint8_t)(0x80))
/** Transmit enable bit on UART4 */
#define UART4_TER_TXEN ((uint8_t)(1<<0))
/** UART4 Transmit Enable Register bit mask */
#define UART4_TER_BITMASK ((uint8_t)(0x01))
/*********************************************************************//**
* Macro defines for Macro defines for UART RS485 Control register
**********************************************************************/
/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
#define UART_RS485CTRL_NMM_EN ((uint32_t)(1<<0))
/** The receiver is disabled */
#define UART_RS485CTRL_RX_DIS ((uint32_t)(1<<1))
/** Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_AADEN ((uint32_t)(1<<2))
/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
#define UART_RS485CTRL_SEL_DTR ((uint32_t)(1<<3))
/** Enable Auto Direction Control */
#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))
/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_OINV_1 ((uint32_t)(1<<5))
/** RS485 control bit-mask value */
#define UART_RS485CTRL_BITMASK ((uint32_t)(0x3F))
/*********************************************************************//**
* Macro defines for Macro defines for UART RS-485 Address Match register
**********************************************************************/
#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Delay value register
**********************************************************************/
/* Macro defines for UART1 RS-485 Delay value register */
#define UART_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
/**
* @}
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup UART_Public_Types UART Public Types
* @{
*/
/**
* @brief UART ID
*/
typedef enum
{
UART_0 = 0,
UART_1,
UART_2,
UART_3,
UART_4,
} UART_ID_Type;
/**
* @brief UART Databit type definitions
*/
typedef enum {
UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
UART_DATABIT_6, /*!< UART 6 bit data mode */
UART_DATABIT_7, /*!< UART 7 bit data mode */
UART_DATABIT_8 /*!< UART 8 bit data mode */
} UART_DATABIT_Type;
/**
* @brief UART Stop bit type definitions
*/
typedef enum {
UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
} UART_STOPBIT_Type;
/**
* @brief UART Parity type definitions
*/
typedef enum {
UART_PARITY_NONE = 0, /*!< No parity */
UART_PARITY_ODD, /*!< Odd parity */
UART_PARITY_EVEN, /*!< Even parity */
UART_PARITY_SP_1, /*!< Forced "1" stick parity */
UART_PARITY_SP_0 /*!< Forced "0" stick parity */
} UART_PARITY_Type;
/**
* @brief FIFO Level type definitions
*/
typedef enum {
UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
} UART_FITO_LEVEL_Type;
/********************************************************************//**
* @brief UART Interrupt Type definitions
**********************************************************************/
typedef enum {
UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
UART_INTCFG_THRE, /*!< THR Interrupt enable*/
UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
UART_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
} UART_INT_Type;
/**
* @brief UART Line Status Type definition
*/
typedef enum {
UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
} UART_LS_Type;
/**
* @brief UART Auto-baudrate mode type definition
*/
typedef enum {
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
} UART_AB_MODE_Type;
/**
* @brief Auto Baudrate mode configuration type definition
*/
typedef struct {
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
FunctionalState AutoRestart; /**< Auto Restart state */
} UART_AB_CFG_Type;
/**
* @brief UART End of Auto-baudrate type definition
*/
typedef enum {
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
}UART_ABEO_Type;
/**
* UART IrDA Control type Definition
*/
typedef enum
{
/** Pulse width = 2 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV2 = 0,
/** Pulse width = 4 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV4,
/** Pulse width = 8 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV8,
/** Pulse width = 16 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV16,
/** Pulse width = 32 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV32,
/**< Pulse width = 64 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV64,
/**< Pulse width = 128 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV128,
/**< Pulse width = 256 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV256
} UART_IrDA_PULSE_Type;
/********************************************************************//**
* @brief UART1 Full modem - Signal states definition
**********************************************************************/
typedef enum {
INACTIVE = 0, /* In-active state */
ACTIVE = !INACTIVE /* Active state */
}UART1_SignalState;
/**
* @brief UART modem status type definition
*/
typedef enum {
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
} UART_MODEM_STAT_type;
/**
* @brief Modem output pin type definition
*/
typedef enum {
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
} UART_MODEM_PIN_Type;
/**
* @brief UART Modem mode type definition
*/
typedef enum {
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
} UART_MODEM_MODE_Type;
/**
* @brief UART Direction Control Pin type definition
*/
typedef enum {
UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
UART_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
} UART_RS485_DIRCTRL_PIN_Type;
/********************************************************************//**
* @brief UART Configuration Structure definition
**********************************************************************/
typedef struct {
uint32_t Baud_rate; /**< UART baud rate */
UART_PARITY_Type Parity; /**< Parity selection, should be:
- UART_PARITY_NONE: No parity
- UART_PARITY_ODD: Odd parity
- UART_PARITY_EVEN: Even parity
- UART_PARITY_SP_1: Forced "1" stick parity
- UART_PARITY_SP_0: Forced "0" stick parity
*/
UART_DATABIT_Type Databits; /**< Number of data bits, should be:
- UART_DATABIT_5: UART 5 bit data mode
- UART_DATABIT_6: UART 6 bit data mode
- UART_DATABIT_7: UART 7 bit data mode
- UART_DATABIT_8: UART 8 bit data mode
*/
UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
- UART_STOPBIT_1: UART 1 Stop Bits Select
- UART_STOPBIT_2: UART 2 Stop Bits Select
*/
} UART_CFG_Type;
/********************************************************************//**
* @brief UART FIFO Configuration Structure definition
**********************************************************************/
typedef struct {
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
- ENABLE: Reset Rx FIFO in UART
- DISABLE: Do not reset Rx FIFO in UART
*/
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
- ENABLE: Reset Tx FIFO in UART
- DISABLE: Do not reset Tx FIFO in UART
*/
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
- ENABLE: Enable DMA mode in UART
- DISABLE: Disable DMA mode in UART
*/
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
*/
} UART_FIFO_CFG_Type;
/********************************************************************//**
* @brief UART1 Full modem - RS485 Control configuration type
**********************************************************************/
typedef struct {
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
FunctionalState Rx_State; /*!< Receiver State:
- ENABLE: Enable Receiver.
- DISABLE: Disable Receiver. */
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
- ENABLE: ENABLE this function.
- DISABLE: Disable this function. */
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
- UART1_RS485_DIRCTRL_RTS:
pin RTS is used for direction control.
- UART1_RS485_DIRCTRL_DTR:
pin DTR is used for direction control. */
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
the RTS (or DTR) pin:
- RESET: The direction control pin will be driven
to logic "0" when the transmitter has data to be sent.
- SET: The direction control pin will be driven
to logic "1" when the transmitter has data to be sent. */
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
} UART1_RS485_CTRLCFG_Type;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup UART_Public_Functions UART Public Functions
* @{
*/
/* UART Init/DeInit functions --------------------------------------------------*/
void UART_Init(UART_ID_Type UartID, UART_CFG_Type *UART_ConfigStruct);
void UART_DeInit(UART_ID_Type UartID);
void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
/* UART Send/Receive functions -------------------------------------------------*/
void UART_SendByte(UART_ID_Type UartID, uint8_t Data);
uint8_t UART_ReceiveByte(UART_ID_Type UartID);
uint32_t UART_Send(UART_ID_Type UartID, uint8_t *txbuf,
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t UART_Receive(UART_ID_Type UartID, uint8_t *rxbuf, \
uint32_t buflen, TRANSFER_BLOCK_Type flag);
/* UART FIFO functions ----------------------------------------------------------*/
void UART_FIFOConfig(UART_ID_Type UartID, UART_FIFO_CFG_Type *FIFOCfg);
void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
/* UART get information functions -----------------------------------------------*/
uint32_t UART_GetIntId(UART_ID_Type UartID);
uint8_t UART_GetLineStatus(UART_ID_Type UartID);
/* UART operate functions -------------------------------------------------------*/
void UART_IntConfig(UART_ID_Type UartID, UART_INT_Type UARTIntCfg, \
FunctionalState NewState);
void UART_TxCmd(UART_ID_Type UartID, FunctionalState NewState);
FlagStatus UART_CheckBusy(UART_ID_Type UartID);
void UART_ForceBreak(UART_ID_Type UartID);
/* UART Auto-baud functions -----------------------------------------------------*/
void UART_ABClearIntPending(UART_ID_Type UartID, UART_ABEO_Type ABIntType);
void UART_ABCmd(UART_ID_Type UartID, UART_AB_CFG_Type *ABConfigStruct, \
FunctionalState NewState);
/* UART1 FullModem functions ----------------------------------------------------*/
void UART_FullModemForcePinState(UART_ID_Type UartID, UART_MODEM_PIN_Type Pin, \
UART1_SignalState NewState);
void UART_FullModemConfigMode(UART_ID_Type UartID, UART_MODEM_MODE_Type Mode, \
FunctionalState NewState);
uint8_t UART_FullModemGetStatus(UART_ID_Type UartID);
/* UART RS485 functions ----------------------------------------------------------*/
void UART_RS485Config(UART_ID_Type UartID,
UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
void UART_RS485ReceiverCmd(UART_ID_Type UartID, FunctionalState NewState);
void UART_RS485SendSlvAddr(UART_ID_Type UartID, uint8_t SlvAddr);
uint32_t UART_RS485SendData(UART_ID_Type UartID, uint8_t *pData, uint32_t size);
/* UART IrDA functions-------------------------------------------------------------*/
void UART_IrDAInvtInputCmd(UART_ID_Type UartID, FunctionalState NewState);
void UART_IrDACmd(UART_ID_Type UartID, FunctionalState NewState);
void UART_IrDAPulseDivConfig(UART_ID_Type UartID, UART_IrDA_PULSE_Type PulseDiv);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_UART_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_wwdt.h 2011-06-02
*//**
* @file lpc_wwdt.h
* @brief Contains all macro definitions and function prototypes
* support forWindow Watchdog Timer firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup WWDT WWDT (Windowed Watchdog Timer)
* @ingroup LPC_CMSIS_FwLib_Drivers
* @{
*/
#ifndef __LPC_WWDT_H_
#define __LPC_WWDT_H_
/* Includes ------------------------------------------------------------------- */
#include "LPC407x_8x_177x_8x.h"
#include "lpc_types.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @defgroup WDT_Private_Macros WDT Private Macros
* @{
*/
// time is calculated by usec
#define WDT_GET_FROM_USEC(time) (time/((WWDT_US_INDEX * 4)/WDT_OSC))
#define WDT_GET_USEC(counter) (counter * ((WWDT_US_INDEX * 4)/WDT_OSC))
#define WWDT_FUNC_OK (0)
#define WWDT_FUNC_BAD_PARAM (-1)
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t)(1<<0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t)(1<<1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t)(1<<2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t)(1<<3))
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t)(1<<4))
/** Define divider index for microsecond ( us ) */
#define WWDT_US_INDEX ((uint32_t)(1000000))
/** WWDT Time out minimum value */
#define WWDT_TIMEOUT_MIN ((uint32_t)(0xFF))
/** WWDT Time out maximum value */
#define WWDT_TIMEOUT_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT Warning minimum value */
#define WWDT_WARNINT_MIN ((uint32_t)(0xFF))
/** WWDT Warning maximum value */
#define WWDT_WARNINT_MAX ((uint32_t)(0x000003FF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MIN ((uint32_t)(0xFF))
/** WWDT Windowed minimum value */
#define WWDT_WINDOW_MAX ((uint32_t)(0x00FFFFFF))
/** WWDT timer constant register mask */
#define WWDT_WDTC_MASK ((uint32_t)(0x00FFFFFF))
/** WWDT warning value register mask */
#define WWDT_WDWARNINT_MASK ((uint32_t)(0x000003FF))
/** WWDT feed sequence register mask */
#define WWDT_WDFEED_MASK ((uint32_t)(0x000000FF))
/** WWDT flag */
#define WWDT_WARNINT_FLAG ((uint8_t)(0))
#define WWDT_TIMEOUT_FLAG ((uint8_t)(1))
/** WWDT mode definitions */
#define WWDT_PROTECT_MODE ((uint8_t)(0))
#define WWDT_RESET_MODE ((uint8_t)(1))
/* WWDT Timer value definition (us) */
#define WWDT_TIMEOUT_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds
#define WWDT_TIMEOUT_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))
#define WWDT_TIMEWARN_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))
#define WWDT_TIMEWARN_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))
#define WWDT_TIMEWINDOWED_USEC_MIN ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))
#define WWDT_TIMEWINDOWED_USEC_MAX ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))
/**
* @}
*/
/** @defgroup WDT_Public_Types WDT Public Types
* @{
*/
/**
* @brief The field to configurate the WatchDog Timer
*/
typedef struct Wdt_Config
{
uint8_t wdtEnable; /**< if ENABLE -> the enable bit is enabled */
uint8_t wdtReset; /**< if ENABLE -> the Reset bit is enabled */
uint8_t wdtProtect; /**< if ENABLE -> the Protect bit is enabled */
uint32_t wdtTmrConst; /**< Set the constant value to timeout the WDT */
uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt */
uint32_t wdtWindowVal; /**< Set a window vaule for WDT */
}st_Wdt_Config;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup WDT_Public_Functions WDT Public Functions
* @{
*/
int8_t WWDT_Init(uint32_t TimeOut);
int8_t WWDT_Start(uint32_t TimeOut);
void WWDT_SetMode(uint8_t mode, FunctionalState NewState);
void WWDT_SetTimerConstant(uint32_t constVal);
void WWDT_Enable(FunctionalState NewState);
void WWDT_Cmd(FunctionalState NewState);
int8_t WWDT_SetWarningRaw(uint32_t warnVal);
int8_t WWDT_SetWarning(uint32_t WarnTime);
int8_t WWDT_SetWindowRaw(uint32_t wndVal);
int8_t WWDT_SetWindow(uint32_t WindowedTime);
void WWDT_UpdateTimeOut(uint32_t TimeOut);
FlagStatus WWDT_GetStatus (uint8_t Status);
void WWDT_ClearStatusFlag (uint8_t flag);
void WWDT_ClrTimeOutFlag (void);
void WWDT_FeedStdSeq (void);
void WWDT_Feed (void);
uint32_t WWDT_GetCurrentCount(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC_WWDT_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_adc.c 2011-06-02
*//**
* @file lpc_adc.c
* @brief Contains all functions support for ADC firmware library on
* LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup ADC
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _ADC
/* Includes ------------------------------------------------------------------- */
#include "lpc_types.h"
#include "lpc_adc.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup ADC_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial for ADC
* + Set bit PCADC
* + Set clock for ADC
* + Set Clock Frequency
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] rate ADC conversion rate, should be <=200KHz
* @return None
**********************************************************************/
void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate)
{
uint32_t ADCPClk, temp, tmp;
// Turn on power and clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCADC, ENABLE);
ADCx->CR = 0;
//Enable PDN bit
tmp = ADC_CR_PDN;
// Set clock frequency
ADCPClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
* A/D converter, which should be less than or equal to 12.4MHz.
* A fully conversion requires 31 of these clocks.
* ADC clock = PCLK_ADC0 / (CLKDIV + 1);
* ADC rate = ADC clock / 31;
*/
temp = rate * 31;
temp = (ADCPClk * 2 + temp)/(2 * temp) - 1; //get the round value by fomular: (2*A + B)/(2*A)
tmp |= ADC_CR_CLKDIV(temp);
ADCx->CR = tmp;
}
/*********************************************************************//**
* @brief Close ADC
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @return None
**********************************************************************/
void ADC_DeInit(LPC_ADC_TypeDef *ADCx)
{
if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before DeInit
ADCx->CR &= ~ADC_CR_START_MASK;
// Clear SEL bits
ADCx->CR &= ~0xFF;
// Clear PDN bit
ADCx->CR &= ~ADC_CR_PDN;
// Turn on power and clock
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCADC, DISABLE);
}
/*********************************************************************//**
* @brief Get Result conversion from A/D data register
* @param[in] channel number which want to read back the result
* @return Result of conversion
*********************************************************************/
uint32_t ADC_GetData(uint32_t channel)
{
uint32_t adc_value;
adc_value = *(uint32_t *)((&LPC_ADC->DR[0]) + channel);
return ADC_GDR_RESULT(adc_value);
}
/*********************************************************************//**
* @brief Set start mode for ADC
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] start_mode Start mode choose one of modes in
* 'ADC_START_OPT' enumeration type definition, should be:
* - ADC_START_CONTINUOUS
* - ADC_START_NOW
* - ADC_START_ON_EINT0
* - ADC_START_ON_CAP01
* - ADC_START_ON_MAT01
* - ADC_START_ON_MAT03
* - ADC_START_ON_MAT10
* - ADC_START_ON_MAT11
* @return None
*********************************************************************/
void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode)
{
ADCx->CR &= ~ADC_CR_START_MASK;
ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode);
}
/*********************************************************************//**
* @brief ADC Burst mode setting
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] NewState
* - 1: Set Burst mode
* - 0: reset Burst mode
* @return None
**********************************************************************/
void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
{
ADCx->CR &= ~ADC_CR_BURST;
if (NewState){
ADCx->CR |= ADC_CR_BURST;
}
}
/*********************************************************************//**
* @brief Set AD conversion in power mode
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] NewState
* - 1: AD converter is optional
* - 0: AD Converter is in power down mode
* @return None
**********************************************************************/
void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
{
ADCx->CR &= ~ADC_CR_PDN;
if (NewState){
ADCx->CR |= ADC_CR_PDN;
}
}
/*********************************************************************//**
* @brief Set Edge start configuration
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING
* 0:ADC_START_ON_RISING
* 1:ADC_START_ON_FALLING
* @return None
**********************************************************************/
void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption)
{
ADCx->CR &= ~ADC_CR_EDGE;
if (EdgeOption){
ADCx->CR |= ADC_CR_EDGE;
}
}
/*********************************************************************//**
* @brief ADC interrupt configuration
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] IntType: type of interrupt, should be:
* - ADC_ADINTEN0: Interrupt channel 0
* - ADC_ADINTEN1: Interrupt channel 1
* ...
* - ADC_ADINTEN7: Interrupt channel 7
* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt
* @param[in] NewState:
* - SET : enable ADC interrupt
* - RESET: disable ADC interrupt
* @return None
**********************************************************************/
void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState)
{
ADCx->INTEN &= ~ADC_INTEN_CH(IntType);
if (NewState){
ADCx->INTEN |= ADC_INTEN_CH(IntType);
}
}
/*********************************************************************//**
* @brief Enable/Disable ADC channel number
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] Channel channel number
* @param[in] NewState Enable or Disable
*
* @return None
**********************************************************************/
void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
ADCx->CR |= ADC_CR_CH_SEL(Channel);
} else {
if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before disable channel
ADCx->CR &= ~ADC_CR_START_MASK;
ADCx->CR &= ~ADC_CR_CH_SEL(Channel);
}
}
/*********************************************************************//**
* @brief Get ADC result
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] channel: channel number, should be 0...7
* @return Data conversion
**********************************************************************/
uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel)
{
uint32_t adc_value;
adc_value = *(uint32_t *) ((&ADCx->DR[0]) + channel);
return ADC_DR_RESULT(adc_value);
}
/*********************************************************************//**
* @brief Get ADC Chanel status from ADC data register
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] channel: channel number, should be 0..7
* @param[in] StatusType
* 0:Burst status
* 1:Done status
* @return SET / RESET
**********************************************************************/
FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType)
{
uint32_t temp;
temp = *(uint32_t *) ((&ADCx->DR[0]) + channel);
if (StatusType)
{
temp &= ADC_DR_DONE_FLAG;
}
else
{
temp &= ADC_DR_OVERRUN_FLAG;
}
if (temp)
{
return SET;
}
else
{
return RESET;
}
}
/*********************************************************************//**
* @brief Get ADC Data from AD Global register
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @return Result of conversion
**********************************************************************/
uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx)
{
return ((uint32_t)(ADCx->GDR));
}
/*********************************************************************//**
* @brief Get ADC Chanel status from AD global data register
* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
* @param[in] StatusType
* 0:Burst status
* 1:Done status
* @return SET / RESET
**********************************************************************/
FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType)
{
uint32_t temp;
temp = ADCx->GDR;
if (StatusType){
temp &= ADC_DR_DONE_FLAG;
}else{
temp &= ADC_DR_OVERRUN_FLAG;
}
if (temp){
return SET;
}else{
return RESET;
}
}
/**
* @}
*/
#endif /*_ADC*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_bod.c 2011-12-09
*//**
* @file lpc_bod.c
* @brief Contain functions related to BOD.
* @version 1.0
* @date 09 December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup BOD
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _BOD
#include "LPC407x_8x_177x_8x.h" /* LPC407x_8x_177x_8x Peripheral Registers */
#include "lpc_bod.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup BOD_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initialize BOD control register
* @param[in] pConfig BOD Configuration
* @return None
**********************************************************************/
void BOD_Init( BOD_Config_Type* pConfig )
{
/* Turn on/off BOD. */
if(pConfig->Enabled == DISABLE)
{
LPC_SC->PCON |= BOD_PCON_BOGD;
return;
}
LPC_SC->PCON &= ~BOD_PCON_BOGD;
/* Brown-Out Reduced Power Mode */
if(pConfig->PowerReduced == ENABLE)
{
LPC_SC->PCON |= BOD_PCON_BODRPM;
}
else
{
LPC_SC->PCON &= ~BOD_PCON_BODRPM;
}
/* Brown-Out Reset */
if(pConfig->ResetOnVoltageDown == DISABLE)
{
LPC_SC->PCON |= BOD_PCON_BORD;
}
else
{
LPC_SC->PCON &= ~BOD_PCON_BORD;
}
/* Enable the BOD Interrupt */
NVIC_EnableIRQ(BOD_IRQn);
return;
}
/*********************************************************************//**
* @brief Get BOD reset source status
* @param[in] None
* @return TRUE/FALSE
**********************************************************************/
int32_t BOD_ResetSourceStatus( void )
{
if((LPC_SC->RSID & BOD_RSID_POR) == 1)
return DISABLE;
return ((LPC_SC->RSID & BOD_RSID_BODR)? ENABLE:DISABLE);
}
/*********************************************************************//**
* @brief Clear BOD reset source bit
* @param[in] None
* @return None
**********************************************************************/
void BOD_ResetSourceClr( void )
{
LPC_SC->RSID |= BOD_RSID_BODR;
}
/**
* @}
*/
#endif /*_BOD */
/**
* @}
*/
/******************************************************************************
** End Of File
******************************************************************************/

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/**********************************************************************
* $Id$ lpc_clkpwr.c 2011-06-02
*//**
* @file lpc_clkpwr.c
* @brief Contains all functions support for Clock and Power Control
* firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup CLKPWR
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _CLKPWR
/* Includes ------------------------------------------------------------------- */
#include "lpc_clkpwr.h"
uint32_t USBFrequency = 0;
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup CLKPWR_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Set value of each Peripheral Clock Selection
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @param[in] DivVal Value of divider. This value should be set as follows:
* - CPU clock: DivVal must be in range: 0..31
* - Peripheral clock: DivVal must be in range: 0..31
* - EMC clock: DivVal must be:
* + 0: The EMC uses the same clock as the CPU
* + 1: The EMC uses a clock at half the rate of the CPU
* - USB clock: DivVal must be:
* + 0: the divider is turned off, no clock will
* be provided to the USB subsystem
* + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
* + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @return none
* Note: Pls assign right DivVal, this function will not check if it is illegal.
**********************************************************************/
void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
{
uint32_t tmp;
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
tmp = LPC_SC->CCLKSEL & ~(0x1F);
tmp |= DivVal & 0x1F;
LPC_SC->CCLKSEL = tmp;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_PER:
tmp = LPC_SC->PCLKSEL & ~(0x1F);
tmp |= DivVal & 0x1F;
LPC_SC->PCLKSEL = tmp;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_EMC:
tmp = LPC_SC->EMCCLKSEL & ~(0x01);
tmp |= DivVal & 0x01;
LPC_SC->EMCCLKSEL = tmp;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_USB:
tmp = LPC_SC->USBCLKSEL & ~(0x1F);
tmp |= DivVal & 0x1F;
LPC_SC->USBCLKSEL |= DivVal & 0x1F;
SystemCoreClockUpdate(); //Update clock
break;
default:
while(1);//Error Loop;
}
}
/*********************************************************************//**
* @brief Get current clock value
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
**********************************************************************/
uint32_t CLKPWR_GetCLK (uint8_t ClkType)
{
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
return SystemCoreClock;
case CLKPWR_CLKTYPE_PER:
return PeripheralClock;
case CLKPWR_CLKTYPE_EMC:
return EMCClock;
case CLKPWR_CLKTYPE_USB:
return USBClock;
default:
while(1);//error loop
}
}
/*********************************************************************//**
* @brief Configure power supply for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
* - CLKPWR_PCONP_PCTIM1 : Timer 1
* - CLKPWR_PCONP_PCUART0 : UART 0
* - CLKPWR_PCONP_PCUART1 : UART 1
* - CLKPWR_PCONP_PCPWM0 : PWM 0
* - CLKPWR_PCONP_PCPWM1 : PWM 1
* - CLKPWR_PCONP_PCI2C0 : I2C 0
* - CLKPWR_PCONP_PCUART4 : UART4
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
* - CLKPWR_PCONP_PCRTC : RTC
* - CLKPWR_PCONP_PCSSP1 : SSP 1
* - CLKPWR_PCONP_PCEMC : EMC
* - CLKPWR_PCONP_PCADC : ADC
* - CLKPWR_PCONP_PCAN1 : CAN 1
* - CLKPWR_PCONP_PCAN2 : CAN 2
* - CLKPWR_PCONP_PCGPIO : GPIO
* - CLKPWR_PCONP_PCMC : MCPWM
* - CLKPWR_PCONP_PCQEI : QEI
* - CLKPWR_PCONP_PCI2C1 : I2C 1
* - CLKPWR_PCONP_PCSSP2 : SSP 2
* - CLKPWR_PCONP_PCSSP0 : SSP 0
* - CLKPWR_PCONP_PCTIM2 : Timer 2
* - CLKPWR_PCONP_PCTIM3 : Timer 3
* - CLKPWR_PCONP_PCUART2 : UART 2
* - CLKPWR_PCONP_PCUART3 : UART 3
* - CLKPWR_PCONP_PCI2C2 : I2C 2
* - CLKPWR_PCONP_PCI2S : I2S
* - CLKPWR_PCONP_PCSDC : SDC
* - CLKPWR_PCONP_PCGPDMA : GPDMA
* - CLKPWR_PCONP_PCENET : Ethernet
* - CLKPWR_PCONP_PCUSB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
{
if (NewState == ENABLE)
{
LPC_SC->PCONP |= PPType;
}
else if (NewState == DISABLE)
{
LPC_SC->PCONP &= ~PPType;
}
}
#if 0
// nxp21346
/*********************************************************************//**
* @brief Configure hardware reset for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_RSTCON0_LCD : LCD
* - CLKPWR_RSTCON0_TIM0 : Timer 0
- CLKPWR_RSTCON0_TIM1 : Timer 1
- CLKPWR_RSTCON0_UART0 : UART 0
- CLKPWR_RSTCON0_UART1 : UART 1
- CLKPWR_RSTCON0_PWM0 : PWM 0
- CLKPWR_RSTCON0_PWM1 : PWM 1
- CLKPWR_RSTCON0_I2C0 : I2C 0
- CLKPWR_RSTCON0_UART4 : UART 4
- CLKPWR_RSTCON0_RTC : RTC
- CLKPWR_RSTCON0_SSP1 : SSP 1
- CLKPWR_RSTCON0_EMC : EMC
- CLKPWR_RSTCON0_ADC : ADC
- CLKPWR_RSTCON0_CAN1 : CAN 1
- CLKPWR_RSTCON0_CAN2 : CAN 2
- CLKPWR_RSTCON0_GPIO : GPIO
- CLKPWR_RSTCON0_MCPWM : MCPWM
- CLKPWR_RSTCON0_QEI : QEI
- CLKPWR_RSTCON0_I2C1 : I2C 1
- CLKPWR_RSTCON0_SSP2 : SSP 2
- CLKPWR_RSTCON0_SSP0 : SSP 0
- CLKPWR_RSTCON0_TIM2 : Timer 2
- CLKPWR_RSTCON0_TIM3 : Timer 3
- CLKPWR_RSTCON0_UART2 : UART 2
- CLKPWR_RSTCON0_UART3 : UART 3
- CLKPWR_RSTCON0_I2C2 : I2C 2
- CLKPWR_RSTCON0_I2S : I2S
- CLKPWR_RSTCON0_SDC : SDC
- CLKPWR_RSTCON0_GPDMA : GPDMA
- CLKPWR_RSTCON0_ENET : Ethernet
- CLKPWR_RSTCON0_USB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
{
if(PType < 32)
{
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
else
LPC_SC->RSTCON0 &=~(1<<PType);
}
else
{
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
}
// nxp21346
#endif
/*********************************************************************//**
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_Sleep(void)
{
LPC_SC->PCON = 0x00;
/* Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepSleep(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x00;
/* Deep Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_PowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x01;
/* Power Down Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepPowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x03;
/* Deep Power Down Mode*/
__WFI();
}
/**
* @}
*/
#endif /*_CLKPWR*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_crc.c 2011-06-02
*//**
* @file lpc_crc.c
* @brief Contains all functions support for CRC firmware library on
* LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _CRC
/* Includes ------------------------------------------------------------------- */
#include "lpc_crc.h"
#include "lpc_clkpwr.h"
/* Private Variables ----------------------------------------------------------- */
volatile CRC_Type crc_cur_type;
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup CRC_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initialize CRC operation
* @param[in] CRCType CRC standard type, should be:
* - CRC_POLY_CRCCCITT: CRC-CCITT polynomial
* - CRC_POLY_CRC16: CRC-16 polynomial
* - CRC_POLY_CRC32: CRC-32 polynomial
* @return None
**********************************************************************/
void CRC_Init(CRC_Type CRCType)
{
if(CRCType == CRC_POLY_CRCCCITT)
{
LPC_CRC->MODE = 0x00;
LPC_CRC->SEED = 0xFFFF;
crc_cur_type = CRC_POLY_CRCCCITT;
}
else if(CRCType == CRC_POLY_CRC16)
{
LPC_CRC->MODE = 0x15;
LPC_CRC->SEED = 0x0000;
crc_cur_type = CRC_POLY_CRC16;
}
else if(CRCType == CRC_POLY_CRC32)
{
LPC_CRC->MODE = 0x36;
LPC_CRC->SEED = 0xFFFFFFFF;
crc_cur_type = CRC_POLY_CRC32;
}
else
{
//Invalid input parameter
while(1);//error loop
}
}
/*********************************************************************//**
* @brief CRC reset
* @param[in] None
* @return None
**********************************************************************/
void CRC_Reset(void)
{
if(crc_cur_type == CRC_POLY_CRCCCITT)
LPC_CRC->SEED = 0xFFFF;
else if (crc_cur_type == CRC_POLY_CRC16)
LPC_CRC->SEED = 0x0000;
else if (crc_cur_type == CRC_POLY_CRC32)
LPC_CRC->SEED = 0xFFFFFFFF;
}
/*********************************************************************//**
* @brief CRC data checksum calculation
* @param[in] data input data
* @return data checksum result
**********************************************************************/
uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType)
{
if(SizeType == CRC_WR_8BIT)
LPC_CRC->WR_DATA_BYTE.DATA = (uint8_t)data;
else if(SizeType == CRC_WR_16BIT)
LPC_CRC->WR_DATA_WORD.DATA = (uint16_t)data;
else
LPC_CRC->WR_DATA_DWORD.DATA = data;
return(LPC_CRC->SUM);
}
/*********************************************************************//**
* @brief CRC block data checksum calculation
* @param[in] blockdata pointer to block input data
* @param[in] blocksize size of block data
* @param[in] SizeType size of data width per write, should be:
- CRC_WR_8BIT : 8-bit write
- CRC_WR_16BIT: 16-bit write
- CRC_WR_32BIT: 32-bit write
* @return block data checksum result
**********************************************************************/
uint32_t CRC_CalcBlockChecksum(void *block_data, uint32_t block_size, CRC_WR_SIZE data_size)
{
uint8_t *data = (uint8_t*) block_data;
while(block_size !=0) {
switch(data_size) {
case CRC_WR_8BIT:
{
uint8_t *tmp = data;
LPC_CRC->WR_DATA_BYTE.DATA = *tmp;
data++;
}
break;
case CRC_WR_16BIT:
{
uint16_t *tmp = (uint16_t*)data;
LPC_CRC->WR_DATA_WORD.DATA = *tmp;
data +=2;
}
break;
default:
{
uint32_t *tmp = (uint32_t*)data;
LPC_CRC->WR_DATA_DWORD.DATA = *tmp;
data += 4;
}
break;
}
block_size--;
}
return(LPC_CRC->SUM);
}
/**
* @}
*/
#endif /*_CRC*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_dac.c 2011-06-02
*//**
* @file lpc_dac.c
* @brief Contains all functions support for DAC firmware library on
* LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup DAC
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _DAC
/* Includes ------------------------------------------------------------------- */
#include "lpc_dac.h"
#include "lpc_clkpwr.h"
#include "lpc_pinsel.h"
/* Private Functions ---------------------------------------------------------- */
/*********************************************************************//**
* @brief Get pointer to DAC peripheral
* @param[in] compId Component ID, normally is zero (0).
* @param[in] pinnum Pin number value, should be in range from 0..31
* @return Pointer to DAC peripheral component
**********************************************************************/
static LPC_DAC_TypeDef * DAC_GetPointer(uint8_t compId)
{
LPC_DAC_TypeDef *pComponent = LPC_DAC;
return pComponent;
}
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup DAC_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial ADC configuration
* - Maximum current is 700 uA
* - Value to AOUT is 0
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @return None
***********************************************************************/
void DAC_Init(uint8_t DAC_Id)
{
/*
* Init DAC pin connect
* AOUT on P0.26
*/
PINSEL_ConfigPin(0, 26, 2);
PINSEL_SetAnalogPinMode(0,26,ENABLE);
//Enable DAC for the pin
PINSEL_DacEnable(0, 26, ENABLE);
//Set maximum current output as default
DAC_SetBias(DAC_Id, DAC_MAX_CURRENT_700uA);
}
/*********************************************************************//**
* @brief Update value to DAC
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @param[in] dac_value : value 10 bit to be converted to output
* @return None
***********************************************************************/
void DAC_UpdateValue (uint8_t DAC_Id,uint32_t dac_value)
{
uint32_t tmp;
LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id);
tmp = pDac->CR & DAC_BIAS_EN;
tmp |= DAC_VALUE(dac_value);
// Update value
pDac->CR = tmp;
}
/*********************************************************************//**
* @brief Set Maximum current for DAC
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @param[in] bias : 0 is 700 uA
* 1 350 uA
* @return None
***********************************************************************/
void DAC_SetBias (uint8_t DAC_Id, uint32_t bias)
{
LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id);
pDac->CR &=~DAC_BIAS_EN;
if (bias == DAC_MAX_CURRENT_350uA)
{
pDac->CR |= DAC_BIAS_EN;
}
}
/*********************************************************************//**
* @brief To enable the DMA operation and control DMA timer
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type
* - DBLBUF_ENA : enable/disable DACR double buffering feature
* - CNT_ENA : enable/disable timer out counter
* - DMA_ENA : enable/disable DMA access
* @return None
***********************************************************************/
void DAC_ConfigDAConverterControl (uint8_t DAC_Id, DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct)
{
LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id);
pDac->CTRL &= ~DAC_DACCTRL_MASK;
if (DAC_ConverterConfigStruct->DBLBUF_ENA)
pDac->CTRL |= DAC_DBLBUF_ENA;
if (DAC_ConverterConfigStruct->CNT_ENA)
pDac->CTRL |= DAC_CNT_ENA;
if (DAC_ConverterConfigStruct->DMA_ENA)
pDac->CTRL |= DAC_DMA_ENA;
}
/*********************************************************************//**
* @brief Set reload value for interrupt/DMA counter
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @param[in] time_out time out to reload for interrupt/DMA counter
* @return None
***********************************************************************/
void DAC_SetDMATimeOut(uint8_t DAC_Id, uint32_t time_out)
{
LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id);
pDac->CNTVAL = DAC_CCNT_VALUE(time_out);
}
/*********************************************************************//**
* @brief Check the interrupt/DMA counter is occured or not because of the timer counter
* @param[in] DAC_Id the ID of the DAC component that is using, should be: zero (0)
* @return None
***********************************************************************/
uint8_t DAC_IsIntRequested(uint8_t DAC_Id)
{
LPC_DAC_TypeDef* pDac = DAC_GetPointer(DAC_Id);
//Return the INT_DMA_REQ bit of D/A control register
return (pDac->CTRL & 0x01);
}
/**
* @}
*/
#endif /*_DAC*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_eeprom.c 2011-06-02
*//**
* @file lpc_eeprom.c
* @brief Contains all functions support for EEPROM firmware library on
* LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup EEPROM
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _EEPROM
/* Includes ------------------------------------------------------------------- */
#include "lpc_eeprom.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/*********************************************************************//**
* @brief Initial EEPROM
* @param[in] None
* @return None
**********************************************************************/
void EEPROM_Init(void)
{
uint32_t val, cclk;
LPC_EEPROM->PWRDWN = 0x0;
/* EEPROM is automate turn on after reset */
/* Setting clock:
* EEPROM required a 375kHz. This clock is generated by dividing the
* system bus clock.
*/
cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU);
val = (cclk/375000)-1;
LPC_EEPROM->CLKDIV = val;
/* Setting wait state */
val = ((((cclk / 1000000) * 15) / 1000) + 1);
val |= (((((cclk / 1000000) * 55) / 1000) + 1) << 8);
val |= (((((cclk / 1000000) * 35) / 1000) + 1) << 16);
LPC_EEPROM->WSTATE = val;
}
/*********************************************************************//**
* @brief Write data to EEPROM at specific address
* @param[in] page_offset offset of data in page register(0 - 63)
* page_address page address (0-62)
* mode Write mode, should be:
* - MODE_8_BIT : write 8 bit mode
* - MODE_16_BIT : write 16 bit mode
* - MODE_32_BIT : write 32 bit mode
* data buffer that contain data that will be written to buffer
* count number written data
* @return None
* @note This function actually write data into EEPROM memory and automatically
* write into next page if current page is overflowed
**********************************************************************/
void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t count)
{
uint32_t i;
uint8_t *tmp8 = (uint8_t *)data;
uint16_t *tmp16 = (uint16_t *)data;
uint32_t *tmp32 = (uint32_t *)data;
LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG));
//check page_offset
if(mode == MODE_16_BIT){
if((page_offset & 0x01)!=0) while(1);
}
else if(mode == MODE_32_BIT){
if((page_offset & 0x03)!=0) while(1);
}
LPC_EEPROM->ADDR = EEPROM_PAGE_OFFSET(page_offset);
for(i=0;i<count;i++)
{
//update data to page register
if(mode == MODE_8_BIT){
LPC_EEPROM->CMD = EEPROM_CMD_8_BIT_WRITE;
LPC_EEPROM -> WDATA = *tmp8;
tmp8++;
page_offset +=1;
}
else if(mode == MODE_16_BIT){
LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_WRITE;
LPC_EEPROM -> WDATA = *tmp16;
tmp16++;
page_offset +=2;
}
else{
LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_WRITE;
LPC_EEPROM -> WDATA = *tmp32;
tmp32++;
page_offset +=4;
}
while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01));
LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW);
if((page_offset >= EEPROM_PAGE_SIZE)|(i==count-1)){
//update to EEPROM memory
LPC_EEPROM->INT_CLR_STATUS = (0x1 << EEPROM_ENDOF_PROG);
LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address);
LPC_EEPROM->CMD = EEPROM_CMD_ERASE_PRG_PAGE;
while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_PROG)&0x01));
LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_PROG);
}
if(page_offset >= EEPROM_PAGE_SIZE)
{
page_offset = 0;
page_address +=1;
LPC_EEPROM->ADDR =0;
if(page_address > EEPROM_PAGE_NUM - 1) page_address = 0;
}
}
}
/*********************************************************************//**
* @brief Read data to EEPROM at specific address
* @param[in]
* data buffer that contain data that will be written to buffer
* mode Read mode, should be:
* - MODE_8_BIT : read 8 bit mode
* - MODE_16_BIT : read 16 bit mode
* - MODE_32_BIT : read 32 bit mode
* count number read data (bytes)
* @return data buffer that contain data that will be read to buffer
**********************************************************************/
void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t count)
{
uint32_t i;
uint8_t *tmp8 = (uint8_t *)data;
uint16_t *tmp16 = (uint16_t *)data;
uint32_t *tmp32 = (uint32_t *)data;
LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG));
LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address)|EEPROM_PAGE_OFFSET(page_offset);
if(mode == MODE_8_BIT)
LPC_EEPROM->CMD = EEPROM_CMD_8_BIT_READ|EEPROM_CMD_RDPREFETCH;
else if(mode == MODE_16_BIT){
LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_READ|EEPROM_CMD_RDPREFETCH;
//check page_offset
if((page_offset &0x01)!=0)
return;
}
else{
LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_READ|EEPROM_CMD_RDPREFETCH;
//page_offset must be a multiple of 0x04
if((page_offset & 0x03)!=0)
return;
}
//read and store data in buffer
for(i=0;i<count;i++){
if(mode == MODE_8_BIT){
*tmp8 = (uint8_t)(LPC_EEPROM -> RDATA);
tmp8++;
page_offset +=1;
}
else if (mode == MODE_16_BIT)
{
*tmp16 = (uint16_t)(LPC_EEPROM -> RDATA);
tmp16++;
page_offset +=2;
}
else{
*tmp32 = (uint32_t)(LPC_EEPROM ->RDATA);
tmp32++;
page_offset +=4;
}
while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01));
LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW);
if((page_offset >= EEPROM_PAGE_SIZE) && (i < count - 1)) {
page_offset = 0;
page_address++;
LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address)|EEPROM_PAGE_OFFSET(page_offset);
if(mode == MODE_8_BIT)
LPC_EEPROM->CMD = EEPROM_CMD_8_BIT_READ|EEPROM_CMD_RDPREFETCH;
else if(mode == MODE_16_BIT)
LPC_EEPROM->CMD = EEPROM_CMD_16_BIT_READ|EEPROM_CMD_RDPREFETCH;
else
LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_READ|EEPROM_CMD_RDPREFETCH;
}
}
}
/*********************************************************************//**
* @brief Erase a page at the specific address
* @param[in] address EEPROM page address (0-62)
* @return data buffer that contain data that will be read to buffer
**********************************************************************/
void EEPROM_Erase(uint16_t page_address)
{
uint32_t i;
uint32_t count = EEPROM_PAGE_SIZE/4;
LPC_EEPROM->INT_CLR_STATUS = ((1 << EEPROM_ENDOF_RW)|(1 << EEPROM_ENDOF_PROG));
//clear page register
LPC_EEPROM->ADDR = EEPROM_PAGE_OFFSET(0);
LPC_EEPROM->CMD = EEPROM_CMD_32_BIT_WRITE;
for(i=0;i<count;i++)
{
LPC_EEPROM->WDATA = 0;
while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_RW)&0x01));
LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_RW);
}
LPC_EEPROM->INT_CLR_STATUS = (0x1 << EEPROM_ENDOF_PROG);
LPC_EEPROM->ADDR = EEPROM_PAGE_ADRESS(page_address);
LPC_EEPROM->CMD = EEPROM_CMD_ERASE_PRG_PAGE;
while(!((LPC_EEPROM->INT_STATUS >> EEPROM_ENDOF_PROG)&0x01));
LPC_EEPROM->INT_CLR_STATUS = (1 << EEPROM_ENDOF_PROG);
}
/*********************************************************************//**
* @brief Enable/Disable EEPROM power down mdoe
* @param[in] NewState PowerDown mode state, should be:
* - ENABLE: Enable power down mode
* - DISABLE: Disable power down mode
* @return None
**********************************************************************/
void EEPROM_PowerDown(FunctionalState NewState)
{
if(NewState == ENABLE)
LPC_EEPROM->PWRDWN = 0x1;
else
LPC_EEPROM->PWRDWN = 0x0;
}
#endif /*_EEPROM*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_exti.c 2011-06-02
*//**
* @file lpc_exti.c
* @brief Contains all functions support for External Interrupt
* firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup EXTI
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _EXTI
/* Includes ------------------------------------------------------------------- */
#include "lpc_exti.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup EXTI_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial for EXT
* - Set EXTINT, EXTMODE, EXTPOLAR registers to default value
* @param[in] None
* @return None
**********************************************************************/
void EXTI_Init(void)
{
LPC_SC->EXTINT = 0xF;
LPC_SC->EXTMODE = 0x0;
LPC_SC->EXTPOLAR = 0x0;
}
/*********************************************************************//**
* @brief Close EXT
* @param[in] None
* @return None
**********************************************************************/
void EXTI_DeInit(void)
{
;
}
/*********************************************************************//**
* @brief Configuration for EXT
* - Set EXTINT, EXTMODE, EXTPOLAR register
* @param[in] EXTICfg Pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the
* specified external interrupt
* @return None
**********************************************************************/
void EXTI_Config(EXTI_InitTypeDef *EXTICfg)
{
LPC_SC->EXTINT = 0x0;
EXTI_SetMode(EXTICfg->EXTI_Line, EXTICfg->EXTI_Mode);
EXTI_SetPolarity(EXTICfg->EXTI_Line, EXTICfg->EXTI_polarity);
}
/*********************************************************************//**
* @brief Set mode for EXTI pin
* @param[in] EXTILine external interrupt line, should be:
* - EXTI_EINT0: external interrupt line 0
* - EXTI_EINT1: external interrupt line 1
* - EXTI_EINT2: external interrupt line 2
* - EXTI_EINT3: external interrupt line 3
* @param[in] mode external mode, should be:
* - EXTI_MODE_LEVEL_SENSITIVE
* - EXTI_MODE_EDGE_SENSITIVE
* @return None
*********************************************************************/
void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode)
{
if(mode == EXTI_MODE_EDGE_SENSITIVE)
{
LPC_SC->EXTMODE |= (1 << EXTILine);
}
else if(mode == EXTI_MODE_LEVEL_SENSITIVE)
{
LPC_SC->EXTMODE &= ~(1 << EXTILine);
}
}
/*********************************************************************//**
* @brief Set polarity for EXTI pin
* @param[in] EXTILine external interrupt line, should be:
* - EXTI_EINT0: external interrupt line 0
* - EXTI_EINT1: external interrupt line 1
* - EXTI_EINT2: external interrupt line 2
* - EXTI_EINT3: external interrupt line 3
* @param[in] polarity external polarity value, should be:
* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE
* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE
* @return None
*********************************************************************/
void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity)
{
if(polarity == EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE)
{
LPC_SC->EXTPOLAR |= (1 << EXTILine);
}
else if(polarity == EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE)
{
LPC_SC->EXTPOLAR &= ~(1 << EXTILine);
}
}
/*********************************************************************//**
* @brief Clear External interrupt flag
* @param[in] EXTILine external interrupt line, should be:
* - EXTI_EINT0: external interrupt line 0
* - EXTI_EINT1: external interrupt line 1
* - EXTI_EINT2: external interrupt line 2
* - EXTI_EINT3: external interrupt line 3
* @return None
*********************************************************************/
void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine)
{
LPC_SC->EXTINT |= (1 << EXTILine);
}
/**
* @}
*/
#endif /*_EXTI*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_gpdma.c 2011-06-02
*//**
* @file lpc_gpdma.c
* @brief Contains all functions support for GPDMA firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup GPDMA
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _GPDMA
/* Includes ------------------------------------------------------------------- */
#include "lpc_gpdma.h"
#include "lpc_clkpwr.h"
/* Private Variables ---------------------------------------------------------- */
/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
* @{
*/
/**
* @brief Lookup Table of Connection Type matched with
* Peripheral Data (FIFO) register base address
*/
volatile const void *GPDMA_LUTPerAddr[] = {
0, // Revered
(&LPC_MCI->FIFO), // SD Card
(&LPC_SSP0->DR), // SSP0 Tx
(&LPC_SSP0->DR), // SSP0 Rx
(&LPC_SSP1->DR), // SSP1 Tx
(&LPC_SSP1->DR), // SSP1 Rx
(&LPC_SSP2->DR), // SSP2 Tx
(&LPC_SSP2->DR), // SSP2 Rx
(&LPC_ADC->GDR), // ADC
(&LPC_DAC->CR), // DAC
(&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
(&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
(&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
(&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
(&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
(&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
(&LPC_TIM0->MR0), // MAT0.0
(&LPC_TIM0->MR1), // MAT0.1
(&LPC_TIM1->MR0), // MAT1.0
(&LPC_TIM1->MR1), // MAT1.1
(&LPC_TIM2->MR0), // MAT2.0
(&LPC_TIM2->MR1), // MAT2.1
(&LPC_I2S->TXFIFO), // I2S Tx
(&LPC_I2S->RXFIFO), // I2S Rx
0, // Reverse
0, // Reverse
(&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
(&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
(&LPC_UART4->/*RBTHDLR.*/THR), // UART4 Tx
(&LPC_UART4->/*RBTHDLR.*/RBR), // UART4 Rx
(&LPC_TIM3->MR0), // MAT3.0
(&LPC_TIM3->MR1), // MAT3.1
};
/**
* @brief Lookup Table of GPDMA Channel Number matched with
* GPDMA channel pointer
*/
const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
LPC_GPDMACH0, // GPDMA Channel 0
LPC_GPDMACH1, // GPDMA Channel 1
LPC_GPDMACH2, // GPDMA Channel 2
LPC_GPDMACH3, // GPDMA Channel 3
LPC_GPDMACH4, // GPDMA Channel 4
LPC_GPDMACH5, // GPDMA Channel 5
LPC_GPDMACH6, // GPDMA Channel 6
LPC_GPDMACH7, // GPDMA Channel 7
};
/**
* @brief Optimized Peripheral Source and Destination burst size
*/
const uint8_t GPDMA_LUTPerBurst[] = {
0, // Reserved
GPDMA_BSIZE_8, // SD Card
GPDMA_BSIZE_4, // SSP0 Tx
GPDMA_BSIZE_4, // SSP0 Rx
GPDMA_BSIZE_4, // SSP1 Tx
GPDMA_BSIZE_4, // SSP1 Rx
GPDMA_BSIZE_4, // SSP2 Tx
GPDMA_BSIZE_4, // SSP2 Rx
GPDMA_BSIZE_1, // ADC
GPDMA_BSIZE_1, // DAC
GPDMA_BSIZE_1, // UART0 Tx
GPDMA_BSIZE_1, // UART0 Rx
GPDMA_BSIZE_1, // UART1 Tx
GPDMA_BSIZE_1, // UART1 Rx
GPDMA_BSIZE_1, // UART2 Tx
GPDMA_BSIZE_1, // UART2 Rx
GPDMA_BSIZE_1, // MAT0.0
GPDMA_BSIZE_1, // MAT0.1
GPDMA_BSIZE_1, // MAT1.0
GPDMA_BSIZE_1, // MAT1.1
GPDMA_BSIZE_1, // MAT2.0
GPDMA_BSIZE_1, // MAT2.1
GPDMA_BSIZE_32, // I2S channel 0
GPDMA_BSIZE_32, // I2S channel 1
0, // Reserved
0, // Reserved
GPDMA_BSIZE_1, // UART3 Tx
GPDMA_BSIZE_1, // UART3 Rx
GPDMA_BSIZE_1, // UART4 Tx
GPDMA_BSIZE_1, // UART4 Rx
GPDMA_BSIZE_1, // MAT3.0
GPDMA_BSIZE_1, // MAT3.1
};
/**
* @brief Optimized Peripheral Source and Destination transfer width
*/
const uint8_t GPDMA_LUTPerWid[] = {
0, // Reserved
GPDMA_WIDTH_WORD, // SD Card
GPDMA_WIDTH_BYTE, // SSP0 Tx
GPDMA_WIDTH_BYTE, // SSP0 Rx
GPDMA_WIDTH_BYTE, // SSP1 Tx
GPDMA_WIDTH_BYTE, // SSP1 Rx
GPDMA_WIDTH_BYTE, // SSP2 Tx
GPDMA_WIDTH_BYTE, // SSP2 Rx
GPDMA_WIDTH_WORD, // ADC
GPDMA_WIDTH_BYTE, // DAC
GPDMA_WIDTH_BYTE, // UART0 Tx
GPDMA_WIDTH_BYTE, // UART0 Rx
GPDMA_WIDTH_BYTE, // UART1 Tx
GPDMA_WIDTH_BYTE, // UART1 Rx
GPDMA_WIDTH_BYTE, // UART2 Tx
GPDMA_WIDTH_BYTE, // UART2 Rx
GPDMA_WIDTH_WORD, // MAT0.0
GPDMA_WIDTH_WORD, // MAT0.1
GPDMA_WIDTH_WORD, // MAT1.0
GPDMA_WIDTH_WORD, // MAT1.1
GPDMA_WIDTH_WORD, // MAT2.0
GPDMA_WIDTH_WORD, // MAT2.1
GPDMA_WIDTH_WORD, // I2S channel 0
GPDMA_WIDTH_WORD, // I2S channel 1
0, // Reserved
0, // Reserved
GPDMA_WIDTH_BYTE, // UART3 Tx
GPDMA_WIDTH_BYTE, // UART3 Rx
GPDMA_WIDTH_BYTE, // UART4 Tx
GPDMA_WIDTH_BYTE, // UART4 Rx
GPDMA_WIDTH_WORD, // MAT3.0
GPDMA_WIDTH_WORD, // MAT3.1
};
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup GPDMA_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initialize GPDMA controller
* @param None
* @return None
*********************************************************************/
void GPDMA_Init(void)
{
/* Enable GPDMA clock */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
// Reset all channel configuration register
LPC_GPDMACH0->CConfig = 0;
LPC_GPDMACH1->CConfig = 0;
LPC_GPDMACH2->CConfig = 0;
LPC_GPDMACH3->CConfig = 0;
LPC_GPDMACH4->CConfig = 0;
LPC_GPDMACH5->CConfig = 0;
LPC_GPDMACH6->CConfig = 0;
LPC_GPDMACH7->CConfig = 0;
/* Clear all DMA interrupt and error flag */
LPC_GPDMA->IntTCClear = 0xFF;
LPC_GPDMA->IntErrClr = 0xFF;
}
/********************************************************************//**
* @brief Setup GPDMA channel peripheral according to the specified
* parameters in the GPDMAChannelConfig.
* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
* structure that contains the configuration
* information for the specified GPDMA channel peripheral.
* @return ERROR if selected channel is enabled before
* or SUCCESS if channel is configured successfully
*********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
LPC_GPDMACH_TypeDef *pDMAch;
uint32_t tmp1, tmp2;
if (LPC_GPDMA->EnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
// This channel is enabled, return ERROR, need to release this channel first
return ERROR;
}
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
// Reset the Interrupt status
LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
// Clear DMA configure
pDMAch->CControl = 0x00;
pDMAch->CConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
/* Set value to Channel Control Registers */
switch (GPDMAChannelConfig->TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M:
// Assign physical source and destination address
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P:
case GPDMA_TRANSFERTYPE_M2P_DEST_CTRL:
// Assign physical source
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M:
case GPDMA_TRANSFERTYPE_P2M_SRC_CTRL:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_I;
break;
// Do not support any more transfer type, return ERROR
default:
return ERROR;
}
/* Re-Configure DMA Request Select for source peripheral */
if((GPDMAChannelConfig->SrcConn != 8)&&(GPDMAChannelConfig->SrcConn != 9))
{
if (GPDMAChannelConfig->SrcConn > 15)
{
LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
} else {
LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn));
}
}
/* Re-Configure DMA Request Select for Destination peripheral */
if((GPDMAChannelConfig->DstConn != 8)&&(GPDMAChannelConfig->DstConn != 9))
{
if (GPDMAChannelConfig->DstConn > 15)
{
LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
} else {
LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn));
}
}
/* Enable DMA channels, little endian */
LPC_GPDMA->Config = GPDMA_DMACConfig_E;
while (!(LPC_GPDMA->Config & GPDMA_DMACConfig_E));
// Calculate absolute value for Connection number
tmp1 = GPDMAChannelConfig->SrcConn;
tmp1 = ((tmp1 > 15) ? (tmp1 - 16) : tmp1);
tmp2 = GPDMAChannelConfig->DstConn;
tmp2 = ((tmp2 > 15) ? (tmp2 - 16) : tmp2);
// Configure DMA Channel, enable Error Counter and Terminate counter
pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
return SUCCESS;
}
/*********************************************************************//**
* @brief Enable/Disable DMA channel
* @param[in] channelNum GPDMA channel, should be in range from 0 to 7
* @param[in] NewState New State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
**********************************************************************/
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
{
LPC_GPDMACH_TypeDef *pDMAch;
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
if (NewState == ENABLE) {
pDMAch->CConfig |= GPDMA_DMACCxConfig_E;
} else {
pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;
}
}
/*********************************************************************//**
* @brief Check if corresponding channel does have an active interrupt
* request or not
* @param[in] type type of status, should be:
* - GPDMA_STAT_INT: GPDMA Interrupt Status
* - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
* - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
* - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
* - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
* - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
* @param[in] channel GPDMA channel, should be in range from 0 to 7
* @return IntStatus status of DMA channel interrupt after masking
* Should be:
* - SET: the corresponding channel has no active interrupt request
* - RESET: the corresponding channel does have an active interrupt request
**********************************************************************/
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
{
switch (type)
{
case GPDMA_STAT_INT: //check status of DMA channel interrupts
if (LPC_GPDMA->IntStat & (GPDMA_DMACIntStat_Ch(channel)))
return SET;
return RESET;
case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
if (LPC_GPDMA->IntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
if (LPC_GPDMA->IntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
if (LPC_GPDMA->RawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
return SET;
return RESET;
case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
if (LPC_GPDMA->RawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
return SET;
return RESET;
default: //check enable status for DMA channels
if (LPC_GPDMA->EnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
return SET;
return RESET;
}
}
/*********************************************************************//**
* @brief Clear one or more interrupt requests on DMA channels
* @param[in] type type of interrupt request, should be:
* - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
* - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
* @param[in] channel GPDMA channel, should be in range from 0 to 7
* @return None
**********************************************************************/
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
{
if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
else // clear the error interrupt request
LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
}
/**
* @}
*/
#endif /* _GPDMA */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_gpio.c 2011-06-02
*//**
* @file lpc_gpio.c
* @brief Contains all functions support for GPIO firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup GPIO
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _GPIO
/* Includes ------------------------------------------------------------------- */
#include "lpc_gpio.h"
#include "lpc_clkpwr.h"
/* definitions ------------------------------------------------------------------- */
#define GPIO_IS_ENABLED(x) (((x) != 0)? ENABLE:DISABLE)
/* Private Functions ---------------------------------------------------------- */
static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum);
static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum);
static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum);
/*********************************************************************//**
* @brief Get pointer to GPIO peripheral due to GPIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to GPIO peripheral
**********************************************************************/
static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum)
{
LPC_GPIO_TypeDef *pGPIO = NULL;
switch (portNum)
{
case 0:
pGPIO = LPC_GPIO0;
break;
case 1:
pGPIO = LPC_GPIO1;
break;
case 2:
pGPIO = LPC_GPIO2;
break;
case 3:
pGPIO = LPC_GPIO3;
break;
case 4:
pGPIO = LPC_GPIO4;
break;
case 5:
pGPIO = LPC_GPIO5;
break;
default:
break;
}
return pGPIO;
}
/*********************************************************************//**
* @brief Get pointer to FIO peripheral in halfword accessible style
* due to FIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to FIO peripheral
**********************************************************************/
static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum)
{
GPIO_HalfWord_TypeDef *pFIO = NULL;
switch (portNum)
{
case 0:
pFIO = GPIO0_HalfWord;
break;
case 1:
pFIO = GPIO1_HalfWord;
break;
case 2:
pFIO = GPIO2_HalfWord;
break;
case 3:
pFIO = GPIO3_HalfWord;
break;
case 4:
pFIO = GPIO4_HalfWord;
break;
case 5:
pFIO = GPIO5_HalfWord;
break;
default:
break;
}
return pFIO;
}
/*********************************************************************//**
* @brief Get pointer to FIO peripheral in byte accessible style
* due to FIO port
* @param[in] portNum Port Number value, should be in range from 0 to 4.
* @return Pointer to FIO peripheral
**********************************************************************/
static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum)
{
GPIO_Byte_TypeDef *pFIO = NULL;
switch (portNum)
{
case 0:
pFIO = GPIO0_Byte;
break;
case 1:
pFIO = GPIO1_Byte;
break;
case 2:
pFIO = GPIO2_Byte;
break;
case 3:
pFIO = GPIO3_Byte;
break;
case 4:
pFIO = GPIO4_Byte;
break;
case 5:
pFIO = GPIO5_Byte;
break;
default:
break;
}
return pFIO;
}
/* End of Private Functions --------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup GPIO_Public_Functions
* @{
*/
/* GPIO ------------------------------------------------------------------------------ */
/*********************************************************************//**
* @brief Initialize the GPIO component by power on the clock
* supplied to it.
* @return None
*
* Note:
**********************************************************************/
void GPIO_Init(void)
{
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCGPIO, ENABLE);
return;
}
/*********************************************************************//**
* @brief De-initialize the GPIO component by power off the clock
* supplied to it.
* @return None
*
* Note:
**********************************************************************/
void GPIO_Deinit(void)
{
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCGPIO, DISABLE);
return;
}
/*********************************************************************//**
* @brief Set Direction for GPIO port.
* @param[in] portNum Port Number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits to set direction,
* in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to set direction for bit 0 and bit 1.
* @param[in] dir Direction value, should be:
* - 0: Input.
* - 1: Output.
* @return None
*
* Note: All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
{
LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
if (pGPIO != NULL)
{
// Enable Output
if (dir)
{
pGPIO->DIR |= bitValue;
}
// Enable Input
else
{
pGPIO->DIR &= ~bitValue;
}
}
}
/*********************************************************************//**
* @brief Set Value for bits that have output direction on GPIO port.
* @param[in] portNum Port number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits on GPIO to set,
* in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to set bit 0 and bit 1.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
{
LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
if (pGPIO != NULL)
{
pGPIO->SET = bitValue;
}
}
/*********************************************************************//**
* @brief Clear Value for bits that have output direction on GPIO port.
* @param[in] portNum Port number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits on GPIO to clear,
* in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to clear bit 0 and bit 1.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
{
LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
if (pGPIO != NULL)
{
pGPIO->CLR = bitValue;
}
}
/*********************************************************************//**
* @brief Output to the GPIO pin an expected value
* @param[in] portNum Port number value, should be in range from 0 to 4
* @param[in] bitValue Value that contains all bits on GPIO to clear,
* in range from 0 to 0xFFFFFFFF.
* example: value 0x5 to clear bit 0 and bit 1.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void GPIO_OutputValue(uint8_t portNum, uint32_t bitMask, uint8_t value)
{
if (value == 0)
{
GPIO_ClearValue(portNum, bitMask);
}
else
{
GPIO_SetValue(portNum, bitMask);
}
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* @param[in] portNum Port number to read value, in range from 0 to 4
* @return Current value of GPIO port.
*
* Note: Return value contain state of each port pin (bit) on that GPIO regardless
* its direction is input or output.
**********************************************************************/
uint32_t GPIO_ReadValue(uint8_t portNum)
{
LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
if (pGPIO != NULL)
{
return pGPIO->PIN;
}
return (0);
}
/*********************************************************************//**
* @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] bitValue Value that contains all bits on GPIO to enable,
* in range from 0 to 0xFFFFFFFF.
* @param[in] edgeState state of edge, should be:
* - 0: Rising edge
* - 1: Falling edge
* @return None
**********************************************************************/
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
{
if((portNum == 0)&&(edgeState == 0))
LPC_GPIOINT->IO0IntEnR = bitValue;
else if ((portNum == 2)&&(edgeState == 0))
LPC_GPIOINT->IO2IntEnR = bitValue;
else if ((portNum == 0)&&(edgeState == 1))
LPC_GPIOINT->IO0IntEnF = bitValue;
else if ((portNum == 2)&&(edgeState == 1))
LPC_GPIOINT->IO2IntEnF = bitValue;
else
//Error
while(1);
}
/*********************************************************************//**
* @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13
* (with port 2)
* @param[in] edgeState state of edge, should be:
* - 0: Rising edge
* - 1: Falling edge
* @return Bool could be:
* - ENABLE: Interrupt has been generated due to a rising
* edge on P0.0
* - DISABLE: A rising edge has not been detected on P0.0
**********************************************************************/
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
{
if((portNum == 0) && (edgeState == 0))//Rising Edge
return GPIO_IS_ENABLED(((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1);
else if ((portNum == 2) && (edgeState == 0))
return GPIO_IS_ENABLED(((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1);
else if ((portNum == 0) && (edgeState == 1))//Falling Edge
return GPIO_IS_ENABLED(((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1);
else if ((portNum == 2) && (edgeState == 1))
return GPIO_IS_ENABLED(((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1);
else
//Error
while(1);
}
/*********************************************************************//**
* @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
* @param[in] portNum Port number to read value, should be: 0 or 2
* @param[in] bitValue Value that contains all bits on GPIO to enable,
* in range from 0 to 0xFFFFFFFF.
* @return None
**********************************************************************/
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue)
{
if(portNum == 0)
LPC_GPIOINT->IO0IntClr = bitValue;
else if (portNum == 2)
LPC_GPIOINT->IO2IntClr = bitValue;
else
//Invalid portNum
while(1);
}
/* FIO word accessible ----------------------------------------------------------------- */
/* Stub function for FIO (word-accessible) style */
/**
* @brief The same with GPIO_SetDir()
*/
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
{
GPIO_SetDir(portNum, bitValue, dir);
}
/**
* @brief The same with GPIO_SetValue()
*/
void FIO_SetValue(uint8_t portNum, uint32_t bitValue)
{
GPIO_SetValue(portNum, bitValue);
}
/**
* @brief The same with GPIO_ClearValue()
*/
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
{
GPIO_ClearValue(portNum, bitValue);
}
/**
* @brief The same with GPIO_ReadValue()
*/
uint32_t FIO_ReadValue(uint8_t portNum)
{
return (GPIO_ReadValue(portNum));
}
/**
* @brief The same with GPIO_IntCmd()
*/
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
{
GPIO_IntCmd(portNum, bitValue, edgeState);
}
/**
* @brief The same with GPIO_GetIntStatus()
*/
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
{
return (GPIO_GetIntStatus(portNum, pinNum, edgeState));
}
/**
* @brief The same with GPIO_ClearInt()
*/
void FIO_ClearInt(uint8_t portNum, uint32_t bitValue)
{
GPIO_ClearInt(portNum, bitValue);
}
/*********************************************************************//**
* @brief Set mask value for bits in FIO port
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] bitValue Value that contains all bits in to set,
* in range from 0 to 0xFFFFFFFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0: not mask.
* - 1: mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue)
{
LPC_GPIO_TypeDef *pFIO = GPIO_GetPointer(portNum);
if(pFIO != NULL)
{
// Mask
if (maskValue)
{
pFIO->MASK |= bitValue;
}
// Un-mask
else
{
pFIO->MASK &= ~bitValue;
}
}
}
/* FIO halfword accessible ------------------------------------------------------------- */
/*********************************************************************//**
* @brief Set direction for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set direction,
* in range from 0 to 0xFFFF.
* @param[in] dir Direction value, should be:
* - 0: Input.
* - 1: Output.
* @return None
*
* Note: All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Output direction
if (dir)
{
// Upper
if(halfwordNum)
{
pFIO->FIODIRU |= bitValue;
}
// lower
else
{
pFIO->FIODIRL |= bitValue;
}
}
// Input direction
else
{
// Upper
if(halfwordNum)
{
pFIO->FIODIRU &= ~bitValue;
}
// lower
else
{
pFIO->FIODIRL &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set mask value for bits in FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set,
* in range from 0 to 0xFFFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0: not mask.
* - 1: mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Mask
if (maskValue)
{
// Upper
if(halfwordNum)
{
pFIO->FIOMASKU |= bitValue;
}
// lower
else
{
pFIO->FIOMASKL |= bitValue;
}
}
// Un-mask
else
{
// Upper
if(halfwordNum)
{
pFIO->FIOMASKU &= ~bitValue;
}
// lower
else
{
pFIO->FIOMASKL &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set bits for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to set,
* in range from 0 to 0xFFFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
pFIO->FIOSETU = bitValue;
}
// lower
else
{
pFIO->FIOSETL = bitValue;
}
}
}
/*********************************************************************//**
* @brief Clear bits for FIO port in halfword accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @param[in] bitValue Value that contains all bits in to clear,
* in range from 0 to 0xFFFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
pFIO->FIOCLRU = bitValue;
}
// lower
else
{
pFIO->FIOCLRL = bitValue;
}
}
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* in halfword accessible style.
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
* @return Current value of FIO port pin of specified halfword.
* Note: Return value contain state of each port pin (bit) on that FIO regardless
* its direction is input or output.
**********************************************************************/
uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum)
{
GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
if(pFIO != NULL)
{
// Upper
if(halfwordNum)
{
return (pFIO->FIOPINU);
}
// lower
else
{
return (pFIO->FIOPINL);
}
}
return (0);
}
/* FIO Byte accessible ------------------------------------------------------------ */
/*********************************************************************//**
* @brief Set direction for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set direction,
* in range from 0 to 0xFF.
* @param[in] dir Direction value, should be:
* - 0: Input.
* - 1: Output.
* @return None
*
* Note: All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if(pFIO != NULL)
{
// Output direction
if (dir)
{
if (byteNum <= 3)
{
pFIO->FIODIR[byteNum] |= bitValue;
}
}
// Input direction
else
{
if (byteNum <= 3)
{
pFIO->FIODIR[byteNum] &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set mask value for bits in FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set mask,
* in range from 0 to 0xFF.
* @param[in] maskValue Mask value contains state value for each bit:
* - 0: not mask.
* - 1: mask.
* @return None
*
* Note:
* - All remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
* - After executing this function, in mask register, value '0' on each bit
* enables an access to the corresponding physical pin via a read or write access,
* while value '1' on bit (masked) that corresponding pin will not be changed
* with write access and if read, will not be reflected in the updated pin.
**********************************************************************/
void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if(pFIO != NULL)
{
// Mask
if (maskValue)
{
if (byteNum <= 3)
{
pFIO->FIOMASK[byteNum] |= bitValue;
}
}
// Un-mask
else {
if (byteNum <= 3)
{
pFIO->FIOMASK[byteNum] &= ~bitValue;
}
}
}
}
/*********************************************************************//**
* @brief Set bits for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to set,
* in range from 0 to 0xFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL) {
if (byteNum <= 3)
{
pFIO->FIOSET[byteNum] = bitValue;
}
}
}
/*********************************************************************//**
* @brief Clear bits for FIO port in byte accessible style
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @param[in] bitValue Value that contains all bits in to clear,
* in range from 0 to 0xFF.
* @return None
*
* Note:
* - For all bits that has been set as input direction, this function will
* not effect.
* - For all remaining bits that are not activated in bitValue (value '0')
* will not be effected by this function.
**********************************************************************/
void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL)
{
if (byteNum <= 3)
{
pFIO->FIOCLR[byteNum] = bitValue;
}
}
}
/*********************************************************************//**
* @brief Read Current state on port pin that have input direction of GPIO
* in byte accessible style.
* @param[in] portNum Port number, in range from 0 to 4
* @param[in] byteNum Byte part number, should be in range from 0 to 3
* @return Current value of FIO port pin of specified byte part.
* Note: Return value contain state of each port pin (bit) on that FIO regardless
* its direction is input or output.
**********************************************************************/
uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum)
{
GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
if (pFIO != NULL)
{
if (byteNum <= 3)
{
return (pFIO->FIOPIN[byteNum]);
}
}
return (0);
}
/**
* @}
*/
#endif /* _GPIO */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_i2s.c 2011-06-02
*//**
* @file lpc_i2s.c
* @brief Contains all functions support for I2S firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup I2S
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _I2S
/* Includes ------------------------------------------------------------------- */
#include "lpc_i2s.h"
#include "lpc_clkpwr.h"
/* definitions ---------------------------------------------------------- */
#define I2S_IS_ENABLED(x) ((x)? ENABLE:DISABLE)
/* Private Functions ---------------------------------------------------------- */
static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
/********************************************************************//**
* @brief Get I2S wordwidth value
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is the I2S mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return The wordwidth value, should be: 8,16 or 32
*********************************************************************/
static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
uint8_t value;
if (TRMode == I2S_TX_MODE) {
value = (I2Sx->DAO) & 0x03; /* get wordwidth bit */
} else {
value = (I2Sx->DAI) & 0x03; /* get wordwidth bit */
}
switch (value) {
case I2S_WORDWIDTH_8:
return 8;
case I2S_WORDWIDTH_16:
return 16;
default:
return 32;
}
}
/********************************************************************//**
* @brief Get I2S channel value
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is the I2S mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return The channel value, should be: 1(mono) or 2(stereo)
*********************************************************************/
static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
uint8_t value;
if (TRMode == I2S_TX_MODE) {
value = ((I2Sx->DAO) & 0x04)>>2; /* get bit[2] */
} else {
value = ((I2Sx->DAI) & 0x04)>>2; /* get bit[2] */
}
if(value == I2S_MONO) return 1;
return 2;
}
/* End of Private Functions --------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup I2S_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initialize I2S
* - Turn on power and clock
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_Init(LPC_I2S_TypeDef *I2Sx) {
// Turn on power and clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, ENABLE);
LPC_I2S->DAI = LPC_I2S->DAO = 0x00;
}
/********************************************************************//**
* @brief Configuration I2S, setting:
* - master/slave mode
* - wordwidth value
* - channel mode
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @param[in] ConfigStruct pointer to I2S_CFG_Type structure
* which will be initialized.
* @return none
*********************************************************************/
void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct)
{
uint32_t bps, config;
/* Setup clock */
bps = (ConfigStruct->wordwidth +1)*8;
/* Calculate audio config */
config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 |
(ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth);
if(TRMode == I2S_RX_MODE){
LPC_I2S->DAI = config;
}else{
LPC_I2S->DAO = config;
}
}
/********************************************************************//**
* @brief DeInitial both I2S transmit or receive
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_DeInit(LPC_I2S_TypeDef *I2Sx) {
// Turn off power and clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, DISABLE);
}
/********************************************************************//**
* @brief Get I2S Buffer Level
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode Transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return current level of Transmit/Receive Buffer
*********************************************************************/
uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode)
{
if(TRMode == I2S_TX_MODE)
{
return ((I2Sx->STATE >> 16) & 0xFF);
}
else
{
return ((I2Sx->STATE >> 8) & 0xFF);
}
}
/********************************************************************//**
* @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @return none
*********************************************************************/
void I2S_Start(LPC_I2S_TypeDef *I2Sx)
{
//Clear STOP,RESET and MUTE bit
I2Sx->DAO &= ~I2S_DAI_RESET;
I2Sx->DAI &= ~I2S_DAI_RESET;
I2Sx->DAO &= ~I2S_DAI_STOP;
I2Sx->DAI &= ~I2S_DAI_STOP;
I2Sx->DAO &= ~I2S_DAI_MUTE;
}
/********************************************************************//**
* @brief I2S Send data
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] BufferData pointer to uint32_t is the data will be send
* @return none
*********************************************************************/
void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData)
{
I2Sx->TXFIFO = BufferData;
}
/********************************************************************//**
* @brief I2S Receive Data
* @param[in] I2Sx pointer to LPC_I2S_TypeDef
* @return received value
*********************************************************************/
uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx)
{
return (I2Sx->RXFIFO);
}
/********************************************************************//**
* @brief I2S Pause
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO |= I2S_DAO_STOP;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_STOP;
}
}
/********************************************************************//**
* @brief I2S Mute
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO |= I2S_DAO_MUTE;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_MUTE;
}
}
/********************************************************************//**
* @brief I2S Stop
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
if (TRMode == I2S_TX_MODE) //Transmit mode
{
I2Sx->DAO &= ~I2S_DAO_MUTE;
I2Sx->DAO |= I2S_DAO_STOP;
I2Sx->DAO |= I2S_DAO_RESET;
} else //Receive mode
{
I2Sx->DAI |= I2S_DAI_STOP;
I2Sx->DAI |= I2S_DAI_RESET;
}
}
/********************************************************************//**
* @brief Set frequency for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] Freq is the frequency for I2S will be set. It can range
* from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz)
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return Status: ERROR or SUCCESS
*********************************************************************/
Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) {
uint32_t cclk;
uint8_t channel, wordwidth;
uint32_t x, y;
uint64_t divider;
uint16_t dif;
uint16_t x_divide, y_divide;
uint16_t err, ErrorOptimal = 0xFFFF;
uint32_t N;
//get cclk
cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU);
if(TRMode == I2S_TX_MODE)
{
channel = i2s_GetChannel(I2Sx,I2S_TX_MODE);
wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE);
}
else
{
channel = i2s_GetChannel(I2Sx,I2S_RX_MODE);
wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE);
}
/* Calculate X and Y divider
* The MCLK rate for the I2S transmitter is determined by the value
* in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE
* setting depends on the desired audio sample rate desired, the format
* (stereo/mono) used, and the data size.
* The formula is:
* I2S_MCLK = CCLK * (X/Y) / 2
* We have:
* I2S_MCLK = Freq * channel*wordwidth * (I2Sx->TXBITRATE+1);
* So: (X/Y) = (Freq * channel*wordwidth * (I2Sx->TXBITRATE+1))/CCLK*2
* We use a loop function to chose the most suitable X,Y value
*/
/* divider is a fixed point number with 16 fractional bits */
divider = (((uint64_t)Freq *channel*wordwidth * 2)<<16) / cclk;
/* find N that make x/y <= 1 -> divider <= 2^16 */
for(N=64;N>0;N--){
if((divider*N) < (1<<16)) break;
}
if(N == 0) return ERROR;
divider *= N;
for (y = 255; y > 0; y--) {
x = y * divider;
if(x & (0xFF000000)) continue;
dif = x & 0xFFFF;
if(dif>0x8000) err = 0x10000-dif;
else err = dif;
if (err == 0)
{
y_divide = y;
break;
}
else if (err < ErrorOptimal)
{
ErrorOptimal = err;
y_divide = y;
}
}
x_divide = ((uint64_t)y_divide * Freq *(channel*wordwidth)* N * 2)/cclk;
if(x_divide >= 256) x_divide = 0xFF;
if(x_divide == 0) x_divide = 1;
if (TRMode == I2S_TX_MODE)// Transmitter
{
I2Sx->TXBITRATE = N-1;
I2Sx->TXRATE = y_divide | (x_divide << 8);
} else //Receiver
{
I2Sx->RXBITRATE = N-1;
I2Sx->TXRATE = y_divide | (x_divide << 8);
}
return SUCCESS;
}
/********************************************************************//**
* @brief I2S set bitrate
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] bitrate value will be set
* bitrate value should be in range: 0 .. 63
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode)
{
if(TRMode == I2S_TX_MODE)
{
I2Sx->TXBITRATE = bitrate;
}
else
{
I2Sx->RXBITRATE = bitrate;
}
}
/********************************************************************//**
* @brief Configuration operating mode for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to
* configure
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig,
uint8_t TRMode)
{
if (TRMode == I2S_TX_MODE) {
I2Sx->TXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
I2Sx->TXMODE |= 0x02;
}
if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
I2Sx->TXMODE |= (1 << 2);
}
if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
I2Sx->TXMODE |= (1 << 3);
}
} else {
I2Sx->RXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
I2Sx->RXMODE |= 0x02;
}
if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
I2Sx->RXMODE |= (1 << 2);
}
if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
I2Sx->RXMODE |= (1 << 3);
}
}
}
/********************************************************************//**
* @brief Configure DMA operation for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return none
*********************************************************************/
void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig,
uint8_t TRMode)
{
if (TRMode == I2S_RX_MODE) {
if (DMAConfig->DMAIndex == I2S_DMA_1) {
LPC_I2S->DMA1 = (DMAConfig->depth) << 8;
} else {
LPC_I2S->DMA2 = (DMAConfig->depth) << 8;
}
} else {
if (DMAConfig->DMAIndex == I2S_DMA_1) {
LPC_I2S->DMA1 = (DMAConfig->depth) << 16;
} else {
LPC_I2S->DMA2 = (DMAConfig->depth) << 16;
}
}
}
/********************************************************************//**
* @brief Enable/Disable DMA operation for I2S
* @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S
* @param[in] DMAIndex chose what DMA is used, should be:
* - I2S_DMA_1 = 0: DMA1
* - I2S_DMA_2 = 1: DMA2
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @param[in] NewState is new state of DMA operation, should be:
* - ENABLE
* - DISABLE
* @return none
*********************************************************************/
void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex, uint8_t TRMode,
FunctionalState NewState)
{
if (TRMode == I2S_RX_MODE) {
if (DMAIndex == I2S_DMA_1) {
if (NewState == ENABLE)
I2Sx->DMA1 |= 0x01;
else
I2Sx->DMA1 &= ~0x01;
} else {
if (NewState == ENABLE)
I2Sx->DMA2 |= 0x01;
else
I2Sx->DMA2 &= ~0x01;
}
} else {
if (DMAIndex == I2S_DMA_1) {
if (NewState == ENABLE)
I2Sx->DMA1 |= 0x02;
else
I2Sx->DMA1 &= ~0x02;
} else {
if (NewState == ENABLE)
I2Sx->DMA2 |= 0x02;
else
I2Sx->DMA2 &= ~0x02;
}
}
}
/********************************************************************//**
* @brief Configure IRQ for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @param[in] level is the FIFO level that triggers IRQ request
* @return none
*********************************************************************/
void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level) {
if (TRMode == I2S_RX_MODE) {
I2Sx->IRQ |= (level << 8);
} else {
I2Sx->IRQ |= (level << 16);
}
}
/********************************************************************//**
* @brief Enable/Disable IRQ for I2S
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @param[in] NewState is new state of DMA operation, should be:
* - ENABLE
* - DISABLE
* @return none
*********************************************************************/
void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, FunctionalState NewState) {
if (TRMode == I2S_RX_MODE) {
if (NewState == ENABLE)
I2Sx->IRQ |= 0x01;
else
I2Sx->IRQ &= ~0x01;
//Enable DMA
} else {
if (NewState == ENABLE)
I2Sx->IRQ |= 0x02;
else
I2Sx->IRQ &= ~0x02;
}
}
/********************************************************************//**
* @brief Get I2S interrupt status
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return FunctionState should be:
* - ENABLE: interrupt is enable
* - DISABLE: interrupt is disable
*********************************************************************/
FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
{
if(TRMode == I2S_TX_MODE)
return I2S_IS_ENABLED((I2Sx->IRQ >> 1)&0x01);
else
return I2S_IS_ENABLED((I2Sx->IRQ)&0x01);
}
/********************************************************************//**
* @brief Get I2S interrupt depth
* @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
* @param[in] TRMode is transmit/receive mode, should be:
* - I2S_TX_MODE = 0: transmit mode
* - I2S_RX_MODE = 1: receive mode
* @return depth of FIFO level on which to create an irq request
*********************************************************************/
uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
{
if(TRMode == I2S_TX_MODE)
return (((I2Sx->IRQ)>>16)&0xFF);
else
return (((I2Sx->IRQ)>>8)&0xFF);
}
/**
* @}
*/
#endif /*_I2S*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_iap.c 2011-11-21
*//**
* @file lpc_iap.c
* @brief Contains all functions support for IAP on LPC
* @version 1.0
* @date 21. November. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _IAP
#include "lpc_iap.h"
#include "lpc_clkpwr.h"
// IAP Command
typedef void (*IAP)(uint32_t *cmd,uint32_t *result);
IAP iap_entry = (IAP) IAP_LOCATION;
#define IAP_Call iap_entry
/** @addtogroup IAP_Public_Functions LCD Public Function
* @ingroup IAP
* @{
*/
/*********************************************************************//**
* @brief Get Sector Number
*
* @param[in] adr Sector Address
*
* @return Sector Number.
*
**********************************************************************/
uint32_t GetSecNum (uint32_t adr)
{
uint32_t n;
n = adr >> 12; // 4kB Sector
if (n >= 0x10) {
n = 0x0E + (n >> 3); // 32kB Sector
}
return (n); // Sector Number
}
/*********************************************************************//**
* @brief Prepare sector(s) for write operation
*
* @param[in] start_sec The number of start sector
* @param[in] end_sec The number of end sector
*
* @return CMD_SUCCESS/BUSY/INVALID_SECTOR.
*
**********************************************************************/
IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec)
{
IAP_COMMAND_Type command;
command.cmd = IAP_PREPARE; // Prepare Sector for Write
command.param[0] = start_sec; // Start Sector
command.param[1] = end_sec; // End Sector
IAP_Call (&command.cmd, &command.status); // Call IAP Command
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Copy RAM to Flash
*
* @param[in] dest destination buffer (in Flash memory).
* @param[in] source source buffer (in RAM).
* @param[in] size the write size.
*
* @return CMD_SUCCESS.
* SRC_ADDR_ERROR/DST_ADDR_ERROR
* SRC_ADDR_NOT_MAPPED/DST_ADDR_NOT_MAPPED
* COUNT_ERROR/SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
* BUSY
*
**********************************************************************/
IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size)
{
uint32_t sec;
IAP_STATUS_CODE status;
IAP_COMMAND_Type command;
// Prepare sectors
sec = GetSecNum((uint32_t)dest);
status = PrepareSector(sec, sec);
if(status != CMD_SUCCESS)
return status;
// write
command.cmd = IAP_COPY_RAM2FLASH; // Copy RAM to Flash
command.param[0] = (uint32_t)dest; // Destination Flash Address
command.param[1] = (uint32_t)source; // Source RAM Address
command.param[2] = size; // Number of bytes
command.param[3] = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / 1000; // CCLK in kHz
IAP_Call (&command.cmd, &command.status); // Call IAP Command
return (IAP_STATUS_CODE)command.status; // Finished without Errors
}
/*********************************************************************//**
* @brief Erase sector(s)
*
* @param[in] start_sec The number of start sector
* @param[in] end_sec The number of end sector
*
* @return CMD_SUCCESS.
* INVALID_SECTOR
* SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
* BUSY
*
**********************************************************************/
IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec)
{
IAP_COMMAND_Type command;
IAP_STATUS_CODE status;
// Prepare sectors
status = PrepareSector(start_sec, end_sec);
if(status != CMD_SUCCESS)
return status;
// Erase sectors
command.cmd = IAP_ERASE; // Prepare Sector for Write
command.param[0] = start_sec; // Start Sector
command.param[1] = end_sec; // End Sector
command.param[2] = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / 1000; // CCLK in kHz
IAP_Call (&command.cmd, &command.status); // Call IAP Command
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Blank check sector(s)
*
* @param[in] start_sec The number of start sector
* @param[in] end_sec The number of end sector
* @param[out] first_nblank_loc The offset of the first non-blank word
* @param[out] first_nblank_val The value of the first non-blank word
*
* @return CMD_SUCCESS.
* INVALID_SECTOR
* SECTOR_NOT_BLANK
* BUSY
*
**********************************************************************/
IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
uint32_t *first_nblank_loc,
uint32_t *first_nblank_val)
{
IAP_COMMAND_Type command;
command.cmd = IAP_BLANK_CHECK; // Prepare Sector for Write
command.param[0] = start_sec; // Start Sector
command.param[1] = end_sec; // End Sector
IAP_Call (&command.cmd, &command.status); // Call IAP Command
if(command.status == SECTOR_NOT_BLANK)
{
// Update out value
if(first_nblank_loc != NULL)
*first_nblank_loc = command.result[0];
if(first_nblank_val != NULL)
*first_nblank_val = command.result[1];
}
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Read part identification number
*
* @param[out] partID Part ID
*
* @return CMD_SUCCESS
*
**********************************************************************/
IAP_STATUS_CODE ReadPartID(uint32_t *partID)
{
IAP_COMMAND_Type command;
command.cmd = IAP_READ_PART_ID;
IAP_Call (&command.cmd, &command.status); // Call IAP Command
if(command.status == CMD_SUCCESS)
{
if(partID != NULL)
*partID = command.result[0];
}
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Read boot code version. The version is interpreted as <major>.<minor>.
*
* @param[out] major The major
* @param[out] minor The minor
*
* @return CMD_SUCCESS
*
**********************************************************************/
IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor)
{
IAP_COMMAND_Type command;
command.cmd = IAP_READ_BOOT_VER;
IAP_Call (&command.cmd, &command.status); // Call IAP Command
if(command.status == CMD_SUCCESS)
{
if(major != NULL)
*major = (command.result[0] >> 8) & 0xFF;
if(minor != NULL)
*minor = (command.result[0]) & 0xFF;
}
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Read Device serial number.
*
* @param[out] uid Serial number.
*
* @return CMD_SUCCESS
*
**********************************************************************/
IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid)
{
IAP_COMMAND_Type command;
command.cmd = IAP_READ_SERIAL_NUMBER;
IAP_Call (&command.cmd, &command.status); // Call IAP Command
if(command.status == CMD_SUCCESS)
{
if(uid != NULL)
{
uint32_t i = 0;
for(i = 0; i < 4; i++)
uid[i] = command.result[i];
}
}
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief compare the memory contents at two locations.
*
* @param[in] addr1 The address of the 1st buffer (in RAM/Flash).
* @param[in] addr2 The address of the 2nd buffer (in RAM/Flash).
* @param[in] size Number of bytes to be compared; should be a multiple of 4.
*
* @return CMD_SUCCESS
* COMPARE_ERROR
* COUNT_ERROR (Byte count is not a multiple of 4)
* ADDR_ERROR
* ADDR_NOT_MAPPED
*
**********************************************************************/
IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size)
{
IAP_COMMAND_Type command;
command.cmd = IAP_COMPARE;
command.param[0] = (uint32_t)addr1;
command.param[1] = (uint32_t)addr2;
command.param[2] = size;
IAP_Call (&command.cmd, &command.status); // Call IAP Command
return (IAP_STATUS_CODE)command.status;
}
/*********************************************************************//**
* @brief Re-invoke ISP.
*
* @param[in] None.
*
* @return None.
*
**********************************************************************/
void InvokeISP(void)
{
IAP_COMMAND_Type command;
command.cmd = IAP_REINVOKE_ISP;
IAP_Call (&command.cmd, &command.status); // Call IAP Command
}
/**
* @}
*/
#endif /*_IAP*/

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/**********************************************************************
* $Id$ lpc_lcd.c 2011-10-14
*//**
* @file lpc_lcd.c
* @brief Contains all functions support for LCD firmware library
* on LPC
* @version 1.0
* @date 14. October. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _LCD
#include "lpc_clkpwr.h"
#include "lpc_pinsel.h"
#include "lpc_gpio.h"
#include "lpc_lcd.h"
uint32_t lcd_hsize = 0, lcd_vsize = 0;
uint32_t lcd_cursor_base_addr = 0;
uint32_t lcd_cursor_size = 64;
LCD_Config_Type lcd_config;
static uint8_t bits_per_pixel[] = { 1, 2, 4, 8, 16, 32, 16, 16 };
uint32_t rect[1024];
static void LCD_SetHorizontalTiming(LCD_HConfig_Type* pConfig);
static void LCD_SetVertialTiming(LCD_VConfig_Type* pConfig);
static void LCD_SetPolarity(LCD_TYPES lcd_type, LCD_POLARITY_Type* pConfig);
static void LCD_CtrlSetup(LCD_Config_Type* pConfig);
/** @addtogroup LCD_Private_Functions LCD Private Function
* @ingroup LCD
* @{
*/
/*********************************************************************//**
* @brief Init LCD. The input clock is CClk
*
* @param[in] pConfig Configuration Information
*
* @return LCD_FUNC_OK Execute successfully
* LCD_FUNC_ERR Error occurred.
*
**********************************************************************/
LCD_RET_CODE LCD_Init (LCD_Config_Type* pConfig)
{
uint8_t clkdiv;
if(pConfig == NULL)
return LCD_FUNC_ERR;
if(pConfig->big_endian_byte & !pConfig->big_endian_pixel)
return LCD_FUNC_ERR;
lcd_config = *pConfig;
// Assign pins
PINSEL_ConfigPin(0,4,7);
PINSEL_ConfigPin(0,5,7);
PINSEL_ConfigPin(0,6,7);
PINSEL_ConfigPin(0,7,7);
PINSEL_ConfigPin(0,8,7);
PINSEL_ConfigPin(0,9,7);
PINSEL_ConfigPin(1,20,7);
PINSEL_ConfigPin(1,21,7);
PINSEL_ConfigPin(1,22,7);
PINSEL_ConfigPin(1,23,7);
PINSEL_ConfigPin(1,24,7);
PINSEL_ConfigPin(1,25,7);
PINSEL_ConfigPin(1,26,7);
PINSEL_ConfigPin(1,27,7);
PINSEL_ConfigPin(1,28,7);
PINSEL_ConfigPin(1,29,7);
PINSEL_ConfigPin(2,0,7);
PINSEL_ConfigPin(2,1,7);
PINSEL_ConfigPin(2,2,7);
PINSEL_ConfigPin(2,3,7);
PINSEL_ConfigPin(2,4,7);
PINSEL_ConfigPin(2,5,7);
PINSEL_ConfigPin(2,6,7);
#ifdef CORE_M4
PINSEL_ConfigPin(0,10,7);
#else
PINSEL_ConfigPin(2,7,7);
#endif
PINSEL_ConfigPin(2,8,7);
PINSEL_ConfigPin(2,9,7);
PINSEL_ConfigPin(2,11,7);
PINSEL_ConfigPin(2,12,7);
PINSEL_ConfigPin(2,13,7);
PINSEL_ConfigPin(4,28,7);
PINSEL_ConfigPin(4,29,7);
//Turn on LCD clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
// Set clock
LPC_LCD->POL &= ~(0x01 << 5);
if( pConfig->panel_clk > 0) {
clkdiv = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU) / pConfig->panel_clk - 1;
LPC_SC->LCD_CFG = clkdiv & 0x1F;
LPC_LCD->POL |=(1<<26);
}
// init Horizontal Timing
LCD_SetHorizontalTiming(&pConfig->hConfig);
// Init Vertical Timing
LCD_SetVertialTiming(&pConfig->vConfig);
// Set Polarity
LCD_SetPolarity(pConfig->lcd_type, &pConfig->polarity);
if(NULL != pConfig->lcd_palette)
{
LCD_SetPalette(pConfig->lcd_palette);
}
// Set Base address
LCD_SetBaseAddress(LCD_PANEL_UPPER, pConfig->lcd_panel_upper);
LCD_SetBaseAddress(LCD_PANEL_LOWER, pConfig->lcd_panel_lower);
// Setup
LCD_CtrlSetup(pConfig);
return LCD_FUNC_OK;
}
/*********************************************************************//**
* @brief Horizontal Timing Setting
*
* @param[in] pConfig Configuration Information
*
* @return None.
*
**********************************************************************/
void LCD_SetHorizontalTiming(LCD_HConfig_Type* pConfig)
{
LPC_LCD->TIMH = 0; //reset TIMH before set value
LPC_LCD->TIMH |= ((pConfig->hbp - 1)& 0xFF)<<24;
LPC_LCD->TIMH |= ((pConfig->hfp - 1)& 0xFF)<<16;
LPC_LCD->TIMH |= ((pConfig->hsw - 1)& 0xFF)<<8;
LPC_LCD->TIMH |= ((pConfig->ppl/16 - 1)& 0x3F)<<2;
lcd_hsize = pConfig->ppl;
}
/*********************************************************************//**
* @brief Vertical Timing Setting
*
* @param[in] pConfig Configuration Information
*
* @return None.
*
**********************************************************************/
void LCD_SetVertialTiming(LCD_VConfig_Type* pConfig)
{
LPC_LCD->TIMV = 0; //reset TIMV value before setting
LPC_LCD->TIMV |= ((pConfig->vbp)& 0xFF)<<24;
LPC_LCD->TIMV |= ((pConfig->vfp)& 0xFF)<<16;
LPC_LCD->TIMV |= ((pConfig->vsw - 1)& 0x3F)<<10;
LPC_LCD->TIMV |= ((pConfig->lpp - 1)& 0x03FF)<<0;
lcd_vsize = pConfig->lpp;
}
/*********************************************************************//**
* @brief Polarity Setting
*
* @param[in] pConfig Configuration Information
* @param[in] lcd_type It can be:
* - LCD_STN_MONOCHROME
* - LCD_STN_COLOR
* - LCD_TFT
*
* @return None.
*
**********************************************************************/
void LCD_SetPolarity(LCD_TYPES lcd_type, LCD_POLARITY_Type* pConfig)
{
// LCDFP pin is active LOW and inactive HIGH
if(pConfig->invert_vsync)
LPC_LCD->POL |= (1<<11);
else
LPC_LCD->POL &= ~(1<<11);
// LCDLP pin is active LOW and inactive HIGH
if(pConfig->invert_hsync)
LPC_LCD->POL |= (1<<12);
else
LPC_LCD->POL &= ~(1<<12);
// data is driven out into the LCD on the falling edge
if(pConfig->invert_panel_clock)
LPC_LCD->POL |= (1<<13);
else
LPC_LCD->POL &= ~(1<<13);
// active high
if(pConfig->active_high) {
LPC_LCD->POL &= ~(1<<14);
}
else
{
LPC_LCD->POL |= (1<<14);
}
LPC_LCD->POL &= ~(0x3FF <<16);
LPC_LCD->POL |= (pConfig->cpl - 1)<<16;
if(lcd_type == LCD_STN_COLOR || lcd_type == LCD_STN_MONOCHROME)
LPC_LCD->POL |= (pConfig->acb & 0x1F) << 6;
}
/*********************************************************************//**
* @brief Set base address of frame buffer
*
* @param[in] panel identify which panel is.
* @param[in] pAddress base address of the inputted panel.
*
* @return None.
*
**********************************************************************/
void LCD_SetBaseAddress(LCD_PANEL panel, uint32_t pAddress)
{
// Frame Base Address doubleword aligned
if(panel == LCD_PANEL_UPPER)
LPC_LCD->UPBASE = pAddress & ~7UL ;
else
LPC_LCD->LPBASE = pAddress & ~7UL ;
}
/*********************************************************************//**
* @brief LCD Setup.
*
* @param[in] pConfig Configuration information.
*
* @return None.
*
**********************************************************************/
void LCD_CtrlSetup(LCD_Config_Type* pConfig)
{
// disable LCD controller
LPC_LCD->CTRL = 0;
// bpp
LPC_LCD->CTRL &= ~(0x07 <<1);
LPC_LCD->CTRL |=((pConfig->lcd_bpp & 0x07)<<1);
if(pConfig->lcd_type == LCD_TFT) {
LPC_LCD->CTRL |= (0x01 << 5); // TFT
}
else {
// Color/Mono
if(pConfig->lcd_type == LCD_STN_COLOR) {
LPC_LCD->CTRL &= ~ (0x01 << 4); // Color
}
else if (pConfig->lcd_type == LCD_STN_MONOCHROME) {
LPC_LCD->CTRL |= (0x01 << 4); // Mono
}
// STN/TFT
LPC_LCD->CTRL &= ~ (0x01 << 5); // STN
// Mono4/8
if(pConfig->lcd_mono8)
LPC_LCD->CTRL |= (0x01 << 6);
else
LPC_LCD->CTRL &= ~(0x01 << 6);
// Single/dual
if(pConfig->lcd_dual)
LPC_LCD->CTRL |= (0x01 << 7);
else
LPC_LCD->CTRL &= ~(0x01 << 7);
}
// notmal output
if(pConfig->lcd_bgr)
LPC_LCD->CTRL |= (1<<8); // BGR
else
LPC_LCD->CTRL &= ~(1<<8); // RGB
// Byte order
if(pConfig->big_endian_byte)
LPC_LCD->CTRL |= (1<<9);
else
LPC_LCD->CTRL &= ~(1<<9);
// Pixel order
if(pConfig->big_endian_pixel)
LPC_LCD->CTRL |= (1<<10);
else
LPC_LCD->CTRL &= ~(1<<10);
// disable power
LPC_LCD->CTRL &= ~(1<<11);
}
/*********************************************************************//**
* @brief Enable/disable LCD Display.
*
* @param[in] bEna 0: disable, 1: enable.
*
* @return None.
*
**********************************************************************/
void LCD_Enable (Bool bEna)
{
volatile uint32_t i;
if (bEna)
{
LPC_LCD->CTRL |= (1<<0);
for(i = LCD_PWR_ENA_DIS_DLY; i; i--);
LPC_LCD->CTRL |= (1<<11);
}
else
{
LPC_LCD->CTRL &= ~(1<<11);
for(i = LCD_PWR_ENA_DIS_DLY; i; i--);
LPC_LCD->CTRL &= ~(1<<0);
}
}
/*********************************************************************//**
* @brief Set palette.
*
* @param[in] bEna 0: disable, 1: enable.
*
* @return None.
*
**********************************************************************/
void LCD_SetPalette (const uint8_t* pPallete)
{
uint32_t i;
uint32_t size = (0x01 << bits_per_pixel[lcd_config.lcd_bpp])/2 ;
uint32_t * pDst = (uint32_t *)LPC_LCD->PAL;
uint32_t * pInput = (uint32_t*) pPallete;
for (i = 0; i < size; i++)
{
*pDst = *pInput;
pDst++;
pInput++;
}
}
/*********************************************************************//**
* @brief Get word offset for the given pixel
*
* @param[in] x x position of input pixel
* @param[in] y y position of input pixel
*
* @return Offset
*
**********************************************************************/
uint32_t LCD_GetWordOffset(uint32_t x, uint32_t y)
{
uint32_t pixel_num = x + y*lcd_hsize;
return (pixel_num * bits_per_pixel[lcd_config.lcd_bpp])/32;
}
/*********************************************************************//**
* @brief Get bit offset for the given pixel
*
* @param[in] x x position of input pixel
* @param[in] y y position of input pixel
*
* @return Offset
*
**********************************************************************/
uint32_t LCD_GetBitOffset(uint32_t x, uint32_t y)
{
uint32_t pixel_num;
uint32_t ofs;
pixel_num = x + y*lcd_hsize;
ofs = (pixel_num * bits_per_pixel[lcd_config.lcd_bpp])%32;
if(lcd_config.big_endian_pixel & lcd_config.big_endian_byte)
{
ofs = 32 - bits_per_pixel[lcd_config.lcd_bpp] - ofs;
}
else if (lcd_config.big_endian_pixel & !lcd_config.big_endian_byte)
{
if(bits_per_pixel[lcd_config.lcd_bpp] < 8)
{
ofs = (ofs/8)*8 + (8 - (ofs%8)-bits_per_pixel[lcd_config.lcd_bpp]);
}
}
return ofs;
}
/*********************************************************************//**
* @brief Copy pixel values from image buffer to frame buffer.
*
* @param[in] panel It can be:
* - LCD_PANEL_UPPER
* - LCD_PANEL_LOWER
* @param[in] pPain point to image buffer.
*
* @return None.
*
**********************************************************************/
void LCD_SetImage(LCD_PANEL panel, const uint8_t *pPain)
{
volatile uint32_t i;
uint32_t * pWordDst = NULL;
uint8_t* pByteDst = NULL;
uint32_t bytes_num;
if(panel == LCD_PANEL_UPPER)
pWordDst = (uint32_t*) LPC_LCD->UPBASE;
else
pWordDst = (uint32_t*) LPC_LCD->LPBASE;
pByteDst = (uint8_t*) pWordDst;
bytes_num = ((lcd_hsize * lcd_vsize) * bits_per_pixel[lcd_config.lcd_bpp]) /8;
if (NULL == pPain)
{
// clear display memory
for( i = 0; bytes_num > i; i++)
{
*pByteDst++ = 0;
}
}
else
{
// set display memory
for(i = 0; bytes_num > i; i++)
{
*pByteDst++ = *pPain++;
}
}
for(i = LCD_PWR_ENA_DIS_DLY; i; i--);
}
/*********************************************************************//**
* @brief Draw a pixel on the given panel.
*
* @param[in] panel It can be:
* - LCD_PANEL_UPPER
* - LCD_PANEL_LOWER
* @param[in] X_Left X position.
* @param[in] Y_Up Y position.
* @param[in] color Color which is placed to the given pixel.
*
* @return None.
*
**********************************************************************/
void LCD_PutPixel (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, LcdPixel_t color)
{
uint32_t k;
uint32_t * pWordData = NULL;
uint8_t* pByteData = NULL;
uint32_t bitOffset;
uint8_t* pByteSrc = (uint8_t*)&color;
uint8_t bpp = bits_per_pixel[lcd_config.lcd_bpp];
uint8_t bytes_per_pixel = bpp/8;
uint32_t start_bit;
if((X_Left >= lcd_hsize)||(Y_Up >= lcd_vsize))
return;
if(panel == LCD_PANEL_UPPER)
pWordData = (uint32_t*) LPC_LCD->UPBASE + LCD_GetWordOffset(X_Left,Y_Up);
else
pWordData = (uint32_t*) LPC_LCD->LPBASE + LCD_GetWordOffset(X_Left,Y_Up);
bitOffset = LCD_GetBitOffset(X_Left,Y_Up);
pByteData = (uint8_t*) pWordData;
pByteData += bitOffset/8;
start_bit = bitOffset%8;
if(bpp < 8)
{
uint8_t bit_pos = start_bit;
uint8_t bit_ofs = 0;
for(bit_ofs = 0;bit_ofs <bpp; bit_ofs++,bit_pos++)
{
*pByteData &= ~ (0x01 << bit_pos);
*pByteData |= ((*pByteSrc >> (k+bit_ofs)) & 0x01) << bit_pos;
}
}
else
{
for(k = 0; k < bytes_per_pixel; k++)
{
*(pByteData+ k) = *pByteSrc++;
}
}
}
/*********************************************************************//**
* @brief Place given image to given position.
*
* @param[in] panel It can be:
* - LCD_PANEL_UPPER
* - LCD_PANEL_LOWER
* @param[in] X_Left Start X position.
* @param[in] Y_Up Start Y position.
* @param[in] pBmp Image information.
* @param[in] Mask Mask on pixel values.
*
* @return None.
*
**********************************************************************/
void LCD_LoadPic (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up,
Bmp_t * pBmp, uint32_t Mask)
{
uint32_t i, j, k, inc;
uint32_t * pWordData = NULL;
uint8_t* pByteData = NULL;
uint32_t bitOffset;
uint8_t* pByteSrc = (uint8_t*) pBmp->pPicStream;
uint32_t X_LeftHold = X_Left;
uint8_t bpp = bits_per_pixel[lcd_config.lcd_bpp];
uint8_t bytes_per_pixel = bpp/8;
uint8_t pixels_per_byte = 8/bpp;
uint32_t hsize, vsize;
uint32_t start_bit;
if(pBmp->BytesPP == 0)
pBmp->BytesPP = bytes_per_pixel;
hsize = pBmp->H_Size;
vsize = pBmp->V_Size;
inc = (pixels_per_byte > 0) ? pixels_per_byte:1;
for(i = 0; i < vsize; i++)
{
if(panel == LCD_PANEL_UPPER)
pWordData = (uint32_t*) LPC_LCD->UPBASE + LCD_GetWordOffset(X_Left,Y_Up);
else
pWordData = (uint32_t*) LPC_LCD->LPBASE + LCD_GetWordOffset(X_Left,Y_Up);
bitOffset = LCD_GetBitOffset(X_Left,Y_Up);
pByteData = (uint8_t*) pWordData;
pByteData += bitOffset/8;
start_bit = bitOffset%8;
if(pBmp->BytesPP > 0)
pByteSrc = (uint8_t*) pBmp->pPicStream + i*hsize*pBmp->BytesPP; // storage of each line must be word alignment
else
pByteSrc = (uint8_t*) pBmp->pPicStream + (i*hsize*pBmp->BitsPP + 7)/8; // storage of each line must be word alignment
X_LeftHold = X_Left;
for(j = 0; j <= hsize; j+= inc)
{
if((X_LeftHold >= lcd_hsize) || (X_LeftHold - X_Left >= hsize))
break;
if(bpp < 8)
{
uint8_t bit_pos = start_bit;
uint8_t bit_ofs = 0;
for(k = 0; k < 8; k+= bpp)
{
for(bit_ofs = 0;bit_ofs <bpp; bit_ofs++,bit_pos++)
{
*pByteData &= ~ (0x01 << bit_pos);
*pByteData |= ((*pByteSrc >> (k+bit_ofs)) & 0x01) << bit_pos;
}
if(lcd_config.big_endian_byte && lcd_config.big_endian_pixel)
{
if(bit_pos >= bpp*2)
bit_pos -= bpp*2;
else
{
bit_pos = 8-bpp;
if((((uint32_t)pByteData)%4) == 0)
pByteData += 7; // change to next word
else
pByteData--; // change to previous byte
}
}
else if( !lcd_config.big_endian_byte && lcd_config.big_endian_pixel)
{
if(bit_pos >= bpp*2)
bit_pos -= bpp*2;
else
{
bit_pos = 8-bpp;
pByteData++; // change to next byte
}
}
else
{
if(bit_pos >= 8)
{
bit_pos = 0;
pByteData++; // change to next byte
}
}
X_LeftHold++;
if((X_LeftHold >= lcd_hsize) ||
(X_LeftHold - X_Left >= hsize))
break;
}
pByteSrc++;
continue;
}
else
{
for(k = 0; k < pBmp->BytesPP; k++)
{
*(pByteData+ k) = *pByteSrc++ ^ Mask;
}
if(lcd_config.big_endian_byte)
{
if((uint32_t)pByteData %4 > 0)
pByteData -= bytes_per_pixel;
else
pByteData += 8 - bytes_per_pixel;
}
else
pByteData+= bytes_per_pixel;
X_LeftHold++;
}
}
if(Y_Up++ >= lcd_vsize)
{
break;
}
}
}
/*********************************************************************//**
* @brief Fill a rectangle.
*
* @param[in] panel It can be:
* - LCD_PANEL_UPPER
* - LCD_PANEL_LOWER
* @param[in] startx Start X position.
* @param[in] endy End X position.
* @param[in] starty Start Y position.
* @param[in] endy End Y position.
*
* @return None.
*
**********************************************************************/
void LCD_FillRect (LCD_PANEL panel, uint32_t startx,uint32_t endx,
uint32_t starty, uint32_t endy,
LcdPixel_t color)
{
uint32_t x, xs, xe, ys, ye;
uint8_t bpp, pixels_per_word;
uint32_t word_val, mask;
uint32_t max_vsize = 0;
Bmp_t bitmap;
uint32_t hsize, vsize;
bpp = bits_per_pixel[lcd_config.lcd_bpp];
pixels_per_word = 32/bpp;
mask = 0;
for( x = 0; x < bpp; x++)
mask |= 0x01 << x;
color &= mask;
word_val = 0;
for(x = 0; x < pixels_per_word; x++)
word_val |= color << (x*bpp);
ys = (starty > endy) ? endy : starty;
ye = (starty > endy) ? starty : endy;
xs = (startx > endx) ? endx : startx;
xe = (startx > endx) ? startx : endx;
bitmap.BitsPP = bpp;
bitmap.BytesPP = bpp/8;
hsize = xe - xs + 1;
bitmap.H_Size = hsize;
vsize = ye - ys + 1;
bitmap.pPicStream = (uint8_t*)rect;
max_vsize = ((1024 * 32)/(hsize*bpp));
for( x = 0; x < 1024; x++)
{
rect[x] = word_val;
}
while(1)
{
if(max_vsize >= vsize)
{
bitmap.V_Size = vsize;
LCD_LoadPic(panel,xs,ys, &bitmap, 0);
break;
}
else {
bitmap.V_Size = max_vsize;
vsize -= bitmap.V_Size;
LCD_LoadPic(panel,xs,ys, &bitmap, 0);
ys += max_vsize;
}
}
}
/*********************************************************************//**
* @brief Configure display of cursor.
*
* @param[in] pConfig Configuration information.
*
* @return None.
*
**********************************************************************/
void LCD_Cursor_Cfg(LCD_Cursor_Config_Type* pConfig)
{
if(pConfig->size32) {
LPC_LCD->CRSR_CFG &= ~(0x01 << 0);
lcd_cursor_size = 32;
}
else {
LPC_LCD->CRSR_CFG |= (0x01 << 0);
lcd_cursor_size = 64;
}
if(pConfig->framesync)
LPC_LCD->CRSR_CFG &= ~(0x01 << 1);
else
LPC_LCD->CRSR_CFG |= (0x01 << 1);
lcd_cursor_base_addr = pConfig->baseaddress;
LPC_LCD->CRSR_PAL0 = pConfig->palette[0].Red |
pConfig->palette[0].Green << 8 |
pConfig->palette[0].Blue << 16;
LPC_LCD->CRSR_PAL1 = pConfig->palette[1].Red |
pConfig->palette[1].Green << 8 |
pConfig->palette[1].Blue << 16;
}
/*********************************************************************//**
* @brief Enable/disable cursor display.
*
* @param[in] enable 0: disable, 1: enable.
* @param[in] cursor identify which cursor image is used.
*
* @return None.
*
**********************************************************************/
void LCD_Cursor_Enable(int enable, int cursor)
{
if(enable) {
LPC_LCD->CRSR_CTRL |= (1<<0);
LPC_LCD->CRSR_CTRL |= (cursor<<4);
}
else {
LPC_LCD->CRSR_CTRL &= ~(1<<0);
}
}
/*********************************************************************//**
* @brief move the cursor to the inputted position.
*
* @param[in] x Position in x-direction.
* @param[in] y Position in y-direction.
*
* @return None.
*
**********************************************************************/
void LCD_Move_Cursor(int x, int y)
{
LPC_LCD->CRSR_CLIP = 0;
LPC_LCD->CRSR_XY = 0;
if(0 <= x)
{//no clipping
LPC_LCD->CRSR_XY |= (x & 0x3FF);
}
else
{//clip x
LPC_LCD->CRSR_CLIP |= -x;
}
if(0 <= y)
{//no clipping
LPC_LCD->CRSR_XY |= (y << 16);
}
else
{//clip y
LPC_LCD->CRSR_CLIP |= (-y << 8);
}
}
/*********************************************************************//**
* @brief Set the cursor image.
*
* @param[in] pCursor point to cursor image.
* @param[in] cursor cursor image number. It has no meaning when cursor size is 64x64
* @param[in] cursor cursor size in words.
*
* @return None.
*
**********************************************************************/
void LCD_Cursor_SetImage (const uint32_t *pCursor, int cursor, int size)
{
uint32_t i ;
uint32_t * pDst = (uint32_t *)lcd_cursor_base_addr;
if(lcd_cursor_size == 32)
pDst += cursor*GET_CURSOR_IMG_SIZE(lcd_cursor_size);
for(i = 0; i < size ; i++)
{
*pDst = *pCursor;
pDst++;
pCursor++;
}
}
/**
* @}
*/
#endif /*_LCD*/

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bsp/lpc408x/Libraries/Drivers/source/lpc_mci.c Normal file
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bsp/lpc408x/Libraries/Drivers/source/lpc_mcpwm.c Normal file
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/**********************************************************************
* $Id$ lpc_mcpwm.c 2011-06-02
*//**
* @file lpc_mcpwm.c
* @brief Contains all functions support for Motor Control PWM
* firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup MCPWM
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _MCPWM
/* Includes ------------------------------------------------------------------- */
#include "lpc_mcpwm.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup MCPWM_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initializes the MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected,
* Should be: LPC_MCPWM
* @return None
**********************************************************************/
void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx)
{
/* Turn On MCPWM PCLK */
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCMCPWM, ENABLE);
MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2);
MCPWMx->INTF_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
| MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
| MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
MCPWMx->INTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
| MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
| MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
}
/*********************************************************************//**
* @brief Configures each channel in MCPWM peripheral according to the
* specified parameters in the MCPWM_CHANNEL_CFG_Type.
* @param[in] MCPWMx Motor Control PWM peripheral selected
* should be: LPC_MCPWM
* @param[in] channelNum Channel number, should be: 0..2.
* @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM channel.
* @return None
**********************************************************************/
void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type * channelSetup)
{
if (channelNum < MCPWM_MAX_CHANNEL)
{
if (channelNum == MCPWM_CHANNEL_0)
{
MCPWMx->TC0 = channelSetup->channelTimercounterValue;
MCPWMx->LIM0 = channelSetup->channelPeriodValue;
MCPWMx->MAT0 = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_1)
{
MCPWMx->TC1 = channelSetup->channelTimercounterValue;
MCPWMx->LIM1 = channelSetup->channelPeriodValue;
MCPWMx->MAT1 = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_2)
{
MCPWMx->TC2 = channelSetup->channelTimercounterValue;
MCPWMx->LIM2 = channelSetup->channelPeriodValue;
MCPWMx->MAT2 = channelSetup->channelPulsewidthValue;
}
else
{
return;
}
if (channelSetup->channelType == MCPWM_CHANNEL_CENTER_MODE)
{
MCPWMx->CON_SET = MCPWM_CON_CENTER(channelNum);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_CENTER(channelNum);
}
if (channelSetup->channelPolarity == MCPWM_CHANNEL_PASSIVE_HI)
{
MCPWMx->CON_SET = MCPWM_CON_POLAR(channelNum);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_POLAR(channelNum);
}
if (channelSetup->channelDeadtimeEnable == ENABLE)
{
MCPWMx->CON_SET = MCPWM_CON_DTE(channelNum);
MCPWMx->DT &= ~(MCPWM_DT(channelNum, 0x3FF));
MCPWMx->DT |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue);
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_DTE(channelNum);
}
if (channelSetup->channelUpdateEnable == ENABLE)
{
MCPWMx->CON_CLR = MCPWM_CON_DISUP(channelNum);
}
else
{
MCPWMx->CON_SET = MCPWM_CON_DISUP(channelNum);
}
}
}
/*********************************************************************//**
* @brief Write to MCPWM shadow registers - Update the value for period
* and pulse width in MCPWM peripheral.
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] channelNum Channel Number, should be: 0..2.
* @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM channel.
* @return None
**********************************************************************/
void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CHANNEL_CFG_Type *channelSetup)
{
if (channelNum == MCPWM_CHANNEL_0)
{
MCPWMx->LIM0 = channelSetup->channelPeriodValue;
MCPWMx->MAT0 = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_1)
{
MCPWMx->LIM1 = channelSetup->channelPeriodValue;
MCPWMx->MAT1 = channelSetup->channelPulsewidthValue;
}
else if (channelNum == MCPWM_CHANNEL_2)
{
MCPWMx->LIM2 = channelSetup->channelPeriodValue;
MCPWMx->MAT2 = channelSetup->channelPulsewidthValue;
}
}
/*********************************************************************//**
* @brief Configures capture function in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] channelNum MCI (Motor Control Input pin) number
* Should be: 0..2
* @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM capture.
* @return
**********************************************************************/
void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
MCPWM_CAPTURE_CFG_Type *captureConfig)
{
if (channelNum < MCPWM_MAX_CHANNEL)
{
if (captureConfig->captureFalling == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
}
if (captureConfig->captureRising == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
}
if (captureConfig->timerReset == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel);
}
if (captureConfig->hnfEnable == ENABLE)
{
MCPWMx->CAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum);
}
else
{
MCPWMx->CAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum);
}
}
}
/*********************************************************************//**
* @brief Clears current captured value in specified capture channel
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] captureChannel Capture channel number, should be: 0..2
* @return None
**********************************************************************/
void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
{
MCPWMx->CAP_CLR = MCPWM_CAPCLR_CAP(captureChannel);
}
/*********************************************************************//**
* @brief Get current captured value in specified capture channel
* @param[in] MCPWMx Motor Control PWM peripheral selected,
* Should be: LPC_MCPWM
* @param[in] captureChannel Capture channel number, should be: 0..2
* @return None
**********************************************************************/
uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
{
if (captureChannel == MCPWM_CHANNEL_0)
{
return (MCPWMx->CAP0);
}
else if (captureChannel == MCPWM_CHANNEL_1)
{
return (MCPWMx->CAP1);
}
else if (captureChannel == MCPWM_CHANNEL_2)
{
return (MCPWMx->CAP2);
}
return (0);
}
/*********************************************************************//**
* @brief Configures Count control in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] channelNum Channel number, should be: 0..2
* @param[in] countMode Count mode, should be:
* - ENABLE: Enables count mode.
* - DISABLE: Disable count mode, the channel is in timer mode.
* @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure
* that contains the configuration information for the
* specified MCPWM count control.
* @return None
**********************************************************************/
void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig)
{
if (channelNum < MCPWM_MAX_CHANNEL)
{
if (countMode == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_CNTR(channelNum);
if (countConfig->countFalling == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
}
if (countConfig->countRising == ENABLE)
{
MCPWMx->CNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
}
}
else
{
MCPWMx->CNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum);
}
}
}
/*********************************************************************//**
* @brief Start MCPWM activity for each MCPWM channel
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] channel0 State of this command on channel 0:
* - ENABLE: 'Start' command will effect on channel 0
* - DISABLE: 'Start' command will not effect on channel 0
* @param[in] channel1 State of this command on channel 1:
* - ENABLE: 'Start' command will effect on channel 1
* - DISABLE: 'Start' command will not effect on channel 1
* @param[in] channel2 State of this command on channel 2:
* - ENABLE: 'Start' command will effect on channel 2
* - DISABLE: 'Start' command will not effect on channel 2
* @return None
**********************************************************************/
void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
uint32_t channel1, uint32_t channel2)
{
uint32_t regVal = 0;
regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
| (channel2 ? MCPWM_CON_RUN(2) : 0);
MCPWMx->CON_SET = regVal;
}
/*********************************************************************//**
* @brief Stop MCPWM activity for each MCPWM channel
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] channel0 State of this command on channel 0:
* - ENABLE: 'Stop' command will effect on channel 0
* - DISABLE: 'Stop' command will not effect on channel 0
* @param[in] channel1 State of this command on channel 1:
* - ENABLE: 'Stop' command will effect on channel 1
* - DISABLE: 'Stop' command will not effect on channel 1
* @param[in] channel2 State of this command on channel 2:
* - ENABLE: 'Stop' command will effect on channel 2
* - DISABLE: 'Stop' command will not effect on channel 2
* @return None
**********************************************************************/
void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
uint32_t channel1, uint32_t channel2)
{
uint32_t regVal = 0;
regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
| (channel2 ? MCPWM_CON_RUN(2) : 0);
MCPWMx->CON_CLR = regVal;
}
/*********************************************************************//**
* @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] acMode State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
**********************************************************************/
void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t acMode)
{
if (acMode)
{
MCPWMx->CON_SET = MCPWM_CON_ACMODE;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_ACMODE;
}
}
/*********************************************************************//**
* @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] dcMode State of this command, should be:
* - ENABLE.
* - DISABLE.
* @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels,
* should be:
* - ENABLE: The MCOB outputs have opposite polarity
* from the MCOA outputs.
* - DISABLE: The MCOB outputs have the same basic
* polarity as the MCOA outputs.
* @param[in] outputPattern A value contains bits that enables/disables the specified
* output pins route to the internal MCOA0 signal, should be:
- MCPWM_PATENT_A0: MCOA0 tracks internal MCOA0
- MCPWM_PATENT_B0: MCOB0 tracks internal MCOA0
- MCPWM_PATENT_A1: MCOA1 tracks internal MCOA0
- MCPWM_PATENT_B1: MCOB1 tracks internal MCOA0
- MCPWM_PATENT_A2: MCOA2 tracks internal MCOA0
- MCPWM_PATENT_B2: MCOB2 tracks internal MCOA0
* @return None
*
* Note: all these outputPatent values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
uint32_t outputInvered, uint32_t outputPattern)
{
if (dcMode)
{
MCPWMx->CON_SET = MCPWM_CON_DCMODE;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_DCMODE;
}
if (outputInvered)
{
MCPWMx->CON_SET = MCPWM_CON_INVBDC;
}
else
{
MCPWMx->CON_CLR = MCPWM_CON_INVBDC;
}
MCPWMx->CP = outputPattern;
}
/*********************************************************************//**
* @brief Configures the specified interrupt in MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT: Fast abort interrupt
* @param[in] NewState New State of this command, should be:
* - ENABLE.
* - DISABLE.
* @return None
*
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState)
{
if (NewState)
{
MCPWMx->INTEN_SET = ulIntType;
}
else
{
MCPWMx->INTEN_CLR = ulIntType;
}
}
/*********************************************************************//**
* @brief Sets/Forces the specified interrupt for MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected
* Should be LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT: Fast abort interrupt
* @return None
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
{
MCPWMx->INTF_SET = ulIntType;
}
/*********************************************************************//**
* @brief Clear the specified interrupt pending for MCPWM peripheral
* @param[in] MCPWMx Motor Control PWM peripheral selected,
* should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT: Fast abort interrupt
* @return None
* Note: all these ulIntType values above can be ORed together for using as input parameter.
**********************************************************************/
void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
{
MCPWMx->INTF_CLR = ulIntType;
}
/*********************************************************************//**
* @brief Check whether if the specified interrupt in MCPWM is set or not
* @param[in] MCPWMx Motor Control PWM peripheral selected,
* should be: LPC_MCPWM
* @param[in] ulIntType Interrupt type, should be:
* - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
* - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
* - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
* - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
* - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
* - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
* - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
* - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
* - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
* - MCPWM_INTFLAG_ABORT: Fast abort interrupt
* @return None
**********************************************************************/
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
{
return ((MCPWMx->INTF & ulIntType) ? SET : RESET);
}
/**
* @}
*/
#endif /*_MCPWM*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_nvic.c 2011-06-02
*//**
* @file lpc_nvic.c
* @brief Contains all expansion functions support for Nesting
* Vectored Interrupt Controller (NVIC) firmware library
* on LPC. The main NVIC functions are defined
* in core_cm3.h
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup NVIC
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _NVIC
/* Includes ------------------------------------------------------------------- */
#include "lpc_nvic.h"
/* Private Macros ------------------------------------------------------------- */
/** @defgroup NVIC_Private_Macros NVIC Private Macros
* @{
*/
/* Vector table offset bit mask */
#define NVIC_VTOR_MASK 0x3FFFFF80
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup NVIC_Public_Functions
* @{
*/
/*****************************************************************************//**
* @brief De-initializes the NVIC peripheral registers to their default
* reset values.
* @param None
* @return None
*
* These following NVIC peripheral registers will be de-initialized:
* - Disable Interrupt (32 IRQ interrupt sources that matched with LPC178X)
* - Clear all Pending Interrupts (32 IRQ interrupt source that matched with LPC178X)
* - Clear all Interrupt Priorities (32 IRQ interrupt source that matched with LPC178X)
*******************************************************************************/
void NVIC_DeInit(void)
{
uint8_t tmp;
/* Disable all interrupts */
NVIC->ICER[0] = 0xFFFFFFFF;
NVIC->ICER[1] = 0x00000001;
/* Clear all pending interrupts */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICPR[1] = 0x00000001;
/* Clear all interrupt priority */
for (tmp = 0; tmp < 32; tmp++) {
NVIC->IP[tmp] = 0x00;
}
}
/*****************************************************************************//**
* @brief De-initializes the SCB peripheral registers to their default
* reset values.
* @param none
* @return none
*
* These following SCB NVIC peripheral registers will be de-initialized:
* - Interrupt Control State register
* - Interrupt Vector Table Offset register
* - Application Interrupt/Reset Control register
* - System Control register
* - Configuration Control register
* - System Handlers Priority Registers
* - System Handler Control and State Register
* - Configurable Fault Status Register
* - Hard Fault Status Register
* - Debug Fault Status Register
*******************************************************************************/
void NVIC_SCBDeInit(void)
{
uint8_t tmp;
SCB->ICSR = 0x0A000000;
SCB->VTOR = 0x00000000;
SCB->AIRCR = 0x05FA0000;
SCB->SCR = 0x00000000;
SCB->CCR = 0x00000000;
for (tmp = 0; tmp < 32; tmp++) {
SCB->SHP[tmp] = 0x00;
}
SCB->SHCSR = 0x00000000;
SCB->CFSR = 0xFFFFFFFF;
SCB->HFSR = 0xFFFFFFFF;
SCB->DFSR = 0xFFFFFFFF;
}
/*****************************************************************************//**
* @brief Set Vector Table Offset value
* @param offset Offset value
* @return None
*******************************************************************************/
void NVIC_SetVTOR(uint32_t offset)
{
// SCB->VTOR = (offset & NVIC_VTOR_MASK);
SCB->VTOR = offset;
}
/**
* @}
*/
#endif /*_NVIC*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_pinsel.c 2011-06-02
*//**
* @file lpc_pinsel.c
* @brief Contains all functions support for Pin-connection block
* firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup PINSEL
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _PINSEL
/* Includes ------------------------------------------------------------------- */
#include "lpc_pinsel.h"
/* Private Functions ---------------------------------------------------------- */
/*********************************************************************//**
* @brief Get pointer to GPIO peripheral due to GPIO port
* @param[in] portnum Port Number value, should be in range from 0..3.
* @param[in] pinnum Pin number value, should be in range from 0..31
* @return Pointer to GPIO peripheral
**********************************************************************/
static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
{
uint32_t *pPIN = NULL;
pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
return pPIN;
}
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup PINSEL_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Get type of a pin.
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @return Port type:
* - PINSEL_PIN_TYPE_D
* - PINSEL_PIN_TYPE_A
* - PINSEL_PIN_TYPE_I
* - PINSEL_PIN_TYPE_W
* - PINSEL_PIN_TYPE_U
* - PINSEL_PIN_TYPE_UNKNOWN: Invalid pin
**********************************************************************/
PinSel_PinType PINSEL_GetPinType(uint8_t portnum, uint8_t pinnum)
{
PinSel_PinType Ret = PINSEL_PIN_TYPE_UNKNOWN;
switch(portnum)
{
case 0:
if((pinnum <=6)||
((pinnum >= 10)&&(pinnum <=11))||
((pinnum >= 14)&&(pinnum <=22)))
Ret = PINSEL_PIN_TYPE_D;
else if ((pinnum == 12)||(pinnum==13)||
((pinnum >= 23)&&(pinnum <=26)))
Ret = PINSEL_PIN_TYPE_A;
else if ((pinnum == 29) || (pinnum==30)|| (pinnum==31))
Ret = PINSEL_PIN_TYPE_U;
else if ((pinnum == 27) || (pinnum==28))
Ret = PINSEL_PIN_TYPE_I;
else if ((pinnum == 7) || (pinnum==8)|| (pinnum==9))
Ret = PINSEL_PIN_TYPE_W;
break;
case 1:
if(pinnum <=29)
Ret = PINSEL_PIN_TYPE_D;
else if ((pinnum == 30) || (pinnum==31))
Ret = PINSEL_PIN_TYPE_A;
break;
case 2:
case 3:
case 4:
Ret = PINSEL_PIN_TYPE_D;
break;
case 5:
if((pinnum <=1)||
(pinnum == 4))
Ret = PINSEL_PIN_TYPE_D;
else if ((pinnum == 2) || (pinnum==3))
Ret = PINSEL_PIN_TYPE_I;
break;
default:
break;
}
return Ret;
}
/*********************************************************************//**
* @brief Setup the pin selection function
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] funcnum Function number, should be range: 0..7
* - 0: Select GPIO (Default)
* - 1: Selects the 1st alternate function
* - 2: Selects the 2nd alternate function
* ...
* - 7: Selects the 7th alternate function
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
pPIN = PIN_GetPointer(portnum, pinnum);
*pPIN &= ~IOCON_FUNC_MASK;//Clear function bits
*pPIN |= funcnum&IOCON_FUNC_MASK;
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup resistor mode for pin of type D,A,W
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] modenum: Mode number, should be in range: 0..3
- PINSEL_BASICMODE_PLAINOUT: Plain output
- PINSEL_BASICMODE_PULLDOWN: Pull-down enable
- PINSEL_BASICMODE_PULLUP: Pull-up enable
- PINSEL_BASICMODE_REPEATER: Repeater mode
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if((type != PINSEL_PIN_TYPE_D )&&
(type != PINSEL_PIN_TYPE_A )&&
(type != PINSEL_PIN_TYPE_W))
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
*(uint32_t *)pPIN &= ~(IOCON_MODE_MASK);//Clear function bits
*(uint32_t *)pPIN |= (modenum << IOCON_MODE_POS)&IOCON_MODE_MASK;
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup hysteresis for pin of type D, W
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Hysteresis mode, should be:
* - ENABLE: Hysteresis enable
* - DISABLE: Hysteresis disable
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if((type != PINSEL_PIN_TYPE_D )&&
(type != PINSEL_PIN_TYPE_W))
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_HYS_ENABLE;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_HYS_ENABLE;
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup input polarity for pin of type A,I,D,W
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Invert mode, should be:
* - ENABLE: Input is inverted.
* - DISABLE: Input isn't inverted.
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetInvertInput(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if(type== PINSEL_PIN_TYPE_U)
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_INVERT_INPUT;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_INVERT_INPUT;
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup Slew rate for pin of type D,W
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Slew rate control, should be:
* - ENABLE: Output slew rate control is enable
* - DISABLE: Output slew rate control is disable
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if((type!= PINSEL_PIN_TYPE_D) &&
(type!= PINSEL_PIN_TYPE_W))
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_SLEW_ENABLE;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_SLEW_ENABLE;
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup I2CMode for only pins that provide special I2C functionality
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] I2CMode I2C mode, should be:
* - PINSEL_I2CMODE_FAST_STANDARD: Fast mode and standard I2C mode
* - PINSEL_I2CMODE_OPENDRAINIO: Open drain I/O
* - PINSEL_I2CMODE_FASTMODEPLUS: Fast Mode Plus I/O
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if(type != PINSEL_PIN_TYPE_I )
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
switch(I2CMode)
{
// Standard/Fast Mode I2C: HS = HIDRIVE = 0
case PINSEL_I2CMODE_FAST_STANDARD:
PINSEL_SetI2CFilter(portnum,pinnum,ENABLE);
*(uint32_t *)pPIN &= ~(IOCON_I2CMODE_FASTPLUS);
break;
// Non-I2C: HS = 1, HIDRIVE = 0
case PINSEL_I2CMODE_OPENDRAINIO:
PINSEL_SetI2CFilter(portnum,pinnum,DISABLE);
*(uint32_t *)pPIN &= ~(IOCON_I2CMODE_FASTPLUS);
break;
// Fast Mode Plus I2C: HS = 0, HIDRIVE =1
case PINSEL_I2CMODE_FASTMODEPLUS:
PINSEL_SetI2CFilter(portnum,pinnum,ENABLE);
*(uint32_t *)pPIN |= (IOCON_I2CMODE_FASTPLUS);
break;
default:
return PINSEL_RET_ERR;
}
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Setup Open-drain mode in pin of type D, A, W
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Open-drain mode:
* - DISABLE: Normal pin I/O mode
* - ENABLE: Open-drain enable
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if((type != PINSEL_PIN_TYPE_D ) &&
(type != PINSEL_PIN_TYPE_A ) &&
(type != PINSEL_PIN_TYPE_W ))
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_OPENDRAIN_MODE;//Clear hys bits
}
else
{
*(uint32_t *)pPIN |= IOCON_OPENDRAIN_MODE;
}
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Enable the Analog mode for each pin of Type A(default is as Digital pins)
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if(type != PINSEL_PIN_TYPE_A )
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(enable)
{
*(uint32_t *)pPIN &= ~(IOCON_DIGITIAL_MODE);
}
else
{
*(uint32_t *)pPIN |= IOCON_DIGITIAL_MODE;//Set 7th bit to one
}
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Choose the DAC mode for pin P0.26
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
// This setting is only for DAC pin (output pin)
if(!((portnum == 0) && (pinnum == 26)))
{
return PINSEL_RET_NOT_SUPPORT;
}
pPIN = PIN_GetPointer(portnum, pinnum);
if(enable)
{
*(uint32_t *)pPIN |= IOCON_DAC_ENABLE;//Set 16th bit to one
}
else
{
*(uint32_t *)pPIN &= ~IOCON_DAC_ENABLE;//Set 16th bit to one
}
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Control the 10ns glitch filter for pin of type A,W
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: The noise pulses below approximately 10ns are filtered out
- DISABLE: No input filtering is done.
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if((type != PINSEL_PIN_TYPE_A ) &&
(type != PINSEL_PIN_TYPE_W ))
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(enable)
{
*(uint32_t *)pPIN &= ~(IOCON_10ns_FILTER_DISABLE);//Clear 8th bit to 0
}
else
{
*(uint32_t *)pPIN |= (IOCON_10ns_FILTER_DISABLE);//Set 8th bit to one
}
return PINSEL_RET_OK;
}
/*********************************************************************//**
* @brief Control the 50ns glitch filter for I2C pins (type I)
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: The noise pulses below approximately 10ns are filtered out
- DISABLE: No input filtering is done.
* @return PINSEL Return Code
* - PINSEL_RET_INVALID_PIN
* - PINSEL_RET_NOT_SUPPORT
* - PINSEL_RET_OK
**********************************************************************/
PINSEL_RET_CODE PINSEL_SetI2CFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
PinSel_PinType type = PINSEL_GetPinType(portnum,pinnum);
if(type == PINSEL_PIN_TYPE_UNKNOWN)
return PINSEL_RET_INVALID_PIN;
if(type != PINSEL_PIN_TYPE_I)
return PINSEL_RET_NOT_SUPPORT;
pPIN = PIN_GetPointer(portnum, pinnum);
if(enable)
{
*(uint32_t *)pPIN &= ~(IOCON_HS_MASK);//Clear 8th bit to 0
}
else
{
*(uint32_t *)pPIN |= (IOCON_I2C_FILTER_DISABLE);//Set 8th bit to one
}
return PINSEL_RET_OK;
}
/**
* @}
*/
#endif /*_PINSEL*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_pwm.c 2011-06-02
*//**
* @file lpc_pwm.c
* @brief Contains all functions support for PWM firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup PWM
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _PWM
/* Includes ------------------------------------------------------------------- */
#include "lpc_pwm.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup PWM_Public_Functions
* @{
*/
static LPC_PWM_TypeDef* PWM_GetPointer (uint8_t pwmId);
/*********************************************************************//**
* @brief Setting CAN baud rate (bps)
* @param[in] canId point to LPC_CAN_TypeDef object, should be:
* - LPC_CAN1: CAN1 peripheral
* - LPC_CAN2: CAN2 peripheral
* @return The pointer to CAN peripheral that's expected to use
***********************************************************************/
static LPC_PWM_TypeDef* PWM_GetPointer (uint8_t pwmId)
{
LPC_PWM_TypeDef* pPwm;
switch (pwmId)
{
case PWM_0:
pPwm = LPC_PWM0;
break;
case PWM_1:
pPwm = LPC_PWM1;
break;
default:
pPwm = NULL;
break;
}
return pPwm;
}
/*********************************************************************//**
* @brief Check whether specified interrupt flag in PWM is set or not
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] IntFlag: PWM interrupt flag, should be:
* - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0
* - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1
* - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2
* - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3
* - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4
* - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5
* - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6
* - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0
* - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1
* @return New State of PWM interrupt flag (SET or RESET)
**********************************************************************/
IntStatus PWM_GetIntStatus(uint8_t pwmId, uint32_t IntFlag)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
return ((pPwm->IR & IntFlag) ? SET : RESET);
}
/*********************************************************************//**
* @brief Clear specified PWM Interrupt pending
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] IntFlag: PWM interrupt flag, should be:
* - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0
* - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1
* - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2
* - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3
* - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4
* - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5
* - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6
* - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0
* - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1
* @return None
**********************************************************************/
void PWM_ClearIntPending(uint8_t pwmId, uint32_t IntFlag)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
pPwm->IR = IntFlag;
}
/*****************************************************************************//**
* @brief Fills each PWM_InitStruct member with its default value:
* - If PWMCounterMode = PWM_MODE_TIMER:
* + PrescaleOption = PWM_TIMER_PRESCALE_USVAL
* + PrescaleValue = 1
* - If PWMCounterMode = PWM_MODE_COUNTER:
* + CountInputSelect = PWM_COUNTER_PCAP1_0
* + CounterOption = PWM_COUNTER_RISING
* @param[in] PWMTimerCounterMode Timer or Counter mode, should be:
* - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode
* - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode
* @param[in] PWM_InitStruct Pointer to structure (PWM_TIMERCFG_Type or
* PWM_COUNTERCFG_Type) which will be initialized.
* @return None
* Note: PWM_InitStruct pointer will be assigned to corresponding structure
* (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode.
*******************************************************************************/
void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct)
{
PWM_TIMERCFG_Type *pTimeCfg;
PWM_COUNTERCFG_Type *pCounterCfg;
pTimeCfg = (PWM_TIMERCFG_Type *) PWM_InitStruct;
pCounterCfg = (PWM_COUNTERCFG_Type *) PWM_InitStruct;
if (PWMTimerCounterMode == PWM_MODE_TIMER )
{
pTimeCfg->PrescaleOption = PWM_TIMER_PRESCALE_USVAL;
pTimeCfg->PrescaleValue = 1;
}
else if (PWMTimerCounterMode == PWM_MODE_COUNTER)
{
pCounterCfg->CountInputSelect = PWM_COUNTER_PCAP1_0;
pCounterCfg->CounterOption = PWM_COUNTER_RISING;
}
}
/*********************************************************************//**
* @brief Initializes the pPwm peripheral corresponding to the specified
* parameters in the PWM_ConfigStruct.
* @param[in] pwmId The Id of the expected PWM component
*
*
* @param[in] PWMTimerCounterMode Timer or Counter mode, should be:
* - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode
* - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode
* @param[in] PWM_ConfigStruct Pointer to structure (PWM_TIMERCFG_Type or
* PWM_COUNTERCFG_Type) which will be initialized.
* @return None
* Note: PWM_ConfigStruct pointer will be assigned to corresponding structure
* (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode.
**********************************************************************/
void PWM_Init(uint8_t pwmId, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
PWM_TIMERCFG_Type *pTimeCfg;
PWM_COUNTERCFG_Type *pCounterCfg;
uint64_t clkdlycnt;
pTimeCfg = (PWM_TIMERCFG_Type *)PWM_ConfigStruct;
pCounterCfg = (PWM_COUNTERCFG_Type *)PWM_ConfigStruct;
if(pwmId == PWM_0)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM0, ENABLE);
}
else if(pwmId == PWM_1)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, ENABLE);
}
else
{
//Trap the error
while(1);
}
// Get peripheral clock of PWM1
clkdlycnt = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
// Clear all interrupts pending
pPwm->IR = 0xFF & PWM_IR_BITMASK;
pPwm->TCR = 0x00;
pPwm->CTCR = 0x00;
pPwm->MCR = 0x00;
pPwm->CCR = 0x00;
pPwm->PCR = 0x00;
pPwm->LER = 0x00;
if (PWMTimerCounterMode == PWM_MODE_TIMER)
{
/* Absolute prescale value */
if (pTimeCfg->PrescaleOption == PWM_TIMER_PRESCALE_TICKVAL)
{
pPwm->PR = pTimeCfg->PrescaleValue - 1;
}
/* uSecond prescale value */
else
{
clkdlycnt = (clkdlycnt * pTimeCfg->PrescaleValue) / 1000000;
pPwm->PR = ((uint32_t) clkdlycnt) - 1;
}
}
else if (PWMTimerCounterMode == PWM_MODE_COUNTER)
{
pPwm->CTCR |= (PWM_CTCR_MODE((uint32_t)pCounterCfg->CounterOption)) \
| (PWM_CTCR_SELECT_INPUT((uint32_t)pCounterCfg->CountInputSelect));
}
}
/*********************************************************************//**
* @brief De-initializes the PWM peripheral registers to their
* default reset values.
* @param[in] pwmId The Id of the expected PWM component
*
* @return None
**********************************************************************/
void PWM_DeInit (uint8_t pwmId)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
// Disable PWM control (timer, counter and PWM)
pPwm->TCR = 0x00;
if(pwmId == PWM_0)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM0, DISABLE);
}
else if(pwmId == PWM_1)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, DISABLE);
}
}
/*********************************************************************//**
* @brief Enable/Disable PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] NewState New State of this function, should be:
* - ENABLE: Enable PWM peripheral
* - DISABLE: Disable PWM peripheral
* @return None
**********************************************************************/
void PWM_Cmd(uint8_t pwmId, FunctionalState NewState)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
if (NewState == ENABLE)
{
pPwm->TCR |= PWM_TCR_PWM_ENABLE;
}
else
{
pPwm->TCR &= (~PWM_TCR_PWM_ENABLE) & PWM_TCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable/Disable Counter in PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] NewState New State of this function, should be:
* - ENABLE: Enable Counter in PWM peripheral
* - DISABLE: Disable Counter in PWM peripheral
* @return None
**********************************************************************/
void PWM_CounterCmd(uint8_t pwmId, FunctionalState NewState)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
if (NewState == ENABLE)
{
pPwm->TCR |= PWM_TCR_COUNTER_ENABLE;
}
else
{
pPwm->TCR &= (~PWM_TCR_COUNTER_ENABLE) & PWM_TCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Reset Counter in PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @return None
**********************************************************************/
void PWM_ResetCounter(uint8_t pwmId)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
pPwm->TCR |= PWM_TCR_COUNTER_RESET;
pPwm->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK;
}
/*********************************************************************//**
* @brief Configures match for PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] PWM_MatchConfigStruct Pointer to a PWM_MATCHCFG_Type structure
* that contains the configuration information for the
* specified PWM match function.
* @return None
**********************************************************************/
void PWM_ConfigMatch(uint8_t pwmId, PWM_MATCHCFG_Type *PWM_MatchConfigStruct)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
//interrupt on MRn
if (PWM_MatchConfigStruct->IntOnMatch == ENABLE)
{
pPwm->MCR |= PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
}
else
{
pPwm->MCR &= (~ PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
& PWM_MCR_BITMASK;
}
//reset on MRn
if (PWM_MatchConfigStruct->ResetOnMatch == ENABLE)
{
pPwm->MCR |= PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
}
else
{
pPwm->MCR &= (~ PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
& PWM_MCR_BITMASK;
}
//stop on MRn
if (PWM_MatchConfigStruct->StopOnMatch == ENABLE)
{
pPwm->MCR |= PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
}
else
{
pPwm->MCR &= (~ PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
& PWM_MCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Configures capture input for PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] PWM_CaptureConfigStruct Pointer to a PWM_CAPTURECFG_Type structure
* that contains the configuration information for the
* specified PWM capture input function.
* @return None
**********************************************************************/
void PWM_ConfigCapture(uint8_t pwmId, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
if (PWM_CaptureConfigStruct->RisingEdge == ENABLE)
{
pPwm->CCR |= PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel);
}
else
{
pPwm->CCR &= (~ PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel)) \
& PWM_CCR_BITMASK;
}
if (PWM_CaptureConfigStruct->FallingEdge == ENABLE)
{
pPwm->CCR |= PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel);
}
else
{
pPwm->CCR &= (~ PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel)) \
& PWM_CCR_BITMASK;
}
if (PWM_CaptureConfigStruct->IntOnCaption == ENABLE)
{
pPwm->CCR |= PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel);
}
else
{
pPwm->CCR &= (~ PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel)) \
& PWM_CCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Read value of capture register PWM peripheral
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] CaptureChannel: capture channel number, should be in
* range 0 to 1
* @return Value of capture register
**********************************************************************/
uint32_t PWM_GetCaptureValue(uint8_t pwmId, uint8_t CaptureChannel)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
switch (CaptureChannel)
{
case 0:
return pPwm->CR0;
case 1:
return pPwm->CR1;
default:
return (0);
}
}
/********************************************************************//**
* @brief Update value for each PWM channel with update type option
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] MatchChannel Match channel
* @param[in] MatchValue Match value
* @param[in] UpdateType Type of Update, should be:
* - PWM_MATCH_UPDATE_NOW: The update value will be updated for
* this channel immediately
* - PWM_MATCH_UPDATE_NEXT_RST: The update value will be updated for
* this channel on next reset by a PWM Match event.
* @return None
*********************************************************************/
void PWM_MatchUpdate(uint8_t pwmId, uint8_t MatchChannel,
uint32_t MatchValue, uint8_t UpdateType)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
switch (MatchChannel)
{
case 0:
pPwm->MR0 = MatchValue;
break;
case 1:
pPwm->MR1 = MatchValue;
break;
case 2:
pPwm->MR2 = MatchValue;
break;
case 3:
pPwm->MR3 = MatchValue;
break;
case 4:
pPwm->MR4 = MatchValue;
break;
case 5:
pPwm->MR5 = MatchValue;
break;
case 6:
pPwm->MR6 = MatchValue;
break;
}
// Write Latch register
pPwm->LER |= PWM_LER_EN_MATCHn_LATCH(MatchChannel);
// In case of update now
if (UpdateType == PWM_MATCH_UPDATE_NOW)
{
pPwm->TCR |= PWM_TCR_COUNTER_RESET;
pPwm->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK;
}
}
/********************************************************************//**
* @brief Configure Edge mode for each PWM channel
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] PWMChannel PWM channel, should be in range from 2 to 6
* @param[in] ModeOption PWM mode option, should be:
* - PWM_CHANNEL_SINGLE_EDGE: Single Edge mode
* - PWM_CHANNEL_DUAL_EDGE: Dual Edge mode
* @return None
* Note: PWM Channel 1 can not be selected for mode option
*********************************************************************/
void PWM_ChannelConfig(uint8_t pwmId, uint8_t PWMChannel, uint8_t ModeOption)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
// Single edge mode
if (ModeOption == PWM_CHANNEL_SINGLE_EDGE)
{
pPwm->PCR &= (~ PWM_PCR_PWMSELn(PWMChannel)) & PWM_PCR_BITMASK;
}
// Double edge mode
else if (PWM_CHANNEL_DUAL_EDGE)
{
pPwm->PCR |= PWM_PCR_PWMSELn(PWMChannel);
}
}
/********************************************************************//**
* @brief Enable/Disable PWM channel output
* @param[in] pwmId The Id of the expected PWM component
*
* @param[in] PWMChannel PWM channel, should be in range from 1 to 6
* @param[in] NewState New State of this function, should be:
* - ENABLE: Enable this PWM channel output
* - DISABLE: Disable this PWM channel output
* @return None
*********************************************************************/
void PWM_ChannelCmd(uint8_t pwmId, uint8_t PWMChannel, FunctionalState NewState)
{
LPC_PWM_TypeDef* pPwm = PWM_GetPointer(pwmId);
if (NewState == ENABLE)
{
pPwm->PCR |= PWM_PCR_PWMENAn(PWMChannel);
}
else
{
pPwm->PCR &= (~ PWM_PCR_PWMENAn(PWMChannel)) & PWM_PCR_BITMASK;
}
}
/**
* @}
*/
#endif /*_PWM*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_qei.c 2011-06-02
*//**
* @file lpc_qei.c
* @brief Contains all functions support for QEI firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup QEI
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _QEI
/* Includes ------------------------------------------------------------------- */
#include "lpc_qei.h"
#include "lpc_clkpwr.h"
/* Private Types -------------------------------------------------------------- */
/** @defgroup QEI_Private_Types QEI Private Types
* @{
*/
/**
* @brief QEI configuration union type definition
*/
typedef union {
QEI_CFG_Type bmQEIConfig;
uint32_t ulQEIConfig;
} QEI_CFGOPT_Type;
/**
* @}
*/
LPC_QEI_TypeDef* QEI_GetPointer(uint8_t qeiId);
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup QEI_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Get the point to typedef of QEI component
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
* @return None
**********************************************************************/
LPC_QEI_TypeDef* QEI_GetPointer(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = NULL;
if(qeiId == 0)
{
pQei = LPC_QEI;
}
return pQei;
}
/*********************************************************************//**
* @brief Resets value for each type of QEI value, such as velocity,
* counter, position, etc..
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulResetType QEI Reset Type, should be one of the following:
* - QEI_RESET_POS: Reset Position Counter
* - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
* - QEI_RESET_VEL: Reset Velocity
* - QEI_RESET_IDX: Reset Index Counter
* @return None
**********************************************************************/
void QEI_Reset(uint8_t qeiId, uint32_t ulResetType)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->CON = ulResetType;
}
/*********************************************************************//**
* @brief Initializes the QEI peripheral according to the specified
* parameters in the QEI_ConfigStruct.
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure
* that contains the configuration information for the
* specified QEI peripheral
* @return None
**********************************************************************/
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
/* Set up clock and power for QEI module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, ENABLE);
// Reset all remaining value in QEI peripheral
pQei->MAXPOS = 0x00;
pQei->CMPOS0 = 0x00;
pQei->CMPOS1 = 0x00;
pQei->CMPOS2 = 0x00;
pQei->INXCMP0 = 0x00;
pQei->VELCOMP = 0x00;
pQei->LOAD = 0x00;
pQei->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;
pQei->FILTERPHA = 0x00;
pQei->FILTERPHB = 0x00;
pQei->FILTERINX = 0x00;
// Disable all Interrupt
pQei->IEC = QEI_IECLR_BITMASK;
// Clear all Interrupt pending
pQei->CLR = QEI_INTCLR_BITMASK;
// Set QEI configuration value corresponding to its setting up value
pQei->CONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig;
}
/*********************************************************************//**
* @brief De-initializes the QEI peripheral registers to their
* default reset values.
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return None
**********************************************************************/
void QEI_DeInit(uint8_t qeiId)
{
/* Turn off clock and power for QEI module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, DISABLE);
}
/*****************************************************************************//**
* @brief Fills each QIE_InitStruct member with its default value:
* - DirectionInvert = QEI_DIRINV_NONE
* - SignalMode = QEI_SIGNALMODE_QUAD
* - CaptureMode = QEI_CAPMODE_4X
* - InvertIndex = QEI_INVINX_NONE
* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure
* which will be initialized.
* @return None
*******************************************************************************/
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct)
{
QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X;
QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE;
QIE_InitStruct->InvertIndex = QEI_INVINX_NONE;
QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD;
}
/*********************************************************************//**
* @brief Check whether if specified flag status is set or not
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulFlagType Status Flag Type, should be one of the following:
* - QEI_STATUS_DIR: Direction Status
* @return New Status of this status flag (SET or RESET)
**********************************************************************/
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return ((pQei->STAT & ulFlagType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Get current position value in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return Current position value of QEI peripheral
**********************************************************************/
uint32_t QEI_GetPosition(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return (pQei->POS);
}
/*********************************************************************//**
* @brief Set max position value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulMaxPos Max position value to set
* @return None
**********************************************************************/
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->MAXPOS = ulMaxPos;
}
/*********************************************************************//**
* @brief Set position compare value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] bPosCompCh Compare Position channel, should be:
* - QEI_COMPPOS_CH_0: QEI compare position channel 0
* - QEI_COMPPOS_CH_1: QEI compare position channel 1
* - QEI_COMPPOS_CH_2: QEI compare position channel 2
* @param[in] ulPosComp Compare Position value to set
* @return None
**********************************************************************/
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
uint32_t *tmp;
tmp = (uint32_t *) (&(pQei->CMPOS0) + bPosCompCh * 4);
*tmp = ulPosComp;
}
/*********************************************************************//**
* @brief Get current index counter of QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return Current value of QEI index counter
**********************************************************************/
uint32_t QEI_GetIndex(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return (pQei->INXCNT);
}
/*********************************************************************//**
* @brief Set value for index compare in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulIndexComp Compare Index Value to set
* @return None
**********************************************************************/
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->INXCMP0 = ulIndexComp;
}
/*********************************************************************//**
* @brief Set timer reload value for QEI peripheral. When the velocity timer is
* over-flow, the value that set for Timer Reload register will be loaded
* into the velocity timer for next period. The calculated velocity in RPM
* therefore will be affect by this value.
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] QEIReloadStruct QEI reload structure
* @return None
**********************************************************************/
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
uint64_t pclk;
if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL)
{
pQei->LOAD = QEIReloadStruct->ReloadValue - 1;
}
else
{
#if 1
pclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1;
pQei->LOAD = (uint32_t)pclk;
#else
ld = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
if (ld/1000000 > 0)
{
ld /= 1000000;
ld *= QEIReloadStruct->ReloadValue;
ld -= 1;
}
else
{
ld *= QEIReloadStruct->ReloadValue;
ld /= 1000000;
ld -= 1;
}
pQei->LOAD = ld;
#endif
}
}
/*********************************************************************//**
* @brief Get current timer counter in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return Current timer counter in QEI peripheral
**********************************************************************/
uint32_t QEI_GetTimer(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return (pQei->TIME);
}
/*********************************************************************//**
* @brief Get current velocity pulse counter in current time period
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return Current velocity pulse counter value
**********************************************************************/
uint32_t QEI_GetVelocity(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return (pQei->VEL);
}
/*********************************************************************//**
* @brief Get the most recently measured velocity of the QEI. When
* the Velocity timer in QEI is over-flow, the current velocity
* value will be loaded into Velocity Capture register.
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @return The most recently measured velocity value
**********************************************************************/
uint32_t QEI_GetVelocityCap(uint8_t qeiId)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return (pQei->CAP);
}
/*********************************************************************//**
* @brief Set Velocity Compare value for QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulVelComp Compare Velocity value to set
* @return None
**********************************************************************/
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->VELCOMP = ulVelComp;
}
/*********************************************************************//**
* @brief Set value of sampling count for the digital filter in
* QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulSamplingPulse Value of sampling count to set
* @return None
**********************************************************************/
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->FILTERPHA = FilterVal.PHA_FilterVal;
pQei->FILTERPHB = FilterVal.PHB_FilterVal;
pQei->FILTERINX = FilterVal.INX_FilterVal;
}
/*********************************************************************//**
* @brief Check whether if specified interrupt flag status in QEI
* peripheral is set or not
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulIntType Interrupt Flag Status type, should be:
- QEI_INTFLAG_INX_Int: index pulse was detected interrupt
- QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
- QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
- QEI_INTFLAG_DIR_Int: Change of direction interrupt
- QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
- QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
- QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
current position interrupt
- QEI_INTFLAG_REV_Int: Index compare value is equal to the current
index count interrupt
- QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
- QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
- QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
* @return New State of specified interrupt flag status (SET or RESET)
**********************************************************************/
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
return((pQei->INTSTAT & ulIntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Enable/Disable specified interrupt in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulIntType Interrupt Flag Status type, should be:
- QEI_INTFLAG_INX_Int: index pulse was detected interrupt
- QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
- QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
- QEI_INTFLAG_DIR_Int: Change of direction interrupt
- QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
- QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
- QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
current position interrupt
- QEI_INTFLAG_REV_Int: Index compare value is equal to the current
index count interrupt
- QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
- QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
- QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
* @param[in] NewState New function state, should be:
* - DISABLE
* - ENABLE
* @return None
**********************************************************************/
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
if (NewState == ENABLE)
{
pQei->IES = ulIntType;
}
else
{
pQei->IEC = ulIntType;
}
}
/*********************************************************************//**
* @brief Sets (forces) specified interrupt in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulIntType Interrupt Flag Status type, should be:
- QEI_INTFLAG_INX_Int: index pulse was detected interrupt
- QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
- QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
- QEI_INTFLAG_DIR_Int: Change of direction interrupt
- QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
- QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
- QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
current position interrupt
- QEI_INTFLAG_REV_Int: Index compare value is equal to the current
index count interrupt
- QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
- QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
- QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
* @return None
**********************************************************************/
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->SET = ulIntType;
}
/*********************************************************************//**
* @brief Clear (force) specified interrupt (pending) in QEI peripheral
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulIntType Interrupt Flag Status type, should be:
- QEI_INTFLAG_INX_Int: index pulse was detected interrupt
- QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
- QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
- QEI_INTFLAG_DIR_Int: Change of direction interrupt
- QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
- QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
- QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
current position interrupt
- QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
current position interrupt
- QEI_INTFLAG_REV_Int: Index compare value is equal to the current
index count interrupt
- QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
- QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
- QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
* @return None
**********************************************************************/
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
pQei->CLR = ulIntType;
}
/*********************************************************************//**
* @brief Calculates the actual velocity in RPM passed via velocity
* capture value and Pulse Per Round (of the encoder) value
* parameter input.
* @param[in] qeiId The Id of the expected QEI component
* It should be 0 (zero) always with LPC
*
* @param[in] ulVelCapValue Velocity capture input value that can
* be got from QEI_GetVelocityCap() function
* @param[in] ulPPR Pulse per round of encoder
* @return The actual value of velocity in RPM (Round per minute)
**********************************************************************/
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR)
{
LPC_QEI_TypeDef* pQei = QEI_GetPointer(qeiId);
uint64_t rpm, clock, Load, edges;
// Get current Clock rate for timer input
clock = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
// Get Timer load value (velocity capture period)
Load = (uint64_t)(pQei->LOAD + 1);
// Get Edge
edges = (uint64_t)((pQei->CONF & QEI_CONF_CAPMODE) ? 4 : 2);
// Calculate RPM
rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges));
return (uint32_t)(rpm);
}
/**
* @}
*/
#endif /*_QEI*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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@ -0,0 +1,998 @@
/**********************************************************************
* $Id$ lpc_rtc.c 2011-06-02
*//**
* @file lpc_rtc.c
* @brief Contains all functions support for RTC firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup RTC
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _RTC
/* Includes ------------------------------------------------------------------- */
#include "lpc_rtc.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup RTC_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initializes the RTC peripheral.
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
*********************************************************************/
void RTC_Init (LPC_RTC_TypeDef *RTCx)
{
/* Set up clock and power for RTC module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, ENABLE);
// Clear all register to be default
RTCx->ILR = 0x00;
RTCx->CCR = 0x00;
RTCx->CIIR = 0x00;
RTCx->AMR = 0xFF;
RTCx->CALIBRATION = 0x00;
}
/*********************************************************************//**
* @brief De-initializes the RTC peripheral registers to their
* default reset values.
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
**********************************************************************/
void RTC_DeInit(LPC_RTC_TypeDef *RTCx)
{
RTCx->CCR = 0x00;
// Disable power and clock for RTC module
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, DISABLE);
}
/*********************************************************************//**
* @brief Reset clock tick counter in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @return None
**********************************************************************/
void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx)
{
RTCx->CCR |= RTC_CCR_CTCRST;
RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
}
/*********************************************************************//**
* @brief Start/Stop RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] NewState New State of this function, should be:
* - ENABLE: The time counters are enabled
* - DISABLE: The time counters are disabled
* @return None
**********************************************************************/
void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
RTCx->CCR |= RTC_CCR_CLKEN;
}
else
{
RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable/Disable Counter increment interrupt for each time type
* in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] CntIncrIntType: Counter Increment Interrupt type,
* an increment of this type value below will generates
* an interrupt, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] NewState New State of this function, should be:
* - ENABLE: Counter Increment interrupt for this
* time type are enabled
* - DISABLE: Counter Increment interrupt for this
* time type are disabled
* @return None
**********************************************************************/
void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
FunctionalState NewState)
{
if (NewState == ENABLE)
{
switch (CntIncrIntType)
{
case RTC_TIMETYPE_SECOND:
RTCx->CIIR |= RTC_CIIR_IMSEC;
break;
case RTC_TIMETYPE_MINUTE:
RTCx->CIIR |= RTC_CIIR_IMMIN;
break;
case RTC_TIMETYPE_HOUR:
RTCx->CIIR |= RTC_CIIR_IMHOUR;
break;
case RTC_TIMETYPE_DAYOFWEEK:
RTCx->CIIR |= RTC_CIIR_IMDOW;
break;
case RTC_TIMETYPE_DAYOFMONTH:
RTCx->CIIR |= RTC_CIIR_IMDOM;
break;
case RTC_TIMETYPE_DAYOFYEAR:
RTCx->CIIR |= RTC_CIIR_IMDOY;
break;
case RTC_TIMETYPE_MONTH:
RTCx->CIIR |= RTC_CIIR_IMMON;
break;
case RTC_TIMETYPE_YEAR:
RTCx->CIIR |= RTC_CIIR_IMYEAR;
break;
}
}
else
{
switch (CntIncrIntType)
{
case RTC_TIMETYPE_SECOND:
RTCx->CIIR &= (~RTC_CIIR_IMSEC) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_MINUTE:
RTCx->CIIR &= (~RTC_CIIR_IMMIN) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_HOUR:
RTCx->CIIR &= (~RTC_CIIR_IMHOUR) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
RTCx->CIIR &= (~RTC_CIIR_IMDOW) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
RTCx->CIIR &= (~RTC_CIIR_IMDOM) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
RTCx->CIIR &= (~RTC_CIIR_IMDOY) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_MONTH:
RTCx->CIIR &= (~RTC_CIIR_IMMON) & RTC_CIIR_BITMASK;
break;
case RTC_TIMETYPE_YEAR:
RTCx->CIIR &= (~RTC_CIIR_IMYEAR) & RTC_CIIR_BITMASK;
break;
}
}
}
/*********************************************************************//**
* @brief Enable/Disable Alarm interrupt for each time type
* in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] AlarmTimeType: Alarm Time Interrupt type,
* an matching of this type value below with current time
* in RTC will generates an interrupt, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] NewState New State of this function, should be:
* - ENABLE: Alarm interrupt for this
* time type are enabled
* - DISABLE: Alarm interrupt for this
* time type are disabled
* @return None
**********************************************************************/
void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
FunctionalState NewState)
{
if (NewState == ENABLE)
{
switch (AlarmTimeType)
{
case RTC_TIMETYPE_SECOND:
RTCx->AMR &= (~RTC_AMR_AMRSEC) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_MINUTE:
RTCx->AMR &= (~RTC_AMR_AMRMIN) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_HOUR:
RTCx->AMR &= (~RTC_AMR_AMRHOUR) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
RTCx->AMR &= (~RTC_AMR_AMRDOW) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
RTCx->AMR &= (~RTC_AMR_AMRDOM) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
RTCx->AMR &= (~RTC_AMR_AMRDOY) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_MONTH:
RTCx->AMR &= (~RTC_AMR_AMRMON) & RTC_AMR_BITMASK;
break;
case RTC_TIMETYPE_YEAR:
RTCx->AMR &= (~RTC_AMR_AMRYEAR) & RTC_AMR_BITMASK;
break;
}
}
else
{
switch (AlarmTimeType)
{
case RTC_TIMETYPE_SECOND:
RTCx->AMR |= (RTC_AMR_AMRSEC);
break;
case RTC_TIMETYPE_MINUTE:
RTCx->AMR |= (RTC_AMR_AMRMIN);
break;
case RTC_TIMETYPE_HOUR:
RTCx->AMR |= (RTC_AMR_AMRHOUR);
break;
case RTC_TIMETYPE_DAYOFWEEK:
RTCx->AMR |= (RTC_AMR_AMRDOW);
break;
case RTC_TIMETYPE_DAYOFMONTH:
RTCx->AMR |= (RTC_AMR_AMRDOM);
break;
case RTC_TIMETYPE_DAYOFYEAR:
RTCx->AMR |= (RTC_AMR_AMRDOY);
break;
case RTC_TIMETYPE_MONTH:
RTCx->AMR |= (RTC_AMR_AMRMON);
break;
case RTC_TIMETYPE_YEAR:
RTCx->AMR |= (RTC_AMR_AMRYEAR);
break;
}
}
}
/*********************************************************************//**
* @brief Set current time value for each time type in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype: Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] TimeValue Time value to set
* @return None
**********************************************************************/
void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue)
{
switch ( Timetype)
{
case RTC_TIMETYPE_SECOND:
if(TimeValue <= RTC_SECOND_MAX)
RTCx->SEC = TimeValue & RTC_SEC_MASK;
break;
case RTC_TIMETYPE_MINUTE:
if(TimeValue <= RTC_MINUTE_MAX)
RTCx->MIN = TimeValue & RTC_MIN_MASK;
break;
case RTC_TIMETYPE_HOUR:
if(TimeValue <= RTC_HOUR_MAX)
RTCx->HOUR = TimeValue & RTC_HOUR_MASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
if(TimeValue <= RTC_DAYOFWEEK_MAX)
RTCx->DOW = TimeValue & RTC_DOW_MASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
if((TimeValue >= RTC_DAYOFMONTH_MIN)&&(TimeValue <= RTC_DAYOFMONTH_MAX))
RTCx->DOM = TimeValue & RTC_DOM_MASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
if((TimeValue >= RTC_DAYOFYEAR_MIN)&&(TimeValue <= RTC_DAYOFYEAR_MAX))
RTCx->DOY = TimeValue & RTC_DOY_MASK;
break;
case RTC_TIMETYPE_MONTH:
if((TimeValue >= RTC_MONTH_MIN)&&(TimeValue <= RTC_MONTH_MAX))
RTCx->MONTH = TimeValue & RTC_MONTH_MASK;
break;
case RTC_TIMETYPE_YEAR:
if(TimeValue <= RTC_YEAR_MAX)
RTCx->YEAR = TimeValue & RTC_YEAR_MASK;
break;
}
}
/*********************************************************************//**
* @brief Get current time value for each type time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype: Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @return Value of time according to specified time type
**********************************************************************/
uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype)
{
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
return (RTCx->SEC & RTC_SEC_MASK);
case RTC_TIMETYPE_MINUTE:
return (RTCx->MIN & RTC_MIN_MASK);
case RTC_TIMETYPE_HOUR:
return (RTCx->HOUR & RTC_HOUR_MASK);
case RTC_TIMETYPE_DAYOFWEEK:
return (RTCx->DOW & RTC_DOW_MASK);
case RTC_TIMETYPE_DAYOFMONTH:
return (RTCx->DOM & RTC_DOM_MASK);
case RTC_TIMETYPE_DAYOFYEAR:
return (RTCx->DOY & RTC_DOY_MASK);
case RTC_TIMETYPE_MONTH:
return (RTCx->MONTH & RTC_MONTH_MASK);
case RTC_TIMETYPE_YEAR:
return (RTCx->YEAR & RTC_YEAR_MASK);
default:
return (0);
}
}
/*********************************************************************//**
* @brief Set full of time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* contains time value in full.
* @return None
**********************************************************************/
void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
{
RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK;
RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK;
RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK;
RTCx->HOUR = pFullTime->HOUR & RTC_HOUR_MASK;
RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK;
RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK;
RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK;
RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Get full of time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* will be stored time in full.
* @return None
**********************************************************************/
void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
{
pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK;
pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK;
pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK;
pFullTime->HOUR = RTCx->HOUR & RTC_HOUR_MASK;
pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK;
pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK;
pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK;
pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Set alarm time value for each time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype: Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @param[in] ALValue Alarm time value to set
* @return None
**********************************************************************/
void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue)
{
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
if(ALValue <= RTC_SECOND_MAX)
RTCx->ALSEC = ALValue & RTC_SEC_MASK;
break;
case RTC_TIMETYPE_MINUTE:
if(ALValue <= RTC_MINUTE_MAX)
RTCx->ALMIN = ALValue & RTC_MIN_MASK;
break;
case RTC_TIMETYPE_HOUR:
if(ALValue <= RTC_HOUR_MAX)
RTCx->ALHOUR = ALValue & RTC_HOUR_MASK;
break;
case RTC_TIMETYPE_DAYOFWEEK:
if(ALValue <= RTC_DAYOFWEEK_MAX)
RTCx->ALDOW = ALValue & RTC_DOW_MASK;
break;
case RTC_TIMETYPE_DAYOFMONTH:
if((ALValue >= RTC_DAYOFMONTH_MIN)&&(ALValue <= RTC_DAYOFMONTH_MAX))
RTCx->ALDOM = ALValue & RTC_DOM_MASK;
break;
case RTC_TIMETYPE_DAYOFYEAR:
if((ALValue >= RTC_DAYOFYEAR_MIN)&&(ALValue <= RTC_DAYOFYEAR_MAX))
RTCx->ALDOY = ALValue & RTC_DOY_MASK;
break;
case RTC_TIMETYPE_MONTH:
if((ALValue >= RTC_MONTH_MIN)&&(ALValue <= RTC_MONTH_MAX))
RTCx->ALMON = ALValue & RTC_MONTH_MASK;
break;
case RTC_TIMETYPE_YEAR:
if(ALValue <= RTC_YEAR_MAX)
RTCx->ALYEAR = ALValue & RTC_YEAR_MASK;
break;
}
}
/*********************************************************************//**
* @brief Get alarm time value for each time type
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Timetype: Time Type, should be:
* - RTC_TIMETYPE_SECOND
* - RTC_TIMETYPE_MINUTE
* - RTC_TIMETYPE_HOUR
* - RTC_TIMETYPE_DAYOFWEEK
* - RTC_TIMETYPE_DAYOFMONTH
* - RTC_TIMETYPE_DAYOFYEAR
* - RTC_TIMETYPE_MONTH
* - RTC_TIMETYPE_YEAR
* @return Value of Alarm time according to specified time type
**********************************************************************/
uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype)
{
switch (Timetype)
{
case RTC_TIMETYPE_SECOND:
return (RTCx->ALSEC & RTC_SEC_MASK);
case RTC_TIMETYPE_MINUTE:
return (RTCx->ALMIN & RTC_MIN_MASK);
case RTC_TIMETYPE_HOUR:
return (RTCx->ALHOUR & RTC_HOUR_MASK);
case RTC_TIMETYPE_DAYOFWEEK:
return (RTCx->ALDOW & RTC_DOW_MASK);
case RTC_TIMETYPE_DAYOFMONTH:
return (RTCx->ALDOM & RTC_DOM_MASK);
case RTC_TIMETYPE_DAYOFYEAR:
return (RTCx->ALDOY & RTC_DOY_MASK);
case RTC_TIMETYPE_MONTH:
return (RTCx->ALMON & RTC_MONTH_MASK);
case RTC_TIMETYPE_YEAR:
return (RTCx->ALYEAR & RTC_YEAR_MASK);
default:
return (0);
}
}
/*********************************************************************//**
* @brief Set full of alarm time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* contains alarm time value in full.
* @return None
**********************************************************************/
void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
{
RTCx->ALDOM = pFullTime->DOM & RTC_DOM_MASK;
RTCx->ALDOW = pFullTime->DOW & RTC_DOW_MASK;
RTCx->ALDOY = pFullTime->DOY & RTC_DOY_MASK;
RTCx->ALHOUR = pFullTime->HOUR & RTC_HOUR_MASK;
RTCx->ALMIN = pFullTime->MIN & RTC_MIN_MASK;
RTCx->ALSEC = pFullTime->SEC & RTC_SEC_MASK;
RTCx->ALMON = pFullTime->MONTH & RTC_MONTH_MASK;
RTCx->ALYEAR = pFullTime->YEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Get full of alarm time in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
* will be stored alarm time in full.
* @return None
**********************************************************************/
void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
{
pFullTime->DOM = RTCx->ALDOM & RTC_DOM_MASK;
pFullTime->DOW = RTCx->ALDOW & RTC_DOW_MASK;
pFullTime->DOY = RTCx->ALDOY & RTC_DOY_MASK;
pFullTime->HOUR = RTCx->ALHOUR & RTC_HOUR_MASK;
pFullTime->MIN = RTCx->ALMIN & RTC_MIN_MASK;
pFullTime->SEC = RTCx->ALSEC & RTC_SEC_MASK;
pFullTime->MONTH = RTCx->ALMON & RTC_MONTH_MASK;
pFullTime->YEAR = RTCx->ALYEAR & RTC_YEAR_MASK;
}
/*********************************************************************//**
* @brief Check whether if specified Location interrupt in
* RTC peripheral is set or not
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] IntType Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt
* block generated an interrupt.
* - RTC_INT_ALARM: Alarm generated an
* interrupt.
* @return New state of specified Location interrupt in RTC peripheral
* (SET or RESET)
**********************************************************************/
IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType)
{
return ((RTCx->ILR & IntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Clear specified Location interrupt pending in
* RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] IntType Interrupt location type, should be:
* - RTC_INT_COUNTER_INCREASE: Clear Counter Increment
* Interrupt pending.
* - RTC_INT_ALARM: Clear alarm interrupt pending
* @return None
**********************************************************************/
void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType)
{
RTCx->ILR |= IntType;
}
/*********************************************************************//**
* @brief Enable/Disable calibration counter in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] NewState New State of this function, should be:
* - ENABLE: The calibration counter is enabled and counting
* - DISABLE: The calibration counter is disabled and reset to zero
* @return None
**********************************************************************/
void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
}
else
{
RTCx->CCR |= RTC_CCR_CCALEN;
}
}
/*********************************************************************//**
* @brief Configures Calibration in RTC peripheral
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] CalibValue Calibration value, should be in range from
* 0 to 131,072
* @param[in] CalibDir Calibration Direction, should be:
* - RTC_CALIB_DIR_FORWARD: Forward calibration
* - RTC_CALIB_DIR_BACKWARD: Backward calibration
* @return None
**********************************************************************/
void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir)
{
RTCx->CALIBRATION = ((CalibValue) & RTC_CALIBRATION_CALVAL_MASK) \
| ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
}
/*********************************************************************//**
* @brief Write value to General purpose registers
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Channel General purpose registers Channel number,
* should be in range from 0 to 4.
* @param[in] Value Value to write
* @return None
* Note: These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset.
**********************************************************************/
void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value)
{
uint32_t *preg;
preg = (uint32_t *)&RTCx->GPREG0;
preg += Channel;
*preg = Value;
}
/*********************************************************************//**
* @brief Read value from General purpose registers
* @param[in] RTCx RTC peripheral selected, should be LPC_RTC
* @param[in] Channel General purpose registers Channel number,
* should be in range from 0 to 4.
* @return Read Value
* Note: These General purpose registers can be used to store important
* information when the main power supply is off. The value in these
* registers is not affected by chip reset.
**********************************************************************/
uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel)
{
uint32_t *preg;
uint32_t value;
preg = (uint32_t *)&RTCx->GPREG0;
preg += Channel;
value = *preg;
return (value);
}
/*********************************************************************//**
* @brief Initialize an variable of type RTC_ER_CONFIG_Type.
* @param[in] pConfig The address of input variable.
* @return None
**********************************************************************/
void RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig)
{
uint32_t tmp;
if(pConfig == NULL)
return;
for(tmp = 0; tmp < RTC_ER_INPUT_CHANNEL_NUM; tmp++)
{
pConfig->InputChannel[tmp].EventOnPosEdge = FALSE;
pConfig->InputChannel[tmp].GPClear= FALSE;
pConfig->InputChannel[tmp].IntWake= FALSE;
}
pConfig->Clk = 64;
}
/*********************************************************************//**
* @brief Initialize Event Monitor/Recorder
* @param[in] pConfig Configuration
* @return SUCCESS/ERROR
* Note: The RTC Module must be intialized before initializing this module.
**********************************************************************/
Status RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig)
{
if(pConfig == NULL)
return ERROR;
if((LPC_RTC->CCR & RTC_CCR_CLKEN) == 0)
return ERROR;
/* EV0 */
if(pConfig->InputChannel[0].EventOnPosEdge)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_POS_EDGE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_POS_EDGE;
if(pConfig->InputChannel[0].IntWake)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_INTWAKE_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_INTWAKE_ENABLE;
if(pConfig->InputChannel[0].GPClear)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_GPCLEAR_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_GPCLEAR_ENABLE;
/* EV1 */
if(pConfig->InputChannel[1].EventOnPosEdge)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_POS_EDGE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_POS_EDGE;
if(pConfig->InputChannel[1].IntWake)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_INTWAKE_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_INTWAKE_ENABLE;
if(pConfig->InputChannel[1].GPClear)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_GPCLEAR_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_GPCLEAR_ENABLE;
/* EV2 */
if(pConfig->InputChannel[2].EventOnPosEdge)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_POS_EDGE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_POS_EDGE;
if(pConfig->InputChannel[2].IntWake)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_INTWAKE_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_INTWAKE_ENABLE;
if(pConfig->InputChannel[2].GPClear)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_GPCLEAR_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_GPCLEAR_ENABLE;
/* Sample Clock */
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_MODE_MASK;
switch(pConfig->Clk)
{
case 0:
LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_CLK_DISABLE;
break;
case 16:
LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_16HZ;
break;
case 64:
LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_64HZ;
break;
case 1000:
LPC_RTC->ERCONTROL |= RTC_ERCTRL_MODE_1KHZ;
break;
default:
return ERROR;
}
return SUCCESS;
}
/*********************************************************************//**
* @brief Enable/Disable a input channel for Event Monitor/Recorder
* @param[in] channel Channel Number. It should be 0~2
* @param[in]state ENABLE/DISABLE
* @return SUCCESS/ERROR
**********************************************************************/
Status RTC_ER_Cmd(uint8_t channel, FunctionalState state)
{
switch(channel)
{
case 0:
if(state)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV0_INPUT_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV0_INPUT_ENABLE;
break;
case 1:
if(state)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV1_INPUT_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV1_INPUT_ENABLE;
break;
case 2:
if(state)
LPC_RTC->ERCONTROL |= RTC_ERCTRL_EV2_INPUT_ENABLE;
else
LPC_RTC->ERCONTROL &= ~RTC_ERCTRL_EV2_INPUT_ENABLE;
break;
default:
return ERROR;
}
return SUCCESS;
}
/*********************************************************************//**
* @brief Get event count on a given channel.
* @param[in] channel Channel Number. It should be 0~2
* @return counter
**********************************************************************/
uint8_t RTC_ER_GetEventCount(uint8_t channel)
{
uint8_t count = 0;
switch(channel)
{
case 0:
count = RTC_ER_EV0_COUNTER(LPC_RTC->ERCOUNTERS);
break;
case 1:
count = RTC_ER_EV1_COUNTER(LPC_RTC->ERCOUNTERS);
break;
case 2:
count = RTC_ER_EV2_COUNTER(LPC_RTC->ERCOUNTERS);
break;
default:
break;
}
return count;
}
/*********************************************************************//**
* @brief Get Event Monirot/Recorder Status.
* @param[in] None
* @return Status. It can includes:
* RTC_ER_EVENTS_ON_EV0_FLG
* RTC_ER_EVENTS_ON_EV1_FLG
* RTC_ER_EVENTS_ON_EV2_FLG
* RTC_ER_STATUS_GP_CLEARED_FLG
* RTC_ER_STATUS_WAKEUP_REQ_PENDING
**********************************************************************/
uint32_t RTC_ER_GetStatus(void)
{
return LPC_RTC->ERSTATUS;
}
/*********************************************************************//**
* @brief Clear Event Monitor/recoder status register.
* @param[in] status Status Flag. It should be:
* RTC_ER_EVENTS_ON_EV0_FLG
* RTC_ER_EVENTS_ON_EV1_FLG
* RTC_ER_EVENTS_ON_EV2_FLG
* RTC_ER_STATUS_GP_CLEARED_FLG
* RTC_ER_STATUS_WAKEUP_REQ_PENDING
* @return None
**********************************************************************/
void RTC_ER_ClearStatus(uint32_t status)
{
LPC_RTC->ERSTATUS |= status;
}
/*********************************************************************//**
* @brief Check whether a Wakup request is pending or not.
* @param[in] None
* @return TRUE/FALSE
**********************************************************************/
Bool RTC_ER_WakupReqPending(void)
{
if(LPC_RTC->ERSTATUS & RTC_ER_STATUS_WAKEUP_REQ_PENDING)
return TRUE;
else
return FALSE;
}
/*********************************************************************//**
* @brief Check whether RTC General Purpose registed has been cleared or not.
* @param[in] None
* @return TRUE/FALSE
**********************************************************************/
Bool RTC_ER_GPCleared(void)
{
if(LPC_RTC->ERSTATUS & RTC_ER_STATUS_GP_CLEARED_FLG)
return TRUE;
else
return FALSE;
}
/*********************************************************************//**
* @brief Get the timestamp of the fist event on a given channel.
* @param[in] channel Channel number (It should be 0~2)
* @param[in] pTimeStamp point to the buffer
* @return SUCCESS/ERROR
**********************************************************************/
Status RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp)
{
if(pTimeStamp == NULL)
return ERROR;
switch(channel)
{
case 0:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV0_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP0);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP0);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP0);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP0);
break;
case 1:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV1_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP1);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP1);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP1);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP1);
break;
case 2:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV2_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERFIRSTSTAMP2);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERFIRSTSTAMP2);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERFIRSTSTAMP2);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERFIRSTSTAMP2);
break;
default:
break;
}
return SUCCESS;
}
/*********************************************************************//**
* @brief Get the timestamp of the last event on a given channel.
* @param[in] channel Channel number (It should be 0~2)
* @param[in] pTimeStamp point to the buffer
* @return SUCCESS/ERROR
**********************************************************************/
Status RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp)
{
if(pTimeStamp == NULL)
return ERROR;
switch(channel)
{
case 0:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV0_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP0);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP0);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP0);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP0);
break;
case 1:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV1_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP1);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP1);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP1);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP1);
break;
case 2:
if((LPC_RTC->ERSTATUS & (1<<RTC_ER_STATUS_EV2_BIT)) == 0)
return ERROR;
pTimeStamp->SEC = RTC_ER_TIMESTAMP_SEC(LPC_RTC->ERLASTSTAMP2);
pTimeStamp->MIN= RTC_ER_TIMESTAMP_MIN(LPC_RTC->ERLASTSTAMP2);
pTimeStamp->HOUR= RTC_ER_TIMESTAMP_HOUR(LPC_RTC->ERLASTSTAMP2);
pTimeStamp->DOY = RTC_ER_TIMESTAMP_DOY(LPC_RTC->ERLASTSTAMP2);
break;
default:
break;
}
return SUCCESS;
}
/**
* @}
*/
#endif /*_RTC*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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bsp/lpc408x/Libraries/Drivers/source/lpc_ssp.c Normal file
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@ -0,0 +1,644 @@
/**********************************************************************
* $Id$ lpc_ssp.c 2011-06-02
*//**
* @file lpc_ssp.c
* @brief Contains all functions support for SSP firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup SSP
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _SSP
/* Includes ------------------------------------------------------------------- */
#include "lpc_ssp.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SSP_Public_Functions
* @{
*/
static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock);
/*********************************************************************//**
* @brief Setup clock rate for SSP device
* @param[in] SSPx SSP peripheral definition, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] target_clock : clock of SSP (Hz)
* @return None
***********************************************************************/
static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock)
{
uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
ssp_clk = CLKPWR_GetCLK (CLKPWR_CLKTYPE_PER);
/* Find closest divider to get at or under the target frequency.
Use smallest prescale possible and rely on the divider to get
the closest target frequency */
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > target_clock)
{
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > target_clock)
{
cr0_div++;
if (cr0_div > 0xFF)
{
cr0_div = 0;
prescale += 2;
}
}
}
/* Write computed prescaler and divider back to register */
SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
SSPx->CPSR = prescale & SSP_CPSR_BITMASK;
}
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SSP_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Initializes the SSPx peripheral according to the specified
* parameters in the SSP_ConfigStruct.
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure
* that contains the configuration information for the
* specified SSP peripheral.
* @return None
*********************************************************************/
void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct)
{
uint32_t tmp;
if(SSPx == LPC_SSP0) {
/* Set up clock and power for SSP0 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, ENABLE);
} else if(SSPx == LPC_SSP1) {
/* Set up clock and power for SSP1 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, ENABLE);
} else if(SSPx == LPC_SSP2) {
/* Set up clock and power for SSP1 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP2, ENABLE);
} else {
return;
}
/* Configure SSP, interrupt is disable, LoopBack mode is disable,
* SSP is disable, Slave output is disable as default
*/
tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \
| (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit))
& SSP_CR0_BITMASK;
// write back to SSP control register
SSPx->CR0 = tmp;
tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK;
// Write back to CR1
SSPx->CR1 = tmp;
// Set clock rate for SSP peripheral
setSSPclock(SSPx, SSP_ConfigStruct->ClockRate);
}
/*********************************************************************//**
* @brief De-initializes the SSPx peripheral registers to their
* default reset values.
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @return None
**********************************************************************/
void SSP_DeInit(LPC_SSP_TypeDef* SSPx)
{
if (SSPx == LPC_SSP0){
/* Set up clock and power for SSP0 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, DISABLE);
} else if (SSPx == LPC_SSP1) {
/* Set up clock and power for SSP1 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, DISABLE);
} else if (SSPx == LPC_SSP2) {
/* Set up clock and power for SSP1 module */
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP2, DISABLE);
}
}
/*****************************************************************************//**
* @brief Get data size bit selected
* @param[in] SSPx pointer to LPC_SSP_TypeDef structure, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @return Data size, could be:
* - SSP_DATABIT_4: 4 bit transfer
* - SSP_DATABIT_5: 5 bit transfer
* ...
* - SSP_DATABIT_16: 16 bit transfer
*******************************************************************************/
uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx)
{
return (SSPx->CR0 & (0xF));
}
/*****************************************************************************//**
* @brief Fills each SSP_InitStruct member with its default value:
* - CPHA = SSP_CPHA_FIRST
* - CPOL = SSP_CPOL_HI
* - ClockRate = 1000000
* - Databit = SSP_DATABIT_8
* - Mode = SSP_MASTER_MODE
* - FrameFormat = SSP_FRAME_SSP
* @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure
* which will be initialized.
* @return None
*******************************************************************************/
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct)
{
SSP_InitStruct->CPHA = SSP_CPHA_FIRST;
SSP_InitStruct->CPOL = SSP_CPOL_HI;
SSP_InitStruct->ClockRate = 1000000;
SSP_InitStruct->Databit = SSP_DATABIT_8;
SSP_InitStruct->Mode = SSP_MASTER_MODE;
SSP_InitStruct->FrameFormat = SSP_FRAME_SPI;
}
/*********************************************************************//**
* @brief Enable or disable SSP peripheral's operation
* @param[in] SSPx SSP peripheral, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] NewState New State of SSPx peripheral's operation
* @return none
**********************************************************************/
void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
SSPx->CR1 |= SSP_CR1_SSP_EN;
}
else
{
SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable or disable Loop Back mode function in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] NewState New State of Loop Back mode, should be:
* - ENABLE: Enable this function
* - DISABLE: Disable this function
* @return None
**********************************************************************/
void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
SSPx->CR1 |= SSP_CR1_LBM_EN;
}
else
{
SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
}
/*********************************************************************//**
* @brief Enable or disable Slave Output function in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] NewState New State of Slave Output function, should be:
* - ENABLE: Slave Output in normal operation
* - DISABLE: Slave Output is disabled. This blocks
* SSP controller from driving the transmit data
* line (MISO)
* Note: This function is available when SSP peripheral in Slave mode
* @return None
**********************************************************************/
void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK;
}
else
{
SSPx->CR1 |= SSP_CR1_SO_DISABLE;
}
}
/*********************************************************************//**
* @brief Transmit a single data through SSPx peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] Data Data to transmit (must be 16 or 8-bit long,
* this depend on SSP data bit number configured)
* @return none
**********************************************************************/
void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data)
{
SSPx->DR = SSP_DR_BITMASK(Data);
}
/*********************************************************************//**
* @brief Receive a single data from SSPx peripheral
* @param[in] SSPx SSP peripheral selected, should be
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @return Data received (16-bit long)
**********************************************************************/
uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx)
{
return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR)));
}
/*********************************************************************//**
* @brief SSP Read write data function
* @param[in] SSPx Pointer to SSP peripheral, should be
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that
* contains specified information about transmit
* data configuration.
* @param[in] xfType Transfer type, should be:
* - SSP_TRANSFER_POLLING: Polling mode
* - SSP_TRANSFER_INTERRUPT: Interrupt mode
* @return Actual Data length has been transferred in polling mode.
* In interrupt mode, always return (0)
* Return (-1) if error.
* Note: This function can be used in both master and slave mode.
***********************************************************************/
int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
SSP_TRANSFER_Type xfType)
{
uint8_t *rdata8;
uint8_t *wdata8;
uint16_t *rdata16;
uint16_t *wdata16;
uint32_t stat;
uint32_t tmp;
int32_t dataword;
dataCfg->rx_cnt = 0;
dataCfg->tx_cnt = 0;
dataCfg->status = 0;
/* Clear all remaining data in RX FIFO */
while (SSPx->SR & SSP_SR_RNE){
tmp = (uint32_t) SSP_ReceiveData(SSPx);
}
// Clear status
SSPx->ICR = SSP_ICR_BITMASK;
if(SSP_GetDataSize(SSPx)>SSP_DATABIT_8)
dataword = 1;
else dataword = 0;
// Polling mode ----------------------------------------------------------------------
if (xfType == SSP_TRANSFER_POLLING){
if (dataword == 0){
rdata8 = (uint8_t *)dataCfg->rx_data;
wdata8 = (uint8_t *)dataCfg->tx_data;
} else {
rdata16 = (uint16_t *)dataCfg->rx_data;
wdata16 = (uint16_t *)dataCfg->tx_data;
}
while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){
if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){
// Write data to buffer
if(dataCfg->tx_data == NULL){
if (dataword == 0){
SSP_SendData(SSPx, 0xFF);
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, 0xFFFF);
dataCfg->tx_cnt += 2;
}
} else {
if (dataword == 0){
SSP_SendData(SSPx, *wdata8);
wdata8++;
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, *wdata16);
wdata16++;
dataCfg->tx_cnt += 2;
}
}
}
// Check overrun error
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
// save status and return
dataCfg->status = stat | SSP_STAT_ERROR;
return (-1);
}
// Check for any data available in RX FIFO
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
// Read data from SSP data
tmp = SSP_ReceiveData(SSPx);
// Store data to destination
if (dataCfg->rx_data != NULL)
{
if (dataword == 0){
*(rdata8) = (uint8_t) tmp;
rdata8++;
} else {
*(rdata16) = (uint16_t) tmp;
rdata16++;
}
}
// Increase counter
if (dataword == 0){
dataCfg->rx_cnt++;
} else {
dataCfg->rx_cnt += 2;
}
}
}
// save status
dataCfg->status = SSP_STAT_DONE;
if (dataCfg->tx_data != NULL){
return dataCfg->tx_cnt;
} else if (dataCfg->rx_data != NULL){
return dataCfg->rx_cnt;
} else {
return (0);
}
}
// Interrupt mode ----------------------------------------------------------------------
else if (xfType == SSP_TRANSFER_INTERRUPT){
while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){
// Write data to buffer
if(dataCfg->tx_data == NULL){
if (dataword == 0){
SSP_SendData(SSPx, 0xFF);
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, 0xFFFF);
dataCfg->tx_cnt += 2;
}
} else {
if (dataword == 0){
SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
dataCfg->tx_cnt++;
} else {
SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
dataCfg->tx_cnt += 2;
}
}
// Check error
if ((stat = SSPx->RIS) & SSP_RIS_ROR){
// save status and return
dataCfg->status = stat | SSP_STAT_ERROR;
return (-1);
}
// Check for any data available in RX FIFO
while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
// Read data from SSP data
tmp = SSP_ReceiveData(SSPx);
// Store data to destination
if (dataCfg->rx_data != NULL)
{
if (dataword == 0){
*(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp;
} else {
*(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp;
}
}
// Increase counter
if (dataword == 0){
dataCfg->rx_cnt++;
} else {
dataCfg->rx_cnt += 2;
}
}
}
// If there more data to sent or receive
if ((dataCfg->rx_cnt < dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){
// Enable all interrupt
SSPx->IMSC = SSP_IMSC_BITMASK;
} else {
// Save status
dataCfg->status = SSP_STAT_DONE;
}
return (0);
}
return (-1);
}
/*********************************************************************//**
* @brief Checks whether the specified SSP status flag is set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] FlagType Type of flag to check status, should be one
* of following:
* - SSP_STAT_TXFIFO_EMPTY: TX FIFO is empty
* - SSP_STAT_TXFIFO_NOTFULL: TX FIFO is not full
* - SSP_STAT_RXFIFO_NOTEMPTY: RX FIFO is not empty
* - SSP_STAT_RXFIFO_FULL: RX FIFO is full
* - SSP_STAT_BUSY: SSP peripheral is busy
* @return New State of specified SSP status flag
**********************************************************************/
FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType)
{
return ((SSPx->SR & FlagType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Enable or disable specified interrupt type in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] IntType Interrupt type in SSP peripheral, should be:
* - SSP_INTCFG_ROR: Receive Overrun interrupt
* - SSP_INTCFG_RT: Receive Time out interrupt
* - SSP_INTCFG_RX: RX FIFO is at least half full interrupt
* - SSP_INTCFG_TX: TX FIFO is at least half empty interrupt
* @param[in] NewState New State of specified interrupt type, should be:
* - ENABLE: Enable this interrupt type
* - DISABLE: Disable this interrupt type
* @return None
* Note: We can enable/disable multi-interrupt type by OR multi value
**********************************************************************/
void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState)
{
if (NewState == ENABLE)
{
SSPx->IMSC |= IntType;
}
else
{
SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK;
}
}
/*********************************************************************//**
* @brief Check whether the specified Raw interrupt status flag is
* set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] RawIntType Raw Interrupt Type, should be:
* - SSP_INTSTAT_RAW_ROR: Receive Overrun interrupt
* - SSP_INTSTAT_RAW_RT: Receive Time out interrupt
* - SSP_INTSTAT_RAW_RX: RX FIFO is at least half full interrupt
* - SSP_INTSTAT_RAW_TX: TX FIFO is at least half empty interrupt
* @return New State of specified Raw interrupt status flag in SSP peripheral
* Note: Enabling/Disabling specified interrupt in SSP peripheral does not
* effect to Raw Interrupt Status flag.
**********************************************************************/
IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType)
{
return ((SSPx->RIS & RawIntType) ? SET : RESET);
}
/*********************************************************************//**
* @brief Get Raw Interrupt Status register
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @return Raw Interrupt Status (RIS) register value
**********************************************************************/
uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx)
{
return (SSPx->RIS);
}
/*********************************************************************//**
* @brief Check whether the specified interrupt status flag is
* set or not
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] IntType Raw Interrupt Type, should be:
* - SSP_INTSTAT_ROR: Receive Overrun interrupt
* - SSP_INTSTAT_RT: Receive Time out interrupt
* - SSP_INTSTAT_RX: RX FIFO is at least half full interrupt
* - SSP_INTSTAT_TX: TX FIFO is at least half empty interrupt
* @return New State of specified interrupt status flag in SSP peripheral
* Note: Enabling/Disabling specified interrupt in SSP peripheral effects
* to Interrupt Status flag.
**********************************************************************/
IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType)
{
return ((SSPx->MIS & IntType) ? SET :RESET);
}
/*********************************************************************//**
* @brief Clear specified interrupt pending in SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] IntType Interrupt pending to clear, should be:
* - SSP_INTCLR_ROR: clears the "frame was received when
* RxFIFO was full" interrupt.
* - SSP_INTCLR_RT: clears the "Rx FIFO was not empty and
* has not been read for a timeout period" interrupt.
* @return None
**********************************************************************/
void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType)
{
SSPx->ICR = IntType;
}
/*********************************************************************//**
* @brief Enable/Disable DMA function for SSP peripheral
* @param[in] SSPx SSP peripheral selected, should be:
* - LPC_SSP0: SSP0 peripheral
* - LPC_SSP1: SSP1 peripheral
* @param[in] DMAMode Type of DMA, should be:
* - SSP_DMA_TX: DMA for the transmit FIFO
* - SSP_DMA_RX: DMA for the Receive FIFO
* @param[in] NewState New State of DMA function on SSP peripheral,
* should be:
* - ENALBE: Enable this function
* - DISABLE: Disable this function
* @return None
**********************************************************************/
void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState)
{
if (NewState == ENABLE)
{
SSPx->DMACR |= DMAMode;
}
else
{
SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK;
}
}
/**
* @}
*/
#endif /*_SSP*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_systick.c 2011-06-02
*//**
* @file lpc_systick.c
* @brief Contains all functions support for SysTick firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup SYSTICK
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _SYSTICK
/* Includes ------------------------------------------------------------------- */
#include "lpc_systick.h"
#include "lpc_clkpwr.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup SYSTICK_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Initial System Tick with using internal CPU clock source
* @param[in] time time interval(ms)
* @return None
* Note: time interval parameter should be less than:
* 1/cclk * (2^24) * 1000 (ms)
* In this case, with cclk = 96Mhz, time interval value < 174ms
**********************************************************************/
void SYSTICK_InternalInit(uint32_t time)
{
uint32_t cclk;
float maxtime;
cclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_CPU);
/* With internal CPU clock frequency for LPC178X is 'SystemCoreClock'
* And limit 24 bit for RELOAD value
* So the maximum time can be set:
* 1/SystemCoreClock * (2^24) * 1000 (ms)
*/
//check time value is available or not
maxtime = (1<<24)/(cclk / 1000) ;
if(time > maxtime)
{
//Error loop
while(1);
}
else
{
//Select CPU clock is System Tick clock source
SysTick->CTRL |= ST_CTRL_CLKSOURCE;
/* Set RELOAD value
* RELOAD = (SystemCoreClock/1000) * time - 1
* with time base is millisecond
*/
SysTick->LOAD = (cclk/1000)*time - 1;
}
}
/*********************************************************************//**
* @brief Initial System Tick with using external clock source
* @param[in] freq external clock frequency(Hz)
* @param[in] time time interval(ms)
* @return None
**********************************************************************/
void SYSTICK_ExternalInit(uint32_t freq, uint32_t time)
{
float maxtime;
/* With external clock frequency for LPC178X is 'freq'
* And limit 24 bit for RELOAD value
* So the maximum time can be set:
* 1/freq * (2^24) * 1000 (ms)
*/
//check time value is available or not
maxtime = (1<<24)/(freq / 1000) ;
if (time>maxtime)
{
//Error Loop
while(1);
}
else
{
//Select external clock is System Tick clock source
SysTick->CTRL &= ~ ST_CTRL_CLKSOURCE;
/* Set RELOAD value
* RELOAD = (freq/1000) * time - 1
* with time base is millisecond
*/
maxtime = (freq/1000)*time - 1;
SysTick->LOAD = (freq/1000)*time - 1;
}
}
/*********************************************************************//**
* @brief Enable/disable System Tick counter
* @param[in] NewState System Tick counter status, should be:
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void SYSTICK_Cmd(FunctionalState NewState)
{
if(NewState == ENABLE)
//Enable System Tick counter
SysTick->CTRL |= ST_CTRL_ENABLE;
else
//Disable System Tick counter
SysTick->CTRL &= ~ST_CTRL_ENABLE;
}
/*********************************************************************//**
* @brief Enable/disable System Tick interrupt
* @param[in] NewState System Tick interrupt status, should be:
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void SYSTICK_IntCmd(FunctionalState NewState)
{
if(NewState == ENABLE)
//Enable System Tick counter
SysTick->CTRL |= ST_CTRL_TICKINT;
else
//Disable System Tick counter
SysTick->CTRL &= ~ST_CTRL_TICKINT;
}
/*********************************************************************//**
* @brief Get current value of System Tick counter
* @param[in] None
* @return current value of System Tick counter
**********************************************************************/
uint32_t SYSTICK_GetCurrentValue(void)
{
return (SysTick->VAL);
}
/*********************************************************************//**
* @brief Clear Counter flag
* @param[in] None
* @return None
**********************************************************************/
void SYSTICK_ClearCounterFlag(void)
{
SysTick->CTRL &= ~ST_CTRL_COUNTFLAG;
}
/**
* @}
*/
#endif /*_SYSTICK*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_timer.c 2011-06-02
*//**
* @file lpc_timer.c
* @brief Contains all functions support for Timer firmware library
* on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup TIMER
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _TIM
/* Includes ------------------------------------------------------------------- */
#include "lpc_timer.h"
#include "lpc_clkpwr.h"
#include "lpc_pinsel.h"
/* Private Functions ---------------------------------------------------------- */
static uint32_t getPClock (uint32_t timernum);
static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec);
static int32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx);
/*********************************************************************//**
* @brief Get peripheral clock of each timer controller
* @param[in] timernum Timer number
* @return Peripheral clock of timer
**********************************************************************/
static uint32_t getPClock (uint32_t timernum)
{
uint32_t clkdlycnt;
clkdlycnt = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
return clkdlycnt;
}
/*********************************************************************//**
* @brief Convert a time to a timer count value
* @param[in] timernum Timer number
* @param[in] usec Time in microseconds
* @return The number of required clock ticks to give the time delay
**********************************************************************/
uint32_t converUSecToVal (uint32_t timernum, uint32_t usec)
{
uint64_t clkdlycnt;
// Get Pclock of timer
clkdlycnt = (uint64_t) getPClock(timernum);
clkdlycnt = (clkdlycnt * usec) / 1000000;
return (uint32_t) clkdlycnt;
}
/*********************************************************************//**
* @brief Convert a timer register pointer to a timer number
* @param[in] TIMx Pointer to LPC_TIM_TypeDef, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @return The timer number (0 to 3) or -1 if register pointer is bad
**********************************************************************/
int32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx)
{
int32_t tnum = -1;
if (TIMx == LPC_TIM0)
{
tnum = 0;
}
else if (TIMx == LPC_TIM1)
{
tnum = 1;
}
else if (TIMx == LPC_TIM2)
{
tnum = 2;
}
else if (TIMx == LPC_TIM3)
{
tnum = 3;
}
return tnum;
}
/* End of Private Functions ---------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup TIM_Public_Functions
* @{
*/
/*********************************************************************//**
* @brief Get Interrupt Status
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] IntFlag Interrupt type, should be:
* - TIM_MR0_INT: Interrupt for Match channel 0
* - TIM_MR1_INT: Interrupt for Match channel 1
* - TIM_MR2_INT: Interrupt for Match channel 2
* - TIM_MR3_INT: Interrupt for Match channel 3
* - TIM_CR0_INT: Interrupt for Capture channel 0
* - TIM_CR1_INT: Interrupt for Capture channel 1
* @return Flag Status for required interrupt
* - SET : interrupt
* - RESET : no interrupt
**********************************************************************/
FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
{
uint8_t temp;
temp = (TIMx->IR)& TIM_IR_CLR(IntFlag);
if (temp)
return SET;
return RESET;
}
/*********************************************************************//**
* @brief Get Capture Interrupt Status
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] IntFlag: interrupt type, should be:
* - TIM_MR0_INT: Interrupt for Match channel 0
* - TIM_MR1_INT: Interrupt for Match channel 1
* - TIM_MR2_INT: Interrupt for Match channel 2
* - TIM_MR3_INT: Interrupt for Match channel 3
* - TIM_CR0_INT: Interrupt for Capture channel 0
* - TIM_CR1_INT: Interrupt for Capture channel 1
* @return FlagStatus
* - SET : interrupt
* - RESET : no interrupt
**********************************************************************/
FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
{
uint8_t temp;
temp = (TIMx->IR) & (1<<(4+IntFlag));
if(temp)
return SET;
return RESET;
}
/*********************************************************************//**
* @brief Clear Interrupt pending
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] IntFlag: interrupt type, should be:
* - TIM_MR0_INT: Interrupt for Match channel 0
* - TIM_MR1_INT: Interrupt for Match channel 1
* - TIM_MR2_INT: Interrupt for Match channel 2
* - TIM_MR3_INT: Interrupt for Match channel 3
* - TIM_CR0_INT: Interrupt for Capture channel 0
* - TIM_CR1_INT: Interrupt for Capture channel 1
* @return None
**********************************************************************/
void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
{
TIMx->IR = TIM_IR_CLR(IntFlag);
}
/*********************************************************************//**
* @brief Clear Capture Interrupt pending
* @param[in] TIMx Timer selection, should be
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] IntFlag interrupt type, should be:
* - TIM_MR0_INT: Interrupt for Match channel 0
* - TIM_MR1_INT: Interrupt for Match channel 1
* - TIM_MR2_INT: Interrupt for Match channel 2
* - TIM_MR3_INT: Interrupt for Match channel 3
* - TIM_CR0_INT: Interrupt for Capture channel 0
* - TIM_CR1_INT: Interrupt for Capture channel 1
* @return None
**********************************************************************/
void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
{
TIMx->IR = (1<<(4+IntFlag));
}
/*********************************************************************//**
* @brief Configuration for Timer at initial time
* @param[in] TimerCounterMode timer counter mode, should be:
* - TIM_TIMER_MODE: Timer mode
* - TIM_COUNTER_RISING_MODE: Counter rising mode
* - TIM_COUNTER_FALLING_MODE: Counter falling mode
* - TIM_COUNTER_ANY_MODE:Counter on both edges
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or
* TIM_COUNTERCFG_Type
* @return None
**********************************************************************/
void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
{
if (TimerCounterMode == TIM_TIMER_MODE )
{
TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL;
pTimeCfg->PrescaleValue = 1;
}
else
{
TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0;
}
}
/*********************************************************************//**
* @brief Initial Timer/Counter device
* Set Clock frequency for Timer
* Set initial configuration for Timer
* @param[in] TIMx Timer selection, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] TimerCounterMode Timer counter mode, should be:
* - TIM_TIMER_MODE: Timer mode
* - TIM_COUNTER_RISING_MODE: Counter rising mode
* - TIM_COUNTER_FALLING_MODE: Counter falling mode
* - TIM_COUNTER_ANY_MODE:Counter on both edges
* @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type
* that contains the configuration information for the
* specified Timer peripheral.
* @return None
**********************************************************************/
void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
{
TIM_TIMERCFG_Type *pTimeCfg;
TIM_COUNTERCFG_Type *pCounterCfg;
//set power
if (TIMx== LPC_TIM0)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE);
}
else if (TIMx== LPC_TIM1)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE);
}
else if (TIMx== LPC_TIM2)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE);
}
else if (TIMx== LPC_TIM3)
{
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE);
}
TIMx->CTCR &= ~TIM_CTCR_MODE_MASK;
TIMx->CTCR |= TIM_TIMER_MODE;
TIMx->TC =0;
TIMx->PC =0;
TIMx->PR =0;
TIMx->TCR |= (1<<1); //Reset Counter
TIMx->TCR &= ~(1<<1); //release reset
if (TimerCounterMode == TIM_TIMER_MODE )
{
pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)
{
TIMx->PR = pTimeCfg->PrescaleValue -1 ;
}
else
{
TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;
}
}
else
{
pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
TIMx->CTCR &= ~TIM_CTCR_INPUT_MASK;
if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)
TIMx->CCR |= _BIT(2);
}
// Clear interrupt pending
TIMx->IR = 0xFFFFFFFF;
}
/*********************************************************************//**
* @brief Close Timer/Counter device
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @return None
**********************************************************************/
void TIM_DeInit (LPC_TIM_TypeDef *TIMx)
{
// Disable timer/counter
TIMx->TCR = 0x00;
// Disable power
if (TIMx== LPC_TIM0)
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, DISABLE);
else if (TIMx== LPC_TIM1)
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, DISABLE);
else if (TIMx== LPC_TIM2)
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE);
else if (TIMx== LPC_TIM3)
CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE);
}
/*********************************************************************//**
* @brief Start/Stop Timer/Counter device
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] NewState
* - ENABLE : set timer enable
* - DISABLE : disable timer
* @return None
**********************************************************************/
void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
TIMx->TCR |= TIM_ENABLE;
}
else
{
TIMx->TCR &= ~TIM_ENABLE;
}
}
/*********************************************************************//**
* @brief Reset Timer/Counter device,
* Make TC and PC are synchronously reset on the next
* positive edge of PCLK
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @return None
**********************************************************************/
void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx)
{
TIMx->TCR |= TIM_RESET;
TIMx->TCR &= ~TIM_RESET;
}
/*********************************************************************//**
* @brief Configuration for Match register
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type
* - MatchChannel : choose channel 0 or 1
* - IntOnMatch : if SET, interrupt will be generated when MRxx match
* the value in TC
* - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match
* the value in TC
* - ResetOnMatch : if SET, Reset on MR0 when MRxx match
* the value in TC
* -ExtMatchOutputType: Select output for external match
* + 0: Do nothing for external output pin if match
* + 1: Force external output pin to low if match
* + 2: Force external output pin to high if match
* + 3: Toggle external output pin if match
* MatchValue: Set the value to be compared with TC value
* @return None
**********************************************************************/
void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct)
{
switch(TIM_MatchConfigStruct->MatchChannel)
{
case 0:
TIMx->MR0 = TIM_MatchConfigStruct->MatchValue;
break;
case 1:
TIMx->MR1 = TIM_MatchConfigStruct->MatchValue;
break;
case 2:
TIMx->MR2 = TIM_MatchConfigStruct->MatchValue;
break;
case 3:
TIMx->MR3 = TIM_MatchConfigStruct->MatchValue;
break;
default:
//Error match value
//Error loop
while(1);
}
//interrupt on MRn
TIMx->MCR &= ~ TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel);
if (TIM_MatchConfigStruct->IntOnMatch)
TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
//reset on MRn
if (TIM_MatchConfigStruct->ResetOnMatch)
TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
//stop on MRn
if (TIM_MatchConfigStruct->StopOnMatch)
TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
// match output type
TIMx->EMR &= ~ TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel);
TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType);
}
/*********************************************************************//**
* @brief Update Match value
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] MatchChannel Match channel, should be: 0..3
* @param[in] MatchValue updated match value
* @return None
**********************************************************************/
void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue)
{
switch(MatchChannel)
{
case 0:
TIMx->MR0 = MatchValue;
break;
case 1:
TIMx->MR1 = MatchValue;
break;
case 2:
TIMx->MR2 = MatchValue;
break;
case 3:
TIMx->MR3 = MatchValue;
break;
default:
//Error Loop
while(1);
}
}
/*********************************************************************//**
* @brief Configuration for Capture register
* @param[in] TIMx Pointer to timer device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type
* - CaptureChannel: set the channel to capture data
* - RisingEdge : if SET, Capture at rising edge
* - FallingEdge : if SET, Capture at falling edge
* - IntOnCaption : if SET, Capture generate interrupt
* @return None
**********************************************************************/
void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct)
{
TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->RisingEdge)
TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->FallingEdge)
TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel);
if (TIM_CaptureConfigStruct->IntOnCaption)
TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel);
}
/*********************************************************************//**
* @brief Read value of capture register in timer/counter device
* @param[in] TIMx Pointer to timer/counter device, should be:
* - LPC_TIM0: TIMER0 peripheral
* - LPC_TIM1: TIMER1 peripheral
* - LPC_TIM2: TIMER2 peripheral
* - LPC_TIM3: TIMER3 peripheral
* @param[in] CaptureChannel: capture channel number, should be:
* - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
* - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
* @return Value of capture register
**********************************************************************/
uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel)
{
if(CaptureChannel==0)
return TIMx->CR0;
else
return TIMx->CR1;
}
/*---------------Advanced TIMER functions -----------------------------------------*/
/*********************************************************************//**
* @brief Timer wait (microseconds)
* @param[in] time number of microseconds waiting
* @return None
**********************************************************************/
void TIM_Waitus(uint32_t time)
{
TIM_MATCHCFG_Type MatchConfigStruct;
LPC_TIM0->IR = 0xFFFFFFFF;
MatchConfigStruct.MatchChannel = 0;
MatchConfigStruct.IntOnMatch = ENABLE;
MatchConfigStruct.ResetOnMatch = ENABLE;
MatchConfigStruct.StopOnMatch = ENABLE;
MatchConfigStruct.ExtMatchOutputType = 0;
MatchConfigStruct.MatchValue = time;
TIM_ConfigMatch(LPC_TIM0, &MatchConfigStruct);
TIM_Cmd(LPC_TIM0,ENABLE);
//wait until interrupt flag occur
while(!(LPC_TIM0->IR & 0x01));
TIM_ResetCounter(LPC_TIM0);
}
/*********************************************************************//**
* @brief Timer wait (milliseconds)
* @param[in] time number of millisecond waiting
* @return None
**********************************************************************/
void TIM_Waitms(uint32_t time)
{
TIM_Waitus(time * 1000);
}
/**
* @}
*/
#endif /*_TIM*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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/**********************************************************************
* $Id$ lpc_wwdt.c 2011-06-02
*//**
* @file lpc_wwdt.c
* @brief Contains all functions support for Wachtdog Timer
* firmware library on LPC
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup WWDT
* @{
*/
#ifdef __BUILD_WITH_EXAMPLE__
#include "lpc_libcfg.h"
#else
#include "lpc_libcfg_default.h"
#endif /* __BUILD_WITH_EXAMPLE__ */
#ifdef _WDT
/* Includes ------------------------------------------------------------------- */
#include "lpc_wwdt.h"
#include "lpc_clkpwr.h"
#include "lpc_pinsel.h"
/* Public Functions ----------------------------------------------------------- */
/** @addtogroup WDT_Public_Functions
* @{
*/
/********************************************************************//**
* @brief Set timeout value to Timer Constant register
* (if enable) to generate a WatchDog event if match
*
* @param[in] timeoutVal The value (counter) will write directly to
* Register w/o pre-calc
*
* @return None
*********************************************************************/
int8_t WWDT_SetTimeOutRaw(uint32_t timeoutVal)
{
int8_t retval = 0;
if(timeoutVal < WWDT_TIMEOUT_MIN)
{
timeoutVal = WWDT_TIMEOUT_MIN;
retval = WWDT_FUNC_BAD_PARAM;
}
else if (timeoutVal > WWDT_TIMEOUT_MAX)
{
timeoutVal = WWDT_TIMEOUT_MAX;
retval = WWDT_FUNC_BAD_PARAM;
}
LPC_WDT->TC = timeoutVal;
return retval;
}
/********************************************************************//**
* @brief Set WDT timeout (cal by usec) to TC register
*
* @param[in] timeout The time (usec) to generate watchdog event if
* the watchdog counter reach this value
*
* @return WWDT_FUNC_OK if success
*********************************************************************/
int8_t WWDT_SetTimeOut(uint32_t timeout)
{
return WWDT_SetTimeOutRaw(WDT_GET_FROM_USEC(timeout));
}
/*********************************************************************//**
* @brief Initial for Watchdog function by setting timeout
*
* @param[in] TimeOut time out value, should be in range:
* 2048 .. 134217728
*
* @return WWDT_FUNC_OK if success
**********************************************************************/
int8_t WWDT_Init(uint32_t TimeOut)
{
return WWDT_SetTimeOut(TimeOut);
}
/*********************************************************************//**
* @brief Configure the WatchDog by initialization all the timing
* value for register (Warning value, Window value,...)
*
* @param wdtCfg a the st_Wdt_Config type value
*
* @return None
**********************************************************************/
void WWDT_Configure(st_Wdt_Config wdtCfg)
{
WWDT_SetTimeOut(wdtCfg.wdtTmrConst);
if(wdtCfg.wdtEnable)
{
LPC_WDT->MOD |= WWDT_WDMOD_WDEN;
}
else
{
LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN;
}
if(wdtCfg.wdtReset)
{
LPC_WDT->MOD |= WWDT_WDMOD_WDRESET;
}
else
{
LPC_WDT->MOD &= ~WWDT_WDMOD_WDRESET;
}
if(wdtCfg.wdtProtect)
{
LPC_WDT->MOD |= WWDT_WDMOD_WDPROTECT;
}
else
{
LPC_WDT->MOD &= ~WWDT_WDMOD_WDPROTECT;
}
WWDT_SetWarning(wdtCfg.wdtWarningVal);
WWDT_SetWindow(wdtCfg.wdtWindowVal);
}
/*********************************************************************//**
* @brief Start WatchDog with specific Timeout
*
* @param TimeOut specific Timeout for WatchDog event
*
* @return WWDT_FUNC_OK if success
**********************************************************************/
int8_t WWDT_Start(uint32_t TimeOut)
{
int8_t retval = WWDT_FUNC_OK;
retval = WWDT_SetTimeOut(TimeOut);
WWDT_Cmd(ENABLE);
return retval;
}
/********************************************************************//**
* @brief Update WDT timeout value and feed
*
* @param[in] WarnTime time to generate watchdog warning interrupt(us)
* should be in range: 2048 .. 134217728
*
* @return None
*********************************************************************/
void WWDT_SetTimerConstant(uint32_t constVal)
{
LPC_WDT->TC = constVal;
}
/*********************************************************************//**
* @brief Enable/Disable WDT function
*
* @param[in] Mode WWDT mode that will be enabled/disabled, should be:
* - WWDT_PROTECT_MODE : protect mode
* - WWDT_RESET_MODE : reset mode
*
* @param[in] NewState new state of protection function, should be:
* - ENABLE: The watchdog reload value can be changed at any time
* - DISABLE: The watchdog reload value can be changed only after
* the counter is below the value of WDWARNINT and WDWINDOW
*
* @return None
**********************************************************************/
void WWDT_SetMode(uint8_t mode, FunctionalState NewState)
{
if (mode == WWDT_PROTECT_MODE )
{
if(NewState == ENABLE)
LPC_WDT->MOD |= WWDT_WDMOD_WDPROTECT;
else
LPC_WDT->MOD &= ~WWDT_WDMOD_WDPROTECT;
}
else if(mode == WWDT_RESET_MODE)
{
if(NewState == ENABLE)
LPC_WDT->MOD |= WWDT_WDMOD_WDRESET;
else
LPC_WDT->MOD &= ~WWDT_WDMOD_WDRESET;
}
}
/*********************************************************************//**
* @brief Enable/Disable WWDT activity
*
* @param[in] NewState To enable/disable the WatchDog
*
* @return None
**********************************************************************/
void WWDT_Enable(FunctionalState NewState)
{
if(NewState == ENABLE)
{
LPC_WDT->MOD |= WWDT_WDMOD_WDEN;
}
else
{
LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN;
}
}
/*********************************************************************//**
* @brief Enable/Disable WWDT activity. In case of Enable, it will
* do feeding WatchDog for its normal operation.
*
* @param[in] NewState To enable/disable the WatchDog
*
* @return None
**********************************************************************/
void WWDT_Cmd(FunctionalState NewState)
{
if(NewState == ENABLE)
{
LPC_WDT->MOD |= WWDT_WDMOD_WDEN;
//Load the Feed register to start using WDT
WWDT_Feed();
}
else
{
LPC_WDT->MOD &= ~WWDT_WDMOD_WDEN;
}
}
/********************************************************************//**
* @brief Set the warning value to register to generate interrupt
* (if enable) if the watchdog timer matches this value.
*
* @param[in] warnVal The value (counter) will write directly to Warning
* Register w/o pre-calc
*
* @return WWDT_FUNC_OK if success
*********************************************************************/
int8_t WWDT_SetWarningRaw(uint32_t warnVal)
{
int8_t retval = WWDT_FUNC_OK;
if(warnVal < WWDT_WARNINT_MIN)
{
warnVal = WWDT_WARNINT_MIN;
retval = WWDT_FUNC_BAD_PARAM;
}
else if (warnVal > WWDT_WARNINT_MAX)
{
warnVal = WWDT_WARNINT_MAX;
retval = WWDT_FUNC_BAD_PARAM;
}
LPC_WDT->WARNINT = warnVal;
return retval;
}
/********************************************************************//**
* @brief Update WDT warning time (cal by usec) to warning register
*
* @param[in] WarnTime The time (usec) to generate watchdog warning
* interrupt should be in range: 2048 .. 8192
*
* @return WWDT_FUNC_OK if success
*********************************************************************/
int8_t WWDT_SetWarning(uint32_t WarnTime)
{
return WWDT_SetWarningRaw(WDT_GET_FROM_USEC(WarnTime));
}
/********************************************************************//**
* @brief Update WDT Windows value (by counter) to Window Register
* of WatchDog
*
* @param[in] wndVal The value (counter) will write directly to Window
* Register w/o pre-calc
*
* @return WWDT_FUNC_OK if success
*********************************************************************/
int8_t WWDT_SetWindowRaw(uint32_t wndVal)
{
int8_t retval = WWDT_FUNC_OK;
if(wndVal < WWDT_WINDOW_MIN)
{
wndVal = WWDT_WINDOW_MIN;
retval = WWDT_FUNC_BAD_PARAM;
}
else if (wndVal > WWDT_WINDOW_MAX)
{
wndVal = WWDT_WINDOW_MAX;
retval = WWDT_FUNC_BAD_PARAM;
}
LPC_WDT->WINDOW = wndVal;
return retval;
}
/********************************************************************//**
* @brief Update WDT Windows value (by usec) to Window Register
* of WatchDog
*
* @param[in] WindowedTime Expected time (usec) to set watchdog window event
*
* @return WWDT_FUNC_OK if success
*********************************************************************/
int8_t WWDT_SetWindow(uint32_t WindowedTime)
{
return WWDT_SetWindowRaw(WDT_GET_FROM_USEC(WindowedTime));
}
/********************************************************************//**
* @brief Update WDT timeout value for WatchDog event(s)
*
* @param[in] TimeOut Time Out value (usec) to be updated, should be
* in range: 2048 .. 134217728
*
* @return None
*********************************************************************/
void WDT_UpdateTimeOut(uint32_t TimeOut)
{
/* check WDPROTECT,
* if it is enable, wait until the counter is below the value of
* WDWARNINT and WDWINDOW
*/
if(LPC_WDT->MOD & (1<<4))
{
while((LPC_WDT->TV <(LPC_WDT->WARNINT & WWDT_WDWARNINT_MASK))\
&&(LPC_WDT->TV <(LPC_WDT->WINDOW & WWDT_WDTC_MASK)));
}
WWDT_SetTimeOut(TimeOut);
}
/********************************************************************//**
* @brief Read WWDT status flag
*
* @param[in] Status kind of status flag that you want to get, should be:
* - WWDT_WARNINT_FLAG: watchdog interrupt flag
* - WWDT_TIMEOUT_FLAG: watchdog time-out flag
*
* @return Time out flag status of WDT
*********************************************************************/
FlagStatus WWDT_GetStatus (uint8_t Status)
{
if(Status == WWDT_WARNINT_FLAG)
{
return ((FlagStatus)(LPC_WDT->MOD & (1<<3)));
}
else if (Status == WWDT_TIMEOUT_FLAG)
{
return ((FlagStatus)(LPC_WDT->MOD & (1<<2)));
}
return RESET;
}
/********************************************************************//**
* @brief Clear WWDT status flag
*
* @param[in] Status kind of status flag that you want to get, should be:
* - WWDT_WARNINT_FLAG: watchdog interrupt flag
* - WWDT_TIMEOUT_FLAG: watchdog time-out flag
*
* @return None
*********************************************************************/
void WWDT_ClearStatusFlag (uint8_t flag)
{
if(flag == WWDT_WARNINT_FLAG)
{
// Write 1 to this bit to clear itself
LPC_WDT->MOD |= WWDT_WDMOD_WDINT;
}
else if(flag == WWDT_TIMEOUT_FLAG)
{
// Write 0 to this bit to clear itself
LPC_WDT->MOD &= ~ WWDT_WDMOD_WDTOF;
}
}
/********************************************************************//**
* @brief Clear WDT Time out flag
* @param None
* @return None
*********************************************************************/
void WWDT_ClrTimeOutFlag (void)
{
LPC_WDT->MOD &= ~ WWDT_WDMOD_WDTOF;
}
/********************************************************************//**
* @brief Following the standard sequence to Feed the WatchDog Timer
*
* @param None
*
* @return None
*********************************************************************/
void WWDT_FeedStdSeq (void)
{
LPC_WDT->FEED = 0xAA;
LPC_WDT->FEED = 0x55;
}
/********************************************************************//**
* @brief After set WDTEN, call this function to start Watchdog
* or reload the Watchdog timer
*
* @param None
*
* @return None
*********************************************************************/
void WWDT_Feed (void)
{
// Disable irq interrupt
__disable_irq();
WWDT_FeedStdSeq();
// Then enable irq interrupt
__enable_irq();
}
/********************************************************************//**
* @brief Get the current value of WDT
*
* @param None
*
* @return Current value of WDT
*********************************************************************/
uint32_t WWDT_GetCurrentCount(void)
{
return LPC_WDT->TV;
}
/**
* @}
*/
#endif /*_WDT*/
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

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########################################################################
# $Id:: makefile 814 2008-06-19 19:57:32Z pdurgesh $
#
# Project: Standard compile makefile
#
# Description:
# Makefile
#
########################################################################
# Software that is described herein is for illustrative purposes only
# which provides customers with programming information regarding the
# products. This software is supplied "AS IS" without any warranties.
# NXP Semiconductors assumes no responsibility or liability for the
# use of the software, conveys no license or title under any patent,
# copyright, or mask work right to the product. NXP Semiconductors
# reserves the right to make changes in the software without
# notification. NXP Semiconductors also make no representation or
# warranty that such application will be suitable for the specified
# use without further testing or modification.
########################################################################
########################################################################
#
# Get the project root
#
########################################################################
PROJ_ROOT = $(CURDIR)/../..
########################################################################
#
# Pick up the configuration file in make section
#
########################################################################
include ../../makesection/makeconfig
########################################################################
#
# Pick up the default build rules
#
########################################################################
include $(PROJ_ROOT)/makesection/makerule/LPC/make.LPC.$(TOOL)
########################################################################
#
# Pick up the assembler and C source files in the directory
#
########################################################################
include $(PROJ_ROOT)/makesection/makerule/common/make.rules.ftypes
AFLAGS +=-I../include
CFLAGS +=-I../include
########################################################################
#
# Build the library
#
########################################################################
$(TARGET_FWLIB_LIB) : .vias $(OBJS) $(FWLIB_LIB_DIR)
$(ECHO) "creating" $(FWLIB) "Firmware support package library"
$(AR) $@ $(OBJS)
$(FWLIB_LIB_DIR):
$(MKDIR) $(FWLIB_LIB_DIR)
# delete all targets this Makefile can make
lib_clean:
-@$(RM) $(TARGET_FWLIB_LIB)
# delete all targets this Makefile can make and all built libraries
# linked in
lib_realclean:
-@$(RM) $(FWLIB_LIB_DIR)/*.a
-@$(RMDIR) $(FWLIB_LIB_DIR)
clean: lib_clean
realclean: lib_realclean
########################################################################
#
# Compile the code base
#
########################################################################
include $(PROJ_ROOT)/makesection/makerule/common/make.rules.build
.PHONY: all lib_clean lib_realclean

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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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from building import *
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

29
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT)
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

45
bsp/lpc408x/applications/application.c Normal file
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-01-02 xiaonong the first version for lpc408x
*/
#include <rtthread.h>
#include <board.h>
#include <components.h>
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/* Initialization RT-Thread Components */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_init();
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device(FINSH_DEVICE_NAME);
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX / 3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;
}

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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
#ifdef LPC_EXT_SDRAM
#include "drv_sdram.h"
#endif
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial LPC40xx board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
/* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/*init uart device*/
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#ifdef LPC_EXT_SDRAM
rt_kprintf("Initialize SDRAM ...");
lpc_sdram_hw_init();
rt_kprintf("done!\n");
#endif
}

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bsp/lpc408x/applications/board.h Normal file
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2010-02-04 Magicoe add board.h to LPC176x bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "LPC407x_8x_177x_8x.h"
#include <rtthread.h>
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Enable External SDRAM memory" default="0" />
//#define LPC_EXT_SDRAM 0
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
#define RT_USING_UART2
// </RDTConfigurator>
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (0x10000000 + 0x10000)
#define FINSH_DEVICE_NAME RT_CONSOLE_DEVICE_NAME
void rt_hw_board_init(void);
#endif

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bsp/lpc408x/applications/sram.c Normal file
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/*
* File : sram.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-19 Bernard The first version for LPC40xx
*/
#include "sram.h"
#include "board.h"
#include <rtthread.h>
#ifdef LPC_EXT_SDRAM
struct rt_memheap system_heap;
void sram_init(void)
{
/* initialize the built-in SRAM as a memory heap */
rt_memheap_init(&system_heap,
"system",
(void *)HEAP_BEGIN,
(rt_uint32_t)HEAP_END - (rt_uint32_t)HEAP_BEGIN);
}
void *sram_malloc(unsigned long size)
{
return rt_memheap_alloc(&system_heap, size);
}
void sram_free(void *ptr)
{
rt_memheap_free(ptr);
}
void *sram_realloc(void *ptr, unsigned long size)
{
return rt_memheap_realloc(&system_heap, ptr, size);
}
#endif

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bsp/lpc408x/applications/sram.h Normal file
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/*
* File : sram.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-19 Bernard The first version for LPC40xx
*/
#ifndef __SRAM_H__
#define __SRAM_H__
void *sram_malloc(unsigned long nbytes);
void sram_free(void *ptr);
void *sram_realloc(void *ptr, unsigned long nbytes);
#endif

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bsp/lpc408x/applications/startup.c Normal file
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2010-03-04 Magicoe for LPC17xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
#if LPC_EXT_SDRAM
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer*/
rt_system_timer_init();
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}

14
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_LWIP') == False:
SrcRemove(src, 'drv_emac.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

144
bsp/lpc408x/drivers/drv_led.c Normal file
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#include <rtthread.h>
#include "board.h"
#define RT_DEVICE_CTRL_RTC_GET_COUNT 0x81 /**< get count */
#define LED_NUM 4
struct led_ctrl
{
uint32_t num;
LPC_GPIO_TypeDef *port;
};
struct lpc_led
{
/* inherit from rt_device */
struct rt_device parent;
struct led_ctrl ctrl[LED_NUM];
};
static struct lpc_led led;
static rt_err_t rt_led_init(rt_device_t dev)
{
/* led0 : P4.14,led1:P4.15 ,led2:P4.16 ,led3:P4.17*/
/* set P4.14,P4.15,P4.16,P4.17 as GPIO. */
LPC_IOCON->P4_14 = 0x00;
LPC_IOCON->P4_15 = 0x00;
LPC_IOCON->P4_16 = 0x00;
LPC_IOCON->P4_17 = 0x00;
/* set P4.14,P4.15,P4.16,P4.17 output. */
LPC_GPIO4->DIR |= (0x0f << 14);
/* turn off all the led */
LPC_GPIO4->SET = (0x0f << 14);
led.ctrl[0].num = 14;
led.ctrl[0].port = LPC_GPIO4;
led.ctrl[1].num = 15;
led.ctrl[1].port = LPC_GPIO4;
led.ctrl[2].num = 16;
led.ctrl[2].port = LPC_GPIO4;
led.ctrl[3].num = 17;
led.ctrl[3].port = LPC_GPIO4;
return RT_EOK;
}
static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_led_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_led_read(rt_device_t dev, rt_off_t pos, void *buffer,
rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nr = size;
rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nr; index++)
{
if ((led.ctrl[pos + index].port->PIN) & 1 << led.ctrl[pos + index].num)
{
*value = 0;
}
else
{
*value = 1;
}
value++;
}
return index;
}
static rt_size_t rt_led_write(rt_device_t dev, rt_off_t pos,
const void *buffer, rt_size_t size)
{
rt_ubase_t index = 0;
rt_ubase_t nw = size;
const rt_uint8_t *value = buffer;
RT_ASSERT(dev == &led.parent);
RT_ASSERT((pos + size) <= LED_NUM);
for (index = 0; index < nw; index++)
{
if (*value++)
{
led.ctrl[pos + index].port->CLR |= (1 << led.ctrl[pos + index].num);
}
else
{
led.ctrl[pos + index].port->SET |= (1 << led.ctrl[pos + index].num);
}
}
return index;
}
static rt_err_t rt_led_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
RT_ASSERT(dev == &led.parent);
if (cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
{
rt_uint32_t *led_num = args;
*led_num = LED_NUM;
}
return RT_EOK;
}
void rt_led_hw_init(void)
{
led.parent.type = RT_Device_Class_Char;
led.parent.rx_indicate = RT_NULL;
led.parent.tx_complete = RT_NULL;
led.parent.init = rt_led_init;
led.parent.open = rt_led_open;
led.parent.close = rt_led_close;
led.parent.read = rt_led_read;
led.parent.write = rt_led_write;
led.parent.control = rt_led_control;
led.parent.user_data = RT_NULL;
/* register a character device */
rt_device_register(&led.parent, "led", RT_DEVICE_FLAG_RDWR);
/* init led device */
rt_led_init(&led.parent);
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void led_test(rt_uint32_t led_num, rt_uint32_t value)
{
rt_uint8_t led_value = value;
rt_led_write(&led.parent, led_num, &led_value, 1);
}
FINSH_FUNCTION_EXPORT(led_test, e.g: led_test(0, 100).)
#endif

0
bsp/lpc408x/drivers/drv_led.h Normal file
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286
bsp/lpc408x/drivers/drv_uart.c Normal file
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/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-18 Bernard The first version for LPC40xx
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "lpc_uart.h"
#include "lpc_pinsel.h"
struct lpc_uart
{
UART_ID_Type UART;
IRQn_Type UART_IRQn;
};
static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct lpc_uart *uart;
UART_CFG_Type UARTConfigStruct;
UART_FIFO_CFG_Type UARTFIFOConfigStruct;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc_uart *)serial->parent.user_data;
/* Initialize UART Configuration parameter structure to default state:
* Baudrate = 115200 bps
* 8 data bit
* 1 Stop bit
* None parity
*/
UART_ConfigStructInit(&UARTConfigStruct);
UARTConfigStruct.Baud_rate = 115200;
// Initialize UART0 peripheral with given to corresponding parameter
UART_Init(uart->UART, &UARTConfigStruct);
/* Initialize FIFOConfigStruct to default state:
* - FIFO_DMAMode = DISABLE
* - FIFO_Level = UART_FIFO_TRGLEV0
* - FIFO_ResetRxBuf = ENABLE
* - FIFO_ResetTxBuf = ENABLE
* - FIFO_State = ENABLE
*/
UART_FIFOConfigStructInit(&UARTFIFOConfigStruct);
// Initialize FIFO for UART0 peripheral
UART_FIFOConfig(uart->UART, &UARTFIFOConfigStruct);
UART_TxCmd(uart->UART, ENABLE);
return RT_EOK;
}
static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct lpc_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct lpc_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_IntConfig(uart->UART, UART_INTCFG_RBR, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_IntConfig(uart->UART, UART_INTCFG_RBR, ENABLE);
break;
}
return RT_EOK;
}
static int lpc_putc(struct rt_serial_device *serial, char c)
{
struct lpc_uart *uart;
uart = (struct lpc_uart *)serial->parent.user_data;
UART_Send(uart->UART, (uint8_t *)&c, 1, BLOCKING);
return 1;
}
static int lpc_getc(struct rt_serial_device *serial)
{
uint8_t ch;
struct lpc_uart *uart;
uart = (struct lpc_uart *)serial->parent.user_data;
if (UART_Receive(uart->UART, &ch, 1, NONE_BLOCKING) == 1)
return (int) ch;
return -1;
}
static const struct rt_uart_ops lpc_uart_ops =
{
lpc_configure,
lpc_control,
lpc_putc,
lpc_getc,
};
#if defined(RT_USING_UART0)
/* UART0 device driver structure */
struct serial_ringbuffer uart0_int_rx;
struct lpc_uart uart0 =
{
UART_0,
UART0_IRQn,
};
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
struct lpc_uart *uart;
uint32_t intsrc, tmp, tmp1;
uart = &uart0;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */
intsrc = UART_GetIntId(uart->UART);
tmp = intsrc & UART_IIR_INTID_MASK;
// Receive Line Status
if (tmp == UART_IIR_INTID_RLS)
{
// Check line status
tmp1 = UART_GetLineStatus(uart->UART);
// Mask out the Receive Ready and Transmit Holding empty status
tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
| UART_LSR_BI | UART_LSR_RXFE);
// If any error exist
if (tmp1)
{
//
}
}
// Receive Data Available or Character time-out
if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
{
rt_hw_serial_isr(&serial0);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(RT_USING_UART2)
/* UART2 device driver structure */
struct serial_ringbuffer uart2_int_rx;
struct lpc_uart uart2 =
{
UART_2,
UART2_IRQn,
};
struct rt_serial_device serial2;
void UART2_IRQHandler(void)
{
struct lpc_uart *uart;
uint32_t intsrc, tmp, tmp1;
uart = &uart2;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */
intsrc = UART_GetIntId(uart->UART);
tmp = intsrc & UART_IIR_INTID_MASK;
// Receive Line Status
if (tmp == UART_IIR_INTID_RLS)
{
// Check line status
tmp1 = UART_GetLineStatus(uart->UART);
// Mask out the Receive Ready and Transmit Holding empty status
tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \
| UART_LSR_BI | UART_LSR_RXFE);
// If any error exist
if (tmp1)
{
//
}
}
// Receive Data Available or Character time-out
if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI))
{
rt_hw_serial_isr(&serial2);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
void rt_hw_uart_init(void)
{
struct lpc_uart *uart;
struct serial_configure config;
#ifdef RT_USING_UART0
uart = &uart0;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial0.ops = &lpc_uart_ops;
serial0.int_rx = &uart0_int_rx;
serial0.config = config;
/*
* Initialize UART0 pin connect
* P0.2: U0_TXD
* P0.3: U0_RXD
*/
PINSEL_ConfigPin(0, 2, 1);
PINSEL_ConfigPin(0, 3, 1);
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->UART_IRQn);
/* register UART1 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
#endif
#ifdef RT_USING_UART2
uart = &uart2;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
serial2.ops = &lpc_uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
/*
* Initialize UART2 pin connect
* P2.8: U2_TXD
* P0.11: U2_RXD
*/
PINSEL_ConfigPin(2, 8, 2);
PINSEL_ConfigPin(0, 11, 1);
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->UART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->UART_IRQn);
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
#endif
}

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#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif

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