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[bsp][renesas] Add a new BSP: RZN2L-RSK

This commit is contained in:
Yuqiang Wang 2024-09-16 01:29:20 +08:00 committed by GitHub
parent 6320f184f5
commit beb7bc42de
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123 changed files with 90442 additions and 0 deletions
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1
.github/workflows/bsp_buildings.yml vendored
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@ -234,6 +234,7 @@ jobs:
- "renesas/ra8d1-ek"
- "renesas/ra8d1-vision-board"
- "renesas/rzt2m_rsk"
- "renesas/rzn2l_rsk"
- "frdm-k64f"
- "xplorer4330/M4"
- RTT_BSP: "gd32_n32_apm32"

2
bsp/renesas/README.md
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@ -19,7 +19,9 @@ RA 系列 BSP 目前支持情况如下表所示：
| [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 |
| [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 |
| [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 |
| **RZ 系列** | |
| [rzt2m_rsk](rzt2m_rsk) | Renesas 官方 RSK-RZT2M 开发板 |
| [rzn2l_rsk](rzn2l_rsk) | Renesas 官方 RSK-RZN2L 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

2
bsp/renesas/rzn2l_rsk/.api_xml Normal file
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@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<ddscApi/>

1194
bsp/renesas/rzn2l_rsk/.config Normal file
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4
bsp/renesas/rzn2l_rsk/.secure_azone Normal file
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@ -0,0 +1,4 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R9A07G084M04GBG.rzone"/>
</azone>

125
bsp/renesas/rzn2l_rsk/.secure_xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="9">
<generalSettings>
<option key="#Board#" value="board.rzn2lrsk.xspi0_x1"/>
<option key="CPU" value="RZN2L"/>
<option key="Core" value="CR52_0"/>
<option key="#TargetName#" value="R9A07G084M04GBG"/>
<option key="#TargetARCHITECTURE#" value="cortex-r52"/>
<option key="#DeviceCommand#" value="R9A07G084M04"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R9A07G084M04GBG.pincfg"/>
<option key="#FSPVersion#" value="2.0.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzn2l_rsk##xspi0_x1_boot"/>
<option key="#SELECTED_TOOLCHAIN#" value="iar.arm.toolchain"/>
</generalSettings>
<raBspConfiguration/>
<raClockConfiguration>
<node id="board.clock.main.freq" option="board.clock.main.freq.25m"/>
<node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/>
<node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/>
<node id="board.clock.pll1" option="board.clock.pll1.initial"/>
<node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/>
<node id="board.clock.ethernet.source" option="board.clock.ethernet.source.main"/>
<node id="board.clock.reference.display" option="board.clock.reference.display.value"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/>
<node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/>
<node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/>
<node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/>
<node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/>
<node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/>
<node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/>
<node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/>
<node id="board.clock.clma0.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma1.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma2.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma3.cmpl" mul="1" option="_edit"/>
<node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/>
<node id="board.clock.clma0.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma1.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma2.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma3.cmph" mul="1023" option="_edit"/>
<node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/>
<node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.2"/>
<node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/>
<node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/>
<node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/>
<node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/>
<node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/>
<node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/>
<node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/>
<node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/>
<node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/>
<node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/>
<node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/>
<node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/>
<node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/>
<node id="board.clock.pclkshost.display" option="board.clock.pclkshost.display.value"/>
<node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/>
<node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/>
<node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/>
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="canfd0.canrx0.p01_7" configurationId="canfd0.canrx0"/>
<configSetting altId="canfd0.cantx0.p02_2" configurationId="canfd0.cantx0"/>
<configSetting altId="ether_gmac.gmac_mdc.p08_7" configurationId="ether_gmac.gmac_mdc"/>
<configSetting altId="ether_gmac.gmac_mdio.p09_0" configurationId="ether_gmac.gmac_mdio"/>
<configSetting altId="iic0.iic_scl0.p13_2" configurationId="iic0.iic_scl0"/>
<configSetting altId="iic0.iic_sda0.p13_3" configurationId="iic0.iic_sda0"/>
<configSetting altId="iic1.iic_scl1.p05_2" configurationId="iic1.iic_scl1"/>
<configSetting altId="iic1.iic_sda1.p05_3" configurationId="iic1.iic_sda1"/>
<configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio" isUsedByDriver="true"/>
<configSetting altId="p03_0.output.low" configurationId="p03_0"/>
<configSetting altId="p04_1.output.low" configurationId="p04_1"/>
<configSetting altId="p04_4.output.low" configurationId="p04_4"/>
<configSetting altId="p05_0.output.low" configurationId="p05_0"/>
<configSetting altId="p05_4.input" configurationId="p05_4"/>
<configSetting altId="p13_4.output.low" configurationId="p13_4"/>
<configSetting altId="p13_5.input" configurationId="p13_5"/>
<configSetting altId="p13_6.input" configurationId="p13_6"/>
<configSetting altId="p13_7.input" configurationId="p13_7"/>
<configSetting altId="p14_0.input" configurationId="p14_0"/>
<configSetting altId="p16_3.input" configurationId="p16_3"/>
<configSetting altId="p17_3.output.low" configurationId="p17_3"/>
<configSetting altId="p18_2.output.low" configurationId="p18_2"/>
<configSetting altId="p22_1.output.low" configurationId="p22_1"/>
<configSetting altId="p22_3.output.low" configurationId="p22_3"/>
<configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0" isUsedByDriver="true"/>
<configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0" isUsedByDriver="true"/>
<configSetting altId="sci3.rxd_miso3.p17_7" configurationId="sci3.rxd_miso3"/>
<configSetting altId="sci3.txd_mosi3.p18_0" configurationId="sci3.txd_mosi3"/>
<configSetting altId="spi2.spi_miso2.p18_6" configurationId="spi2.spi_miso2"/>
<configSetting altId="spi2.spi_mosi2.p18_5" configurationId="spi2.spi_mosi2"/>
<configSetting altId="spi2.spi_rspck2.p18_4" configurationId="spi2.spi_rspck2"/>
<configSetting altId="spi2.spi_ssl20.p21_1" configurationId="spi2.spi_ssl20"/>
<configSetting altId="usb_hs.usb_ovrcur.p17_5" configurationId="usb_hs.usb_ovrcur"/>
<configSetting altId="usb_hs.usb_vbusen.p19_0" configurationId="usb_hs.usb_vbusen"/>
<configSetting altId="usb_hs.usb_vbusin.p07_4" configurationId="usb_hs.usb_vbusin"/>
<configSetting altId="xspi0.xspi0_ckn.p14_5" configurationId="xspi0.xspi0_ckn"/>
<configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp"/>
<configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash"/>
<configSetting altId="xspi0.xspi0_cs1_hash.p16_0" configurationId="xspi0.xspi0_cs1_hash"/>
<configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds"/>
<configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash"/>
<configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0"/>
<configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1"/>
<configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2"/>
<configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3"/>
<configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4"/>
<configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5"/>
<configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6"/>
<configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7"/>
<configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

24
bsp/renesas/rzn2l_rsk/.settings/standalone.prefs Normal file
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@ -0,0 +1,24 @@
#Sat Sep 14 16:03:03 CST 2024
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=907937621,script/fsp_xspi0_boot.icf|3822962514,rzn/board/rzn2l_rsk/board_leds.c|358444977,rzn/board/rzn2l_rsk/board_init.c|2067006575,rzn/board/rzn2l_rsk/board.h|736691883,rzn/board/rzn2l_rsk/board_ethernet_phy.h|1631979823,rzn/board/rzn2l_rsk/board_leds.h|1430483072,rzn/board/rzn2l_rsk/board_init.h
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.86814920=false
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/all=908052335,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3563504244,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|870156648,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|368480523,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1280798555,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3352808441,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h|1310386533,rzn/fsp/src/bsp/mcu/all/bsp_io.h|3643995939,rzn/fsp/src/bsp/mcu/all/bsp_cache.h|1033616941,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h|1572168446,rzn/fsp/src/bsp/mcu/all/bsp_io.c|3001342594,rzn/fsp/src/bsp/mcu/all/bsp_common.h|263477342,rzn/fsp/src/bsp/mcu/all/bsp_reset.h|2534029381,rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h|4193244082,rzn/fsp/src/bsp/mcu/all/bsp_irq.h|2136575248,rzn/fsp/src/bsp/mcu/all/bsp_tfu.h|2170977041,rzn/fsp/src/bsp/mcu/all/bsp_delay.c|526389185,rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h|8162287,rzn/fsp/src/bsp/mcu/all/bsp_clocks.h|3045644015,rzn/fsp/src/bsp/mcu/all/bsp_common.c|1908923075,rzn/fsp/src/bsp/mcu/all/bsp_clocks.c|1289851302,rzn/fsp/src/bsp/mcu/all/bsp_irq.c|358242822,rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c|2321472163,rzn/fsp/src/bsp/mcu/all/bsp_cache.c|225356254,rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h|2518644892,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c|392613868,rzn/fsp/src/bsp/mcu/all/bsp_reset.c|2238656401,rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1611830052,rzn/fsp/src/bsp/mcu/all/bsp_delay.h|2060190483,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|1543064539,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|3717942516,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|3396795463,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|2195931215,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|1126344352,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|1926319940,rzn/fsp/inc/fsp_features.h|2508067197,rzn/fsp/inc/fsp_version.h|3571247719,rzn/fsp/inc/fsp_common_api.h|3347087544,rzn/fsp/inc/instances/r_ioport.h|1765016794,rzn/fsp/inc/api/bsp_api.h|250199021,rzn/fsp/inc/api/r_ioport_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzn/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzn/fsp/inc/instances/r_sci_uart.h|1119704027,rzn/fsp/inc/api/r_uart_api.h|3586794436,rzn/fsp/inc/api/r_transfer_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/all=3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/all=2989202485,rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c|1967641730,rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h|1508541487,rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h|1088535767,rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c|1458388275,rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h|617637586,rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/all=615913359,rzn/fsp/src/r_ioport/r_ioport.c|3347087544,rzn/fsp/inc/instances/r_ioport.h|250199021,rzn/fsp/inc/api/r_ioport_api.h

17
bsp/renesas/rzn2l_rsk/Kconfig Normal file
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@ -0,0 +1,17 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
# you can change the RTT_ROOT default "rt-thread"
# example : default "F:/git_repositories/rt-thread"
PKGS_DIR := packages
ENV_DIR := /
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
source "$(BSP_DIR)/board/Kconfig"

168
bsp/renesas/rzn2l_rsk/README.md Normal file
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@ -0,0 +1,168 @@
# Renesas RSK-RZN2L Development Board BSP Documentation
**English** | [**中文**](./README_zh.md)
## Introduction
This document provides the BSP (Board Support Package) for the Renesas RSK-RZN2L development board. By following the Quick Start Guide, developers can quickly get started with the BSP and run RT-Thread on the development board.
The main contents include:
- Development Board Introduction
- BSP Quick Start Guide
## Development Board Introduction
The RSK-RZN2L MCU evaluation board is based on Renesas RZ/N2L and is designed for developing embedded system applications with flexible software package configuration and IDE support.
The front appearance of the development board is shown below:
![image-20240914173709363](figures/image-20240914173709363.png)
The commonly used **onboard resources** for this development board are as follows:
- MPU: R9A07G084M04GBG, maximum operating frequency of 400MHz, Arm® Cortex®-R52 with on-chip FPU (Floating Point Unit) and NEON™, 1.5 MB on-chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 High-Speed, CAN/CANFD, various communication interfaces such as xSPI and ΔΣ interfaces, and security functions.
- Debug Interface: Onboard J-Link interface
- Expansion Interface: Two PMOD connectors
**More detailed information and tools**
## Peripheral Support
The current peripheral support in this BSP is as follows:
| **On-chip Peripheral** | **Support Status** | **Remarks** |
| :----------------- | :----------------- | :------------- |
| UART | Supported | UART0 is the default log output port |
| GPIO | Supported | |
| HWIMER | Supported | |
| IIC | Supported | |
| WDT | Supported | |
| RTC | Supported | |
| ADC | Supported | |
| DAC | Supported | |
| SPI | Supported | |
| FLASH | Supported | |
| PWM | Supported | |
| CAN | Supported | |
| ETH | Supported | |
| More updates... | | |
## Instructions
The instructions are divided into the following two sections:
- Quick Start
This section is for beginners who are new to RT-Thread. By following simple steps, you can run the RT-Thread OS on this development board and observe the experimental results.
- Advanced Usage
This section is for developers who want to use more resources on the development board with RT-Thread. Using the ENV tool to configure the BSP, you can enable more onboard resources and achieve more advanced features.
### Quick Start
Currently, this BSP only provides an IAR project. Below is an example of how to get the system running using the [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) development environment.
**Hardware Connection**
Connect the development board to the PC using a USB data cable, and use the J-Link interface to download and debug programs.
**Compilation and Download**
- Go to the BSP directory, open ENV, and use the command `scons --target=iar` to generate the IAR project.
- Compile: Double-click the `project.eww` file to open the IAR project and compile the program.
- Debug: Click `Project->Download and Debug` in the IAR toolbar to download and start debugging.
**View Running Results**
After successfully downloading the program, the system will run automatically and print system information.
Connect the corresponding serial port of the development board to the PC. Open the corresponding serial port in a terminal tool (115200-8-1-N). After resetting the device, you can see the RT-Thread output. Enter the `help` command to view the supported commands in the system.
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Mar 14 2024 18:26:01
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
==================================================
This is a iar project which mode is xspi0 execution!
==================================================
msh >help
RT-Thread shell commands:
clear - clear the terminal screen
version - show RT-Thread version information
list - list objects
backtrace - print backtrace of a thread
help - RT-Thread shell help
ps - List threads in the system
free - Show the memory usage in the system
pin - pin [option]
msh >
```
**Application Entry Function**
The application layer's entry function is in `src\hal_entry.c` in the `void hal_entry(void)` function. User source files can be placed directly in the `src` directory.
```c
#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
rt_kprintf("==================================================\n");
rt_kprintf("This is a iar project which mode is xspi0 execution!\n");
rt_kprintf("==================================================\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### Advanced Usage
**Resources and Documentation**
- [Development Board Official Homepage](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications)
- [Development Board Data Sheet](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651)
- [Development Board Hardware Manual](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651)
- [RZ/N2L MCU Quick Start Guide](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651)
- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651)
- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651)
**FSP Configuration**
If you need to modify Renesas BSP peripheral configurations or add new peripheral ports, you will need to use the Renesas [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) configuration tool. Please follow the steps below. If you encounter any issues during the configuration, feel free to ask on the [RT-Thread Community Forum](https://club.rt-thread.org/).
1. [Download the Flexible Software Package (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe), please use version FSP 2.0.0.
2. Refer to the document [How to Import Board Support Package](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) to add the **"RSK-RZN2L Board Support Package"** to FSP.
3. Refer to the document: [RA Series Using FSP to Configure Peripheral Drivers](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动).
**ENV Configuration**
- How to use the ENV tool: [RT-Thread ENV Tool User Manual](https://www.rt-thread.org/document/site/#/development-tools/env/env)
By default, this BSP only enables UART0. To use more advanced features like components, software packages, etc., you need to configure the BSP using the ENV tool.
Steps:
1. Open the env tool in the BSP directory.
2. Enter the `menuconfig` command to configure the project. After configuration, save and exit.
3. Enter the `pkgs --update` command to update the software packages.
4. Enter the `scons --target=iar` command to regenerate the project.
## Contact Information
If you have any thoughts or suggestions during usage, feel free to contact us via the [RT-Thread Community Forum](https://club.rt-thread.org/).
## Contribute Code
If you are interested in the RSK-RZN2L and have some exciting projects to share with the community, we welcome your code contributions. You can refer to [How to Contribute Code to RT-Thread](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).

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# 瑞萨 RSK-RZN2L 开发板 BSP 说明
**中文** | [**English**](./README.md)
## 简介
本文档为瑞萨 RSK-RZN2L 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RZ/N2L 开发的 RSK-RZN2L MCU 评估板，通过灵活配置软件包和 IDE，对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![image-20240914173709363](figures/image-20240914173709363.png)
该开发板常用 **板载资源** 如下：
- MPU：R9A07G084M04GBG，最大工作频率 400MHz，Arm® Cortex®-R52 片上浮点单元（FPU）和 NEON™，1.5 MB 片上 SRAM，Ethernet MAC，EtherCAT，USB 2.0 高速，CAN/CANFD，xSPI 和 ΔΣ 接口等各种通信接口，以及安全功能。
- 调试接口：板载 J-Link 接口
- 扩展接口：两个 PMOD 连接器
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
| UART | 支持 | UART0 为默认日志输出端口 |
| GPIO | 支持 | |
| HWIMER | 支持 | |
| IIC | 支持 | |
| WDT | 支持 | |
| RTC | 支持 | |
| ADC | 支持 | |
| DAC | 支持 | |
| SPI | 支持 | |
| FLASH | 支持 | |
| PWM | 支持 | |
| CAN | 支持 | |
| ETH | 支持 | |
| 持续更新中... | | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 目前仅提供 IAR 工程。下面以 [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) 开发环境为例，介绍如何将系统运行起来。
**硬件连接**
使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。
**编译下载**
- 进入 bsp 目录下，打开 ENV 使用命令 `scons --target=iar` 生成 IAR工程。
- 编译：双击 project.eww 文件，打开 IAR 工程，编译程序。
- 调试：IAR 左上方导航栏点击 `Project->Download and Debug`下载并启动调试。
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Mar 14 2024 18:26:01
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
==================================================
This is a iar project which mode is xspi0 execution!
==================================================
msh >help
RT-Thread shell commands:
clear - clear the terminal screen
version - show RT-Thread version information
list - list objects
backtrace - print backtrace of a thread
help - RT-Thread shell help
ps - List threads in the system
free - Show the memory usage in the system
pin - pin [option]
msh >
```
**应用入口函数**
应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
rt_kprintf("==================================================\n");
rt_kprintf("This is a iar project which mode is xspi0 execution!\n");
rt_kprintf("==================================================\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板官网主页](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications)
- [开发板数据手册](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651)
- [开发板硬件手册](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651)
- [RZ/N2L MCU 快速入门指南](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651)
- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651)
- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651)
**FSP 配置**
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe)，请使用 FSP 2.0.0 版本
2. 如何将 **”RSK-RZN2L板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
3. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART0 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=iar` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 RSK-RZN2L 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
CPPPATH = [cwd]
group = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
group = DefineGroup('', src, depend = [''], CPPPATH = CPPPATH)
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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menu "Hardware Drivers Config"
config SOC_R9A07G084
bool
select SOC_SERIES_R9A07G0
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_ETHERCAT_EOE
bool "Enable EtherCAT EOE example"
select BSP_USING_ETH
default n
if BSP_USING_ETHERCAT_EOE
config RT_LWIP_IPADDR
string "set static ip address for eoe slaver"
default "192.168.10.100"
config RT_LWIP_GWADDR
string "set static gateway address for eoe slaver"
default "192.168.10.1"
config RT_LWIP_MSKADDR
string "set static mask address for eoe slaver"
default "255.255.255.0"
endif
endmenu
menu "On-chip Peripheral Drivers"
rsource "../../libraries/HAL_Drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART0
bool "Enable UART0"
default n
if BSP_USING_UART0
config BSP_UART0_RX_USING_DMA
bool "Enable UART0 RX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_TX_USING_DMA
bool "Enable UART0 TX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART0_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_CANFD
bool "Enable CANFD"
default n
select RT_USING_CAN
select RT_CAN_USING_CANFD
if BSP_USING_CANFD
config BSP_USING_CANFD0
bool "Enable CANFD0"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C0
bool "Enable Hardware I2C0 BUS"
default n
endif
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
if !BSP_USING_HW_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x0B03
config BSP_I2C1_SDA_PIN
hex "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x050E
endif
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM0
bool "Enable TIM0"
default n
config BSP_USING_TIM1
bool "Enable TIM1"
default n
endif
config BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_SAL
select RT_USING_LWIP
select RT_USING_NETDEV
default n
endmenu
menu "Board extended module Drivers"
menuconfig BSP_USING_RW007
bool "Enable RW007"
default n
select PKG_USING_RW007
select BSP_USING_SPI
select BSP_USING_SPI2
select RT_USING_MEMPOOL
select RW007_NOT_USE_EXAMPLE_DRIVERS
if BSP_USING_RW007
config RA_RW007_SPI_BUS_NAME
string "RW007 BUS NAME"
default "spi2"
config RA_RW007_CS_PIN
hex "(HEX)CS pin index"
default 0x1207
config RA_RW007_BOOT0_PIN
hex "(HEX)BOOT0 pin index (same as spi clk pin)"
default 0x1204
config RA_RW007_BOOT1_PIN
hex "(HEX)BOOT1 pin index (same as spi cs pin)"
default 0x1207
config RA_RW007_INT_BUSY_PIN
hex "(HEX)INT/BUSY pin index"
default 0x1102
config RA_RW007_RST_PIN
hex "(HEX)RESET pin index"
default 0x1706
endif
endmenu
endmenu

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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd]
src = Glob('*.c')
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-11 Wangyuqiang first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <rtdef.h>
#include <cp15.h>
#include <hal_data.h>
#define RZ_SRAM_SIZE 512 /* The SRAM size of the chip needs to be modified */
#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024 - 1)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
#define HEAP_BEGIN (0x10000000)
#endif
#define HEAP_END RZ_SRAM_END
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define MAX_HANDLERS (512)
#define GIC_IRQ_START 0
#define GIC_ACK_INTID_MASK (0x000003FFU)
/* number of interrupts on board */
#define ARM_GIC_NR_IRQS (448)
/* only one GIC available */
#define ARM_GIC_MAX_NR 1
/* end defined */
#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000)
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
rt_uint32_t gic_base;
__get_cp(15, 1, gic_base, 15, 3, 0);
return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
}
#ifdef __cplusplus
}
#endif
#endif

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bsp/renesas/rzn2l_rsk/board/ports/SConscript Normal file
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import os
from building import *
objs = []
src = Glob('*.c')
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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bsp/renesas/rzn2l_rsk/board/ports/gpio_cfg.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-11 Wangyuqiang first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_00_PIN_1: \
case BSP_IO_PORT_09_PIN_2: \
case BSP_IO_PORT_18_PIN_3: \
return 0; \
case BSP_IO_PORT_00_PIN_3: \
case BSP_IO_PORT_07_PIN_4: \
case BSP_IO_PORT_18_PIN_4: \
return 1; \
case BSP_IO_PORT_01_PIN_2: \
return 2; \
case BSP_IO_PORT_01_PIN_4: \
return 3; \
case BSP_IO_PORT_02_PIN_0: \
case BSP_IO_PORT_22_PIN_2: \
return 4; \
case BSP_IO_PORT_03_PIN_5: \
case BSP_IO_PORT_13_PIN_2: \
return 5; \
case BSP_IO_PORT_14_PIN_2: \
case BSP_IO_PORT_21_PIN_5: \
return 6; \
case BSP_IO_PORT_16_PIN_3: \
return 7; \
case BSP_IO_PORT_03_PIN_6: \
case BSP_IO_PORT_16_PIN_6: \
return 8; \
case BSP_IO_PORT_03_PIN_7: \
case BSP_IO_PORT_21_PIN_6: \
return 9; \
case BSP_IO_PORT_04_PIN_4: \
case BSP_IO_PORT_18_PIN_1: \
case BSP_IO_PORT_21_PIN_7: \
return 10; \
case BSP_IO_PORT_10_PIN_4: \
case BSP_IO_PORT_18_PIN_6: \
return 11; \
case BSP_IO_PORT_05_PIN_0: \
case BSP_IO_PORT_05_PIN_4: \
case BSP_IO_PORT_05_PIN_6: \
return 12; \
case BSP_IO_PORT_00_PIN_4: \
case BSP_IO_PORT_00_PIN_7: \
case BSP_IO_PORT_05_PIN_1: \
return 13; \
case BSP_IO_PORT_02_PIN_2: \
case BSP_IO_PORT_03_PIN_0: \
case BSP_IO_PORT_05_PIN_2: \
return 14; \
case BSP_IO_PORT_02_PIN_3: \
case BSP_IO_PORT_05_PIN_3: \
case BSP_IO_PORT_22_PIN_0: \
return 15; \
default : \
return -1; \
} \
}

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<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<iarProjectConnection version="1.8" name="Flex Software">
<device>
<name>R9A07G084M04</name>
</device>
<includePath>
<path>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</path>
<path>$PROJ_DIR$/rzn/fsp/inc</path>
<path>$PROJ_DIR$/rzn/fsp/inc/api</path>
<path>$PROJ_DIR$/rzn/fsp/inc/instances</path>
<path>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</path>
<path>$PROJ_DIR$/rzn_gen</path>
<path>$PROJ_DIR$/src</path>
<path>$PROJ_DIR$</path>
</includePath>
<defines>
<define>_RZN_ORDINAL=1</define>
<define>_RZN_CORE=CR52_0</define>
<define>_RENESAS_RZN_</define>
</defines>
<asmIncludePath>
<path>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</path>
<path>$PROJ_DIR$/rzn/fsp/inc</path>
<path>$PROJ_DIR$/rzn/fsp/inc/api</path>
<path>$PROJ_DIR$/rzn/fsp/inc/instances</path>
<path>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</path>
<path>$PROJ_DIR$/rzn_gen</path>
<path>$PROJ_DIR$/src</path>
<path>$PROJ_DIR$</path>
</asmIncludePath>
<asmDefines>
<define>_RZN_ORDINAL=1</define>
<define>_RZN_CORE=CR52_0</define>
<define>_RENESAS_RZN_</define>
</asmDefines>
<linkerFile>
<override>true</override>
<path>$PROJ_DIR$/script/fsp_xspi0_boot.icf</path>
</linkerFile>
<linkerExtraOptions>
<arg>--config_search "$PROJ_DIR$"</arg>
</linkerExtraOptions>
<programEntryPoint>
<symbol>system_init</symbol>
</programEntryPoint>
<customArgVars>
<group name="RA Smart Configurator">
<argVar>
<name>RASC_EXE_PATH</name>
<value>D:\manufacture_apps\Renesas\fsp\rzn_v2.0.0\eclipse\rasc.exe</value>
</argVar>
</group>
</customArgVars>
<files>
<group name="Components">
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h</path>
<path>rzn/arm/CMSIS_5/LICENSE.txt</path>
<path>rzn/board/rzn2l_rsk/board.h</path>
<path>rzn/board/rzn2l_rsk/board_ethernet_phy.h</path>
<path>rzn/board/rzn2l_rsk/board_init.c</path>
<path>rzn/board/rzn2l_rsk/board_init.h</path>
<path>rzn/board/rzn2l_rsk/board_leds.c</path>
<path>rzn/board/rzn2l_rsk/board_leds.h</path>
<path>rzn/fsp/inc/api/bsp_api.h</path>
<path>rzn/fsp/inc/api/r_ioport_api.h</path>
<path>rzn/fsp/inc/api/r_transfer_api.h</path>
<path>rzn/fsp/inc/api/r_uart_api.h</path>
<path>rzn/fsp/inc/fsp_common_api.h</path>
<path>rzn/fsp/inc/fsp_features.h</path>
<path>rzn/fsp/inc/fsp_version.h</path>
<path>rzn/fsp/inc/instances/r_ioport.h</path>
<path>rzn/fsp/inc/instances/r_sci_uart.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_cache.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_cache.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_clocks.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_clocks.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_common.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_common.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_delay.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_delay.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_io.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_io.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_irq.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_irq.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_reset.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_reset.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_tfu.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h</path>
<path>rzn/fsp/src/r_ioport/r_ioport.c</path>
<path>rzn/fsp/src/r_sci_uart/r_sci_uart.c</path>
</group>
<group name="Build Configuration">
<path>rzn_cfg/fsp_cfg/bsp/board_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h</path>
<path>rzn_cfg/fsp_cfg/r_ioport_cfg.h</path>
<path>rzn_cfg/fsp_cfg/r_sci_uart_cfg.h</path>
</group>
<group name="Generated Data">
<path>rzn_gen/bsp_clock_cfg.h</path>
<path>rzn_gen/common_data.c</path>
<path>rzn_gen/common_data.h</path>
<path>rzn_gen/hal_data.c</path>
<path>rzn_gen/hal_data.h</path>
<path>rzn_gen/main.c</path>
<path>rzn_gen/pin_data.c</path>
<path>rzn_gen/vector_data.c</path>
<path>rzn_gen/vector_data.h</path>
</group>
<group name="Program Entry">
<path>src/hal_entry.c</path>
</group>
</files>
</iarProjectConnection>

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bsp/renesas/rzn2l_rsk/memory_regions.icf Normal file
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/* generated memory regions file - do not edit */
define symbol ATCM_START = 0x00000000;
define symbol ATCM_LENGTH = 0x20000;
define symbol BTCM_START = 0x00100000;
define symbol BTCM_LENGTH = 0x20000;
define symbol SYSTEM_RAM_START = 0x10000000;
define symbol SYSTEM_RAM_LENGTH = 0x180000;
define symbol SYSTEM_RAM_MIRROR_START = 0x30000000;
define symbol SYSTEM_RAM_MIRROR_LENGTH = 0x180000;
define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000;
define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000;
define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000;
define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS0_SPACE_MIRROR_START = 0x50000000;
define symbol CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS2_SPACE_MIRROR_START = 0x54000000;
define symbol CS2_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS3_SPACE_MIRROR_START = 0x58000000;
define symbol CS3_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS5_SPACE_MIRROR_START = 0x5C000000;
define symbol CS5_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI0_CS0_SPACE_START = 0x60000000;
define symbol xSPI0_CS0_SPACE_LENGTH = 0x4000000;
define symbol xSPI0_CS1_SPACE_START = 0x64000000;
define symbol xSPI0_CS1_SPACE_LENGTH = 0x4000000;
define symbol xSPI1_CS0_SPACE_START = 0x68000000;
define symbol xSPI1_CS0_SPACE_LENGTH = 0x4000000;
define symbol CS0_SPACE_START = 0x70000000;
define symbol CS0_SPACE_LENGTH = 0x4000000;
define symbol CS2_SPACE_START = 0x74000000;
define symbol CS2_SPACE_LENGTH = 0x4000000;
define symbol CS3_SPACE_START = 0x78000000;
define symbol CS3_SPACE_LENGTH = 0x4000000;
define symbol CS5_SPACE_START = 0x7C000000;
define symbol CS5_SPACE_LENGTH = 0x4000000;

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
#define ARCH_ARM
#define ARCH_ARM_CORTEX_R
#define ARCH_ARM_CORTEX_R52
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
#define RT_SERIAL_USING_DMA
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_FAMILY_RENESAS
#define SOC_SERIES_R9A07G0
/* Hardware Drivers Config */
#define SOC_R9A07G084
/* Onboard Peripheral Drivers */
/* end of Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_BUFSIZE 256
#define BSP_UART0_TX_BUFSIZE 0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Board extended module Drivers */
/* end of Hardware Drivers Config */
#endif

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import os
import sys
# toolchains options
ARCH='arm'
CPU='cortex-r52'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armclang'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'D:/IAR Systems/Embedded Workbench 9.2'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
# BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
NM = PREFIX + 'nm'
DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -munaligned-access -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -funwind-tables'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=arm '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp_xspi0_boot.ld -L script/'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g -Wall'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -Os'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
# POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-R52'
CFLAGS += ' -e'
CFLAGS += ' --arm'
CFLAGS += ' --float-abi=hard'
CFLAGS += ' --fpu=neon-fp-armv8'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-R52'
AFLAGS += ' --arm'
AFLAGS += ' --float-abi hard'
AFLAGS += ' --fpu neon-fp-armv8'
# AFLAGS += ' --unaligned-access'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "script/fsp_xspi0_boot.icf"'
LFLAGS += ' --entry Reset_Handler'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c')
src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c')
src += Glob(cwd + '/fsp/src/r_*/*.c')
src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('rzn', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h"
*
* Changes:
* - No Changes.
*/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_cp15.h
* @brief CMSIS compiler specific macros, functions, instructions
* @date 02. February 2024
******************************************************************************/
/*
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "CMSIS\Core_A\Include\cmsis_cp15.h"
*
* Changes:
* Renesas Electronics Corporation on 2021-08-31
* - Changed to be related to Cortex-R52 by
* Renesas Electronics Corporation on 2024-02-02
* - Functions are sorted according to the Arm technical reference.
* - Added some functions to convert BSP into C language.
*/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_CP15_H
#define __CMSIS_CP15_H
/** \brief Get CTR
\return Cache Type Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CTR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 1);
return result;
}
/** \brief Get MPIDR
This function returns the value of the Multiprocessor Affinity Register.
\return Multiprocessor Affinity Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 5);
return result;
}
/** \brief Get CCSIDR
\return CCSIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
{
uint32_t result;
__get_CP(15, 1, result, 0, 0, 0);
return result;
}
/** \brief Get CLIDR
\return CLIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
{
uint32_t result;
__get_CP(15, 1, result, 0, 0, 1);
return result;
}
/** \brief Get CSSELR
\return CSSELR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
{
uint32_t result;
__get_CP(15, 2, result, 0, 0, 0);
return result;
}
/** \brief Set CSSELR
*/
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
{
__set_CP(15, 2, value, 0, 0, 0);
}
/** \brief Get SCTLR
This function assigns the given value to the System Control Register.
\return System Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 0);
return result;
}
/** \brief Set SCTLR
\param [in] value System Control Register value to set
*/
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t value)
{
__set_CP(15, 0, value, 1, 0, 0);
}
/** \brief Get ACTLR
\return Auxiliary Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return(result);
}
/** \brief Set ACTLR
\param [in] value Auxiliary Control value to set
*/
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t value)
{
__set_CP(15, 0, value, 1, 0, 1);
}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 2);
return result;
}
/** \brief Set CPACR
\param [in] value Coprocessor Access Control value to set
*/
__STATIC_FORCEINLINE void __set_CPACR(uint32_t value)
{
__set_CP(15, 0, value, 1, 0, 2);
}
/** \brief Get TTBR0
This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
{
uint32_t result;
__get_CP(15, 0, result, 2, 0, 0);
return result;
}
/** \brief Set TTBR0
This function assigns the given value to the Translation Table Base Register 0.
\param [in] value Translation Table Base Register 0 value to set
*/
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t value)
{
__set_CP(15, 0, value, 2, 0, 0);
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 3, 0, 0);
return result;
}
/** \brief Set DACR
This function assigns the given value to the Domain Access Control Register.
\param [in] value Domain Access Control Register value to set
*/
__STATIC_FORCEINLINE void __set_DACR(uint32_t value)
{
__set_CP(15, 0, value, 3, 0, 0);
}
/** \brief Get ICC_PMR
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_PMR(void)
{
uint32_t result;
__get_CP(15, 0, result, 4, 6, 0);
return result;
}
/** \brief Set ICC_PMR
*/
__STATIC_FORCEINLINE void __set_ICC_PMR(uint32_t value)
{
__set_CP(15, 0, value, 4, 6, 0);
}
/** \brief Get DFSR
\return Data Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 0);
return result;
}
/** \brief Set DFSR
\param [in] value Data Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_DFSR(uint32_t value)
{
__set_CP(15, 0, value, 5, 0, 0);
}
/** \brief Get IFSR
\return Instruction Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 1);
return result;
}
/** \brief Set IFSR
\param [in] value Instruction Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_IFSR(uint32_t value)
{
__set_CP(15, 0, value, 5, 0, 1);
}
/** \brief Set PRSELR
This function assigns the given value to the Protection Region Selection Register.
\param [in] value Protection Region Selection Register to set
*/
__STATIC_FORCEINLINE void __set_PRSELR(uint32_t value)
{
__set_CP(15, 0, value, 6, 2, 1);
}
/** \brief Get PRBAR
This function returns the value of the Protection Region Base Address Register.
\return Protection Region Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_PRBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 6, 3, 0);
return result;
}
/** \brief Set PRBAR
This function assigns the given value to the Protection Region Base Address Register.
\param [in] value Protection Region Base Address Register to set
*/
__STATIC_FORCEINLINE void __set_PRBAR(uint32_t value)
{
__set_CP(15, 0, value, 6, 3, 0);
}
/** \brief Get PRLAR
This function returns the value of the Protection Region Limit Address Register.
\return Protection Region Limit Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_PRLAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 6, 3, 1);
return result;
}
/** \brief Set PRLAR
This function assigns the given value to the Protection Region Limit Address Register.
\param [in] value Protection Region Limit Address Register to set
*/
__STATIC_FORCEINLINE void __set_PRLAR(uint32_t value)
{
__set_CP(15, 0, value, 6, 3, 1);
}
/** \brief Set ICIALLU
Instruction Cache Invalidate All
*/
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 0);
}
/** \brief Set ICIVAU
*/
__STATIC_FORCEINLINE void __set_ICIVAU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 1);
}
/** \brief Set BPIALL.
Branch Predictor Invalidate All
*/
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 6);
}
/** \brief Set DCIMVAC
Data cache invalidate
*/
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCIVAC
*/
__STATIC_FORCEINLINE void __set_DCIVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCISW
*/
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 2);
}
/** \brief Set DCCMVAC
Data cache clean
*/
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCCVAC
*/
__STATIC_FORCEINLINE void __set_DCCVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCCSW
*/
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 2);
}
/** \brief Set DCCIMVAC
Data cache clean and invalidate
*/
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set DCCIVAC
*/
__STATIC_FORCEINLINE void __set_DCCIVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set DCCISW
*/
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 2);
}
/** \brief Set TLBIALL
TLB Invalidate All
*/
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
{
__set_CP(15, 0, value, 8, 7, 0);
}
/** \brief Set MAIR0
This function assigns the given value to the Memory Attribute Indirection Registers 0.
\param [in] value Memory Attribute Indirection Registers 0 to set
*/
__STATIC_FORCEINLINE void __set_MAIR0(uint32_t value)
{
__set_CP(15, 0, value, 10, 2, 0);
}
/** \brief Set MAIR1
This function assigns the given value to the Memory Attribute Indirection Registers 1.
\param [in] value Memory Attribute Indirection Registers 1 to set
*/
__STATIC_FORCEINLINE void __set_MAIR1(uint32_t value)
{
__set_CP(15, 0, value, 10, 2, 1);
}
/** \brief Get IMP_SLAVEPCTLR
This function returns the value of the Slave Port Control Register.
\return Slave Port Control Register
*/
__STATIC_FORCEINLINE uint32_t __get_IMP_SLAVEPCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 11, 0, 0);
return result;
}
/** \brief Set IMP_SLAVEPCTLR
This function assigns the given value to the Slave Port Control Register.
\param [in] value Slave Port Control Register value to set
*/
__STATIC_FORCEINLINE void __set_IMP_SLAVEPCTLR(uint32_t value)
{
__set_CP(15, 0, value, 11, 0, 0);
}
/** \brief Get VBAR
This function returns the value of the Vector Base Address Register.
\return Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 0);
return result;
}
/** \brief Set VBAR
This function assigns the given value to the Vector Base Address Register.
\param [in] value Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t value)
{
__set_CP(15, 0, value, 12, 0, 0);
}
/** \brief Get MVBAR
This function returns the value of the Monitor Vector Base Address Register.
\return Monitor Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 1);
return result;
}
/** \brief Set MVBAR
This function assigns the given value to the Monitor Vector Base Address Register.
\param [in] value Monitor Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t value)
{
__set_CP(15, 0, value, 12, 0, 1);
}
/** \brief Get ISR
\return Interrupt Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 1, 0);
return result;
}
/** \brief Get ICC_RPR
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_RPR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 11, 3);
return result;
}
/** \brief Get ICC_IAR1
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_IAR1(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 12, 0);
return result;
}
/** \brief Set ICC_EOIR1
*/
__STATIC_FORCEINLINE void __set_ICC_EOIR1(uint32_t value)
{
__set_CP(15, 0, value, 12, 12, 0);
}
/** \brief Get ICC_HPPIR1
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_HPPIR1(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 12, 2);
return result;
}
/** \brief Get ICC_BPR1
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_BPR1(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 12, 3);
return result;
}
/** \brief Set ICC_BPR1
*/
__STATIC_FORCEINLINE void __set_ICC_BPR1(uint32_t value)
{
__set_CP(15, 0, value, 12, 12, 3);
}
/** \brief Get ICC_CTLR
*/
__STATIC_FORCEINLINE uint32_t __get_ICC_CTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 12, 4);
return result;
}
/** \brief Set ICC_CTLR
*/
__STATIC_FORCEINLINE void __set_ICC_CTLR(uint32_t value)
{
__set_CP(15, 0, value, 12, 12, 4);
}
/** \brief Set ICC_IGRPEN1
*/
__STATIC_FORCEINLINE void __set_ICC_IGRPEN1(uint32_t value)
{
__set_CP(15, 0, value, 12, 12, 7);
}
/** \brief Set CNTFRQ
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\param [in] value CNTFRQ Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
{
__set_CP(15, 0, value, 14, 0, 0);
}
/** \brief Get CNTFRQ
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 0, 0);
return result;
}
/** \brief Set CNTKCTL
This function assigns the given value to Counter-timer Kernel Control Register (CNTKCTL).
\param [in] value CNTKCTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTKCTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 1, 0);
}
/** \brief Get CNTKCTL
This function returns the value of the Counter-timer kernel Control Register (CNTKCTL).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTKCTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 1, 0);
return result;
}
/** \brief Set CNTP_TVAL
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
\param [in] value CNTP_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 0);
}
/** \brief Get CNTP_TVAL
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
\return CNTP_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 0);
return result;
}
/** \brief Set CNTP_CTL
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
\param [in] value CNTP_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 1);
}
/** \brief Get CNTP_CTL register
\return CNTP_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 1);
return result;
}
/** \brief Set CNTV_CTL
This function assigns the given value to PL1 Virtual Timer Control Register (CNTV_CTL).
\param [in] value CNTV_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 3, 1);
}
/** \brief Get CNTV_CTL register
\return CNTV_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 3, 1);
return result;
}
/** \brief Get CBAR
\return Configuration Base Address register value
*/
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
{
uint32_t result;
__get_CP(15, 4, result, 15, 0, 0);
return result;
}
/** \brief Get CNTPCT
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
\return CNTPCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
{
uint64_t result;
__get_CP64(15, 0, result, 14);
return result;
}
/** \brief Set ICC_SGI1R
*/
__STATIC_FORCEINLINE void __set_ICC_SGI1R(uint64_t value)
{
__set_CP64(15, 0, value, 12);
}
/** \brief Get CNTVCT
This function returns the value of the 64 bits PL1 Virtual Count Register (CNTVCT).
\return CNTVCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void)
{
uint64_t result;
__get_CP64(15, 1, result, 14);
return result;
}
/** \brief Set CNTP_CVAL
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\param [in] value CNTP_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
{
__set_CP64(15, 2, value, 14);
}
/** \brief Get CNTP_CVAL
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\return CNTP_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
{
uint64_t result;
__get_CP64(15, 2, result, 14);
return result;
}
#endif

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @date 02. February 2024
******************************************************************************/
// ------------------------------------------------------------------------------
//
// Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
//
// This file is based on the "\CMSIS\Core\Include\cmsis_iccarm.h"
//
// Changes:
// Renesas Electronics Corporation on 2021-08-31
// - Changed to be related to Cortex-R52 by
// Renesas Electronics Corporation on 2024-02-02
// - Added functions related to FPEXC registers.
// - Moved the process of defining compiler macros for CPU architectures to renesas.h.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#define __get_FPEXC() (__arm_rsr("FPEXC"))
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", (VALUE)))
#else
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void) VALUE)
#define __get_FPEXC() (0)
#define __set_FPEXC(VALUE) ((void) VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#define __get_FPEXC() (0)
#define __set_FPEXC(VALUE) ((void) VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* __CMSIS_ICCARM_H__ */

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bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h Normal file
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\cmsis_version.h"
*
* Changes:
* - No Changes.
*/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

312
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/**************************************************************************//**
* @file core_cr52.h
* @brief CMSIS Cortex-R52 Core Peripheral Access Layer Header File
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\core_armv8mml.h"
*
* Changes:
* Renesas Electronics Corporation on 2021-08-31
* - Changed to be related to Cortex-R52 by
*/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CR52_H_GENERIC
#define __CORE_CR52_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_R52
@{
*/
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#define __FPU_D32 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#ifndef __ARMVFP_D16__
#define __FPU_D32 1U
#endif
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_version.h"
/* CMSIS CR52 definitions */
#define __CR52_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CR52_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CR52_CMSIS_VERSION ((__CR52_CMSIS_VERSION_MAIN << 16U) | \
__CR52_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_R (52U) /*!< Cortex-R Core */
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CR52_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CR52_H_DEPENDANT
#define __CORE_CR52_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_R52 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_GIC Generic Interrupt Controller (GIC)
\brief Type definitions for the GIC Registers
@{
*/
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICD.
*/
typedef struct
{
__IOM uint32_t GICD_CTLR; /*!< Offset: 0x0000 (R/W) Distributor Control Register */
__IM uint32_t GICD_TYPER; /*!< Offset: 0x0004 (R/ ) Interrupt Controller Type Register */
__IM uint32_t GICD_IIDR; /*!< Offset: 0x0008 (R/ ) Distributor Implementer Identification Register */
uint32_t RESERVED0[30U];
__IOM uint32_t GICD_IGROUPR[30U]; /*!< Offset: 0x0084 (R/W) Interrupt Group Registers 1 - 30 */
uint32_t RESERVED1[2U];
__IOM uint32_t GICD_ISENABLER[30U]; /*!< Offset: 0x0104 (R/W) Interrupt Set-Enable Registers 1 - 30 */
uint32_t RESERVED2[2U];
__IOM uint32_t GICD_ICENABLER[30U]; /*!< Offset: 0x0184 (R/W) Interrupt Clear-Enable Registers 1 - 30 */
uint32_t RESERVED3[2U];
__IOM uint32_t GICD_ISPENDR[30U]; /*!< Offset: 0x0204 (R/W) Interrupt Set-Pending Registers 1 - 30 */
uint32_t RESERVED4[2U];
__IOM uint32_t GICD_ICPENDR[30U]; /*!< Offset: 0x0284 (R/W) Interrupt Clear-Pending Registers 1 - 30 */
uint32_t RESERVED5[2U];
__IOM uint32_t GICD_ISACTIVER[30U]; /*!< Offset: 0x0304 (R/W) Interrupt Set-Active Registers 1 - 30 */
uint32_t RESERVED6[2U];
__IOM uint32_t GICD_ICACTIVER[30U]; /*!< Offset: 0x0384 (R/W) Interrupt Clear-Active Registers 1 - 30 */
uint32_t RESERVED7[9U];
__IOM uint32_t GICD_IPRIORITYR[240U]; /*!< Offset: 0x0420 (R/W) Interrupt Priority Registers 8 - 247 */
uint32_t RESERVED8[266U];
__IOM uint32_t GICD_ICFGR[60U]; /*!< Offset: 0x0C08 (R/W) Interrupt Configuration Registers 2 - 61 */
} GICD_Type;
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target.
*/
typedef struct
{
__IM uint32_t GICR_CTLR; /*!< Offset: 0x0000 (R/ ) Redistributor Control Register */
__IM uint32_t GICR_IIDR; /*!< Offset: 0x0004 (R/ ) Redistributor Implementer Identification Register */
__IM uint32_t GICR_TYPER[2]; /*!< Offset: 0x0008 (R/ ) Redistributor Type Register */
uint32_t RESERVED0;
__IOM uint32_t GICR_WAKER; /*!< Offset: 0x0014 (R/W) Redistributor Wake Register */
} GICR_CONTROL_TARGET_Type;
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI.
*/
typedef struct
{
uint32_t RESERVED0[32];
__IOM uint32_t GICR_IGROUPR0; /*!< Offset: 0x0080 (R/W) Interrupt Group Register 0 */
uint32_t RESERVED1[31];
__IOM uint32_t GICR_ISENABLER0; /*!< Offset: 0x0100 (R/W) Interrupt Set-Enable Register 0 */
uint32_t RESERVED2[31];
__IOM uint32_t GICR_ICENABLER0; /*!< Offset: 0x0180 (R/W) Interrupt Clear-Enable Register 0 */
uint32_t RESERVED3[31];
__IOM uint32_t GICR_ISPENDR0; /*!< Offset: 0x0200 (R/W) Interrupt Set-Pending Register 0 */
uint32_t RESERVED4[31];
__IOM uint32_t GICR_ICPENDR0; /*!< Offset: 0x0280 (R/W) Interrupt Clear-Pending Register 0 */
uint32_t RESERVED5[31];
__IOM uint32_t GICR_ISACTIVER0; /*!< Offset: 0x0300 (R/W) Interrupt Set-Active Register 0 */
uint32_t RESERVED6[31];
__IOM uint32_t GICR_ICACTIVER0; /*!< Offset: 0x0380 (R/W) Interrupt Clear-Active Register 0 */
uint32_t RESERVED7[31];
__IOM uint32_t GICR_IPRIORITYR[8]; /*!< Offset: 0x0400 (R/W) Interrupt Priority Registers 0 - 7 */
uint32_t RESERVED8[504];
__IM uint32_t GICR_ICFGR0; /*!< Offset: 0x0C00 (R/ ) Interrupt Configuration Register 0 */
__IOM uint32_t GICR_ICFGR1; /*!< Offset: 0x0C04 (R/W) Interrupt Configuration Register 1 */
} GICR_SGI_PPI_Type;
/*@} end of group CMSIS_GIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define GIC0_BASE (0x94000000UL) /*!< GIC0 Base Address */
#define GIC1_BASE (0x9C000000UL) /*!< GIC1 Base Address */
#define GICR_TARGET0_BASE (0x00100000UL) /*!< GICR Base Address (for Control target 0) */
#define GICR_TARGET0_SGI_PPI_BASE (0x00110000UL) /*!< GICR Base Address (for SGI and PPI target 0) */
#define GICD0 ((GICD_Type *) GIC0_BASE ) /*!< GICD configuration struct */
#define GICD1 ((GICD_Type *) GIC1_BASE ) /*!< GICD configuration struct */
#define GICR0_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */
#define GICR1_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */
#define GICR0_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */
#define GICR1_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */
/*@} */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief Get CPSR Register
This function returns the content of the CPSR Register.
\return CPSR Register value
*/
__STATIC_INLINE uint32_t __get_CPSR(void)
{
register uint32_t __regCPSR __ASM("cpsr");
return(__regCPSR);
}
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
#include <intrinsics.h>
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CR52_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board.h
* Description : Includes and API function available for this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARDS
* @defgroup BOARD_RZN2L_RSK
* @brief BSP for the RZN2L_RSK Board
*
* The RZN2L_RSK is a development kit for the Renesas RZN2L microcontroller.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_H
#define BOARD_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP Board Specific Includes. */
#include "board_init.h"
#include "board_leds.h"
#include "board_ethernet_phy.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BOARD_RZN2L_RSK
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end defgroup BSP_CONFIG_RZN2L) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2_RSK
* @defgroup BOARD_RZN2_RSK_ETHERNET_PHY Board Ethernet Phy
* @brief Ethernet Phy information for this board.
*
* This is code specific to the RZN2_RSK board.
*
* @{
**********************************************************************************************************************/
#ifndef BSP_ETHERNET_PHY_H
#define BSP_ETHERNET_PHY_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE (1)
#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_VSC8541
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2_RSK_ETHERNET_PHY) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_init.c
* Description : This module calls any initialization code specific to this BSP.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RZN2L_RSK_INIT
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RZN2L_RSK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Performs any initialization specific to this BSP.
*
* @param[in] p_args Pointer to arguments of the user's choice.
**********************************************************************************************************************/
void bsp_init (void * p_args)
{
FSP_PARAMETER_NOT_USED(p_args);
}
#endif
/** @} (end addtogroup BOARD_RZN2L_RSK_INIT) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_init.h
* Description : This module calls any initialization code specific to this BSP.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2L_RSK
* @defgroup BOARD_RZN2L_RSK_INIT
* @brief Board specific code for the RZN2L_RSK Board
*
* This include file is specific to the RZN2L_RSK board.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_INIT_H
#define BOARD_INIT_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void bsp_init(void * p_args);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2L_RSK_INIT) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_leds.c
* Description : This module has information about the LEDs on this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RZN2L_RSK_LEDS
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RZN2L_RSK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Array of LED IOPORT pins. */
static const uint32_t g_bsp_prv_leds[][2] =
{
{(uint32_t) BSP_IO_PORT_18_PIN_2, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED0
{(uint32_t) BSP_IO_PORT_22_PIN_3, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED1
{(uint32_t) BSP_IO_PORT_04_PIN_1, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED2
{(uint32_t) BSP_IO_PORT_17_PIN_3, (uint32_t) BSP_IO_REGION_SAFE} ///< RLED3
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** Structure with LED information for this board. */
const bsp_leds_t g_bsp_leds =
{
.led_count = (uint16_t) (sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0])),
.p_leds = g_bsp_prv_leds
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#endif
/** @} (end addtogroup BOARD_RZN2L_RSK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_leds.h
* Description : This module has information about the LEDs on this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2L_RSK
* @defgroup BOARD_RZN2L_RSK_LEDS Board LEDs
* @brief LED information for this board.
*
* This is code specific to the RZN2L_RSK board. It includes info on the number of LEDs and which pins are they
* are on.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_LEDS_H
#define BOARD_LEDS_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Information on how many LEDs and what pins they are on. */
typedef struct st_bsp_leds
{
uint16_t led_count; ///< The number of LEDs on this board
uint32_t const (*p_leds)[2]; ///< Pointer to an array of IOPORT pins for controlling LEDs
} bsp_leds_t;
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
* found in the bsp_leds_t structure. */
typedef enum e_bsp_led
{
BSP_LED_RLED0 = 0, ///< Green
BSP_LED_RLED1 = 1, ///< Yellow
BSP_LED_RLED2 = 2, ///< Red
BSP_LED_RLED3 = 3, ///< Red
} bsp_led_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2L_RSK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic push
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "../../src/bsp/mcu/all/bsp_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
#if defined(BSP_API_OVERRIDE)
#include BSP_API_OVERRIDE
#else
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_SYSTEM_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
* @brief Interface for accessing I/O ports and configuring I/O functionality.
*
* @section IOPORT_API_SUMMARY Summary
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
* Port and pin direction can be changed.
*
*
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_API_H
#define R_IOPORT_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_IOPORT_SIZE_T
/** IO port type used with ports */
typedef uint16_t ioport_size_t; ///< IO port size
#endif
/** Pin identifier and pin configuration value */
typedef struct st_ioport_pin_cfg
{
uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure
bsp_io_port_pin_t pin; ///< Pin identifier
} ioport_pin_cfg_t;
/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */
typedef struct st_ioport_cfg
{
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
const void * p_extend; ///< Pointer to hardware extend configuration
} ioport_cfg_t;
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
*/
typedef void ioport_ctrl_t;
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
typedef struct st_ioport_api
{
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
* multiple pins.
*
* @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Close the API.
*
* @param[in] p_ctrl Pointer to control structure.
**/
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
/** Configure multiple pins.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Configure settings for an individual pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] cfg Configuration options for the pin.
*/
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
/** Read the event input data of the specified pin and return the level.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_event Pointer to return the event data.
*/
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
/** Write pin event data.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin event data is to be written to.
* @param[in] pin_value Level to be written to pin output event.
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/** Read level of a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_value Pointer to return the pin level.
*/
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
/** Write specified level to a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be written to.
* @param[in] level State to be written to the pin.
*/
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
/** Set the direction of one or more pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port being configured.
* @param[in] direction_values Value controlling direction of pins on port.
* @param[in] mask Mask controlling which pins on the port are to be configured.
*/
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
ioport_size_t mask);
/** Read captured event data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_event_data Pointer to return the event data.
*/
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
/** Write event output data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port event data will be written to.
* @param[in] event_data Data to be written as event data to specified port.
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
* being written to port.
*/
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
ioport_size_t mask_value);
/** Read states of pins on the specified port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_port_value Pointer to return the port value.
*/
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
/** Write to multiple pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be written to.
* @param[in] value Value to be written to the port.
* @param[in] mask Mask controlling which pins on the port are written to.
*/
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
} ioport_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_ioport_instance
{
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
} ioport_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_TRANSFER_INTERFACES
* @defgroup TRANSFER_API Transfer Interface
*
* @brief Interface for data transfer functions.
*
* @section TRANSFER_API_SUMMARY Summary
* The transfer interface supports background data transfer (no CPU intervention).
*
*
* @{
**********************************************************************************************************************/
#ifndef R_TRANSFER_API_H
#define R_TRANSFER_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define TRANSFER_SETTINGS_MODE_BITS (30U)
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
*/
typedef void transfer_ctrl_t;
#ifndef BSP_OVERRIDE_TRANSFER_MODE_T
/** Transfer mode describes what will happen when a transfer request occurs. */
typedef enum e_transfer_mode
{
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
* the destination pointer. The transfer length is decremented and the source and address pointers are
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
* will not cause any further transfers. */
TRANSFER_MODE_NORMAL = 0,
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
TRANSFER_MODE_REPEAT = 1,
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
* After each individual transfer, the source and destination pointers are updated according to
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
* further transfers. */
TRANSFER_MODE_BLOCK = 2,
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
* within a block (to split blocks into arrays of their first data, second data, etc.) */
TRANSFER_MODE_REPEAT_BLOCK = 3
} transfer_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T
/** Transfer size specifies the size of each individual transfer.
* Total transfer length = transfer_size_t * transfer_length_t
*/
typedef enum e_transfer_size
{
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
} transfer_size_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
typedef enum e_transfer_addr_mode
{
/** Address pointer remains fixed after each transfer. */
TRANSFER_ADDR_MODE_FIXED = 0,
/** Offset is added to the address pointer after each transfer. */
TRANSFER_ADDR_MODE_OFFSET = 1,
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_INCREMENTED = 2,
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_DECREMENTED = 3
} transfer_addr_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
* the selected pointer returns to its original value after each transfer. */
typedef enum e_transfer_repeat_area
{
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_DESTINATION = 0,
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_SOURCE = 1
} transfer_repeat_area_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T
/** Chain transfer mode options.
* @note Only applies for DTC. */
typedef enum e_transfer_chain_mode
{
/** Chain mode not used. */
TRANSFER_CHAIN_MODE_DISABLED = 0,
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
TRANSFER_CHAIN_MODE_EACH = 2,
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
TRANSFER_CHAIN_MODE_END = 3
} transfer_chain_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T
/** Interrupt options. */
typedef enum e_transfer_irq
{
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
* the interrupt will occur only after subsequent chained transfer(s) are complete.
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
* prevent activation source interrupts until the transfer is complete. */
TRANSFER_IRQ_END = 0,
/** Interrupt occurs after each transfer.
* @note Not available in all HAL drivers. See HAL driver for details. */
TRANSFER_IRQ_EACH = 1
} transfer_irq_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T
/** Callback function parameter data. */
typedef struct st_transfer_callback_args_t
{
void const * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t.
} transfer_callback_args_t;
#endif
/** Driver specific information. */
typedef struct st_transfer_properties
{
uint32_t block_count_max; ///< Maximum number of blocks
uint32_t block_count_remaining; ///< Number of blocks remaining
uint32_t transfer_length_max; ///< Maximum number of transfers
uint32_t transfer_length_remaining; ///< Number of transfers remaining
} transfer_properties_t;
#ifndef BSP_OVERRIDE_TRANSFER_INFO_T
/** This structure specifies the properties of the transfer.
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
* have a unique transfer_info_t.
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
* structure must remain in scope until the transfer it is used for is closed.
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
typedef struct st_transfer_info
{
union
{
struct
{
uint32_t : 16;
uint32_t : 2;
/** Select what happens to destination pointer after each transfer. */
transfer_addr_mode_t dest_addr_mode : 2;
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
transfer_repeat_area_t repeat_area : 1;
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
* transfers. */
transfer_irq_t irq : 1;
/** Select when the chain transfer ends. */
transfer_chain_mode_t chain_mode : 2;
uint32_t : 2;
/** Select what happens to source pointer after each transfer. */
transfer_addr_mode_t src_addr_mode : 2;
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
transfer_size_t size : 2;
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
} transfer_settings_word_b;
uint32_t transfer_settings_word;
};
void const * volatile p_src; ///< Source pointer
void * volatile p_dest; ///< Destination pointer
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
volatile uint16_t num_blocks;
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
* and @ref TRANSFER_MODE_REPEAT_BLOCK
* see HAL driver for details. */
volatile uint16_t length;
} transfer_info_t;
#endif
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
* initialized. */
typedef struct st_transfer_cfg
{
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
* an array of chained transfers that will be completed in order. */
transfer_info_t * p_info;
void const * p_extend; ///< Extension parameter for hardware specific settings.
} transfer_cfg_t;
/** Select whether to start single or repeated transfer with software start. */
typedef enum e_transfer_start_mode
{
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
} transfer_start_mode_t;
/** Transfer functions implemented at the HAL layer will follow this API. */
typedef struct st_transfer_api
{
/** Initial configuration.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
* must be set by user.
*/
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
/** Reconfigure the transfer.
* Enable the transfer if p_info is valid.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_info Pointer to a new transfer info structure.
*/
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
* Enable the transfer if p_src, p_dest, and length are valid.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
* repeat mode. Not used in repeat mode for DTC.
*/
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint16_t const num_transfers);
/** Enable transfer. Transfers occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source).
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
/** Disable transfer. Transfers do not occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source).
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
* transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
/** Start transfer in software.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
* @note Not supported for DTC.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] mode Select mode from @ref transfer_start_mode_t.
*/
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
* @note Not supported for DTC.
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
/** Provides information about this transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[out] p_properties Driver specific information.
*/
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
/** To update next transfer information without interruption during transfer.
* Allow further transfer continuation.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or block mode.
*/
fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint32_t const num_transfers);
/** Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_callback Callback function to register
* @param[in] p_context Pointer to send to callback function
* @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *),
void const * const p_context, transfer_callback_args_t * const p_callback_memory);
} transfer_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_transfer_instance
{
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
} transfer_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup TRANSFER_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_CONNECTIVITY_INTERFACES
* @defgroup UART_API UART Interface
* @brief Interface for UART communications.
*
* @section UART_INTERFACE_SUMMARY Summary
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
* - Full-duplex UART communication
* - Interrupt driven transmit/receive processing
* - Callback function with returned event code
* - Runtime baud-rate change
* - Hardware resource locking during a transaction
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
*
*
* @{
**********************************************************************************************************************/
#ifndef R_UART_API_H
#define R_UART_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** UART Event codes */
#ifndef BSP_OVERRIDE_UART_EVENT_T
typedef enum e_sf_event
{
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
} uart_event_t;
#endif
#ifndef BSP_OVERRIDE_UART_DATA_BITS_T
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
} uart_data_bits_t;
#endif
#ifndef BSP_OVERRIDE_UART_PARITY_T
/** UART Parity definition */
typedef enum e_uart_parity
{
UART_PARITY_OFF = 0U, ///< No parity
UART_PARITY_ZERO = 1U, ///< Zero parity
UART_PARITY_EVEN = 2U, ///< Even parity
UART_PARITY_ODD = 3U, ///< Odd parity
} uart_parity_t;
#endif
/** UART Stop bits definition */
typedef enum e_uart_stop_bits
{
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
} uart_stop_bits_t;
/** UART transaction definition */
typedef enum e_uart_dir
{
UART_DIR_RX_TX = 3U, ///< Both RX and TX
UART_DIR_RX = 1U, ///< Only RX
UART_DIR_TX = 2U, ///< Only TX
} uart_dir_t;
/** UART driver specific information */
typedef struct st_uart_info
{
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
uint32_t write_bytes_max;
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
uint32_t read_bytes_max;
} uart_info_t;
/** UART Callback parameter definition */
typedef struct st_uart_callback_arg
{
uint32_t channel; ///< Device channel number
uart_event_t event; ///< Event code
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
uint32_t data;
void const * p_context; ///< Context provided to user during callback
} uart_callback_args_t;
/** UART Configuration */
typedef struct st_uart_cfg
{
/* UART generic configuration */
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
uart_parity_t parity; ///< Parity type (none or odd or even)
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
uint8_t rxi_ipl; ///< Receive interrupt priority
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
uint8_t txi_ipl; ///< Transmit interrupt priority
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
uint8_t tei_ipl; ///< Transmit end interrupt priority
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
uint8_t eri_ipl; ///< Error interrupt priority
IRQn_Type eri_irq; ///< Error interrupt IRQ number
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
transfer_instance_t const * p_transfer_rx;
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
transfer_instance_t const * p_transfer_tx;
/* Configuration for UART Event processing */
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
void const * p_context; ///< User defined context passed into callback function
/* Pointer to UART peripheral specific configuration */
void const * p_extend; ///< UART hardware dependent configuration
} uart_cfg_t;
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
*/
typedef void uart_ctrl_t;
/** Shared Interface definition for UART */
typedef struct st_uart_api
{
/** Open UART device.
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
* user.
*/
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
* the callback function with event UART_EVENT_RX_CHAR.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
* @param[in] bytes Read data length.
*/
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
* the callback called with event UART_EVENT_TX_COMPLETE.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
* @param[in] bytes Write data length.
*/
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
/** Change baud rate.
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
* settings have been applied.
*
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
*/
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
/** Get the driver specific information.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] baudrate Baud rate in bps.
*/
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
/**
* Abort ongoing transfer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
*/
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
/**
* Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *),
void const * const p_context, uart_callback_args_t * const p_callback_memory);
/** Close UART device.
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
/** Stop ongoing read and return the number of bytes remaining in the read.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
*/
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_uart_instance
{
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
} uart_instance_t;
/** @} (end defgroup UART_API) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_COMMON_API_H
#define FSP_COMMON_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <assert.h>
#include <stdint.h>
/* Includes FSP version macros. */
#include "fsp_version.h"
/*******************************************************************************************************************//**
* @ingroup RENESAS_COMMON
* @defgroup RENESAS_ERROR_CODES Common Error Codes
* All FSP modules share these common error codes.
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
* about using this implementation is that it does not take any extra RAM or ROM. */
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
/** Determine if a C++ compiler is being used.
* If so, ensure that standard C is used to process the API information. */
#if defined(__cplusplus)
#define FSP_CPP_HEADER extern "C" {
#define FSP_CPP_FOOTER }
#else
#define FSP_CPP_HEADER
#define FSP_CPP_FOOTER
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
#define FSP_SECURE_ARGUMENT (NULL)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Common error codes */
typedef enum e_fsp_err
{
FSP_SUCCESS = 0,
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
FSP_ERR_ABORTED = 18, ///< An operation was aborted
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
FSP_ERR_TIMEOUT = 20, ///< Timeout error
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, ///< Internal error
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
/* Start of UART specific */
FSP_ERR_FRAMING = 200, ///< Framing error occurs
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
FSP_ERR_PARITY = 202, ///< Parity error occurs
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
/* Start of SPI specific */
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
FSP_ERR_OVERRUN = 304, ///< Overrun error.
/* Start of CGC Specific */
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
/* Start of FLASH Specific */
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
/* Start of IIRFA Specific */
FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity.
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
/* Start of JPEG Specific */
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
/* Start of IIRFA specific */
FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected
FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
/* Start of USB specific */
FSP_ERR_USB_FAILED = 1500,
FSP_ERR_USB_BUSY = 1501,
FSP_ERR_USB_SIZE_SHORT = 1502,
FSP_ERR_USB_SIZE_OVER = 1503,
FSP_ERR_USB_NOT_OPEN = 1504,
FSP_ERR_USB_NOT_SUSPEND = 1505,
FSP_ERR_USB_PARAMETER = 1506,
/* Start of Message framework specific */
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
/* Start of 2DG Driver specific */
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
/* Start of ETHER Driver specific */
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active.
/* Start of ETHER_PHY Driver specific */
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
/* Start of BYTEQ library specific */
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
/* Start of CTSU Driver specific */
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet.
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed.
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed.
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed.
FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed.
FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed.
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed.
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed.
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed.
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed.
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed.
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed.
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed.
/* Start of SDMMC specific */
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
/* Start of FX_IO specific */
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
/* Start of CAN specific */
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
/* Start of SF_WIFI Specific */
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
/* Start of SF_BLE specific */
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
/* Start of SF_BLE_ABS specific */
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal.
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred.
/* Start of Crypto RSIP specific (0x10100) */
FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy
FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return
FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error
FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal
FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed
/* Start of SF_CRYPTO specific */
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
* Refer to sf_cryoto_err.h for Crypto error codes.
*/
/* Start of Sensor specific */
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
/* Start of COMMS specific */
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
} fsp_err_t;
/** @} */
/***********************************************************************************************************************
* Function prototypes
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_FEATURES_H
#define FSP_FEATURES_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
/* Different compiler support. */
#include "fsp_common_api.h"
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Available modules. */
typedef enum e_fsp_ip
{
FSP_IP_CGC = 1, ///< Clock Generation Circuit
FSP_IP_CLMA = 2, ///< Clock Monitor Circuit
FSP_IP_MSTP = 3, ///< Module Stop
FSP_IP_ICU = 4, ///< Interrupt Control Unit
FSP_IP_BSC = 5, ///< Bus State Contoller
FSP_IP_CKIO = 6, ///< CKIO
FSP_IP_DMAC = 7, ///< DMA Controller
FSP_IP_ELC = 8, ///< Event Link Controller
FSP_IP_IOPORT = 9, ///< I/O Ports
FSP_IP_MTU3 = 10, ///< Multi-Function Timer Pulse Unit
FSP_IP_POE3 = 11, ///< Port Output Enable for MTU3
FSP_IP_GPT = 12, ///< General PWM Timer
FSP_IP_POEG = 13, ///< Port Output Enable for GPT
FSP_IP_TFU = 14, ///< Arithmetic Unit for Trigonometric Functions
FSP_IP_CMT = 15, ///< Compare Match Timer
FSP_IP_CMTW = 16, ///< Compare Match Timer W
FSP_IP_WDT = 17, ///< Watch Dog Timer
FSP_IP_RTC = 18, ///< Real Time Clock
FSP_IP_ETHSS = 19, ///< Ethernet Subsystem
FSP_IP_GMAC = 20, ///< Ethernet MAC
FSP_IP_ETHSW = 21, ///< Ethernet Switch
FSP_IP_ESC = 22, ///< EtherCAT Slave Controller
FSP_IP_USBHS = 23, ///< USB High Speed
FSP_IP_SCI = 24, ///< Serial Communications Interface
FSP_IP_IIC = 25, ///< I2C Bus Interface
FSP_IP_CANFD = 26, ///< Controller Area Network with Flexible Data Rate
FSP_IP_SPI = 27, ///< Serial Peripheral Interface
FSP_IP_XSPI = 28, ///< expanded Serial Peripheral Interface
FSP_IP_CRC = 29, ///< Cyclic Redundancy Check Calculator
FSP_IP_BSCAN = 30, ///< Boundary Scan
FSP_IP_DSMIF = 31, ///< Delta Sigma Interface
FSP_IP_ADC12 = 32, ///< 12-Bit A/D Converter
FSP_IP_TSU = 33, ///< Temperature Sensor
FSP_IP_DOC = 34, ///< Data Operation Circuit
FSP_IP_SYSRAM = 35, ///< System SRAM
FSP_IP_ENCIF = 36, ///< Encoder Interface
FSP_IP_SHOSTIF = 37, ///< Serial Host Interface
FSP_IP_PHOSTIF = 38, ///< Parallel Host Interface
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
typedef enum e_fsp_signal
{
FSP_SIGNAL_INTCPU0 = (0), ///< Software interrupt 0
FSP_SIGNAL_INTCPU1 = (1), ///< Software interrupt 1
FSP_SIGNAL_INTCPU2 = (2), ///< Software interrupt 2
FSP_SIGNAL_INTCPU3 = (3), ///< Software interrupt 3
FSP_SIGNAL_INTCPU4 = (4), ///< Software interrupt 4
FSP_SIGNAL_INTCPU5 = (5), ///< Software interrupt 5
FSP_SIGNAL_IRQ0 = (6), ///< External pin interrupt 0
FSP_SIGNAL_IRQ1 = (7), ///< External pin interrupt 1
FSP_SIGNAL_IRQ2 = (8), ///< External pin interrupt 2
FSP_SIGNAL_IRQ3 = (9), ///< External pin interrupt 3
FSP_SIGNAL_IRQ4 = (10), ///< External pin interrupt 4
FSP_SIGNAL_IRQ5 = (11), ///< External pin interrupt 5
FSP_SIGNAL_IRQ6 = (12), ///< External pin interrupt 6
FSP_SIGNAL_IRQ7 = (13), ///< External pin interrupt 7
FSP_SIGNAL_IRQ8 = (14), ///< External pin interrupt 8
FSP_SIGNAL_IRQ9 = (15), ///< External pin interrupt 9
FSP_SIGNAL_IRQ10 = (16), ///< External pin interrupt 10
FSP_SIGNAL_IRQ11 = (17), ///< External pin interrupt 11
FSP_SIGNAL_IRQ12 = (18), ///< External pin interrupt 12
FSP_SIGNAL_IRQ13 = (19), ///< External pin interrupt 13
FSP_SIGNAL_BSC_CMI = (20), ///< Refresh compare match interrupt
FSP_SIGNAL_DMAC0_INT0 = (21), ///< DMAC0 transfer completion 0
FSP_SIGNAL_DMAC0_INT1 = (22), ///< DMAC0 transfer completion 1
FSP_SIGNAL_DMAC0_INT2 = (23), ///< DMAC0 transfer completion 2
FSP_SIGNAL_DMAC0_INT3 = (24), ///< DMAC0 transfer completion 3
FSP_SIGNAL_DMAC0_INT4 = (25), ///< DMAC0 transfer completion 4
FSP_SIGNAL_DMAC0_INT5 = (26), ///< DMAC0 transfer completion 5
FSP_SIGNAL_DMAC0_INT6 = (27), ///< DMAC0 transfer completion 6
FSP_SIGNAL_DMAC0_INT7 = (28), ///< DMAC0 transfer completion 7
FSP_SIGNAL_DMAC1_INT0 = (37), ///< DMAC1 transfer completion 0
FSP_SIGNAL_DMAC1_INT1 = (38), ///< DMAC1 transfer completion 1
FSP_SIGNAL_DMAC1_INT2 = (39), ///< DMAC1 transfer completion 2
FSP_SIGNAL_DMAC1_INT3 = (40), ///< DMAC1 transfer completion 3
FSP_SIGNAL_DMAC1_INT4 = (41), ///< DMAC1 transfer completion 4
FSP_SIGNAL_DMAC1_INT5 = (42), ///< DMAC1 transfer completion 5
FSP_SIGNAL_DMAC1_INT6 = (43), ///< DMAC1 transfer completion 6
FSP_SIGNAL_DMAC1_INT7 = (44), ///< DMAC1 transfer completion 7
FSP_SIGNAL_CMT0_CMI = (53), ///< CMT0 Compare match
FSP_SIGNAL_CMT1_CMI = (54), ///< CMT1 Compare match
FSP_SIGNAL_CMT2_CMI = (55), ///< CMT2 Compare match
FSP_SIGNAL_CMT3_CMI = (56), ///< CMT3 Compare match
FSP_SIGNAL_CMT4_CMI = (57), ///< CMT4 Compare match
FSP_SIGNAL_CMT5_CMI = (58), ///< CMT5 Compare match
FSP_SIGNAL_CMTW0_CMWI = (59), ///< CMTW0 Compare match
FSP_SIGNAL_CMTW0_IC0I = (60), ///< CMTW0 Input capture of register 0
FSP_SIGNAL_CMTW0_IC1I = (61), ///< CMTW0 Input capture of register 1
FSP_SIGNAL_CMTW0_OC0I = (62), ///< CMTW0 Output compare of register 0
FSP_SIGNAL_CMTW0_OC1I = (63), ///< CMTW0 Output compare of register 1
FSP_SIGNAL_CMTW1_CMWI = (64), ///< CMTW1 Compare match
FSP_SIGNAL_CMTW1_IC0I = (65), ///< CMTW1 Input capture of register 0
FSP_SIGNAL_CMTW1_IC1I = (66), ///< CMTW1 Input capture of register 1
FSP_SIGNAL_CMTW1_OC0I = (67), ///< CMTW1 Output compare of register 0
FSP_SIGNAL_CMTW1_OC1I = (68), ///< CMTW1 Output compare of register 1
FSP_SIGNAL_TGIA0 = (69), ///< MTU0.TGRA input capture/compare match
FSP_SIGNAL_TGIB0 = (70), ///< MTU0.TGRB input capture/compare match
FSP_SIGNAL_TGIC0 = (71), ///< MTU0.TGRC input capture/compare match
FSP_SIGNAL_TGID0 = (72), ///< MTU0.TGRD input capture/compare match
FSP_SIGNAL_TCIV0 = (73), ///< MTU0.TCNT overflow
FSP_SIGNAL_TGIE0 = (74), ///< MTU0.TGRE compare match
FSP_SIGNAL_TGIF0 = (75), ///< MTU0.TGRF compare match
FSP_SIGNAL_TGIA1 = (76), ///< MTU1.TGRA input capture/compare match
FSP_SIGNAL_TGIB1 = (77), ///< MTU1.TGRB input capture/compare match
FSP_SIGNAL_TCIV1 = (78), ///< MTU1.TCNT overflow
FSP_SIGNAL_TCIU1 = (79), ///< MTU1.TCNT underflow
FSP_SIGNAL_TGIA2 = (80), ///< MTU2.TGRA input capture/compare match
FSP_SIGNAL_TGIB2 = (81), ///< MTU2.TGRB input capture/compare match
FSP_SIGNAL_TCIV2 = (82), ///< MTU2.TCNT overflow
FSP_SIGNAL_TCIU2 = (83), ///< MTU2.TCNT underflow
FSP_SIGNAL_TGIA3 = (84), ///< MTU3.TGRA input capture/compare match
FSP_SIGNAL_TGIB3 = (85), ///< MTU3.TGRB input capture/compare match
FSP_SIGNAL_TGIC3 = (86), ///< MTU3.TGRC input capture/compare match
FSP_SIGNAL_TGID3 = (87), ///< MTU3.TGRD input capture/compare match
FSP_SIGNAL_TCIV3 = (88), ///< MTU3.TCNT overflow
FSP_SIGNAL_TGIA4 = (89), ///< MTU4.TGRA input capture/compare match
FSP_SIGNAL_TGIB4 = (90), ///< MTU4.TGRB input capture/compare match
FSP_SIGNAL_TGIC4 = (91), ///< MTU4.TGRC input capture/compare match
FSP_SIGNAL_TGID4 = (92), ///< MTU4.TGRD input capture/compare match
FSP_SIGNAL_TCIV4 = (93), ///< MTU4.TCNT overflow/underflow
FSP_SIGNAL_TGIU5 = (94), ///< MTU5.TGRU input capture/compare match
FSP_SIGNAL_TGIV5 = (95), ///< MTU5.TGRV input capture/compare match
FSP_SIGNAL_TGIW5 = (96), ///< MTU5.TGRW input capture/compare match
FSP_SIGNAL_TGIA6 = (97), ///< MTU6.TGRA input capture/compare match
FSP_SIGNAL_TGIB6 = (98), ///< MTU6.TGRB input capture/compare match
FSP_SIGNAL_TGIC6 = (99), ///< MTU6.TGRC input capture/compare match
FSP_SIGNAL_TGID6 = (100), ///< MTU6.TGRD input capture/compare match
FSP_SIGNAL_TCIV6 = (101), ///< MTU6.TCNT overflow
FSP_SIGNAL_TGIA7 = (102), ///< MTU7.TGRA input capture/compare match
FSP_SIGNAL_TGIB7 = (103), ///< MTU7.TGRB input capture/compare match
FSP_SIGNAL_TGIC7 = (104), ///< MTU7.TGRC input capture/compare match
FSP_SIGNAL_TGID7 = (105), ///< MTU7.TGRD input capture/compare match
FSP_SIGNAL_TCIV7 = (106), ///< MTU7.TCNT overflow/underflow
FSP_SIGNAL_TGIA8 = (107), ///< MTU8.TGRA input capture/compare match
FSP_SIGNAL_TGIB8 = (108), ///< MTU8.TGRB input capture/compare match
FSP_SIGNAL_TGIC8 = (109), ///< MTU8.TGRC input capture/compare match
FSP_SIGNAL_TGID8 = (110), ///< MTU8.TGRD input capture/compare match
FSP_SIGNAL_TCIV8 = (111), ///< MTU8.TCNT overflow
FSP_SIGNAL_OEI1 = (112), ///< Output enable interrupt 1
FSP_SIGNAL_OEI2 = (113), ///< Output enable interrupt 2
FSP_SIGNAL_OEI3 = (114), ///< Output enable interrupt 3
FSP_SIGNAL_OEI4 = (115), ///< Output enable interrupt 4
FSP_SIGNAL_GPT0_CCMPA = (116), ///< GPT0 GTCCRA input capture/compare match
FSP_SIGNAL_GPT0_CCMPB = (117), ///< GPT0 GTCCRB input capture/compare match
FSP_SIGNAL_GPT0_CMPC = (118), ///< GPT0 GTCCRC compare match
FSP_SIGNAL_GPT0_CMPD = (119), ///< GPT0 GTCCRD compare match
FSP_SIGNAL_GPT0_CMPE = (120), ///< GPT0 GTCCRE compare match
FSP_SIGNAL_GPT0_CMPF = (121), ///< GPT0 GTCCRF compare match
FSP_SIGNAL_GPT0_OVF = (122), ///< GPT0 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT0_UDF = (123), ///< GPT0 GTCNT underflow
FSP_SIGNAL_GPT0_DTE = (124), ///< GPT0 Dead time error
FSP_SIGNAL_GPT1_CCMPA = (125), ///< GPT1 GTCCRA input capture/compare match
FSP_SIGNAL_GPT1_CCMPB = (126), ///< GPT1 GTCCRB input capture/compare match
FSP_SIGNAL_GPT1_CMPC = (127), ///< GPT1 GTCCRC compare match
FSP_SIGNAL_GPT1_CMPD = (128), ///< GPT1 GTCCRD compare match
FSP_SIGNAL_GPT1_CMPE = (129), ///< GPT1 GTCCRE compare match
FSP_SIGNAL_GPT1_CMPF = (130), ///< GPT1 GTCCRF compare match
FSP_SIGNAL_GPT1_OVF = (131), ///< GPT1 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT1_UDF = (132), ///< GPT1 GTCNT underflow
FSP_SIGNAL_GPT1_DTE = (133), ///< GPT1 Dead time error
FSP_SIGNAL_GPT2_CCMPA = (134), ///< GPT2 GTCCRA input capture/compare match
FSP_SIGNAL_GPT2_CCMPB = (135), ///< GPT2 GTCCRB input capture/compare match
FSP_SIGNAL_GPT2_CMPC = (136), ///< GPT2 GTCCRC compare match
FSP_SIGNAL_GPT2_CMPD = (137), ///< GPT2 GTCCRD compare match
FSP_SIGNAL_GPT2_CMPE = (138), ///< GPT2 GTCCRE compare match
FSP_SIGNAL_GPT2_CMPF = (139), ///< GPT2 GTCCRF compare match
FSP_SIGNAL_GPT2_OVF = (140), ///< GPT2 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT2_UDF = (141), ///< GPT2 GTCNT underflow
FSP_SIGNAL_GPT2_DTE = (142), ///< GPT2 Dead time error
FSP_SIGNAL_GPT3_CCMPA = (143), ///< GPT3 GTCCRA input capture/compare match
FSP_SIGNAL_GPT3_CCMPB = (144), ///< GPT3 GTCCRB input capture/compare match
FSP_SIGNAL_GPT3_CMPC = (145), ///< GPT3 GTCCRC compare match
FSP_SIGNAL_GPT3_CMPD = (146), ///< GPT3 GTCCRD compare match
FSP_SIGNAL_GPT3_CMPE = (147), ///< GPT3 GTCCRE compare match
FSP_SIGNAL_GPT3_CMPF = (148), ///< GPT3 GTCCRF compare match
FSP_SIGNAL_GPT3_OVF = (149), ///< GPT3 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT3_UDF = (150), ///< GPT3 GTCNT underflow
FSP_SIGNAL_GPT3_DTE = (151), ///< GPT3 Dead time error
FSP_SIGNAL_GPT4_CCMPA = (152), ///< GPT4 GTCCRA input capture/compare match
FSP_SIGNAL_GPT4_CCMPB = (153), ///< GPT4 GTCCRB input capture/compare match
FSP_SIGNAL_GPT4_CMPC = (154), ///< GPT4 GTCCRC compare match
FSP_SIGNAL_GPT4_CMPD = (155), ///< GPT4 GTCCRD compare match
FSP_SIGNAL_GPT4_CMPE = (156), ///< GPT4 GTCCRE compare match
FSP_SIGNAL_GPT4_CMPF = (157), ///< GPT4 GTCCRF compare match
FSP_SIGNAL_GPT4_OVF = (158), ///< GPT4 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT4_UDF = (159), ///< GPT4 GTCNT underflow
FSP_SIGNAL_GPT4_DTE = (160), ///< GPT4 Dead time error
FSP_SIGNAL_GPT5_CCMPA = (161), ///< GPT5 GTCCRA input capture/compare match
FSP_SIGNAL_GPT5_CCMPB = (162), ///< GPT5 GTCCRB input capture/compare match
FSP_SIGNAL_GPT5_CMPC = (163), ///< GPT5 GTCCRC compare match
FSP_SIGNAL_GPT5_CMPD = (164), ///< GPT5 GTCCRD compare match
FSP_SIGNAL_GPT5_CMPE = (165), ///< GPT5 GTCCRE compare match
FSP_SIGNAL_GPT5_CMPF = (166), ///< GPT5 GTCCRF compare match
FSP_SIGNAL_GPT5_OVF = (167), ///< GPT5 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT5_UDF = (168), ///< GPT5 GTCNT underflow
FSP_SIGNAL_GPT5_DTE = (169), ///< GPT5 Dead time error
FSP_SIGNAL_GPT6_CCMPA = (170), ///< GPT6 GTCCRA input capture/compare match
FSP_SIGNAL_GPT6_CCMPB = (171), ///< GPT6 GTCCRB input capture/compare match
FSP_SIGNAL_GPT6_CMPC = (172), ///< GPT6 GTCCRC compare match
FSP_SIGNAL_GPT6_CMPD = (173), ///< GPT6 GTCCRD compare match
FSP_SIGNAL_GPT6_CMPE = (174), ///< GPT6 GTCCRE compare match
FSP_SIGNAL_GPT6_CMPF = (175), ///< GPT6 GTCCRF compare match
FSP_SIGNAL_GPT6_OVF = (176), ///< GPT6 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT6_UDF = (177), ///< GPT6 GTCNT underflow
FSP_SIGNAL_GPT6_DTE = (178), ///< GPT6 Dead time error
FSP_SIGNAL_GPT7_CCMPA = (179), ///< GPT7 GTCCRA input capture/compare match
FSP_SIGNAL_GPT7_CCMPB = (180), ///< GPT7 GTCCRB input capture/compare match
FSP_SIGNAL_GPT7_CMPC = (181), ///< GPT7 GTCCRC compare match
FSP_SIGNAL_GPT7_CMPD = (182), ///< GPT7 GTCCRD compare match
FSP_SIGNAL_GPT7_CMPE = (183), ///< GPT7 GTCCRE compare match
FSP_SIGNAL_GPT7_CMPF = (184), ///< GPT7 GTCCRF compare match
FSP_SIGNAL_GPT7_OVF = (185), ///< GPT7 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT7_UDF = (186), ///< GPT7 GTCNT underflow
FSP_SIGNAL_GPT7_DTE = (187), ///< GPT7 Dead time error
FSP_SIGNAL_GPT8_CCMPA = (188), ///< GPT8 GTCCRA input capture/compare match
FSP_SIGNAL_GPT8_CCMPB = (189), ///< GPT8 GTCCRB input capture/compare match
FSP_SIGNAL_GPT8_CMPC = (190), ///< GPT8 GTCCRC compare match
FSP_SIGNAL_GPT8_CMPD = (191), ///< GPT8 GTCCRD compare match
FSP_SIGNAL_GPT8_CMPE = (192), ///< GPT8 GTCCRE compare match
FSP_SIGNAL_GPT8_CMPF = (193), ///< GPT8 GTCCRF compare match
FSP_SIGNAL_GPT8_OVF = (194), ///< GPT8 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT8_UDF = (195), ///< GPT8 GTCNT underflow
FSP_SIGNAL_GPT8_DTE = (196), ///< GPT8 Dead time error
FSP_SIGNAL_GPT9_CCMPA = (197), ///< GPT9 GTCCRA input capture/compare match
FSP_SIGNAL_GPT9_CCMPB = (198), ///< GPT9 GTCCRB input capture/compare match
FSP_SIGNAL_GPT9_CMPC = (199), ///< GPT9 GTCCRC compare match
FSP_SIGNAL_GPT9_CMPD = (200), ///< GPT9 GTCCRD compare match
FSP_SIGNAL_GPT9_CMPE = (201), ///< GPT9 GTCCRE compare match
FSP_SIGNAL_GPT9_CMPF = (202), ///< GPT9 GTCCRF compare match
FSP_SIGNAL_GPT9_OVF = (203), ///< GPT9 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT9_UDF = (204), ///< GPT9 GTCNT underflow
FSP_SIGNAL_GPT9_DTE = (205), ///< GPT9 Dead time error
FSP_SIGNAL_GPT10_CCMPA = (206), ///< GPT10 GTCCRA input capture/compare match
FSP_SIGNAL_GPT10_CCMPB = (207), ///< GPT10 GTCCRB input capture/compare match
FSP_SIGNAL_GPT10_CMPC = (208), ///< GPT10 GTCCRC compare match
FSP_SIGNAL_GPT10_CMPD = (209), ///< GPT10 GTCCRD compare match
FSP_SIGNAL_GPT10_CMPE = (210), ///< GPT10 GTCCRE compare match
FSP_SIGNAL_GPT10_CMPF = (211), ///< GPT10 GTCCRF compare match
FSP_SIGNAL_GPT10_OVF = (212), ///< GPT10 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT10_UDF = (213), ///< GPT10 GTCNT underflow
FSP_SIGNAL_GPT10_DTE = (214), ///< GPT10 Dead time error
FSP_SIGNAL_GPT11_CCMPA = (215), ///< GPT11 GTCCRA input capture/compare match
FSP_SIGNAL_GPT11_CCMPB = (216), ///< GPT11 GTCCRB input capture/compare match
FSP_SIGNAL_GPT11_CMPC = (217), ///< GPT11 GTCCRC compare match
FSP_SIGNAL_GPT11_CMPD = (218), ///< GPT11 GTCCRD compare match
FSP_SIGNAL_GPT11_CMPE = (219), ///< GPT11 GTCCRE compare match
FSP_SIGNAL_GPT11_CMPF = (220), ///< GPT11 GTCCRF compare match
FSP_SIGNAL_GPT11_OVF = (221), ///< GPT11 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT11_UDF = (222), ///< GPT11 GTCNT underflow
FSP_SIGNAL_GPT11_DTE = (223), ///< GPT11 Dead time error
FSP_SIGNAL_GPT12_CCMPA = (224), ///< GPT12 GTCCRA input capture/compare match
FSP_SIGNAL_GPT12_CCMPB = (225), ///< GPT12 GTCCRB input capture/compare match
FSP_SIGNAL_GPT12_CMPC = (226), ///< GPT12 GTCCRC compare match
FSP_SIGNAL_GPT12_CMPD = (227), ///< GPT12 GTCCRD compare match
FSP_SIGNAL_GPT12_CMPE = (228), ///< GPT12 GTCCRE compare match
FSP_SIGNAL_GPT12_CMPF = (229), ///< GPT12 GTCCRF compare match
FSP_SIGNAL_GPT12_OVF = (230), ///< GPT12 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT12_UDF = (231), ///< GPT12 GTCNT underflow
FSP_SIGNAL_GPT12_DTE = (232), ///< GPT12 Dead time error
FSP_SIGNAL_GPT13_CCMPA = (233), ///< GPT13 GTCCRA input capture/compare match
FSP_SIGNAL_GPT13_CCMPB = (234), ///< GPT13 GTCCRB input capture/compare match
FSP_SIGNAL_GPT13_CMPC = (235), ///< GPT13 GTCCRC compare match
FSP_SIGNAL_GPT13_CMPD = (236), ///< GPT13 GTCCRD compare match
FSP_SIGNAL_GPT13_CMPE = (237), ///< GPT13 GTCCRE compare match
FSP_SIGNAL_GPT13_CMPF = (238), ///< GPT13 GTCCRF compare match
FSP_SIGNAL_GPT13_OVF = (239), ///< GPT13 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT13_UDF = (240), ///< GPT13 GTCNT underflow
FSP_SIGNAL_GPT13_DTE = (241), ///< GPT13 Dead time error
FSP_SIGNAL_POEG0_GROUP0 = (242), ///< POEG group A interrupt for channels in LLPP
FSP_SIGNAL_POEG0_GROUP1 = (243), ///< POEG group B interrupt for channels in LLPP
FSP_SIGNAL_POEG0_GROUP2 = (244), ///< POEG group C interrupt for channels in LLPP
FSP_SIGNAL_POEG0_GROUP3 = (245), ///< POEG group D interrupt for channels in LLPP
FSP_SIGNAL_POEG1_GROUP0 = (246), ///< POEG group A interrupt for channels in NONSAFETY
FSP_SIGNAL_POEG1_GROUP1 = (247), ///< POEG group B interrupt for channels in NONSAFETY
FSP_SIGNAL_POEG1_GROUP2 = (248), ///< POEG group C interrupt for channels in NONSAFETY
FSP_SIGNAL_POEG1_GROUP3 = (249), ///< POEG group D interrupt for channels in NONSAFETY
FSP_SIGNAL_GMAC_LPI = (250), ///< GMAC1 energy efficient
FSP_SIGNAL_GMAC_PMT = (251), ///< GMAC1 power management
FSP_SIGNAL_GMAC_SBD = (252), ///< GMAC1 general interrupt
FSP_SIGNAL_ETHSW_INTR = (253), ///< Ethernet Switch interrupt
FSP_SIGNAL_ETHSW_DLR = (254), ///< Ethernet Switch DLR interrupt
FSP_SIGNAL_ETHSW_PRP = (255), ///< Ethernet Switch PRP interrupt
FSP_SIGNAL_ETHSW_IHUB = (256), ///< Ethernet Switch Integrated Hub interrupt
FSP_SIGNAL_ETHSW_PTRN0 = (257), ///< Ethernet Switch RX Pattern Matcher interrupt 0
FSP_SIGNAL_ETHSW_PTRN1 = (258), ///< Ethernet Switch RX Pattern Matcher interrupt 1
FSP_SIGNAL_ETHSW_PTRN2 = (259), ///< Ethernet Switch RX Pattern Matcher interrupt 2
FSP_SIGNAL_ETHSW_PTRN3 = (260), ///< Ethernet Switch RX Pattern Matcher interrupt 3
FSP_SIGNAL_ETHSW_PTRN4 = (261), ///< Ethernet Switch RX Pattern Matcher interrupt 4
FSP_SIGNAL_ETHSW_PTRN5 = (262), ///< Ethernet Switch RX Pattern Matcher interrupt 5
FSP_SIGNAL_ETHSW_PTRN6 = (263), ///< Ethernet Switch RX Pattern Matcher interrupt 6
FSP_SIGNAL_ETHSW_PTRN7 = (264), ///< Ethernet Switch RX Pattern Matcher interrupt 7
FSP_SIGNAL_ETHSW_PTRN8 = (265), ///< Ethernet Switch RX Pattern Matcher interrupt 8
FSP_SIGNAL_ETHSW_PTRN9 = (266), ///< Ethernet Switch RX Pattern Matcher interrupt 9
FSP_SIGNAL_ETHSW_PTRN10 = (267), ///< Ethernet Switch RX Pattern Matcher interrupt 10
FSP_SIGNAL_ETHSW_PTRN11 = (268), ///< Ethernet Switch RX Pattern Matcher interrupt 11
FSP_SIGNAL_ETHSW_PTPOUT0 = (269), ///< Ethernet switch timer pulse output 0
FSP_SIGNAL_ETHSW_PTPOUT1 = (270), ///< Ethernet switch timer pulse output 1
FSP_SIGNAL_ETHSW_PTPOUT2 = (271), ///< Ethernet switch timer pulse output 2
FSP_SIGNAL_ETHSW_PTPOUT3 = (272), ///< Ethernet switch timer pulse output 3
FSP_SIGNAL_ETHSW_TDMAOUT0 = (273), ///< Ethernet Switch TDMA timer output 0
FSP_SIGNAL_ETHSW_TDMAOUT1 = (274), ///< Ethernet Switch TDMA timer output 1
FSP_SIGNAL_ETHSW_TDMAOUT2 = (275), ///< Ethernet Switch TDMA timer output 2
FSP_SIGNAL_ETHSW_TDMAOUT3 = (276), ///< Ethernet Switch TDMA timer output 3
FSP_SIGNAL_ESC_SYNC0 = (277), ///< EtherCAT Sync0 interrupt
FSP_SIGNAL_ESC_SYNC1 = (278), ///< EtherCAT Sync1 interrupt
FSP_SIGNAL_ESC_CAT = (279), ///< EtherCAT interrupt
FSP_SIGNAL_ESC_SOF = (280), ///< EtherCAT SOF interrupt
FSP_SIGNAL_ESC_EOF = (281), ///< EtherCAT EOF interrupt
FSP_SIGNAL_ESC_WDT = (282), ///< EtherCAT WDT interrupt
FSP_SIGNAL_ESC_RST = (283), ///< EtherCAT RESET interrupt
FSP_SIGNAL_USB_HI = (284), ///< USB (Host) interrupt
FSP_SIGNAL_USB_FI = (285), ///< USB (Function) interrupt
FSP_SIGNAL_USB_FDMA0 = (286), ///< USB (Function) DMA 0 transmit completion
FSP_SIGNAL_USB_FDMA1 = (287), ///< USB (Function) DMA 1 transmit completion
FSP_SIGNAL_SCI0_ERI = (288), ///< SCI0 Receive error
FSP_SIGNAL_SCI0_RXI = (289), ///< SCI0 Receive data full
FSP_SIGNAL_SCI0_TXI = (290), ///< SCI0 Transmit data empty
FSP_SIGNAL_SCI0_TEI = (291), ///< SCI0 Transmit end
FSP_SIGNAL_SCI1_ERI = (292), ///< SCI1 Receive error
FSP_SIGNAL_SCI1_RXI = (293), ///< SCI1 Receive data full
FSP_SIGNAL_SCI1_TXI = (294), ///< SCI1 Transmit data empty
FSP_SIGNAL_SCI1_TEI = (295), ///< SCI1 Transmit end
FSP_SIGNAL_SCI2_ERI = (296), ///< SCI2 Receive error
FSP_SIGNAL_SCI2_RXI = (297), ///< SCI2 Receive data full
FSP_SIGNAL_SCI2_TXI = (298), ///< SCI2 Transmit data empty
FSP_SIGNAL_SCI2_TEI = (299), ///< SCI2 Transmit end
FSP_SIGNAL_SCI3_ERI = (300), ///< SCI3 Receive error
FSP_SIGNAL_SCI3_RXI = (301), ///< SCI3 Receive data full
FSP_SIGNAL_SCI3_TXI = (302), ///< SCI3 Transmit data empty
FSP_SIGNAL_SCI3_TEI = (303), ///< SCI3 Transmit end
FSP_SIGNAL_SCI4_ERI = (304), ///< SCI4 Receive error
FSP_SIGNAL_SCI4_RXI = (305), ///< SCI4 Receive data full
FSP_SIGNAL_SCI4_TXI = (306), ///< SCI4 Transmit data empty
FSP_SIGNAL_SCI4_TEI = (307), ///< SCI4 Transmit end
FSP_SIGNAL_IIC0_EEI = (308), ///< IIC0 Transfer error or event generation
FSP_SIGNAL_IIC0_RXI = (309), ///< IIC0 Receive data full
FSP_SIGNAL_IIC0_TXI = (310), ///< IIC0 Transmit data empty
FSP_SIGNAL_IIC0_TEI = (311), ///< IIC0 Transmit end
FSP_SIGNAL_IIC1_EEI = (312), ///< IIC1 Transfer error or event generation
FSP_SIGNAL_IIC1_RXI = (313), ///< IIC1 Receive data full
FSP_SIGNAL_IIC1_TXI = (314), ///< IIC1 Transmit data empty
FSP_SIGNAL_IIC1_TEI = (315), ///< IIC1 Transmit end
FSP_SIGNAL_CAN_RXF = (316), ///< CANFD RX FIFO interrupt
FSP_SIGNAL_CAN_GLERR = (317), ///< CANFD Global error interrupt
FSP_SIGNAL_CAN0_TX = (318), ///< CAFND0 Channel TX interrupt
FSP_SIGNAL_CAN0_CHERR = (319), ///< CAFND0 Channel CAN error interrupt
FSP_SIGNAL_CAN0_COMFRX = (320), ///< CAFND0 Common RX FIFO or TXQ interrupt
FSP_SIGNAL_CAN1_TX = (321), ///< CAFND1 Channel TX interrupt
FSP_SIGNAL_CAN1_CHERR = (322), ///< CAFND1 Channel CAN error interrupt
FSP_SIGNAL_CAN1_COMFRX = (323), ///< CAFND1 Common RX FIFO or TXQ interrupt
FSP_SIGNAL_SPI0_SPRI = (324), ///< SPI0 Reception buffer full
FSP_SIGNAL_SPI0_SPTI = (325), ///< SPI0 Transmit buffer empty
FSP_SIGNAL_SPI0_SPII = (326), ///< SPI0 SPI idle
FSP_SIGNAL_SPI0_SPEI = (327), ///< SPI0 errors
FSP_SIGNAL_SPI0_SPCEND = (328), ///< SPI0 Communication complete
FSP_SIGNAL_SPI1_SPRI = (329), ///< SPI1 Reception buffer full
FSP_SIGNAL_SPI1_SPTI = (330), ///< SPI1 Transmit buffer empty
FSP_SIGNAL_SPI1_SPII = (331), ///< SPI1 SPI idle
FSP_SIGNAL_SPI1_SPEI = (332), ///< SPI1 errors
FSP_SIGNAL_SPI1_SPCEND = (333), ///< SPI1 Communication complete
FSP_SIGNAL_SPI2_SPRI = (334), ///< SPI2 Reception buffer full
FSP_SIGNAL_SPI2_SPTI = (335), ///< SPI2 Transmit buffer empty
FSP_SIGNAL_SPI2_SPII = (336), ///< SPI2 SPI idle
FSP_SIGNAL_SPI2_SPEI = (337), ///< SPI2 errors
FSP_SIGNAL_SPI2_SPCEND = (338), ///< SPI2 Communication complete
FSP_SIGNAL_XSPI0_INT = (339), ///< xSPI0 Interrupt
FSP_SIGNAL_XSPI0_INTERR = (340), ///< xSPI0 Error interrupt
FSP_SIGNAL_XSPI1_INT = (341), ///< xSPI1 Interrupt
FSP_SIGNAL_XSPI1_INTERR = (342), ///< xSPI1 Error interrupt
FSP_SIGNAL_DSMIF0_CDRUI = (343), ///< DSMIF0 current data register update (ORed ch0 to ch2)
FSP_SIGNAL_DSMIF1_CDRUI = (344), ///< DSMIF1 current data register update (ORed ch3 to ch5)
FSP_SIGNAL_ADC0_ADI = (345), ///< ADC0 A/D scan end interrupt
FSP_SIGNAL_ADC0_GBADI = (346), ///< ADC0 A/D scan end interrupt for Group B
FSP_SIGNAL_ADC0_GCADI = (347), ///< ADC0 A/D scan end interrupt for Group C
FSP_SIGNAL_ADC0_CMPAI = (348), ///< ADC0 Window A compare match
FSP_SIGNAL_ADC0_CMPBI = (349), ///< ADC0 Window B compare match
FSP_SIGNAL_ADC1_ADI = (350), ///< ADC1 A/D scan end interrupt
FSP_SIGNAL_ADC1_GBADI = (351), ///< ADC1 A/D scan end interrupt for Group B
FSP_SIGNAL_ADC1_GCADI = (352), ///< ADC1 A/D scan end interrupt for Group C
FSP_SIGNAL_ADC1_CMPAI = (353), ///< ADC1 Window A compare match
FSP_SIGNAL_ADC1_CMPBI = (354), ///< ADC1 Window B compare match
FSP_SIGNAL_MBX_INT0 = (372), ///< Mailbox (Host CPU to Cortex-R52) interrupt 0
FSP_SIGNAL_MBX_INT1 = (373), ///< Mailbox (Host CPU to Cortex-R52) interrupt 1
FSP_SIGNAL_MBX_INT2 = (374), ///< Mailbox (Host CPU to Cortex-R52) interrupt 2
FSP_SIGNAL_MBX_INT3 = (375), ///< Mailbox (Host CPU to Cortex-R52) interrupt 3
FSP_SIGNAL_CPU0_ERR0 = (384), ///< Cortex-R52 CPU0 error event 0
FSP_SIGNAL_CPU0_ERR1 = (385), ///< Cortex-R52 CPU0 error event 1
FSP_SIGNAL_PERI_ERR0 = (388), ///< Peripherals error event 0
FSP_SIGNAL_PERI_ERR1 = (389), ///< Peripherals error event 1
FSP_SIGNAL_SHOST_INT = (390), ///< SHOSTIF interrupt
FSP_SIGNAL_PHOST_INT = (391), ///< PHOSTIF interrupt
FSP_SIGNAL_INTCPU6 = (392), ///< Software interrupt 6
FSP_SIGNAL_INTCPU7 = (393), ///< Software interrupt 7
FSP_SIGNAL_IRQ14 = (394), ///< External pin interrupt 14
FSP_SIGNAL_IRQ15 = (395), ///< External pin interrupt 15
FSP_SIGNAL_GPT14_CCMPA = (396), ///< GPT14 GTCCRA input capture/compare match
FSP_SIGNAL_GPT14_CCMPB = (397), ///< GPT14 GTCCRB input capture/compare match
FSP_SIGNAL_GPT14_CMPC = (398), ///< GPT14 GTCCRC compare match
FSP_SIGNAL_GPT14_CMPD = (399), ///< GPT14 GTCCRD compare match
FSP_SIGNAL_GPT14_CMPE = (400), ///< GPT14 GTCCRE compare match
FSP_SIGNAL_GPT14_CMPF = (401), ///< GPT14 GTCCRF compare match
FSP_SIGNAL_GPT14_OVF = (402), ///< GPT14 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT14_UDF = (403), ///< GPT14 GTCNT underflow
FSP_SIGNAL_GPT15_CCMPA = (404), ///< GPT15 GTCCRA input capture/compare match
FSP_SIGNAL_GPT15_CCMPB = (405), ///< GPT15 GTCCRB input capture/compare match
FSP_SIGNAL_GPT15_CMPC = (406), ///< GPT15 GTCCRC compare match
FSP_SIGNAL_GPT15_CMPD = (407), ///< GPT15 GTCCRD compare match
FSP_SIGNAL_GPT15_CMPE = (408), ///< GPT15 GTCCRE compare match
FSP_SIGNAL_GPT15_CMPF = (409), ///< GPT15 GTCCRF compare match
FSP_SIGNAL_GPT15_OVF = (410), ///< GPT15 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT15_UDF = (411), ///< GPT15 GTCNT underflow
FSP_SIGNAL_GPT16_CCMPA = (412), ///< GPT16 GTCCRA input capture/compare match
FSP_SIGNAL_GPT16_CCMPB = (413), ///< GPT16 GTCCRB input capture/compare match
FSP_SIGNAL_GPT16_CMPC = (414), ///< GPT16 GTCCRC compare match
FSP_SIGNAL_GPT16_CMPD = (415), ///< GPT16 GTCCRD compare match
FSP_SIGNAL_GPT16_CMPE = (416), ///< GPT16 GTCCRE compare match
FSP_SIGNAL_GPT16_CMPF = (417), ///< GPT16 GTCCRF compare match
FSP_SIGNAL_GPT16_OVF = (418), ///< GPT16 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT16_UDF = (419), ///< GPT16 GTCNT underflow
FSP_SIGNAL_GPT17_CCMPA = (420), ///< GPT17 GTCCRA input capture/compare match
FSP_SIGNAL_GPT17_CCMPB = (421), ///< GPT17 GTCCRB input capture/compare match
FSP_SIGNAL_GPT17_CMPC = (422), ///< GPT17 GTCCRC compare match
FSP_SIGNAL_GPT17_CMPD = (423), ///< GPT17 GTCCRD compare match
FSP_SIGNAL_GPT17_CMPE = (424), ///< GPT17 GTCCRE compare match
FSP_SIGNAL_GPT17_CMPF = (425), ///< GPT17 GTCCRF compare match
FSP_SIGNAL_GPT17_OVF = (426), ///< GPT17 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT17_UDF = (427), ///< GPT17 GTCNT underflow
FSP_SIGNAL_POEG2_GROUP0 = (428), ///< POEG group A interrupt for channels in SAFETY
FSP_SIGNAL_POEG2_GROUP1 = (429), ///< POEG group B interrupt for channels in SAFETY
FSP_SIGNAL_POEG2_GROUP2 = (430), ///< POEG group C interrupt for channels in SAFETY
FSP_SIGNAL_POEG2_GROUP3 = (431), ///< POEG group D interrupt for channels in SAFETY
FSP_SIGNAL_RTC_ALM = (432), ///< Alarm interrupt
FSP_SIGNAL_RTC_1S = (433), ///< 1 second interrupt
FSP_SIGNAL_RTC_PRD = (434), ///< Fixed interval interrupt
FSP_SIGNAL_SCI5_ERI = (435), ///< SCI5 Receive error
FSP_SIGNAL_SCI5_RXI = (436), ///< SCI5 Receive data full
FSP_SIGNAL_SCI5_TXI = (437), ///< SCI5 Transmit data empty
FSP_SIGNAL_SCI5_TEI = (438), ///< SCI5 Transmit end
FSP_SIGNAL_IIC2_EEI = (439), ///< IIC2 Transfer error or event generation
FSP_SIGNAL_IIC2_RXI = (440), ///< IIC2 Receive data full
FSP_SIGNAL_IIC2_TXI = (441), ///< IIC2 Transmit data empty
FSP_SIGNAL_IIC2_TEI = (442), ///< IIC2 Transmit end
FSP_SIGNAL_SPI3_SPRI = (443), ///< SPI3 Reception buffer full
FSP_SIGNAL_SPI3_SPTI = (444), ///< SPI3 Transmit buffer empty
FSP_SIGNAL_SPI3_SPII = (445), ///< SPI3 SPI idle
FSP_SIGNAL_SPI3_SPEI = (446), ///< SPI3 errors
FSP_SIGNAL_SPI3_SPCEND = (447), ///< SPI3 Communication complete
FSP_SIGNAL_DREQ = (448), ///< External DMA request
FSP_SIGNAL_CAN_RF_DMAREQ0 = (449), ///< CAFND RX FIFO 0 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ1 = (450), ///< CAFND RX FIFO 1 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ2 = (451), ///< CAFND RX FIFO 2 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ3 = (452), ///< CAFND RX FIFO 3 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ4 = (453), ///< CAFND RX FIFO 4 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ5 = (454), ///< CAFND RX FIFO 5 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ6 = (455), ///< CAFND RX FIFO 6 DMA request
FSP_SIGNAL_CAN_RF_DMAREQ7 = (456), ///< CAFND RX FIFO 7 DMA request
FSP_SIGNAL_CAN0_CF_DMAREQ = (457), ///< CAFND0 First common FIFO DMA request
FSP_SIGNAL_CAN1_CF_DMAREQ = (458), ///< CAFND1 First common FIFO DMA request
FSP_SIGNAL_ADC0_WCMPM = (459), ///< ADC0 compare match
FSP_SIGNAL_ADC0_WCMPUM = (460), ///< ADC0 compare mismatch
FSP_SIGNAL_ADC1_WCMPM = (461), ///< ADC1 compare match
FSP_SIGNAL_ADC1_WCMPUM = (462), ///< ADC1 compare mismatch
FSP_SIGNAL_TCIV4_OF = (463), ///< MTU4.TCNT overflow
FSP_SIGNAL_TCIV4_UF = (464), ///< MTU4.TCNT underflow
FSP_SIGNAL_TCIV7_OF = (465), ///< MTU7.TCNT overflow
FSP_SIGNAL_TCIV7_UF = (466), ///< MTU7.TCNT underflow
FSP_SIGNAL_IOPORT_GROUP1 = (467), ///< Input edge detection of input port group 1
FSP_SIGNAL_IOPORT_GROUP2 = (468), ///< Input edge detection of input port group 2
FSP_SIGNAL_IOPORT_SINGLE0 = (469), ///< Input edge detection of single input port 0
FSP_SIGNAL_IOPORT_SINGLE1 = (470), ///< Input edge detection of single input port 1
FSP_SIGNAL_IOPORT_SINGLE2 = (471), ///< Input edge detection of single input port 2
FSP_SIGNAL_IOPORT_SINGLE3 = (472), ///< Input edge detection of single input port 3
FSP_SIGNAL_GPT0_ADTRGA = (473), ///< GPT0 GTADTRA compare match
FSP_SIGNAL_GPT0_ADTRGB = (474), ///< GPT0 GTADTRB compare match
FSP_SIGNAL_GPT1_ADTRGA = (475), ///< GPT1 GTADTRA compare match
FSP_SIGNAL_GPT1_ADTRGB = (476), ///< GPT1 GTADTRB compare match
FSP_SIGNAL_GPT2_ADTRGA = (477), ///< GPT2 GTADTRA compare match
FSP_SIGNAL_GPT2_ADTRGB = (478), ///< GPT2 GTADTRB compare match
FSP_SIGNAL_GPT3_ADTRGA = (479), ///< GPT3 GTADTRA compare match
FSP_SIGNAL_GPT3_ADTRGB = (480), ///< GPT3 GTADTRB compare match
FSP_SIGNAL_GPT4_ADTRGA = (481), ///< GPT4 GTADTRA compare match
FSP_SIGNAL_GPT4_ADTRGB = (482), ///< GPT4 GTADTRB compare match
FSP_SIGNAL_GPT5_ADTRGA = (483), ///< GPT5 GTADTRA compare match
FSP_SIGNAL_GPT5_ADTRGB = (484), ///< GPT5 GTADTRB compare match
FSP_SIGNAL_GPT6_ADTRGA = (485), ///< GPT6 GTADTRA compare match
FSP_SIGNAL_GPT6_ADTRGB = (486), ///< GPT6 GTADTRB compare match
FSP_SIGNAL_GPT7_ADTRGA = (487), ///< GPT7 GTADTRA compare match
FSP_SIGNAL_GPT7_ADTRGB = (488), ///< GPT7 GTADTRB compare match
FSP_SIGNAL_GPT8_ADTRGA = (489), ///< GPT8 GTADTRA compare match
FSP_SIGNAL_GPT8_ADTRGB = (490), ///< GPT8 GTADTRB compare match
FSP_SIGNAL_GPT9_ADTRGA = (491), ///< GPT9 GTADTRA compare match
FSP_SIGNAL_GPT9_ADTRGB = (492), ///< GPT9 GTADTRB compare match
FSP_SIGNAL_GPT10_ADTRGA = (493), ///< GPT10 GTADTRA compare match
FSP_SIGNAL_GPT10_ADTRGB = (494), ///< GPT10 GTADTRB compare match
FSP_SIGNAL_GPT11_ADTRGA = (495), ///< GPT11 GTADTRA compare match
FSP_SIGNAL_GPT11_ADTRGB = (496), ///< GPT11 GTADTRB compare match
FSP_SIGNAL_GPT12_ADTRGA = (497), ///< GPT12 GTADTRA compare match
FSP_SIGNAL_GPT12_ADTRGB = (498), ///< GPT12 GTADTRB compare match
FSP_SIGNAL_GPT13_ADTRGA = (499), ///< GPT13 GTADTRA compare match
FSP_SIGNAL_GPT13_ADTRGB = (500), ///< GPT13 GTADTRB compare match
FSP_SIGNAL_NONE
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (2U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (0U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("2.0.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with RZ/N Flexible Software Package version 2.0.0")
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** FSP Pack version structure */
typedef union st_fsp_pack_version
{
/** Version id */
uint32_t version_id;
/** Code version parameters, little endian order. */
struct version_id_b_s
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
} version_id_b;
} fsp_pack_version_t;
/** @} */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_H
#define R_IOPORT_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "r_ioport_api.h"
#include "r_ioport_cfg.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define IOPORT_SINGLE_PORT_NUM (4)
#define IOPORT_PORT_GROUP_NUM (2)
#define IOPORT_PORT_GROUP_1 (0)
#define IOPORT_PORT_GROUP_2 (1)
#define IOPORT_SINGLE_PORT_0 (0)
#define IOPORT_SINGLE_PORT_1 (1)
#define IOPORT_SINGLE_PORT_2 (2)
#define IOPORT_SINGLE_PORT_3 (3)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Pin selection for port group
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_pin_selection
{
IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group
IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group
} ioport_event_pin_selection_t;
/** Port group operation
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_output_operation
{
IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation
} ioport_event_output_operation_t;
/** Input port group event control
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_control
{
IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link
IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link
} ioport_event_control_t;
/** Single port event direction
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_direction
{
IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port
IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port
} ioport_event_direction_t;
/** Input event edge detection
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_detection
{
IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event
IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event
IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event
} ioport_event_detection_t;
/** Initial value for buffer register
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_initial_buffer_value
{
IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low input to initial value of buffer register for input port group
IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high input to initial value of buffer register for input port group
} ioport_event_initial_buffer_value_t;
/** Single port configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_single
{
ioport_event_control_t event_control; ///< Event link control for single port
ioport_event_direction_t direction; ///< Event direction for single port
uint16_t port_num; ///< Port number specified to single port
ioport_event_output_operation_t operation; ///< Single port operation select
ioport_event_detection_t edge_detection; ///< Edge detection select
} ioport_event_single_t;
/** Output port group configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_group_output
{
uint8_t pin_select; ///< Port number specified to output port group
ioport_event_output_operation_t operation; ///< Port group operation select
} ioport_event_group_output_t;
/** Input port group configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_group_input
{
ioport_event_control_t event_control; ///< Event link control for input port group
ioport_event_detection_t edge_detection; ///< Edge detection select
ioport_event_control_t overwrite_control; ///< Buffer register overwrite control
uint8_t pin_select; ///< Port number specified to input port group
uint8_t buffer_init_value; ///< Buffer register initial value
} ioport_event_group_input_t;
/** IOPORT extended configuration for event link function
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_extend_cfg
{
ioport_event_group_output_t port_group_output_cfg[IOPORT_PORT_GROUP_NUM]; ///< Output port group configuration
ioport_event_group_input_t port_group_input_cfg[IOPORT_PORT_GROUP_NUM]; ///< Input port group configuration
ioport_event_single_t single_port_cfg[IOPORT_SINGLE_PORT_NUM]; ///< Single input port configuration
} ioport_extend_cfg_t;
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
typedef struct st_ioport_instance_ctrl
{
uint32_t open; // Whether or not ioport is open
void const * p_context; // Pointer to context to be passed into callback
ioport_cfg_t const * p_cfg; // Pointer to the configuration block
} ioport_instance_ctrl_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const ioport_api_t g_ioport_on_ioport;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask);
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif // R_IOPORT_H

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SCI_UART_H
#define R_SCI_UART_H
/*******************************************************************************************************************//**
* @addtogroup SCI_UART
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_uart_api.h"
#include "r_sci_uart_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Enumeration for SCI clock source */
typedef enum e_sci_uart_clock
{
SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
} sci_uart_clock_t;
/** UART flow control mode definition */
typedef enum e_sci_uart_flow_control
{
SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS
SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS
SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS
SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS
} sci_uart_flow_control_t;
/** UART instance control block. */
typedef struct st_sci_uart_instance_ctrl
{
/* Parameters to control UART peripheral device */
uint8_t fifo_depth; // FIFO depth of the UART channel
uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
uint32_t open; // Used to determine if the channel is configured
bsp_io_port_pin_t flow_pin;
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint8_t const * p_tx_src;
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint32_t tx_src_bytes;
/* Destination buffer pointer used for receiving data. */
uint8_t const * p_rx_dest;
/* Size of destination buffer pointer used for receiving data. */
uint32_t rx_dest_bytes;
/* Pointer to the configuration block. */
uart_cfg_t const * p_cfg;
/* Base register for this channel */
R_SCI0_Type * p_reg;
void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_uart_instance_ctrl_t;
/** Receive FIFO trigger configuration. */
typedef enum e_sci_uart_rx_fifo_trigger
{
SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_uart_start_bit
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
} sci_uart_start_bit_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
{
SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8
} sci_uart_noise_cancellation_t;
/** RS-485 Enable/Disable. */
typedef enum e_sci_uart_rs485_enable
{
SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
} sci_uart_rs485_enable_t;
/** The polarity of the RS-485 DE signal. */
typedef enum e_sci_uart_rs485_de_polarity
{
SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
} sci_uart_rs485_de_polarity_t;
/** Source clock selection options for SCI. */
typedef enum e_sci_uart_clock_source
{
SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0,
SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1,
SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2,
SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3,
SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4,
SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5,
SCI_UART_CLOCK_SOURCE_PCLKM = 6,
} sci_uart_clock_source_t;
/** Baudrate calculation configuration. */
typedef struct st_sci_uart_baud_calculation
{
uint32_t baudrate; ///< Target baudrate
bool bitrate_modulation; ///< Whether bitrate modulation use or not
uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error
} sci_uart_baud_calculation_t;
/** Register settings to achieve a desired baud rate and modulation duty. */
typedef struct st_sci_baud_setting_t
{
union
{
uint32_t baudrate_bits;
struct
{
uint32_t : 4;
uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select
uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
uint32_t : 1;
uint32_t brr : 8; ///< Bit Rate Register setting
uint32_t brme : 1; ///< Bit Rate Modulation Enable
uint32_t : 3;
uint32_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint32_t : 2;
uint32_t mddr : 8; ///< Modulation Duty Register setting
} baudrate_bits_b;
};
} sci_baud_setting_t;
/** Configuration settings for controlling the DE signal for RS-485. */
typedef struct st_sci_uart_rs485_setting
{
sci_uart_rs485_enable_t enable; ///< Enable the DE signal.
sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer.
uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated.
} sci_uart_rs485_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used.
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_uart_flow_control_t flow_control; ///< CTS/RTS function
sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
/** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */
sci_uart_clock_source_t clock_source;
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const uart_api_t g_uart_on_sci;
/** @endcond */
fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting);
fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl);
fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target,
sci_uart_clock_source_t clock_source,
sci_baud_setting_t * const p_baud_setting);
fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_UART)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/* Ensure Renesas MCU variation definitions are included to ensure MCU
* specific register variations are handled correctly. */
#ifndef BSP_FEATURE_H
#error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
#endif
/** @addtogroup Renesas Electronics Corporation
* @{
*/
/** @addtogroup RZN2
* @{
*/
#ifndef RZN2_H
#define RZN2_H
#ifdef __cplusplus
extern "C" {
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5. */
#if defined(__ICCARM__)
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternative core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8R__) && (__CORE__ == __ARM8R__)
#define __ARM_ARCH_8R__ 1
#else
#error "Unknown target."
#endif
#endif
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */
/** @} */ /* End of group Configuration_of_CMSIS */
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
#if __ARM_ARCH_7EM__
#define RENESAS_CORTEX_M4
#elif __ARM_ARCH_6M__
#define RENESAS_CORTEX_M0PLUS
#elif __ARM_ARCH_8M_BASE__
#define RENESAS_CORTEX_M23
#elif __ARM_ARCH_8M_MAIN__
#define RENESAS_CORTEX_M33
#elif __ARM_ARCH_8R__
#define RENESAS_CORTEX_R52
#else
#warning Unsupported Architecture
#endif
#if BSP_MCU_GROUP_RZN2L
#include "R9A07G084.h"
#else
#warning Unsupported MCU
#endif
#ifdef __cplusplus
}
#endif
#endif /* RZN2_H */
/** @} */ /* End of group RZN2 */
/** @} */ /* End of group Renesas Electronics Corporation */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef SYSTEM_RENESAS_ARM_H
#define SYSTEM_RENESAS_ARM_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_HACTLR_BIT_L (0xB783) /* HACTLR EL1 access enable(0b1011 0111 1000 0011) */
#define BSP_HCR_HCD_DISABLE (0x20000000) /* HCR.HCD = 1 : HVC disable */
#define BSP_MODE_MASK (0x1F) /* Bit mask for mode bits in CPSR */
#define BSP_SVC_MODE (0x13) /* Supervisor mode */
#if defined(__ICCARM__)
#define BSP_IRQ_STACK_END_ADDRESS __section_end(".irq_stack")
#define BSP_FIQ_STACK_END_ADDRESS __section_end(".fiq_stack")
#define BSP_SVC_STACK_END_ADDRESS __section_end(".svc_stack")
#define BSP_ABORT_STACK_END_ADDRESS __section_end(".abt_stack")
#define BSP_UNDEFINED_STACK_END_ADDRESS __section_end(".und_stack")
#define BSP_SYSTEM_STACK_END_ADDRESS __section_end(".sys_stack")
#elif defined(__GNUC__)
#define BSP_IRQ_STACK_END_ADDRESS &__IrqStackLimit
#define BSP_FIQ_STACK_END_ADDRESS &__FiqStackLimit
#define BSP_SVC_STACK_END_ADDRESS &__SvcStackLimit
#define BSP_ABORT_STACK_END_ADDRESS &__AbtStackLimit
#define BSP_UNDEFINED_STACK_END_ADDRESS &__UndStackLimit
#define BSP_SYSTEM_STACK_END_ADDRESS &__SysStackLimit
#endif
#define BSP_IMP_BTCMREGIONR_MASK_L (0x1FFC) /* Masked out BASEADDRESS and ENABLEELx bits(L) */
#define BSP_IMP_BTCMREGIONR_ENABLEEL_L (0x0003) /* Set base address and enable EL2, EL1, EL0 access(L) */
#define BSP_IMP_BTCMREGIONR_ENABLEEL_H (0x0010) /* Set base address and enable EL2, EL1, EL0 access(H) */
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#if defined(__ICCARM__)
#pragma section=".irq_stack"
#pragma section=".fiq_stack"
#pragma section=".svc_stack"
#pragma section=".abt_stack"
#pragma section=".und_stack"
#pragma section=".sys_stack"
#elif defined(__GNUC__)
extern void * __IrqStackLimit;
extern void * __FiqStackLimit;
extern void * __SvcStackLimit;
extern void * __AbtStackLimit;
extern void * __UndStackLimit;
extern void * __SysStackLimit;
#endif
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#if __FPU_USED
extern void bsp_fpu_advancedsimd_init(void);
#endif
extern void bsp_slavetcm_enable(void);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
int32_t main(void);
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init(void) BSP_PLACE_IN_SECTION(".loader_text");
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init(void);
BSP_TARGET_ARM void fpu_slavetcm_init(void);
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors(void) BSP_PLACE_IN_SECTION(".intvec");
__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler(void);
__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler(void) BSP_PLACE_IN_SECTION(".reset_handler");
void Default_Handler(void);
/* Stacks */
BSP_DONT_REMOVE static uint8_t g_fiq_stack[BSP_CFG_STACK_FIQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_FIQ_STACK);
BSP_DONT_REMOVE static uint8_t g_irq_stack[BSP_CFG_STACK_IRQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_IRQ_STACK);
BSP_DONT_REMOVE static uint8_t g_abt_stack[BSP_CFG_STACK_ABT_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_ABT_STACK);
BSP_DONT_REMOVE static uint8_t g_und_stack[BSP_CFG_STACK_UND_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_UND_STACK);
BSP_DONT_REMOVE static uint8_t g_sys_stack[BSP_CFG_STACK_SYS_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_SYS_STACK);
BSP_DONT_REMOVE static uint8_t g_svc_stack[BSP_CFG_STACK_SVC_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_SVC_STACK);
/* Heap */
#if (BSP_CFG_HEAP_BYTES > 0)
BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
#endif
#if defined(__GNUC__)
BSP_DONT_REMOVE static const void * g_bsp_dummy BSP_PLACE_IN_SECTION(".dummy");
#if BSP_CFG_RAM_EXECUTION
BSP_DONT_REMOVE static const void * g_bsp_loader_dummy BSP_PLACE_IN_SECTION(".loader_dummy");
#endif
#endif
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void)
{
__asm volatile (
" LDR pc,=Reset_Handler \n"
" LDR pc,=Undefined_Handler \n"
" LDR pc,=SVC_Handler \n"
" LDR pc,=Prefetch_Handler \n"
" LDR pc,=Abort_Handler \n"
" LDR pc,=Reserved_Handler \n"
" LDR pc,=IRQ_Handler \n"
" LDR pc,=FIQ_Handler \n"
::: "memory");
}
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Default exception handler.
**********************************************************************************************************************/
void Default_Handler (void)
{
/** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
* or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
* registers for more information.
*/
BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
}
/*******************************************************************************************************************//**
* After boot processing, LSI starts executing here.
**********************************************************************************************************************/
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init (void)
{
__asm volatile (
"set_hactlr: \n"
" MOVW r0, %[bsp_hactlr_bit_l] \n" /* Set HACTLR bits(L) */
" MOVT r0, #0 \n"
" MCR p15, #4, r0, c1, c0, #1 \n" /* Write r0 to HACTLR */
::[bsp_hactlr_bit_l] "i" (BSP_HACTLR_BIT_L) : "memory");
__asm volatile (
"set_hcr: \n"
" MRC p15, #4, r1, c1, c1, #0 \n" /* Read Hyp Configuration Register */
" ORR r1, r1, %[bsp_hcr_hcd_disable] \n" /* HVC instruction disable */
" MCR p15, #4, r1, c1, c1, #0 \n" /* Write Hyp Configuration Register */
::[bsp_hcr_hcd_disable] "i" (BSP_HCR_HCD_DISABLE) : "memory");
__asm volatile (
"set_vbar: \n"
" LDR r0, =__Vectors \n"
" MCR p15, #0, r0, c12, c0, #0 \n" /* Write r0 to VBAR */
::: "memory");
__asm volatile (
"LLPP_access_enable: \n"
/* Enable PERIPHPREGIONR (LLPP) */
" MRC p15, #0, r1, c15, c0,#0 \n" /* PERIPHPREGIONR */
" ORR r1, r1, #(0x1 << 1) \n" /* Enable PERIPHPREGIONR EL2 */
" ORR r1, r1, #(0x1) \n" /* Enable PERIPHPREGIONR EL1 and EL0 */
" DSB \n" /* Ensuring memory access complete */
" MCR p15, #0, r1, c15, c0,#0 \n" /* PERIPHREGIONR */
" ISB \n" /* Ensuring Context-changing */
::: "memory");
__asm volatile (
"cpsr_save: \n"
" MRS r0, CPSR \n" /* Original PSR value */
" BIC r0, r0, %[bsp_mode_mask] \n" /* Clear the mode bits */
" ORR r0, r0, %[bsp_svc_mode] \n" /* Set SVC mode bits */
" MSR SPSR_hyp, r0 \n"
::[bsp_mode_mask] "i" (BSP_MODE_MASK), [bsp_svc_mode] "i" (BSP_SVC_MODE) : "memory");
__asm volatile (
"exception_return: \n"
" LDR r1, =stack_init \n"
" MSR ELR_hyp, r1 \n"
" ERET \n" /* Branch to stack_init and enter EL1 */
::: "memory");
}
/** @} (end addtogroup BSP_MCU) */
#if defined(__ICCARM__)
#define BSP_SYSTEMINIT_B_INSTRUCTION SystemInit();
#define WEAK_REF_ATTRIBUTE
#pragma weak Undefined_Handler = Default_Handler
#pragma weak SVC_Handler = Default_Handler
#pragma weak Prefetch_Handler = Default_Handler
#pragma weak Abort_Handler = Default_Handler
#pragma weak Reserved_Handler = Default_Handler
#pragma weak FIQ_Handler = Default_Handler
#elif defined(__GNUC__)
#define BSP_SYSTEMINIT_B_INSTRUCTION __asm volatile ("B SystemInit");
#define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler")))
#endif
void Undefined_Handler(void) WEAK_REF_ATTRIBUTE;
void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
void Prefetch_Handler(void) WEAK_REF_ATTRIBUTE;
void Abort_Handler(void) WEAK_REF_ATTRIBUTE;
void Reserved_Handler(void) WEAK_REF_ATTRIBUTE;
void FIQ_Handler(void) WEAK_REF_ATTRIBUTE;
/*******************************************************************************************************************//**
* After system_init, EL1 settings start here.
**********************************************************************************************************************/
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init (void)
{
__asm volatile (
"stack_initialization: \n"
/* Stack setting for EL1 */
" CPS #17 \n" /* FIQ mode */
" MOV sp, %[bsp_fiq_stack_end_address] \n"
" CPS #18 \n" /* IRQ mode */
" MOV sp, %[bsp_irq_stack_end_address] \n"
" CPS #23 \n" /* Abort mode */
" MOV sp, %[bsp_abort_stack_end_address] \n"
" CPS #27 \n" /* Undefined mode */
" MOV sp, %[bsp_undefined_stack_end_address] \n"
" CPS #31 \n" /* System mode */
" MOV sp, %[bsp_system_stack_end_address] \n"
" CPS #19 \n" /* SVC mode */
" MOV sp, %[bsp_svc_stack_end_address] \n"
" B fpu_slavetcm_init \n" /* Branch to fpu_slavetcm_init */
::[bsp_fiq_stack_end_address] "r" (BSP_FIQ_STACK_END_ADDRESS),
[bsp_irq_stack_end_address] "r" (BSP_IRQ_STACK_END_ADDRESS),
[bsp_abort_stack_end_address] "r" (BSP_ABORT_STACK_END_ADDRESS),
[bsp_undefined_stack_end_address] "r" (BSP_UNDEFINED_STACK_END_ADDRESS),
[bsp_system_stack_end_address] "r" (BSP_SYSTEM_STACK_END_ADDRESS),
[bsp_svc_stack_end_address] "r" (BSP_SVC_STACK_END_ADDRESS) : "memory");
}
/*******************************************************************************************************************//**
* Enable FPU and enable privileged/unprivileged access for TCM.
**********************************************************************************************************************/
BSP_TARGET_ARM void fpu_slavetcm_init (void)
{
#if __FPU_USED
/* Initialize FPU and Advanced SIMD setting */
bsp_fpu_advancedsimd_init();
#endif
/* Enable SLAVEPCTLR TCM access lvl slaves */
bsp_slavetcm_enable();
BSP_SYSTEMINIT_B_INSTRUCTION
}
__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler (void)
{
__asm volatile (
"SUB lr, lr, #4 \n"
"SRSDB sp!, #31 \n" /* Store LR_irq and SPSR_irq in system mode stack. */
"CPS #31 \n" /* Switch to system mode. */
"PUSH {r0-r3, r12} \n" /* Store other AAPCS registers. */
#if __FPU_USED
"VMRS r0, FPSCR \n"
"STMDB sp!, {r0} \n" /* Store FPSCR register. */
"SUB sp, sp, #4 \n"
"VPUSH {d0-d15} \n" /* Store FPU registers. */
"VPUSH {d16-d31} \n" /* Store FPU registers. */
#endif
"MRC p15, #0, r3, c12, c12, #2 \n" /* Read HPPIR1 to r3. */
"MRC p15, #0, r0, c12, c12, #0 \n" /* Read IAR1 to r0. */
"PUSH {r0} \n" /* Store the INTID. */
"MOV r1, sp \n" /* Make alignment for stack. */
"AND r1, r1, #4 \n"
"SUB sp, sp, r1 \n"
"PUSH {r1, lr} \n"
"LDR r1,=bsp_common_interrupt_handler \n"
"BLX r1 \n" /* Jump to bsp_common_interrupt_handler, First argument (r0) = ICC_IAR1 read value. */
"POP {r1, lr} \n"
"ADD sp, sp, r1 \n"
"POP {r0} \n" /* Restore the INTID to r0. */
"MCR p15, #0, r0, c12, c12, #1 \n" /* Write INTID to EOIR. */
#if __FPU_USED
"VPOP {d16-d31} \n" /* Restore FPU registers. */
"VPOP {d0-d15} \n" /* Restore FPU registers. */
"ADD sp, sp, #4 \n"
"POP {r0} \n"
"VMSR FPSCR, r0 \n" /* Restore FPSCR register. */
#endif
"POP {r0-r3, r12} \n" /* Restore registers. */
"RFEIA sp! \n" /* Return from system mode tack using RFE. */
::: "memory");
}
__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler (void)
{
/* Enable access to BTCM */
__asm volatile (
"set_IMP_BTCMREGIONR: \n"
" MRC p15, #0, r0, c9, c1, #1 \n" /* Read IMP_BTCMREGIONR to r0 */
" MOVW r1, %[bsp_imp_btcmregionr_mask_l] \n"
" MOVT r1, #0 \n"
" AND r0, r0, r1 \n" /* Masked out BASEADDRESS and ENABLEELx bits */
" MOVW r1, %[bsp_imp_btcmregionr_enableel_l] \n"
" MOVT r1, %[bsp_imp_btcmregionr_enableel_h] \n"
" ORR r0, r0, r1 \n" /* Set base address and enable EL2, EL1, EL0 access */
" DSB \n" /* Ensuring memory access complete */
" MCR p15, #0, r0, c9, c1, #1 \n" /* Write r0 to IMP_BTCMREGIONR */
" ISB \n" /* Ensuring Context-changing */
::[bsp_imp_btcmregionr_mask_l] "i" (BSP_IMP_BTCMREGIONR_MASK_L),
[bsp_imp_btcmregionr_enableel_l] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_L),
[bsp_imp_btcmregionr_enableel_h] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_H) : "memory");
/* Branch to system_init */
__asm volatile ("B system_init");
}

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bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c Normal file
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@ -0,0 +1,617 @@
/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include <string.h>
#include "bsp_api.h"
#include "../../../../../mcu/all/bsp_clocks.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_CPCAR_CP_ENABLE (0x00F00000)
#define BSP_FPEXC_EN_ENABLE (0x40000000)
#define BSP_TCM_ALL_ACCESS_ENABLE (0x00000003)
#define BSP_PRIORITY_MASK BSP_FEATURE_BSP_IRQ_PRIORITY_MASK /* Priority mask value for GIC */
#define BSP_ENABLE_GROUP_INT (0x00000001) /* Enable Group1 interrupt value */
#define BSP_ICC_CTLR (0x00000001) /* ICC_BPR0 is used for Group1 interrupt */
#define BSP_BG_REGION_ENABLE (0x00020000) /* Enable EL1 background region */
#define BSP_BG_REGION_DISABLE (0x00000000) /* Disable EL1 background region */
#define BSP_SCTLR_BR_BIT (BSP_CFG_SCTLR_BR_BIT) /* Enable EL1 background region */
#define BSP_ICACHE_ENABLE (0x00001000)
#define BSP_ICACHE_DISABLE (0x00000000)
#define BSP_DATACACHE_ENABLE (0x00000004)
#define BSP_DATACACHE_DISABLE (0x00000000)
#define BSP_WRITE_THROUGH_TRANSIENT (0x0003) /* Normal-Memory: Write-Through transient */
#define BSP_NON_CACHEABLE (0x0004) /* Normal-Memory: Non-Cacheable */
#define BSP_WRITE_BACK_TRANSIENT (0x0007) /* Normal-Memory: Write-Back transient */
#define BSP_WRITE_NON_THROUGH (0x000B) /* Normal-Memory: Write-Through non-transient. */
#define BSP_WRITE_BACK_NON_TRANSIENT (0x000F) /* Normal-Memory: Write-Back non-transient. */
#define BSP_TYPE_NORMAL_MEMORY (0)
#define BSP_TYPE_DEVICE_MEMORY (1)
#define BSP_READ_ALLOCATE (0xFFFF) /* Read allocate (bit1=1, "1" mask except bit1) */
#define BSP_READ_NOT_ALLOCATE (0xFFFD) /* Read not allocate (bit1=0, "1" mask except bit1) */
#define BSP_WRITE_ALLOCATE (0xFFFF) /* Write allocate (bit0=1, "1" mask except bit0) */
#define BSP_WRITE_NOT_ALLOCATE (0xFFFE) /* Write not allocate (bit0=0, "1" mask except bit0) */
#define BSP_DEVICE_NGNRNE (0x0000) /* Device-nGnRnE memory */
#define BSP_DEVICE_NGNRE (0x0004) /* Device-nGnRE memory */
#define BSP_DEVICE_NGRE (0x0008) /* Device-nGRE memory */
#define BSP_DEVICE_GRE (0x000C) /* Device-GRE memory */
#define BSP_OFFSET_ATTR0_INNER (0)
#define BSP_OFFSET_ATTR0_OUTER (4)
#define BSP_OFFSET_ATTR0_DEVICE (0)
#define BSP_OFFSET_ATTR1_INNER (8)
#define BSP_OFFSET_ATTR1_OUTER (12)
#define BSP_OFFSET_ATTR1_DEVICE (8)
#define BSP_OFFSET_ATTR2_INNER (16)
#define BSP_OFFSET_ATTR2_OUTER (20)
#define BSP_OFFSET_ATTR2_DEVICE (16)
#define BSP_OFFSET_ATTR3_INNER (24)
#define BSP_OFFSET_ATTR3_OUTER (28)
#define BSP_OFFSET_ATTR3_DEVICE (24)
#define BSP_OFFSET_ATTR4_INNER (0)
#define BSP_OFFSET_ATTR4_OUTER (4)
#define BSP_OFFSET_ATTR4_DEVICE (0)
#define BSP_OFFSET_ATTR5_INNER (8)
#define BSP_OFFSET_ATTR5_OUTER (12)
#define BSP_OFFSET_ATTR5_DEVICE (8)
#define BSP_OFFSET_ATTR6_INNER (16)
#define BSP_OFFSET_ATTR6_OUTER (20)
#define BSP_OFFSET_ATTR6_DEVICE (16)
#define BSP_OFFSET_ATTR7_INNER (24)
#define BSP_OFFSET_ATTR7_OUTER (28)
#define BSP_OFFSET_ATTR7_DEVICE (24)
#define BSP_NON_SHAREABLE (0 << 3)
#define BSP_OUTER_SHAREABLE (2 << 3)
#define BSP_INNER_SHAREABLE (3 << 3)
#define BSP_EL1RW_EL0NO (0 << 1)
#define BSP_EL1RW_EL0RW (1 << 1)
#define BSP_EL1RO_EL0NO (2 << 1)
#define BSP_EL1RO_EL0RO (3 << 1)
#define BSP_EXECUTE_ENABLE (0)
#define BSP_EXECUTE_NEVER (1)
#define BSP_REGION_DISABLE (0)
#define BSP_REGION_ENABLE (1)
#define BSP_ATTRINDEX0 (0 << 1)
#define BSP_ATTRINDEX1 (1 << 1)
#define BSP_ATTRINDEX2 (2 << 1)
#define BSP_ATTRINDEX3 (3 << 1)
#define BSP_ATTRINDEX4 (4 << 1)
#define BSP_ATTRINDEX5 (5 << 1)
#define BSP_ATTRINDEX6 (6 << 1)
#define BSP_ATTRINDEX7 (7 << 1)
/* Attr0 */
#if BSP_CFG_CPU_MPU_ATTR0_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR0 (BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE << BSP_OFFSET_ATTR0_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR0 (((BSP_CFG_CPU_MPU_ATTR0_INNER & \
(BSP_CFG_CPU_MPU_ATTR0_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) << BSP_OFFSET_ATTR0_INNER) | \
((BSP_CFG_CPU_MPU_ATTR0_OUTER & \
(BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) << BSP_OFFSET_ATTR0_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR0_TYPE */
/* Attr1 */
#if BSP_CFG_CPU_MPU_ATTR1_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR1 (BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE << BSP_OFFSET_ATTR1_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR1 (((BSP_CFG_CPU_MPU_ATTR1_INNER & \
(BSP_CFG_CPU_MPU_ATTR1_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) << BSP_OFFSET_ATTR1_INNER) | \
((BSP_CFG_CPU_MPU_ATTR1_OUTER & \
(BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) << BSP_OFFSET_ATTR1_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR1_TYPE */
/* Attr2 */
#if BSP_CFG_CPU_MPU_ATTR2_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR2 (BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE << BSP_OFFSET_ATTR2_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR2 (((BSP_CFG_CPU_MPU_ATTR2_INNER & \
(BSP_CFG_CPU_MPU_ATTR2_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) << BSP_OFFSET_ATTR2_INNER) | \
((BSP_CFG_CPU_MPU_ATTR2_OUTER & \
(BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) << BSP_OFFSET_ATTR2_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR2_TYPE */
/* Attr3 */
#if BSP_CFG_CPU_MPU_ATTR3_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR3 (BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE << BSP_OFFSET_ATTR3_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR3 (((BSP_CFG_CPU_MPU_ATTR3_INNER & \
(BSP_CFG_CPU_MPU_ATTR3_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) << BSP_OFFSET_ATTR3_INNER) | \
((BSP_CFG_CPU_MPU_ATTR3_OUTER & \
(BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) << BSP_OFFSET_ATTR3_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR3_TYPE */
/* Attr4 */
#if BSP_CFG_CPU_MPU_ATTR4_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR4 (BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE << BSP_OFFSET_ATTR4_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR4 (((BSP_CFG_CPU_MPU_ATTR4_INNER & \
(BSP_CFG_CPU_MPU_ATTR4_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) << BSP_OFFSET_ATTR4_INNER) | \
((BSP_CFG_CPU_MPU_ATTR4_OUTER & \
(BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) << BSP_OFFSET_ATTR4_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR4_TYPE */
/* Attr5 */
#if BSP_CFG_CPU_MPU_ATTR5_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR5 (BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE << BSP_OFFSET_ATTR5_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR5 (((BSP_CFG_CPU_MPU_ATTR5_INNER & \
(BSP_CFG_CPU_MPU_ATTR5_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) << BSP_OFFSET_ATTR5_INNER) | \
((BSP_CFG_CPU_MPU_ATTR5_OUTER & \
(BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) << BSP_OFFSET_ATTR5_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR5_TYPE */
/* Attr6 */
#if BSP_CFG_CPU_MPU_ATTR6_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR6 (BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE << BSP_OFFSET_ATTR6_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR6 (((BSP_CFG_CPU_MPU_ATTR6_INNER & \
(BSP_CFG_CPU_MPU_ATTR6_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) << BSP_OFFSET_ATTR6_INNER) | \
((BSP_CFG_CPU_MPU_ATTR6_OUTER & \
(BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) << BSP_OFFSET_ATTR6_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR6_TYPE */
/* Attr7 */
#if BSP_CFG_CPU_MPU_ATTR7_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */
#define BSP_CFG_CPU_MPU_ATTR7 (BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE << BSP_OFFSET_ATTR7_DEVICE)
#else /* MEMORY TYPE == NORMAL MEMORY */
#define BSP_CFG_CPU_MPU_ATTR7 (((BSP_CFG_CPU_MPU_ATTR7_INNER & \
(BSP_CFG_CPU_MPU_ATTR7_INNER_READ) & \
(BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) << BSP_OFFSET_ATTR7_INNER) | \
((BSP_CFG_CPU_MPU_ATTR7_OUTER & \
(BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) & \
(BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) << BSP_OFFSET_ATTR7_OUTER))
#endif /* BSP_CFG_CPU_MPU_ATTR7_TYPE */
#define ATTR_3_2_1_0 (BSP_CFG_CPU_MPU_ATTR3 | BSP_CFG_CPU_MPU_ATTR2 | BSP_CFG_CPU_MPU_ATTR1 | \
BSP_CFG_CPU_MPU_ATTR0)
#define ATTR_7_6_5_4 (BSP_CFG_CPU_MPU_ATTR7 | BSP_CFG_CPU_MPU_ATTR6 | BSP_CFG_CPU_MPU_ATTR5 | \
BSP_CFG_CPU_MPU_ATTR4)
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR0_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR1_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR2_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR3_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR4_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR5_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR6_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR7_TYPE)
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_INNER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_OUTER) && \
(BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) && \
(BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE))
#error "If you select Write-Through transient, set either Read or Write to allocate."
#endif
#endif
/* Region template */
#define EL1_MPU_REGION_COUNT (24)
#define EL1_MPU_REGIONXX_BASE(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _BASE & 0xFFFFFFC0) | \
BSP_CFG_EL1_MPU_REGION ## n ## _SH | \
BSP_CFG_EL1_MPU_REGION ## n ## _AP | \
BSP_CFG_EL1_MPU_REGION ## n ## _XN)
#define EL1_MPU_REGIONXX_LIMIT(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _LIMIT & 0xFFFFFFC0) | \
BSP_CFG_EL1_MPU_REGION ## n ## _ATTRINDEX | \
BSP_CFG_EL1_MPU_REGION ## n ## _ENABLE)
/* region 0 */
#define EL1_MPU_REGION00_BASE EL1_MPU_REGIONXX_BASE(00)
#define EL1_MPU_REGION00_LIMIT EL1_MPU_REGIONXX_LIMIT(00)
/* region 1 */
#define EL1_MPU_REGION01_BASE EL1_MPU_REGIONXX_BASE(01)
#define EL1_MPU_REGION01_LIMIT EL1_MPU_REGIONXX_LIMIT(01)
/* region 2 */
#define EL1_MPU_REGION02_BASE EL1_MPU_REGIONXX_BASE(02)
#define EL1_MPU_REGION02_LIMIT EL1_MPU_REGIONXX_LIMIT(02)
/* region 3 */
#define EL1_MPU_REGION03_BASE EL1_MPU_REGIONXX_BASE(03)
#define EL1_MPU_REGION03_LIMIT EL1_MPU_REGIONXX_LIMIT(03)
/* region 4 */
#define EL1_MPU_REGION04_BASE EL1_MPU_REGIONXX_BASE(04)
#define EL1_MPU_REGION04_LIMIT EL1_MPU_REGIONXX_LIMIT(04)
/* region 5 */
#define EL1_MPU_REGION05_BASE EL1_MPU_REGIONXX_BASE(05)
#define EL1_MPU_REGION05_LIMIT EL1_MPU_REGIONXX_LIMIT(05)
/* region 6 */
#define EL1_MPU_REGION06_BASE EL1_MPU_REGIONXX_BASE(06)
#define EL1_MPU_REGION06_LIMIT EL1_MPU_REGIONXX_LIMIT(06)
/* region 7 */
#define EL1_MPU_REGION07_BASE EL1_MPU_REGIONXX_BASE(07)
#define EL1_MPU_REGION07_LIMIT EL1_MPU_REGIONXX_LIMIT(07)
/* region 8 */
#define EL1_MPU_REGION08_BASE EL1_MPU_REGIONXX_BASE(08)
#define EL1_MPU_REGION08_LIMIT EL1_MPU_REGIONXX_LIMIT(08)
/* region 9 */
#define EL1_MPU_REGION09_BASE EL1_MPU_REGIONXX_BASE(09)
#define EL1_MPU_REGION09_LIMIT EL1_MPU_REGIONXX_LIMIT(09)
/* region 10 */
#define EL1_MPU_REGION10_BASE EL1_MPU_REGIONXX_BASE(10)
#define EL1_MPU_REGION10_LIMIT EL1_MPU_REGIONXX_LIMIT(10)
/* region 11 */
#define EL1_MPU_REGION11_BASE EL1_MPU_REGIONXX_BASE(11)
#define EL1_MPU_REGION11_LIMIT EL1_MPU_REGIONXX_LIMIT(11)
/* region 12 */
#define EL1_MPU_REGION12_BASE EL1_MPU_REGIONXX_BASE(12)
#define EL1_MPU_REGION12_LIMIT EL1_MPU_REGIONXX_LIMIT(12)
/* region 13 */
#define EL1_MPU_REGION13_BASE EL1_MPU_REGIONXX_BASE(13)
#define EL1_MPU_REGION13_LIMIT EL1_MPU_REGIONXX_LIMIT(13)
/* region 14 */
#define EL1_MPU_REGION14_BASE EL1_MPU_REGIONXX_BASE(14)
#define EL1_MPU_REGION14_LIMIT EL1_MPU_REGIONXX_LIMIT(14)
/* region 15 */
#define EL1_MPU_REGION15_BASE EL1_MPU_REGIONXX_BASE(15)
#define EL1_MPU_REGION15_LIMIT EL1_MPU_REGIONXX_LIMIT(15)
/* region 16 */
#define EL1_MPU_REGION16_BASE EL1_MPU_REGIONXX_BASE(16)
#define EL1_MPU_REGION16_LIMIT EL1_MPU_REGIONXX_LIMIT(16)
/* region 17 */
#define EL1_MPU_REGION17_BASE EL1_MPU_REGIONXX_BASE(17)
#define EL1_MPU_REGION17_LIMIT EL1_MPU_REGIONXX_LIMIT(17)
/* region 18 */
#define EL1_MPU_REGION18_BASE EL1_MPU_REGIONXX_BASE(18)
#define EL1_MPU_REGION18_LIMIT EL1_MPU_REGIONXX_LIMIT(18)
/* region 19 */
#define EL1_MPU_REGION19_BASE EL1_MPU_REGIONXX_BASE(19)
#define EL1_MPU_REGION19_LIMIT EL1_MPU_REGIONXX_LIMIT(19)
/* region 20 */
#define EL1_MPU_REGION20_BASE EL1_MPU_REGIONXX_BASE(20)
#define EL1_MPU_REGION20_LIMIT EL1_MPU_REGIONXX_LIMIT(20)
/* region 21 */
#define EL1_MPU_REGION21_BASE EL1_MPU_REGIONXX_BASE(21)
#define EL1_MPU_REGION21_LIMIT EL1_MPU_REGIONXX_LIMIT(21)
/* region 22 */
#define EL1_MPU_REGION22_BASE EL1_MPU_REGIONXX_BASE(22)
#define EL1_MPU_REGION22_LIMIT EL1_MPU_REGIONXX_LIMIT(22)
/* region 23 */
#define EL1_MPU_REGION23_BASE EL1_MPU_REGIONXX_BASE(23)
#define EL1_MPU_REGION23_LIMIT EL1_MPU_REGIONXX_LIMIT(23)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
typedef struct st_bsp_mpu_config
{
uint32_t base;
uint32_t limit;
} bsp_mpu_config_t;
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
static const bsp_mpu_config_t g_bsp_el1_mpu[EL1_MPU_REGION_COUNT] =
{
{EL1_MPU_REGION00_BASE, EL1_MPU_REGION00_LIMIT},
{EL1_MPU_REGION01_BASE, EL1_MPU_REGION01_LIMIT},
{EL1_MPU_REGION02_BASE, EL1_MPU_REGION02_LIMIT},
{EL1_MPU_REGION03_BASE, EL1_MPU_REGION03_LIMIT},
{EL1_MPU_REGION04_BASE, EL1_MPU_REGION04_LIMIT},
{EL1_MPU_REGION05_BASE, EL1_MPU_REGION05_LIMIT},
{EL1_MPU_REGION06_BASE, EL1_MPU_REGION06_LIMIT},
{EL1_MPU_REGION07_BASE, EL1_MPU_REGION07_LIMIT},
{EL1_MPU_REGION08_BASE, EL1_MPU_REGION08_LIMIT},
{EL1_MPU_REGION09_BASE, EL1_MPU_REGION09_LIMIT},
{EL1_MPU_REGION10_BASE, EL1_MPU_REGION10_LIMIT},
{EL1_MPU_REGION11_BASE, EL1_MPU_REGION11_LIMIT},
{EL1_MPU_REGION12_BASE, EL1_MPU_REGION12_LIMIT},
{EL1_MPU_REGION13_BASE, EL1_MPU_REGION13_LIMIT},
{EL1_MPU_REGION14_BASE, EL1_MPU_REGION14_LIMIT},
{EL1_MPU_REGION15_BASE, EL1_MPU_REGION15_LIMIT},
{EL1_MPU_REGION16_BASE, EL1_MPU_REGION16_LIMIT},
{EL1_MPU_REGION17_BASE, EL1_MPU_REGION17_LIMIT},
{EL1_MPU_REGION18_BASE, EL1_MPU_REGION18_LIMIT},
{EL1_MPU_REGION19_BASE, EL1_MPU_REGION19_LIMIT},
{EL1_MPU_REGION20_BASE, EL1_MPU_REGION20_LIMIT},
{EL1_MPU_REGION21_BASE, EL1_MPU_REGION21_LIMIT},
{EL1_MPU_REGION22_BASE, EL1_MPU_REGION22_LIMIT},
{EL1_MPU_REGION23_BASE, EL1_MPU_REGION23_LIMIT},
};
#if __FPU_USED
void bsp_fpu_advancedsimd_init(void);
#endif
void bsp_slavetcm_enable(void);
void bsp_memory_protect_setting(void);
void bsp_mpu_init(uint32_t region, uint32_t base, uint32_t limit);
void bsp_irq_cfg_common(void);
#if __FPU_USED
/*******************************************************************************************************************//**
* Initialize FPU and Advanced SIMD setting.
**********************************************************************************************************************/
void bsp_fpu_advancedsimd_init (void)
{
uint32_t apacr;
uint32_t fpexc;
/* Enables cp10 and cp11 accessing */
apacr = __get_CPACR();
apacr |= BSP_CPCAR_CP_ENABLE;
__set_CPACR(apacr);
__ISB();
/* Enables the FPU */
fpexc = __get_FPEXC();
fpexc |= BSP_FPEXC_EN_ENABLE;
__set_FPEXC(fpexc);
__ISB();
}
#endif
/*******************************************************************************************************************//**
* Settings the privilege level required for the AXIS to access the TCM.
**********************************************************************************************************************/
void bsp_slavetcm_enable (void)
{
uint32_t imp_slavepctlr;
/* Enable TCM access privilege and non privilege */
imp_slavepctlr = __get_IMP_SLAVEPCTLR();
imp_slavepctlr |= BSP_TCM_ALL_ACCESS_ENABLE;
__DSB();
__set_IMP_SLAVEPCTLR(imp_slavepctlr);
__ISB();
}
/*******************************************************************************************************************//**
* Initialize memory protection settings.
**********************************************************************************************************************/
void bsp_memory_protect_setting (void)
{
uint32_t sctlr;
uint32_t mair0;
uint32_t mair1;
uint32_t region;
/* Adopt EL1 default memory map as background map */
sctlr = __get_SCTLR();
sctlr |= BSP_SCTLR_BR_BIT;
__DSB();
__set_SCTLR(sctlr);
__ISB();
/* Configure Memory Attribute Indirection Registers */
mair0 = ATTR_3_2_1_0;
mair1 = ATTR_7_6_5_4;
__set_MAIR0(mair0);
__set_MAIR1(mair1);
__DSB();
/* Setup region. */
for (region = 0; region < EL1_MPU_REGION_COUNT; region++)
{
bsp_mpu_init(region, g_bsp_el1_mpu[region].base, g_bsp_el1_mpu[region].limit);
}
R_BSP_CacheInvalidateAll();
R_BSP_CacheEnableMemoryProtect();
#if (BSP_ICACHE_ENABLE == BSP_CFG_SCTLR_I_BIT)
R_BSP_CacheEnableInst();
#else
R_BSP_CacheDisableInst();
#endif
#if (BSP_DATACACHE_ENABLE == BSP_CFG_SCTLR_C_BIT)
R_BSP_CacheEnableData();
#else
R_BSP_CacheDisableData();
#endif
}
/*******************************************************************************************************************//**
* Core MPU initialization block.
**********************************************************************************************************************/
void bsp_mpu_init (uint32_t region, uint32_t base, uint32_t limit)
{
/* Selects the current EL1-controlled MPU region registers, PRBAR, and PRLAR */
__set_PRSELR(region);
__DSB();
/* Set the base address and attributes of the MPU region controlled by EL1 */
__set_PRBAR(base);
__DSB();
/* Set the limit address and attributes of the MPU region controlled by EL1 */
__set_PRLAR(limit);
__DSB();
}
/*******************************************************************************************************************//**
* Initialize common configuration settings for interrupts
**********************************************************************************************************************/
void bsp_irq_cfg_common (void)
{
uint32_t icc_pmr;
uint32_t icc_igrpen1;
uint32_t icc_ctlr;
/* Set priority mask level for CPU interface */
icc_pmr = BSP_PRIORITY_MASK;
__set_ICC_PMR(icc_pmr);
/* Enable group 1 interrupts */
icc_igrpen1 = BSP_ENABLE_GROUP_INT;
__set_ICC_IGRPEN1(icc_igrpen1);
/* Use ICC_BPR0 for interrupt preemption for both group 0 and group 1 interrupts */
icc_ctlr = __get_ICC_CTLR();
icc_ctlr |= BSP_ICC_CTLR;
__set_ICC_CTLR(icc_ctlr);
__ISB();
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
extern void bsp_master_mpu_init(void);
extern void bsp_global_system_counter_init(void);
#if BSP_FEATURE_TFU_SUPPORTED
extern void bsp_tfu_init(void);
#endif
#if BSP_CFG_C_RUNTIME_INIT
extern void bsp_loader_data_init(void);
extern void bsp_loader_bss_init(void);
extern void bsp_static_constructor_init(void);
#endif
#if !(BSP_CFG_RAM_EXECUTION)
extern void bsp_copy_to_ram(void);
extern void bsp_application_bss_init(void);
#endif
#if !BSP_CFG_PORT_PROTECT
extern void bsp_release_port_protect(void);
#endif
extern void bsp_memory_protect_setting(void);
extern void bsp_irq_cfg_common(void);
extern void R_BSP_WarmStart(bsp_warm_start_event_t event);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
int32_t main(void);
#if BSP_CFG_EARLY_INIT
static void bsp_init_uninitialized_vars(void);
#endif
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Initialize the MCU and the runtime environment.
**********************************************************************************************************************/
void SystemInit (void)
{
#if BSP_CFG_EARLY_INIT
/* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */
bsp_init_uninitialized_vars();
#endif
/* Call before initializing clock and variables. */
R_BSP_WarmStart(BSP_WARM_START_RESET);
/* Configure system clocks. */
bsp_clock_init();
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
#if BSP_CFG_C_RUNTIME_INIT
/* Copy the loader data from external Flash to internal RAM. */
bsp_loader_data_init();
/* Clear loader bss section in internal RAM. */
bsp_loader_bss_init();
#endif
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
/* Set memory attributes, etc. */
bsp_memory_protect_setting();
#if !(BSP_CFG_RAM_EXECUTION)
/* Copy the application program from external Flash to internal RAM. */
bsp_copy_to_ram();
/* Clear bss section in internal RAM. */
bsp_application_bss_init();
#endif
#if BSP_CFG_C_RUNTIME_INIT
/* Initialize static constructors */
bsp_static_constructor_init();
#endif
#if !BSP_CFG_PORT_PROTECT
/* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
bsp_release_port_protect();
#endif
/* Call Post C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_C);
/* Initialize the Master-MPU settings. */
bsp_master_mpu_init();
/* Initialize global system counter. The counter is enabled and is incrementing. */
bsp_global_system_counter_init();
/* GIC initialization */
bsp_irq_cfg_common();
/* Initialize GIC interrupts. */
bsp_irq_cfg();
#if BSP_FEATURE_TFU_SUPPORTED
/* Initialize the TFU settings. */
bsp_tfu_init();
#endif
#if defined(__GNUC__)
extern void entry(void);
entry();
#elif defined(__ICCARM__)
extern void __low_level_init(void);
__low_level_init();
#else
/* Jump to main. */
main();
#endif
}
/** @} (end addtogroup BSP_MCU) */
#if BSP_CFG_EARLY_INIT
/*******************************************************************************************************************//**
* Initialize BSP variables not handled by C runtime startup.
**********************************************************************************************************************/
static void bsp_init_uninitialized_vars (void)
{
g_protect_port_counter = 0;
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++)
{
g_protect_counters[i] = 0;
}
SystemCoreClockUpdate();
}
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_PRV_MASTER_MPU_REGION_NUM (8)
#define BSP_PRV_MASTER_MPU_STADD(master, region) (BSP_CFG_MPU ## master ## _STADD ## region | \
(BSP_CFG_MPU ## master ## _WRITE ## region << 1) | \
BSP_CFG_MPU ## master ## _READ ## region)
#define BSP_PRV_MASTER_MPU_ENDADD(master, region) (BSP_CFG_MPU ## master ## _ENDADD ## region)
#if defined(__ICCARM__)
#if BSP_CFG_C_RUNTIME_INIT
#define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS __section_begin("LDR_DATA_RBLOCK")
#define BSP_PRV_SECTION_LDR_DATA_RAM_START __section_begin("LDR_DATA_WBLOCK")
#define BSP_PRV_SECTION_LDR_DATA_RAM_END __section_end("LDR_DATA_WBLOCK")
#define BSP_PRV_SECTION_LDR_DATA_BSS_START __section_begin("LDR_DATA_ZBLOCK")
#define BSP_PRV_SECTION_LDR_DATA_BSS_END __section_end("LDR_DATA_ZBLOCK")
#endif
#if !(BSP_CFG_RAM_EXECUTION)
#define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS __section_begin("VECTOR_RBLOCK")
#define BSP_PRV_SECTION_VECTOR_RAM_START __section_begin("VECTOR_WBLOCK")
#define BSP_PRV_SECTION_VECTOR_RAM_END __section_end("VECTOR_WBLOCK")
#define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS __section_begin("USER_PRG_RBLOCK")
#define BSP_PRV_SECTION_USER_PRG_RAM_START __section_begin("USER_PRG_WBLOCK")
#define BSP_PRV_SECTION_USER_PRG_RAM_END __section_end("USER_PRG_WBLOCK")
#define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS __section_begin("USER_DATA_RBLOCK")
#define BSP_PRV_SECTION_USER_DATA_RAM_START __section_begin("USER_DATA_WBLOCK")
#define BSP_PRV_SECTION_USER_DATA_RAM_END __section_end("USER_DATA_WBLOCK")
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS __section_begin("USER_DATA_NONCACHE_RBLOCK")
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START __section_begin("USER_DATA_NONCACHE_WBLOCK")
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END __section_end("USER_DATA_NONCACHE_WBLOCK")
#define BSP_PRV_SECTION_USER_DATA_BSS_START __section_begin("USER_DATA_ZBLOCK")
#define BSP_PRV_SECTION_USER_DATA_BSS_END __section_end("USER_DATA_ZBLOCK")
#endif
#if BSP_CFG_RAM_EXECUTION
#define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START __section_begin("NONCACHE_BUFFER_ZBLOCK")
#define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END __section_end("NONCACHE_BUFFER_ZBLOCK")
#define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START __section_begin("SHARED_NONCACHE_BUFFER_ZBLOCK")
#define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END __section_end("SHARED_NONCACHE_BUFFER_ZBLOCK")
#define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START __section_begin("DMAC_LINK_MODE_ZBLOCK")
#define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END __section_end("DMAC_LINK_MODE_ZBLOCK")
#endif
#elif defined(__GNUC__)
#if BSP_CFG_C_RUNTIME_INIT
#define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS &_mloader_data
#define BSP_PRV_SECTION_LDR_DATA_RAM_START &__loader_data_start
#define BSP_PRV_SECTION_LDR_DATA_RAM_END &__loader_data_end
#define BSP_PRV_SECTION_LDR_DATA_BSS_START &__loader_bss_start
#define BSP_PRV_SECTION_LDR_DATA_BSS_END &__loader_bss_end
#endif
#if !(BSP_CFG_RAM_EXECUTION)
#define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS &_mfvector
#define BSP_PRV_SECTION_VECTOR_RAM_START &_fvector_start
#define BSP_PRV_SECTION_VECTOR_RAM_END &_fvector_end
#define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS &_mtext
#define BSP_PRV_SECTION_USER_PRG_RAM_START &_text_start
#define BSP_PRV_SECTION_USER_PRG_RAM_END &_text_end
#define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS &_mdata
#define BSP_PRV_SECTION_USER_DATA_RAM_START &_data_start
#define BSP_PRV_SECTION_USER_DATA_RAM_END &_data_end
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS &_mdata_noncache
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START &_data_noncache_start
#define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END &_data_noncache_end
#endif
#define BSP_PRV_SECTION_USER_DATA_BSS_START &__bss_start__
#define BSP_PRV_SECTION_USER_DATA_BSS_END &__bss_end__
#if BSP_CFG_RAM_EXECUTION
#define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START &_ncbuffer_start
#define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END &_ncbuffer_end
#define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START &_sncbuffer_start
#define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END &_sncbuffer_end
#define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START &_DmacLinkMode_start
#define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END &_DmacLinkMode_end
#endif
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/** System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = 0U;
/** @} (end addtogroup BSP_MCU) */
#if defined(__ICCARM__)
#if BSP_CFG_C_RUNTIME_INIT
#pragma section="LDR_DATA_RBLOCK"
#pragma section="LDR_DATA_WBLOCK"
#pragma section="LDR_DATA_ZBLOCK"
#endif
#if !(BSP_CFG_RAM_EXECUTION)
#pragma section="VECTOR_RBLOCK"
#pragma section="VECTOR_WBLOCK"
#pragma section="USER_PRG_RBLOCK"
#pragma section="USER_PRG_WBLOCK"
#pragma section="USER_DATA_RBLOCK"
#pragma section="USER_DATA_WBLOCK"
#pragma section="USER_DATA_ZBLOCK"
#pragma section="USER_DATA_NONCACHE_RBLOCK"
#pragma section="USER_DATA_NONCACHE_WBLOCK"
#endif
#if BSP_CFG_RAM_EXECUTION
#pragma section="NONCACHE_BUFFER_ZBLOCK"
#pragma section="SHARED_NONCACHE_BUFFER_ZBLOCK"
#pragma section="DMAC_LINK_MODE_ZBLOCK"
#endif
#elif defined(__GNUC__)
#if BSP_CFG_C_RUNTIME_INIT
extern void * _mloader_data;
extern void * __loader_data_start;
extern void * __loader_data_end;
extern void * __loader_bss_start;
extern void * __loader_bss_end;
extern void (* __preinit_array_start[])(void);
extern void (* __preinit_array_end[])(void);
extern void (* __init_array_start[])(void);
extern void (* __init_array_end[])(void);
#endif
#if !(BSP_CFG_RAM_EXECUTION)
extern void * _mfvector;
extern void * _fvector_start;
extern void * _fvector_end;
extern void * _mtext;
extern void * _text_start;
extern void * _text_end;
extern void * _mdata;
extern void * _data_start;
extern void * _data_end;
extern void * _mdata_noncache;
extern void * _data_noncache_start;
extern void * _data_noncache_end;
#endif
extern void * __bss_start__;
extern void * __bss_end__;
#if BSP_CFG_RAM_EXECUTION
extern void * _ncbuffer_start;
extern void * _ncbuffer_end;
extern void * _sncbuffer_start;
extern void * _sncbuffer_end;
extern void * _DmacLinkMode_start;
extern void * _DmacLinkMode_end;
#endif
#endif
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#if defined(__ICCARM__)
#if BSP_CFG_C_RUNTIME_INIT
extern void __iar_data_init3(void);
#endif
#endif
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED)
const uint32_t g_bsp_master_mpu0_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(0, 0), BSP_PRV_MASTER_MPU_ENDADD(0, 0)},
{BSP_PRV_MASTER_MPU_STADD(0, 1), BSP_PRV_MASTER_MPU_ENDADD(0, 1)},
{BSP_PRV_MASTER_MPU_STADD(0, 2), BSP_PRV_MASTER_MPU_ENDADD(0, 2)},
{BSP_PRV_MASTER_MPU_STADD(0, 3), BSP_PRV_MASTER_MPU_ENDADD(0, 3)},
{BSP_PRV_MASTER_MPU_STADD(0, 4), BSP_PRV_MASTER_MPU_ENDADD(0, 4)},
{BSP_PRV_MASTER_MPU_STADD(0, 5), BSP_PRV_MASTER_MPU_ENDADD(0, 5)},
{BSP_PRV_MASTER_MPU_STADD(0, 6), BSP_PRV_MASTER_MPU_ENDADD(0, 6)},
{BSP_PRV_MASTER_MPU_STADD(0, 7), BSP_PRV_MASTER_MPU_ENDADD(0, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED)
const uint32_t g_bsp_master_mpu1_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(1, 0), BSP_PRV_MASTER_MPU_ENDADD(1, 0)},
{BSP_PRV_MASTER_MPU_STADD(1, 1), BSP_PRV_MASTER_MPU_ENDADD(1, 1)},
{BSP_PRV_MASTER_MPU_STADD(1, 2), BSP_PRV_MASTER_MPU_ENDADD(1, 2)},
{BSP_PRV_MASTER_MPU_STADD(1, 3), BSP_PRV_MASTER_MPU_ENDADD(1, 3)},
{BSP_PRV_MASTER_MPU_STADD(1, 4), BSP_PRV_MASTER_MPU_ENDADD(1, 4)},
{BSP_PRV_MASTER_MPU_STADD(1, 5), BSP_PRV_MASTER_MPU_ENDADD(1, 5)},
{BSP_PRV_MASTER_MPU_STADD(1, 6), BSP_PRV_MASTER_MPU_ENDADD(1, 6)},
{BSP_PRV_MASTER_MPU_STADD(1, 7), BSP_PRV_MASTER_MPU_ENDADD(1, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED)
const uint32_t g_bsp_master_mpu2_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(2, 0), BSP_PRV_MASTER_MPU_ENDADD(2, 0)},
{BSP_PRV_MASTER_MPU_STADD(2, 1), BSP_PRV_MASTER_MPU_ENDADD(2, 1)},
{BSP_PRV_MASTER_MPU_STADD(2, 2), BSP_PRV_MASTER_MPU_ENDADD(2, 2)},
{BSP_PRV_MASTER_MPU_STADD(2, 3), BSP_PRV_MASTER_MPU_ENDADD(2, 3)},
{BSP_PRV_MASTER_MPU_STADD(2, 4), BSP_PRV_MASTER_MPU_ENDADD(2, 4)},
{BSP_PRV_MASTER_MPU_STADD(2, 5), BSP_PRV_MASTER_MPU_ENDADD(2, 5)},
{BSP_PRV_MASTER_MPU_STADD(2, 6), BSP_PRV_MASTER_MPU_ENDADD(2, 6)},
{BSP_PRV_MASTER_MPU_STADD(2, 7), BSP_PRV_MASTER_MPU_ENDADD(2, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED)
const uint32_t g_bsp_master_mpu3_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(3, 0), BSP_PRV_MASTER_MPU_ENDADD(3, 0)},
{BSP_PRV_MASTER_MPU_STADD(3, 1), BSP_PRV_MASTER_MPU_ENDADD(3, 1)},
{BSP_PRV_MASTER_MPU_STADD(3, 2), BSP_PRV_MASTER_MPU_ENDADD(3, 2)},
{BSP_PRV_MASTER_MPU_STADD(3, 3), BSP_PRV_MASTER_MPU_ENDADD(3, 3)},
{BSP_PRV_MASTER_MPU_STADD(3, 4), BSP_PRV_MASTER_MPU_ENDADD(3, 4)},
{BSP_PRV_MASTER_MPU_STADD(3, 5), BSP_PRV_MASTER_MPU_ENDADD(3, 5)},
{BSP_PRV_MASTER_MPU_STADD(3, 6), BSP_PRV_MASTER_MPU_ENDADD(3, 6)},
{BSP_PRV_MASTER_MPU_STADD(3, 7), BSP_PRV_MASTER_MPU_ENDADD(3, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED)
const uint32_t g_bsp_master_mpu4_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(4, 0), BSP_PRV_MASTER_MPU_ENDADD(4, 0)},
{BSP_PRV_MASTER_MPU_STADD(4, 1), BSP_PRV_MASTER_MPU_ENDADD(4, 1)},
{BSP_PRV_MASTER_MPU_STADD(4, 2), BSP_PRV_MASTER_MPU_ENDADD(4, 2)},
{BSP_PRV_MASTER_MPU_STADD(4, 3), BSP_PRV_MASTER_MPU_ENDADD(4, 3)},
{BSP_PRV_MASTER_MPU_STADD(4, 4), BSP_PRV_MASTER_MPU_ENDADD(4, 4)},
{BSP_PRV_MASTER_MPU_STADD(4, 5), BSP_PRV_MASTER_MPU_ENDADD(4, 5)},
{BSP_PRV_MASTER_MPU_STADD(4, 6), BSP_PRV_MASTER_MPU_ENDADD(4, 6)},
{BSP_PRV_MASTER_MPU_STADD(4, 7), BSP_PRV_MASTER_MPU_ENDADD(4, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED)
const uint32_t g_bsp_master_mpu6_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(6, 0), BSP_PRV_MASTER_MPU_ENDADD(6, 0)},
{BSP_PRV_MASTER_MPU_STADD(6, 1), BSP_PRV_MASTER_MPU_ENDADD(6, 1)},
{BSP_PRV_MASTER_MPU_STADD(6, 2), BSP_PRV_MASTER_MPU_ENDADD(6, 2)},
{BSP_PRV_MASTER_MPU_STADD(6, 3), BSP_PRV_MASTER_MPU_ENDADD(6, 3)},
{BSP_PRV_MASTER_MPU_STADD(6, 4), BSP_PRV_MASTER_MPU_ENDADD(6, 4)},
{BSP_PRV_MASTER_MPU_STADD(6, 5), BSP_PRV_MASTER_MPU_ENDADD(6, 5)},
{BSP_PRV_MASTER_MPU_STADD(6, 6), BSP_PRV_MASTER_MPU_ENDADD(6, 6)},
{BSP_PRV_MASTER_MPU_STADD(6, 7), BSP_PRV_MASTER_MPU_ENDADD(6, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED)
const uint32_t g_bsp_master_mpu7_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(7, 0), BSP_PRV_MASTER_MPU_ENDADD(7, 0)},
{BSP_PRV_MASTER_MPU_STADD(7, 1), BSP_PRV_MASTER_MPU_ENDADD(7, 1)},
{BSP_PRV_MASTER_MPU_STADD(7, 2), BSP_PRV_MASTER_MPU_ENDADD(7, 2)},
{BSP_PRV_MASTER_MPU_STADD(7, 3), BSP_PRV_MASTER_MPU_ENDADD(7, 3)},
{BSP_PRV_MASTER_MPU_STADD(7, 4), BSP_PRV_MASTER_MPU_ENDADD(7, 4)},
{BSP_PRV_MASTER_MPU_STADD(7, 5), BSP_PRV_MASTER_MPU_ENDADD(7, 5)},
{BSP_PRV_MASTER_MPU_STADD(7, 6), BSP_PRV_MASTER_MPU_ENDADD(7, 6)},
{BSP_PRV_MASTER_MPU_STADD(7, 7), BSP_PRV_MASTER_MPU_ENDADD(7, 7)}
};
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED)
const uint32_t g_bsp_master_mpu8_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] =
{
{BSP_PRV_MASTER_MPU_STADD(8, 0), BSP_PRV_MASTER_MPU_ENDADD(8, 0)},
{BSP_PRV_MASTER_MPU_STADD(8, 1), BSP_PRV_MASTER_MPU_ENDADD(8, 1)},
{BSP_PRV_MASTER_MPU_STADD(8, 2), BSP_PRV_MASTER_MPU_ENDADD(8, 2)},
{BSP_PRV_MASTER_MPU_STADD(8, 3), BSP_PRV_MASTER_MPU_ENDADD(8, 3)},
{BSP_PRV_MASTER_MPU_STADD(8, 4), BSP_PRV_MASTER_MPU_ENDADD(8, 4)},
{BSP_PRV_MASTER_MPU_STADD(8, 5), BSP_PRV_MASTER_MPU_ENDADD(8, 5)},
{BSP_PRV_MASTER_MPU_STADD(8, 6), BSP_PRV_MASTER_MPU_ENDADD(8, 6)},
{BSP_PRV_MASTER_MPU_STADD(8, 7), BSP_PRV_MASTER_MPU_ENDADD(8, 7)}
};
#endif
#if defined(__ICCARM__)
void R_BSP_WarmStart(bsp_warm_start_event_t event);
#pragma weak R_BSP_WarmStart
#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
#endif
#if BSP_CFG_C_RUNTIME_INIT
void bsp_loader_data_init(void);
void bsp_loader_bss_init(void);
void bsp_static_constructor_init(void);
#endif
void bsp_copy_multibyte(uintptr_t * src, uintptr_t * dst, uintptr_t bytesize);
void bsp_bss_init_multibyte(uintptr_t * src, uintptr_t bytesize);
#if !(BSP_CFG_RAM_EXECUTION)
void bsp_copy_to_ram(void);
void bsp_application_bss_init(void);
#endif
void bsp_master_mpu_init(void);
void bsp_global_system_counter_init(void);
#if BSP_FEATURE_TFU_SUPPORTED
void bsp_tfu_init(void);
#endif
#if !BSP_CFG_PORT_PROTECT
void bsp_release_port_protect(void);
#endif
/*******************************************************************************************************************//**
* Initialize the Master-MPU settings.
**********************************************************************************************************************/
void bsp_master_mpu_init (void)
{
/* Disable register protection for Master-MPU related registers. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM);
for (uint8_t region_num = 0; region_num < BSP_PRV_MASTER_MPU_REGION_NUM; region_num++)
{
#if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED)
R_MPU0->RGN[region_num].STADD = g_bsp_master_mpu0_cfg[region_num][0];
R_MPU0->RGN[region_num].ENDADD = g_bsp_master_mpu0_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED)
R_MPU1->RGN[region_num].STADD = g_bsp_master_mpu1_cfg[region_num][0];
R_MPU1->RGN[region_num].ENDADD = g_bsp_master_mpu1_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED)
R_MPU2->RGN[region_num].STADD = g_bsp_master_mpu2_cfg[region_num][0];
R_MPU2->RGN[region_num].ENDADD = g_bsp_master_mpu2_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED)
R_MPU3->RGN[region_num].STADD = g_bsp_master_mpu3_cfg[region_num][0];
R_MPU3->RGN[region_num].ENDADD = g_bsp_master_mpu3_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED)
R_MPU4->RGN[region_num].STADD = g_bsp_master_mpu4_cfg[region_num][0];
R_MPU4->RGN[region_num].ENDADD = g_bsp_master_mpu4_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED)
R_MPU6->RGN[region_num].STADD = g_bsp_master_mpu6_cfg[region_num][0];
R_MPU6->RGN[region_num].ENDADD = g_bsp_master_mpu6_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED)
R_MPU7->RGN[region_num].STADD = g_bsp_master_mpu7_cfg[region_num][0];
R_MPU7->RGN[region_num].ENDADD = g_bsp_master_mpu7_cfg[region_num][1];
#endif
#if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED)
R_MPU8->RGN[region_num].STADD = g_bsp_master_mpu8_cfg[region_num][0];
R_MPU8->RGN[region_num].ENDADD = g_bsp_master_mpu8_cfg[region_num][1];
#endif
}
/* Enable register protection for Master-MPU related registers. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM);
}
/*******************************************************************************************************************//**
* Initialize global system counter. The counter is enabled and is incrementing.
**********************************************************************************************************************/
void bsp_global_system_counter_init (void)
{
/* Initialize registers related the global system counter. */
R_GSC->CNTCR &= (uint32_t) (~R_GSC_CNTCR_EN_Msk);
R_GSC->CNTFID0 = BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ;
R_GSC->CNTCVL = 0;
R_GSC->CNTCVU = 0;
R_GSC->CNTCR |= R_GSC_CNTCR_EN_Msk;
}
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* This function is called at various points during the startup process.
* This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
* implemented version. One of the main uses for this function is to call functional safety code during the startup
* process. To use this function just copy this function into your own code and modify it to meet your needs.
*
* @param[in] event Where the code currently is in the start up process
*
*
* @note All programs to be executed when BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK event occurs should be
* placed in BTCM. These events occur before copying the application program in startup code is executed, and
* therefore the application program is located on ROM and cannot be executed at that time.
* Linker script for FSP specifies that .warm_start section is to be placed at BTCM. Adding the section
* designation to function or variable definition makes it easy to place at BTCM.
**********************************************************************************************************************/
void R_BSP_WarmStart (bsp_warm_start_event_t event)
{
if (BSP_WARM_START_RESET == event)
{
/* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
}
if (BSP_WARM_START_POST_CLOCK == event)
{
/* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
}
else if (BSP_WARM_START_POST_C == event)
{
/* C runtime environment, system clocks, and pins are all setup. */
}
else
{
/* Do nothing */
}
}
/** @} (end addtogroup BSP_MCU) */
#if BSP_CFG_C_RUNTIME_INIT
/*******************************************************************************************************************//**
* Copy the loader data block from external Flash to internal RAM.
**********************************************************************************************************************/
void bsp_loader_data_init (void)
{
#if (!defined(__GNUC__) || !(BSP_CFG_RAM_EXECUTION))
/* Define destination/source address pointer and block size */
uintptr_t * src;
uintptr_t * dst;
uintptr_t size;
/* Copy loader data block */
src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS;
dst = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_RAM_START;
size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_START;
bsp_copy_multibyte(src, dst, size);
#endif
}
/*******************************************************************************************************************//**
* Clear the loader bss block in internal RAM.
**********************************************************************************************************************/
void bsp_loader_bss_init (void)
{
/* Define source address pointer and block size */
uintptr_t * src;
uintptr_t size;
/* Clear loader bss block. */
src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_START;
bsp_bss_init_multibyte(src, size);
#if BSP_CFG_RAM_EXECUTION
#if defined(__ICCARM__)
/* Initialize the application data and clear the application bss.
* This code is for RAM Execution. If you want to boot with ROM,
* enable app_copy and app_bss_init, and disable this code.
* Also need to change icf file. */
__iar_data_init3();
#elif defined(__GNUC__)
/* Clear application bss block. */
src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START;
bsp_bss_init_multibyte(src, size);
#endif
/* Clear non-cache buffer block. */
src = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END -
(uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START;
bsp_bss_init_multibyte(src, size);
/* Clear shared non-cache buffer block. */
src = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END -
(uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START;
bsp_bss_init_multibyte(src, size);
/* Clear DMAC link mode data block. */
src = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END -
(uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START;
bsp_bss_init_multibyte(src, size);
#endif
}
#endif
/*******************************************************************************************************************//**
* Copy the memory block from Source address to Destination address by the multi byte unit.
**********************************************************************************************************************/
void bsp_copy_multibyte (uintptr_t * src, uintptr_t * dst, uintptr_t bytesize)
{
uintptr_t i;
uintptr_t cnt;
uintptr_t src_mod;
uint8_t * src_single_byte;
uint8_t * dst_single_byte;
if (0 != bytesize)
{
/* Copy Count in single byte unit */
src_mod = (uintptr_t) src % sizeof(uintptr_t);
if (0 != src_mod)
{
src_single_byte = (uint8_t *) src;
dst_single_byte = (uint8_t *) dst;
for (i = 0; i < src_mod; i++)
{
*dst_single_byte++ = *src_single_byte++;
}
dst = (uintptr_t *) dst_single_byte;
src = (uintptr_t *) src_single_byte;
bytesize -= src_mod;
}
else
{
/* Do nothing */
}
/* Copy Count in multi byte unit */
cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t);
for (i = 0; i < cnt; i++)
{
*dst++ = *src++;
}
/* Ensuring data-changing */
__asm volatile ("DSB SY");
}
else
{
/* Do nothing */
}
}
/*******************************************************************************************************************//**
* Clear the bss block by the multi byte unit.
**********************************************************************************************************************/
void bsp_bss_init_multibyte (uintptr_t * src, uintptr_t bytesize)
{
uintptr_t i;
uintptr_t cnt;
uintptr_t zero = 0;
uintptr_t src_mod;
uint8_t * src_single_byte;
uint8_t zero_single_byte = 0;
if (0 != bytesize)
{
/* Clear Count in single byte unit */
src_mod = (uintptr_t) src % sizeof(uintptr_t);
if (0 != src_mod)
{
src_single_byte = (uint8_t *) src;
for (i = 0; i < src_mod; i++)
{
*src_single_byte++ = zero_single_byte;
}
src = (uintptr_t *) src_single_byte;
bytesize -= src_mod;
}
else
{
/* Do nothing */
}
/* Clear Count in multi byte unit */
cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t);
for (i = 0; i < cnt; i++)
{
*src++ = zero;
}
/* Ensuring data-changing */
__asm volatile ("DSB SY");
}
else
{
/* Do nothing */
}
}
#if !(BSP_CFG_RAM_EXECUTION)
/*******************************************************************************************************************//**
* Copy the application program block from external Flash to internal RAM.
**********************************************************************************************************************/
void bsp_copy_to_ram (void)
{
/* Define destination/source address pointer and block size */
uintptr_t * src;
uintptr_t * dst;
uintptr_t size;
/* Copy exception vector block */
src = (uintptr_t *) BSP_PRV_SECTION_VECTOR_ROM_ADDRESS;
dst = (uintptr_t *) BSP_PRV_SECTION_VECTOR_RAM_START;
size = (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_END - (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START;
bsp_copy_multibyte(src, dst, size);
/* Copy user program block */
src = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS;
dst = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_RAM_START;
size = (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_START;
bsp_copy_multibyte(src, dst, size);
/* Copy user data block */
src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS;
dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_RAM_START;
size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_START;
bsp_copy_multibyte(src, dst, size);
/* Copy user data_noncache block */
src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS;
dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END -
(uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START;
bsp_copy_multibyte(src, dst, size);
}
/*******************************************************************************************************************//**
* Clear the application bss block in internal RAM.
**********************************************************************************************************************/
void bsp_application_bss_init (void)
{
/* Define source address pointer and block size */
uintptr_t * src;
uintptr_t size;
/* Clear application bss block. */
src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START;
size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START;
bsp_bss_init_multibyte(src, size);
}
#endif
#if BSP_FEATURE_TFU_SUPPORTED
void bsp_tfu_init (void)
{
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
R_BSP_MODULE_START(FSP_IP_TFU, 0U);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
}
#endif
#if !BSP_CFG_PORT_PROTECT
void bsp_release_port_protect (void)
{
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
}
#endif
/*******************************************************************************************************************//**
* Initialize static constructors.
**********************************************************************************************************************/
#if BSP_CFG_C_RUNTIME_INIT
void bsp_static_constructor_init (void)
{
#if defined(__ICCARM__)
#if !(BSP_CFG_RAM_EXECUTION)
/* In the case of ROM boot, initialization of static constructors is performed by __iar_data_init3(). */
__iar_data_init3();
#endif
#elif defined(__GNUC__)
intptr_t count;
intptr_t i;
count = __preinit_array_end - __preinit_array_start;
for (i = 0; i < count; i++)
{
__preinit_array_start[i]();
}
count = __init_array_end - __init_array_start;
for (i = 0; i < count; i++)
{
__init_array_start[i]();
}
#endif
}
#endif
/* This vector table is for SGI and PPI interrupts. */
BSP_DONT_REMOVE fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES] =
{
NULL, /* INTID0 : SOFTWARE_GENERATE_INT0 */
NULL, /* INTID1 : SOFTWARE_GENERATE_INT1 */
NULL, /* INTID2 : SOFTWARE_GENERATE_INT2 */
NULL, /* INTID3 : SOFTWARE_GENERATE_INT3 */
NULL, /* INTID4 : SOFTWARE_GENERATE_INT4 */
NULL, /* INTID5 : SOFTWARE_GENERATE_INT5 */
NULL, /* INTID6 : SOFTWARE_GENERATE_INT6 */
NULL, /* INTID7 : SOFTWARE_GENERATE_INT7 */
NULL, /* INTID8 : SOFTWARE_GENERATE_INT8 */
NULL, /* INTID9 : SOFTWARE_GENERATE_INT9 */
NULL, /* INTID10 : SOFTWARE_GENERATE_INT10 */
NULL, /* INTID11 : SOFTWARE_GENERATE_INT11 */
NULL, /* INTID12 : SOFTWARE_GENERATE_INT12 */
NULL, /* INTID13 : SOFTWARE_GENERATE_INT13 */
NULL, /* INTID14 : SOFTWARE_GENERATE_INT14 */
NULL, /* INTID15 : SOFTWARE_GENERATE_INT15 */
NULL, /* INTID16 : RESERVED */
NULL, /* INTID17 : RESERVED */
NULL, /* INTID18 : RESERVED */
NULL, /* INTID19 : RESERVED */
NULL, /* INTID20 : RESERVED */
NULL, /* INTID21 : RESERVED */
NULL, /* INTID22 : DEBUG_COMMUNICATIONS_CHANNEL_INT */
NULL, /* INTID23 : PERFORMANCE_MONITOR_COUNTER_OVERFLOW_INT */
NULL, /* INTID24 : CROSS_TRIGGER_INTERFACE_INT */
NULL, /* INTID25 : VIRTUAL_CPU_INTERFACE_MAINTENANCE_INT */
NULL, /* INTID26 : HYPERVISOR_TIMER_INT */
NULL, /* INTID27 : VIRTUAL_TIMER_INT */
NULL, /* INTID28 : RESERVED */
NULL, /* INTID29 : RESERVED */
NULL, /* INTID30 : NON-SECURE_PHYSICAL_TIMER_INT */
NULL, /* INTID31 : RESERVED */
};

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@ -0,0 +1,752 @@
/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_PRV_SCTLR_ELX_BIT_I (0x1000U)
#define BSP_PRV_SCTLR_ELX_BIT_C (0x4U)
#define BSP_PRV_SCTLR_ELX_BIT_M (0x1U)
#define BSP_PRV_CLIDR_CTYPE_OFFSET (3U)
#define BSP_PRV_CLIDR_CTYPE_MASK (7U)
#define BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE (2U)
#define BSP_PRV_CLIDR_LOC_OFFSET (24U)
#define BSP_PRV_CLIDR_LOC_MASK (7U)
#define BSP_PRV_CCSIDR_LINESIZE_OFFSET (0U)
#define BSP_PRV_CCSIDR_LINESIZE_MASK (7U)
#define BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE (4U)
#define BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET (3U)
#define BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK (0x3FFU)
#define BSP_PRV_CCSIDR_NUMSETS_OFFSET (13U)
#define BSP_PRV_CCSIDR_NUMSETS_MASK (0x7FFFU)
#define BSP_PRV_CCSIDR_SHIFT_MAX (32U)
#define BSP_PRV_CSSELR_LEVEL_OFFSET (1U)
#define BSP_PRV_CTR_IMINLINE_OFFSET (0U)
#define BSP_PRV_CTR_IMINLINE_MASK (0xFU)
#define BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS (4U)
#define BSP_PRV_CTR_IMINLINE_ADDRESS_MASK (1U)
#define BSP_PRV_CTR_DMINLINE_OFFSET (16U)
#define BSP_PRV_CTR_DMINLINE_MASK (0xFU)
#define BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS (4U)
#define BSP_PRV_CTR_DMINLINE_ADDRESS_MASK (1U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Enable instruction caching.
**********************************************************************************************************************/
void R_BSP_CacheEnableInst (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr |= BSP_PRV_SCTLR_ELX_BIT_I;
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Enable data caching.
**********************************************************************************************************************/
void R_BSP_CacheEnableData (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr |= BSP_PRV_SCTLR_ELX_BIT_C;
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Enable memory protect.
**********************************************************************************************************************/
void R_BSP_CacheEnableMemoryProtect (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr |= BSP_PRV_SCTLR_ELX_BIT_M;
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Disable instruction caching.
**********************************************************************************************************************/
void R_BSP_CacheDisableInst (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_I);
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Disable data caching.
**********************************************************************************************************************/
void R_BSP_CacheDisableData (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_C);
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Disable memory protect.
**********************************************************************************************************************/
void R_BSP_CacheDisableMemoryProtect (void)
{
uintptr_t sctlr;
sctlr = __get_SCTLR();
sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_M);
__asm volatile ("DSB SY");
__set_SCTLR(sctlr);
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Clean data cache by set/way.
* Clean means writing the cache data to memory and clear the dirty bits
* if there is a discrepancy between the cache and memory data.
**********************************************************************************************************************/
void R_BSP_CacheCleanAll (void)
{
uintptr_t clidr;
uintptr_t clidr_loc;
uintptr_t clidr_ctype;
uintptr_t clidr_ctype_shift;
uintptr_t csselr;
uintptr_t csselr_level;
uintptr_t ccsidr;
uintptr_t ccsidr_linesize;
uintptr_t ccsidr_associativity;
uintptr_t ccsidr_associativity_clz;
uintptr_t ccsidr_associativity_value;
uintptr_t ccsidr_associativity_msb;
uintptr_t ccsidr_numsets;
uintptr_t ccsidr_numsets_total;
uintptr_t dccsw;
__asm volatile ("DSB SY");
__set_ICIALLU(0);
__asm volatile ("DMB SY");
/* Reads the maximum level of cache implemented */
clidr = __get_CLIDR();
clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
/* If the cache does not exist, do not process */
if (0 != clidr_loc)
{
/* Loop until all levels of cache are processed */
for (csselr = 0; csselr < clidr_loc; csselr++)
{
/* Read the current level cache type */
clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
/* If no data cache exists in the current level of cache, do not process */
if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
{
/* Set the current level to Cache Size Selection Register */
csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
__set_CSSELR(csselr_level);
__asm volatile ("DSB SY");
/* Read the line size, number of ways, and number of sets for the current level of cache */
ccsidr = __get_CCSIDR();
ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
/* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
{
ccsidr_associativity_clz--;
}
else
{
/* Do Nothing */
}
/* Loop until all sets are processed */
while (1)
{
/* Working copy of number of ways */
ccsidr_associativity_value = ccsidr_associativity;
/* Loop until all ways are processed */
while (1)
{
ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
csselr_level; /* Left shift way */
ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */
dccsw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
/* DCCSW - Data or unified Cache line Clean by Set/Way */
__set_DCCSW(dccsw);
if (0 != ccsidr_associativity_value)
{
ccsidr_associativity_value--;
}
else
{
break;
}
}
if (0 != ccsidr_numsets)
{
ccsidr_numsets--;
}
else
{
break;
}
}
}
else
{
/* Do Nothing */
}
}
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
else
{
/* Do Nothing */
}
}
/*******************************************************************************************************************//**
* Invalidate data cache by set/way.
* Also Invalidate instruction cache.
*
* Invalidate means to delete cache data.
**********************************************************************************************************************/
void R_BSP_CacheInvalidateAll (void)
{
uintptr_t clidr;
uintptr_t clidr_loc;
uintptr_t clidr_ctype;
uintptr_t clidr_ctype_shift;
uintptr_t csselr;
uintptr_t csselr_level;
uintptr_t ccsidr;
uintptr_t ccsidr_linesize;
uintptr_t ccsidr_associativity;
uintptr_t ccsidr_associativity_clz;
uintptr_t ccsidr_associativity_value;
uintptr_t ccsidr_associativity_msb;
uintptr_t ccsidr_numsets;
uintptr_t ccsidr_numsets_total;
uintptr_t dcisw;
__asm volatile ("DSB SY");
__set_ICIALLU(0);
__asm volatile ("DMB SY");
/* Reads the maximum level of cache implemented */
clidr = __get_CLIDR();
clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
/* If the cache does not exist, do not process */
if (0 != clidr_loc)
{
/* Loop until all levels of cache are processed */
for (csselr = 0; csselr < clidr_loc; csselr++)
{
/* Read the current level cache type */
clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
/* If no data cache exists in the current level of cache, do not process */
if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
{
/* Set the current level to Cache Size Selection Register */
csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
__set_CSSELR(csselr_level);
__asm volatile ("DSB SY");
/* Read the line size, number of ways, and number of sets for the current level of cache */
ccsidr = __get_CCSIDR();
ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
/* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
{
ccsidr_associativity_clz--;
}
else
{
/* Do Nothing */
}
/* Loop until all sets are processed */
while (1)
{
/* Working copy of number of ways */
ccsidr_associativity_value = ccsidr_associativity;
/* Loop until all ways are processed */
while (1)
{
ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
csselr_level; /* Left shift way */
ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */
dcisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
/* DCISW - Data or unified Cache line Invalidate by Set/Way */
__set_DCISW(dcisw);
if (0 != ccsidr_associativity_value)
{
ccsidr_associativity_value--;
}
else
{
break;
}
}
if (0 != ccsidr_numsets)
{
ccsidr_numsets--;
}
else
{
break;
}
}
}
else
{
/* Do Nothing */
}
}
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
else
{
/* Do Nothing */
}
}
/*******************************************************************************************************************//**
* Clean and Invalidate data cache by set/way.
* Also Invalidate instruction cache.
*
* Clean means writing the cache data to memory and clear the dirty bits
* if there is a discrepancy between the cache and memory data.
*
* Invalidate means to delete cache data.
**********************************************************************************************************************/
void R_BSP_CacheCleanInvalidateAll (void)
{
uintptr_t clidr;
uintptr_t clidr_loc;
uintptr_t clidr_ctype;
uintptr_t clidr_ctype_shift;
uintptr_t csselr;
uintptr_t csselr_level;
uintptr_t ccsidr;
uintptr_t ccsidr_linesize;
uintptr_t ccsidr_associativity;
uintptr_t ccsidr_associativity_clz;
uintptr_t ccsidr_associativity_value;
uintptr_t ccsidr_associativity_msb;
uintptr_t ccsidr_numsets;
uintptr_t ccsidr_numsets_total;
uintptr_t dccisw;
__asm volatile ("DSB SY");
__set_ICIALLU(0);
__asm volatile ("DMB SY");
/* Reads the maximum level of cache implemented */
clidr = __get_CLIDR();
clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK;
/* If the cache does not exist, do not process */
if (0 != clidr_loc)
{
/* Loop until all levels of cache are processed */
for (csselr = 0; csselr < clidr_loc; csselr++)
{
/* Read the current level cache type */
clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET;
clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK;
/* If no data cache exists in the current level of cache, do not process */
if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype)
{
/* Set the current level to Cache Size Selection Register */
csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET;
__set_CSSELR(csselr_level);
__asm volatile ("DSB SY");
/* Read the line size, number of ways, and number of sets for the current level of cache */
ccsidr = __get_CCSIDR();
ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) +
BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE;
ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) &
BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK;
ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK;
/* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */
ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity);
if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz)
{
ccsidr_associativity_clz--;
}
else
{
/* Do Nothing */
}
/* Loop until all sets are processed */
while (1)
{
/* Working copy of number of ways */
ccsidr_associativity_value = ccsidr_associativity;
/* Loop until all ways are processed */
while (1)
{
ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) |
csselr_level; /* Left shift way */
ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */
dccisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */
/* DCCISW - Data or unified Cache line Clean and Invalidate by Set/Way */
__set_DCCISW(dccisw);
if (0 != ccsidr_associativity_value)
{
ccsidr_associativity_value--;
}
else
{
break;
}
}
if (0 != ccsidr_numsets)
{
ccsidr_numsets--;
}
else
{
break;
}
}
}
else
{
/* Do Nothing */
}
}
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
else
{
/* Do Nothing */
}
}
/*******************************************************************************************************************//**
* Clean data cache and Invalidate instruction cache by address.
*
* Clean means writing the cache data to memory and clear the dirty bits
* if there is a discrepancy between the cache and memory data.
*
* Invalidate means to delete cache data.
*
* @param[in] base_address Start address of area you want to Clean.
* @param[in] length Size of area you want to Clean.
**********************************************************************************************************************/
void R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length)
{
uintptr_t end_address;
uintptr_t ctr;
uintptr_t dminline;
uintptr_t dminline_size;
uintptr_t dccvac;
uintptr_t iminline;
uintptr_t iminline_size;
uintptr_t icivau;
end_address = base_address + length;
/* Calculate data cache line size */
ctr = __get_CTR();
dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
/* Align base address with cache line */
dccvac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
do
{
/* Data or unified Cache line Clean by VA to PoC */
__set_DCCVAC(dccvac);
dccvac += dminline_size; /* Next data line */
} while (end_address > dccvac);
__asm volatile ("DSB SY");
/* Calculate instruction cache line size */
iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
/* Align base address with cache line */
icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
do
{
/* Instruction Cache line Invalidate by VA to PoU */
__set_ICIVAU(icivau);
icivau += iminline_size; /* Next data line */
} while (end_address == icivau);
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Invalidate instruction and data cache by address.
*
* Invalidate means to delete cache data.
*
* @param[in] base_address Start address of area you want to Invalidate.
* @param[in] length Size of area you want to Invalidate.
**********************************************************************************************************************/
void R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length)
{
uintptr_t end_address;
uintptr_t ctr;
uintptr_t dminline;
uintptr_t dminline_size;
uintptr_t dcivac;
uintptr_t iminline;
uintptr_t iminline_size;
uintptr_t icivau;
end_address = base_address + length;
/* Calculate data cache line size */
ctr = __get_CTR();
dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
/* Align base address with cache line */
dcivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
do
{
/* Data or unified Cache line Invalidate by VA to PoC */
__set_DCIVAC(dcivac);
dcivac += dminline_size; /* Next data line */
} while (end_address > dcivac);
__asm volatile ("DSB SY");
/* Calculate instruction cache line size */
iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
/* Align base address with cache line */
icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
do
{
/* Instruction Cache line Invalidate by VA to PoU */
__set_ICIVAU(icivau);
icivau += iminline_size; /* Next data line */
} while (end_address == icivau);
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Clean and Invalidate data cache and Invalidate instruction cache by address.
*
* Clean means writing the cache data to memory and clear the dirty bits
* if there is a discrepancy between the cache and memory data.
*
* Invalidate means to delete cache data.
*
* @param[in] base_address Start address of area you want to Clean and Invalidate.
* @param[in] length Size of area you want to Clean and Invalidate.
**********************************************************************************************************************/
void R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length)
{
uintptr_t end_address;
uintptr_t ctr;
uintptr_t dminline;
uintptr_t dminline_size;
uintptr_t dccivac;
uintptr_t iminline;
uintptr_t iminline_size;
uintptr_t icivau;
end_address = base_address + length;
/* Calculate data cache line size */
ctr = __get_CTR();
dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK;
dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline);
/* Align base address with cache line */
dccivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK);
do
{
/* Data or unified Cache line Clean and Invalidate by VA to PoC */
__set_DCCIVAC(dccivac);
dccivac += dminline_size; /* Next data line */
} while (end_address > dccivac);
__asm volatile ("DSB SY");
/* Calculate instruction cache line size */
iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK;
iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline);
/* Align base address with cache line */
icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK);
do
{
/* Instruction Cache line Invalidate by VA to PoU */
__set_ICIVAU(icivau);
icivau += iminline_size; /* Next data line */
} while (end_address == icivau);
__asm volatile ("DSB SY");
__asm volatile ("ISB SY");
}
/*******************************************************************************************************************//**
* Powers on and off the L3 cache way.
* CA55 only.
**********************************************************************************************************************/
void R_BSP_CacheL3PowerCtrl (void)
{
r_bsp_cache_l3_power_ctrl();
}
/*******************************************************************************************************************//**
* @} (end addtogroup BSP_MCU)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_CACHE_H
#define BSP_CACHE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if defined(BSP_CFG_CORE_CR52)
#include "cr/bsp_cache_core.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void R_BSP_CacheEnableInst(void);
void R_BSP_CacheEnableData(void);
void R_BSP_CacheEnableMemoryProtect(void);
void R_BSP_CacheDisableInst(void);
void R_BSP_CacheDisableData(void);
void R_BSP_CacheDisableMemoryProtect(void);
void R_BSP_CacheCleanAll(void);
void R_BSP_CacheInvalidateAll(void);
void R_BSP_CacheCleanInvalidateAll(void);
void R_BSP_CacheCleanRange(uintptr_t base_address, uintptr_t length);
void R_BSP_CacheInvalidateRange(uintptr_t base_address, uintptr_t length);
void R_BSP_CacheCleanInvalidateRange(uintptr_t base_address, uintptr_t length);
void R_BSP_CacheL3PowerCtrl(void);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_clocks.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_CGC_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x1U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
/* Key code for writing PCMD register. */
#define BSP_PRV_PCMD_KEY (0xA5U)
/* Calculate the value to write to SCKCR. */
#define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U)
#define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U)
#define BSP_PRV_STARTUP_SCKCR_CKIO_BITS ((BSP_CFG_CKIO & 7U) << 16U)
#define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U)
#define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS ((BSP_CFG_PHYSEL & 1U) << 21U)
#define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS ((BSP_CFG_CLMASEL & 1U) << 22U)
#define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U)
#define BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS ((BSP_CFG_SPI1ASYNCCLK & 1U) << 25U)
#define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U)
#define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U)
#define BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS ((BSP_CFG_SCI1ASYNCCLK & 1U) << 28U)
#define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U)
#define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U)
#define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U)
/* Calculate the value to write to SCKCR2. */
#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U)
#define BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS (1U << 4U) // The write value should be 1.
#define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS ((BSP_CFG_DIVSELSUB & 1U) << 5U)
#define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS ((BSP_CFG_SPI3ASYNCCLK & 1U) << 24U)
#define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U)
#define BSP_PRV_STARTUP_SCKCR (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \
BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \
BSP_PRV_STARTUP_SCKCR_CKIO_BITS | \
BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS | \
BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS)
#define BSP_PRV_STARTUP_SCKCR2 (BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS | \
BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS | \
BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS | \
BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \
BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS)
#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2 << \
R_SYSC_S_SCKCR2_FSELCPU0_Pos)
/* Calculate the value to write to HIZCTRLEN. */
#define BSP_PRV_STARTUP_HIZCTRLEN ((BSP_CFG_CLMA1MASK << 2) | (BSP_CFG_CLMA0MASK << 1) | \
BSP_CFG_CLMA3MASK)
/* Frequencies of clocks. */
#define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz
#define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz
/* Command sequence for enabling CLMA. */
#define BSP_PRV_CTL0_ENABLE_TARGET_CMD (0x01)
#define BSP_PRV_CTL0_ENABLE_REVERSED_CMD (0xFE)
#define BSP_PRV_LOCO_STABILIZATION_COUNT (40000)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if !BSP_CFG_SOFT_RESET_SUPPORTED
static void bsp_prv_clock_set_hard_reset(void);
#endif
/*******************************************************************************************************************//**
* @internal
* @addtogroup BSP_MCU_PRV Internal BSP Documentation
* @ingroup RENESAS_INTERNAL
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Update SystemCoreClock variable based on current clock settings.
**********************************************************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t devselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB;
uint32_t fselcpu = (R_SYSC_S->SCKCR2_b.FSELCPU0 & 1U);
if (0U == devselsub)
{
SystemCoreClock = BSP_PRV_CPU_FREQ_200_MHZ << fselcpu;
}
else
{
SystemCoreClock = BSP_PRV_CPU_FREQ_150_MHZ << fselcpu;
}
}
/*******************************************************************************************************************//**
* Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this
* configuration and the CGC registers are expected to be unlocked in PRCR.
*
* @param[in] sckcr Value to set in SCKCR register
* @param[in] sckcr2 Value to set in SCKCR2 register
**********************************************************************************************************************/
void bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2)
{
volatile uint32_t dummy;
sckcr = sckcr & BSP_PRV_SCKCR_MASK;
sckcr2 = sckcr2 & BSP_PRV_SCKCR2_MASK;
/* Set the system source clock */
R_SYSC_S->SCKCR2 = sckcr2;
/** In order to secure processing after clock frequency is changed,
* dummy read the same register at least eight times.
* Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
R_SYSC_NS->SCKCR = sckcr;
/** In order to secure processing after clock frequency is changed,
* dummy read the same register at least eight times.
* Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
FSP_PARAMETER_NOT_USED(dummy);
/* Clock is now at requested frequency. */
/* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
SystemCoreClockUpdate();
}
#if !BSP_CFG_SOFT_RESET_SUPPORTED
static void bsp_prv_clock_set_hard_reset (void)
{
volatile uint32_t dummy;
uint32_t sckcr = BSP_PRV_STARTUP_SCKCR & BSP_PRV_SCKCR_MASK;
uint32_t sckcr2 = BSP_PRV_STARTUP_SCKCR2 & BSP_PRV_SCKCR2_MASK;
/* Set the system source clock */
R_SYSC_S->SCKCR2 = sckcr2;
/** In order to secure processing after clock frequency is changed,
* dummy read the same register at least eight times.
* Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
dummy = R_SYSC_S->SCKCR2;
R_SYSC_NS->SCKCR = sckcr;
/** In order to secure processing after clock frequency is changed,
* dummy read the same register at least eight times.
* Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
dummy = R_SYSC_NS->SCKCR;
FSP_PARAMETER_NOT_USED(dummy);
/* Clock is now at requested frequency. */
/* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
SystemCoreClockUpdate();
}
#endif
/*******************************************************************************************************************//**
* Initializes system clocks. Makes no assumptions about current register settings.
**********************************************************************************************************************/
void bsp_clock_init (void)
{
volatile uint32_t dummy = 0;
/* Unlock CGC protection registers. */
R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK;
/* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
SystemCoreClockUpdate();
/* Set source clock and dividers. */
#if BSP_CFG_SOFT_RESET_SUPPORTED
bsp_prv_clock_set(BSP_PRV_STARTUP_SCKCR, BSP_PRV_STARTUP_SCKCR2);
#else
bsp_prv_clock_set_hard_reset();
#endif
#if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1)
R_SYSC_S->PLL1EN = BSP_CFG_PLL1;
#endif
#if (BSP_CLOCKS_LOCO_ENABLE == BSP_CFG_LOCO_ENABLE)
R_SYSC_S->LOCOCR = BSP_CLOCKS_LOCO_ENABLE;
/* Only start using the LOCO clock after
* the LOCO oscillation stabilization time (tLOCOWT) has elapsed. */
for (uint16_t i = 0; i < BSP_PRV_LOCO_STABILIZATION_COUNT; i++)
{
__asm volatile ("nop");
}
#endif
R_SYSC_S->HIZCTRLEN = BSP_PRV_STARTUP_HIZCTRLEN;
#if (BSP_CLOCKS_CLMA0_ENABLE == BSP_CFG_CLMA0_ENABLE)
/* Set the lower and upper limit for comparing frequency domains. */
R_CLMA0->CMPL = BSP_CFG_CLMA0_CMPL;
R_CLMA0->CMPH = BSP_CFG_CLMA0_CMPH;
/* Enabling CLMA0 operation. */
do
{
R_CLMA0->PCMD = BSP_PRV_PCMD_KEY;
R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
if (1 != R_CLMA0->CTL0)
{
/* Check the value of PROTSR register. */
dummy = R_CLMA0->PROTSR;
}
} while (1 == R_CLMA0->PROTSR_b.PRERR);
#endif
#if (BSP_CLOCKS_CLMA1_ENABLE == BSP_CFG_CLMA1_ENABLE)
/* Set the lower and upper limit for comparing frequency domains. */
R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL;
R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH;
/* Enabling CLMA1 operation. */
do
{
R_CLMA1->PCMD = BSP_PRV_PCMD_KEY;
R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
if (1 != R_CLMA1->CTL0)
{
/* Check the value of PROTSR register. */
dummy = R_CLMA1->PROTSR;
}
} while (1 == R_CLMA1->PROTSR_b.PRERR);
#endif
#if (BSP_CLOCKS_CLMA2_ENABLE == BSP_CFG_CLMA2_ENABLE)
/* Set the lower and upper limit for comparing frequency domains. */
R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL;
R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH;
/* Enabling CLMA2 operation. */
do
{
R_CLMA2->PCMD = BSP_PRV_PCMD_KEY;
R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
if (1 != R_CLMA2->CTL0)
{
/* Check the value of PROTSR register. */
dummy = R_CLMA2->PROTSR;
}
} while (1 == R_CLMA2->PROTSR_b.PRERR);
#endif
#if (BSP_CLOCKS_CLMA3_ENABLE == BSP_CFG_CLMA3_ENABLE)
/* Set the lower and upper limit for comparing frequency domains. */
R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL;
R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH;
/* Enabling CLMA3 operation. */
do
{
R_CLMA3->PCMD = BSP_PRV_PCMD_KEY;
R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD;
R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD;
if (1 != R_CLMA3->CTL0)
{
/* Check the value of PROTSR register. */
dummy = R_CLMA3->PROTSR;
}
} while (1 == R_CLMA3->PROTSR_b.PRERR);
#endif
/* Lock CGC and LPM protection registers. */
R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_LOCK;
R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_LOCK;
FSP_PARAMETER_NOT_USED(dummy);
}
/** @} (end addtogroup BSP_MCU_PRV) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_CLOCKS_H
#define BSP_CLOCKS_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_clock_cfg.h"
#include "bsp_api.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
* not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
/* xSPI unit0 clock options. */
#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI0 base clock 800MHz and xSPI0 clock 133.3MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI0 base clock 800MHz and xSPI0 clock 100.0 MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI0 base clock 800MHz and xSPI0 clock 50.0 MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI0 base clock 800MHz and xSPI0 clock 25.0 MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI0 base clock 800MHz and xSPI0 clock 12.5 MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI0 base clock 600MHz and xSPI0 clock 75.0 MHz.
#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI0 base clock 600MHz and xSPI0 clock 37.5 MHz.
/* xSPI unit1 clock options. */
#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI1 base clock 800MHz and xSPI1 clock 133.3MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI1 base clock 800MHz and xSPI1 clock 100.0 MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI1 base clock 800MHz and xSPI1 clock 50.0 MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI1 base clock 800MHz and xSPI1 clock 25.0 MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI1 base clock 800MHz and xSPI1 clock 12.5 MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI1 base clock 600MHz and xSPI1 clock 75.0 MHz.
#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI1 base clock 600MHz and xSPI1 clock 37.5 MHz.
/* CKIO clock options. */
#define BSP_CLOCKS_CKIO_ICLK_DIV2 (0) // CKIO clock 100.0 MHz (when SCKCR2.DIVSELSUB = 0),
// or 75.0 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV3 (1) // CKIO clock 66.7 MHz (when SCKCR2.DIVSELSUB = 0),
// or 50.0 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV4 (2) // CKIO clock 50.0 MHz (when SCKCR2.DIVSELSUB = 0),
// or 37.5 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV5 (3) // CKIO clock 40.0 MHz (when SCKCR2.DIVSELSUB = 0),
// or 30.0 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV6 (4) // CKIO clock 33.3 MHz (when SCKCR2.DIVSELSUB = 0),
// or 25.0 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV7 (5) // CKIO clock 28.6 MHz (when SCKCR2.DIVSELSUB = 0),
// or 21.4 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_CKIO_ICLK_DIV8 (6) // CKIO clock 25.0 MHz (when SCKCR2.DIVSELSUB = 0),
// or 18.75 MHz (when SCKCR2.DIVSELSUB = 1).
/* CANFD clock options. */
#define BSP_CLOCKS_CANFD_CLOCK_80_MHZ (0) // CANFD clock 80 MHz.
#define BSP_CLOCKS_CANFD_CLOCK_40_MHZ (1) // CANFD clock 40 MHz.
/* Ethernet PHY reference clock (ETHn_REFCLK : n = 0 to 2) options. */
#define BSP_CLOCKS_PHYSEL_PLL1_DIV (0) // PLL1 devider clock.
#define BSP_CLOCKS_PHYSEL_MAINOSC_DIV (1) // Main clock oscillator.
/* Alternative clock options when main clock abnormal oscillation is detected in CLMA3. */
#define BSP_CLOCKS_CLMASEL_LOCO (0) // LOCO clock.
#define BSP_CLOCKS_CLMASEL_PLL (1) // PLL clock.
/* SPI clock options. */
#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI0 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI0 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI1 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI1 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI2 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI2 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI3 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI3 asynchronous serial clock 96.0 MHz.
/* SCI clock options. */
#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI0 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI0 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI1 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI1 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI2 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI2 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI3 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI3 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI4 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI4 asynchronous serial clock 96.0 MHz.
#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI5 asynchronous serial clock 75.0 MHz.
#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI5 asynchronous serial clock 96.0 MHz.
/* CPU0 clock options. */
#define BSP_CLOCKS_FSELCPU0_ICLK_MUL2 (1) // CPU0 clock 400 MHz (when SCKCR2.DIVSELSUB = 0),
// or 300 MHz (when SCKCR2.DIVSELSUB = 1).
#define BSP_CLOCKS_FSELCPU0_ICLK_MUL1 (0) // CPU0 clock 200 MHz (when SCKCR2.DIVSELSUB = 0),
// or 150 MHz (when SCKCR2.DIVSELSUB = 1).
/* Peripheral module base clock options. */
#define BSP_CLOCKS_DIVSELSUB_0 (0) // ICLK:200MHz, PCLKH:200MHz, PCLKM:100MHz,
// PCLKL:50MHz, PCLKADC:25MHz, PCLKGPTL:400MHz.
#define BSP_CLOCKS_DIVSELSUB_1 (1) // ICLK:150MHz, PCLKH:150MHz, PCLKM:75 MHz,
// PCLKL:37.5MHz, PCLKADC:18.75MHz, PCLKGPTL:300MHz.
/* LOCO enable options. */
#define BSP_CLOCKS_LOCO_DISABLE (0) // LOCO Stop
#define BSP_CLOCKS_LOCO_ENABLE (1) // LOCO Run
/* PLL1 enable options. */
#define BSP_CLOCKS_PLL1_INITIAL (0xFF) // Initial (This value should not be reflected in the register)
#define BSP_CLOCKS_PLL1_STANDBY (0) // PLL1 is standby state.
#define BSP_CLOCKS_PLL1_NORMAL (1) // PLL1 is normal state.
/* CLMA error mask options. */
#define BSP_CLOCKS_CLMA0_ERROR_MASK (0) // CLMA0 error is not transferred to POE3 and POEG.
#define BSP_CLOCKS_CLMA0_ERROR_NOT_MASK (1) // CLMA0 error is transferred to POE3 and POEG.
#define BSP_CLOCKS_CLMA1_ERROR_MASK (0) // CLMA1 error is not transferred to POE3 and POEG.
#define BSP_CLOCKS_CLMA1_ERROR_NOT_MASK (1) // CLMA1 error is transferred to POE3 and POEG.
#define BSP_CLOCKS_CLMA3_ERROR_MASK (0) // CLMA3 error is not transferred to POE3 and POEG.
#define BSP_CLOCKS_CLMA3_ERROR_NOT_MASK (1) // CLMA3 error is transferred to POE3 and POEG.
/* CLMA enable options. */
#define BSP_CLOCKS_CLMA0_DISABLE (0) // Disable CLMA0 operation.
#define BSP_CLOCKS_CLMA0_ENABLE (1) // Enable CLMA0 operation.
#define BSP_CLOCKS_CLMA1_DISABLE (0) // Disable CLMA1 operation.
#define BSP_CLOCKS_CLMA1_ENABLE (1) // Enable CLMA1 operation.
#define BSP_CLOCKS_CLMA2_DISABLE (0) // Disable CLMA2 operation.
#define BSP_CLOCKS_CLMA2_ENABLE (1) // Enable CLMA2 operation.
#define BSP_CLOCKS_CLMA3_DISABLE (0) // Disable CLMA3 operation.
#define BSP_CLOCKS_CLMA3_ENABLE (1) // Enable CLMA3 operation.
/* Create a mask of valid bits in SCKCR. */
#define BSP_PRV_SCKCR_FSELXSPI0_MASK (7U << 0)
#define BSP_PRV_SCKCR_DIVSELXSPI0_MASK (1U << 6)
#define BSP_PRV_SCKCR_FSELXSPI1_MASK (7U << 8)
#define BSP_PRV_SCKCR_DIVSELXSPI1_MASK (1U << 14)
#define BSP_PRV_SCKCR_CKIO_MASK (7U << 16)
#define BSP_PRV_SCKCR_FSELCANFD_MASK (1U << 20)
#define BSP_PRV_SCKCR_PHYSEL_MASK (1U << 21)
#define BSP_PRV_SCKCR_CLMASEL_MASK (1U << 22)
#define BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK (1U << 24)
#define BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK (1U << 25)
#define BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK (1U << 26)
#define BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK (1U << 27)
#define BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK (1U << 28)
#define BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK (1U << 29)
#define BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK (1U << 30)
#define BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK (1U << 31)
#define BSP_PRV_SCKCR_MASK (((((((((((((((BSP_PRV_SCKCR_FSELXSPI0_MASK | \
BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \
BSP_PRV_SCKCR_FSELXSPI1_MASK) | \
BSP_PRV_SCKCR_DIVSELXSPI1_MASK) | \
BSP_PRV_SCKCR_CKIO_MASK) | \
BSP_PRV_SCKCR_FSELCANFD_MASK) | \
BSP_PRV_SCKCR_PHYSEL_MASK) | \
BSP_PRV_SCKCR_CLMASEL_MASK) | \
BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK) | \
BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK)
#define BSP_PRV_SCKCR_DIVSELXSPI_MASK (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \
BSP_PRV_SCKCR_DIVSELXSPI1_MASK)
/* Create a mask of valid bits in SCKCR2. */
#define BSP_PRV_SCKCR2_FSELCPU0_MASK (3U << 0)
#define BSP_PRV_SCKCR2_RESERVED_BIT4_MASK (1U << 4)
#define BSP_PRV_SCKCR2_DIVSELSUB_MASK (1U << 5)
#define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK (1U << 24)
#define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK (1U << 25)
#define BSP_PRV_SCKCR2_MASK ((((BSP_PRV_SCKCR2_FSELCPU0_MASK | \
BSP_PRV_SCKCR2_RESERVED_BIT4_MASK) | \
BSP_PRV_SCKCR2_DIVSELSUB_MASK) | \
BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) | \
BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK)
#define BSP_PRV_FSELCPU0_INIT (0x02U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_clock_init(void); // Used internally by BSP
/* Used internally by CGC */
void bsp_prv_clock_set(uint32_t sckcr, uint32_t sckcr2);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ICCARM__)
#define WEAK_ERROR_ATTRIBUTE
#define WEAK_INIT_ATTRIBUTE
#pragma weak fsp_error_log = fsp_error_log_internal
#pragma weak bsp_init = bsp_init_internal
#elif defined(__GNUC__)
#define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal")))
#define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal")))
#endif
#define FSP_SECTION_VERSION ".version"
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* System clock frequency information */
const uint32_t g_bsp_system_clock_select[][2] =
{
{BSP_PRV_CPU_FREQ_200_MHZ, BSP_PRV_CPU_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_CPU0
{0, 0 }, // Reserved
{BSP_PRV_ICLK_FREQ_200_MHZ, BSP_PRV_ICLK_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_ICLK
{BSP_PRV_PCLKH_FREQ_200_MHZ, BSP_PRV_PCLKH_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_PCLKH
{BSP_PRV_PCLKM_FREQ_100_MHZ, BSP_PRV_PCLKM_FREQ_75_MHZ }, // FSP_PRIV_CLOCK_PCLKM
{BSP_PRV_PCLKL_FREQ_50_MHZ, BSP_PRV_PCLKL_FREQ_37_5_MHZ }, // FSP_PRIV_CLOCK_PCLKL
{BSP_PRV_PCLKADC_FREQ_25_MHZ, BSP_PRV_PCLKADC_FREQ_18_75_MHZ}, // FSP_PRIV_CLOCK_PCLKADC
{BSP_PRV_PCLKGPTL_FREQ_400_MHZ, BSP_PRV_PCLKGPTL_FREQ_300_MHZ }, // FSP_PRIV_CLOCK_PCLKGPTL
{BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI0
{BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI1
{BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI2
{BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI3
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI0
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI1
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI2
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI3
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI4
{BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI5
{BSP_PRV_PCLKCAN_FREQ_80_MHZ, BSP_PRV_PCLKCAN_FREQ_40_MHZ }, // FSP_PRIV_CLOCK_PCLKCAN
};
/* System clock frequency information for CKIO */
const uint32_t g_bsp_system_clock_select_ckio[][2] =
{
{BSP_PRV_CKIO_FREQ_100_MHZ, BSP_PRV_CKIO_FREQ_75_MHZ }, // CKIO = 000b
{BSP_PRV_CKIO_FREQ_66_7_MHZ, BSP_PRV_CKIO_FREQ_50_MHZ }, // CKIO = 001b
{BSP_PRV_CKIO_FREQ_50_MHZ, BSP_PRV_CKIO_FREQ_37_5_MHZ }, // CKIO = 010b
{BSP_PRV_CKIO_FREQ_40_MHZ, BSP_PRV_CKIO_FREQ_30_MHZ }, // CKIO = 011b
{BSP_PRV_CKIO_FREQ_33_3_MHZ, BSP_PRV_CKIO_FREQ_25_MHZ }, // CKIO = 100b
{BSP_PRV_CKIO_FREQ_28_6_MHZ, BSP_PRV_CKIO_FREQ_21_4_MHZ }, // CKIO = 101b
{BSP_PRV_CKIO_FREQ_25_MHZ, BSP_PRV_CKIO_FREQ_18_75_MHZ }, // CKIO = 110b
{BSP_PRV_CKIO_FREQ_NOT_SUPPORTED, BSP_PRV_CKIO_FREQ_NOT_SUPPORTED}, // CKIO = 111b
};
/* System clock frequency information for XSPI_CLK */
const uint32_t g_bsp_system_clock_select_xspi_clk[][2] =
{
{BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 000b
{BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 001b
{BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 010b
{BSP_PRV_XSPI_CLK_FREQ_100_MHZ, BSP_PRV_XSPI_CLK_FREQ_75_MHZ }, // FSELXSPIn = 011b
{BSP_PRV_XSPI_CLK_FREQ_50_MHZ, BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ }, // FSELXSPIn = 100b
{BSP_PRV_XSPI_CLK_FREQ_25_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 101b
{BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 110b
{BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 111b
};
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
.version_id_b =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
}
};
/* Public FSP version name. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_STRING;
/* Unique FSP version ID. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_BUILD_STRING;
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/** Prototype of initialization function called before main. This prototype sets the weak association of this
* function to an internal example implementation. If this function is defined in the application code, the
* application code version is used. */
void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
void bsp_init_internal(void * p_args); /// Default initialization function
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This
* prototype sets the weak association of this function to an internal example implementation. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function
#endif
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Get the FSP version based on compile time macros.
*
* @param[out] p_version Memory address to return version information to.
*
* @retval FSP_SUCCESS Version information stored.
* @retval FSP_ERR_ASSERTION The parameter p_version is NULL.
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/** Verify parameters are valid */
FSP_ASSERT(NULL != p_version);
#endif
*p_version = g_fsp_version;
return FSP_SUCCESS;
}
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/*******************************************************************************************************************//**
* Default error logger function, used only if fsp_error_log is not defined in the user application.
*
* @param[in] err The error code encountered.
* @param[in] file The file name in which the error code was encountered.
* @param[in] line The line number at which the error code was encountered.
**********************************************************************************************************************/
void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
{
/** Do nothing. Do not generate any 'unused' warnings. */
FSP_PARAMETER_NOT_USED(err);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
}
#endif
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Default initialization function, used only if bsp_init is not defined in the user application.
**********************************************************************************************************************/
void bsp_init_internal (void * p_args)
{
/* Do nothing. */
FSP_PARAMETER_NOT_USED(p_args);
}
#if defined(__ARMCC_VERSION)
/*******************************************************************************************************************//**
* Default implementation of assert for AC6.
**********************************************************************************************************************/
__attribute__((weak, noreturn))
void __aeabi_assert (const char * expr, const char * file, int line) {
FSP_PARAMETER_NOT_USED(expr);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_COMMON_H
#define BSP_COMMON_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
#include <string.h>
/* Different compiler support. */
#include "../../inc/fsp_common_api.h"
#include "bsp_compiler_support.h"
#include "bsp_cfg.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** Used to signify that an ELC event is not able to be used as an interrupt. */
#define BSP_IRQ_DISABLED (0xFFU)
/* Vector Number offset */
#define BSP_VECTOR_NUM_OFFSET (32)
#define BSP_INTERRUPT_TYPE_OFFSET (16U)
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
#define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz
#define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz
#define BSP_PRV_ICLK_FREQ_200_MHZ (200000000U) // ICLK frequency is 200 MHz
#define BSP_PRV_ICLK_FREQ_150_MHZ (150000000U) // ICLK frequency is 150 MHz
#define BSP_PRV_PCLKH_FREQ_200_MHZ (200000000U) // PCLKH frequency is 200 MHz
#define BSP_PRV_PCLKH_FREQ_150_MHZ (150000000U) // PCLKH frequency is 150 MHz
#define BSP_PRV_PCLKM_FREQ_100_MHZ (100000000U) // PCLKM frequency is 100 MHz
#define BSP_PRV_PCLKM_FREQ_75_MHZ (75000000U) // PCLKM frequency is 750 MHz
#define BSP_PRV_PCLKL_FREQ_50_MHZ (50000000U) // PCLKL frequency is 50 MHz
#define BSP_PRV_PCLKL_FREQ_37_5_MHZ (37500000U) // PCLKL frequency is 37.5 MHz
#define BSP_PRV_PCLKADC_FREQ_25_MHZ (25000000U) // PCLKADC frequency is 25 MHz
#define BSP_PRV_PCLKADC_FREQ_18_75_MHZ (18750000U) // PCLKADC frequency is 18.75 MHz
#define BSP_PRV_PCLKGPTL_FREQ_400_MHZ (400000000U) // PCLKGPTL frequency is 400 MHz
#define BSP_PRV_PCLKGPTL_FREQ_300_MHZ (300000000U) // PCLKGPTL frequency is 300 MHz
#define BSP_PRV_PCLKSCI_FREQ_75_MHZ (75000000U) // PCLKSCI frequency is 75 MHz
#define BSP_PRV_PCLKSCI_FREQ_96_MHZ (96000000U) // PCLKSCI frequency is 96 MHz
#define BSP_PRV_PCLKSPI_FREQ_75_MHZ (75000000U) // PCLKSPI frequency is 75 MHz
#define BSP_PRV_PCLKSPI_FREQ_96_MHZ (96000000U) // PCLKSPI frequency is 96 MHz
#define BSP_PRV_PCLKCAN_FREQ_80_MHZ (80000000U) // PCLKCAN frequency is 80 MHz
#define BSP_PRV_PCLKCAN_FREQ_40_MHZ (40000000U) // PCLKCAN frequency is 40 MHz
#define BSP_PRV_CKIO_FREQ_100_MHZ (100000000U) // CKIO frequency is 100 MHz
#define BSP_PRV_CKIO_FREQ_75_MHZ (75000000U) // CKIO frequency is 75 MHz
#define BSP_PRV_CKIO_FREQ_66_7_MHZ (66666666U) // CKIO frequency is 66.7 MHz
#define BSP_PRV_CKIO_FREQ_50_MHZ (50000000U) // CKIO frequency is 50 MHz
#define BSP_PRV_CKIO_FREQ_40_MHZ (40000000U) // CKIO frequency is 40 MHz
#define BSP_PRV_CKIO_FREQ_37_5_MHZ (37500000U) // CKIO frequency is 37.5 MHz
#define BSP_PRV_CKIO_FREQ_33_3_MHZ (33333333U) // CKIO frequency is 33.3MHz
#define BSP_PRV_CKIO_FREQ_30_MHZ (30000000U) // CKIO frequency is 30 MHz
#define BSP_PRV_CKIO_FREQ_28_6_MHZ (28571428U) // CKIO frequency is 28.6 MHz
#define BSP_PRV_CKIO_FREQ_25_MHZ (25000000U) // CKIO frequency is 25 MHz
#define BSP_PRV_CKIO_FREQ_21_4_MHZ (21428571U) // CKIO frequency is 21.4 MHz
#define BSP_PRV_CKIO_FREQ_18_75_MHZ (18750000U) // CKIO frequency is 18.75 MHz
#define BSP_PRV_CKIO_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // CKIO frequency is not supported
#define BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ (133333333U) // XSPI_CLK frequency is 133.3 MHz
#define BSP_PRV_XSPI_CLK_FREQ_100_MHZ (100000000U) // XSPI_CLK frequency is 100.0 MHz
#define BSP_PRV_XSPI_CLK_FREQ_75_MHZ (75000000U) // XSPI_CLK frequency is 75.0 MHz
#define BSP_PRV_XSPI_CLK_FREQ_50_MHZ (50000000U) // XSPI_CLK frequency is 50.0 MHz
#define BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ (37500000U) // XSPI_CLK frequency is 37.5 MHz
#define BSP_PRV_XSPI_CLK_FREQ_25_MHZ (25000000U) // XSPI_CLK frequency is 25.0 MHz
#define BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ (12500000U) // XSPI_CLK frequency is 12.5 MHz
#define BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // XSPI_CLK frequency is not supported
/** Macro to log and return error without an assertion. */
#ifndef FSP_RETURN
#define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
return err;
#endif
/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
* user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
#if (1 == BSP_CFG_ERROR_LOG)
#ifndef FSP_ERROR_LOG
#define FSP_ERROR_LOG(err) \
fsp_error_log((err), __FILE__, __LINE__);
#endif
#else
#define FSP_ERROR_LOG(err)
#endif
/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
* functions. */
#if (3 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a)
#elif (2 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a) {assert(a);}
#else
#define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
#endif // ifndef FSP_ASSERT
/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
* to identify runtime errors in FSP functions. */
#define FSP_ERROR_RETURN(a, err) \
{ \
if ((a)) \
{ \
(void) 0; /* Do nothing */ \
} \
else \
{ \
FSP_ERROR_LOG(err); \
return err; \
} \
}
/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
* This macro can be redefined to add a timeout if necessary. */
#ifndef FSP_HARDWARE_REGISTER_WAIT
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
/* Function-like macro used to wait for a condition to be met with timeout,
* most often used to wait for hardware register updates. */
#define BSP_HARDWARE_REGISTER_WAIT_WTIH_TIMEOUT(reg, required_value, timeout) \
while ((timeout)) \
{ \
if ((required_value) == (reg)) \
{ \
break; \
} \
(timeout)--; \
}
#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
/* This macro defines a variable for saving previous mask value */
#ifndef FSP_CRITICAL_SECTION_DEFINE
#define FSP_CRITICAL_SECTION_DEFINE uintptr_t old_mask_level = 0U
#endif
/* These macros abstract methods to save and restore the interrupt state. */
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_ICC_PMR
#define FSP_CRITICAL_SECTION_SET_STATE __set_ICC_PMR
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT))
/** This macro temporarily saves the current interrupt state and disables interrupts. */
#ifndef FSP_CRITICAL_SECTION_ENTER
#define FSP_CRITICAL_SECTION_ENTER \
old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
#endif
/** This macro restores the previously saved interrupt state, reenabling interrupts. */
#ifndef FSP_CRITICAL_SECTION_EXIT
#define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
#endif
/* Number of Cortex processor exceptions. */
#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (32U)
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
/* This macro Enable or Disable interrupts. */
#define BSP_INTERRUPT_ENABLE __asm volatile ("cpsie i"); \
__asm volatile ("isb");
#define BSP_INTERRUPT_DISABLE __asm volatile ("cpsid i"); \
__asm volatile ("isb");
/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
* alert the user of the error. The user can override this default behavior by defining their own
* BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
*/
#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Different warm start entry locations in the BSP. */
typedef enum e_bsp_warm_start_event
{
BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up
} bsp_warm_start_event_t;
/* Private enum used in R_FSP_SystemClockHzGet. */
typedef enum e_fsp_priv_clock
{
FSP_PRIV_CLOCK_CPU0 = 0,
FSP_PRIV_CLOCK_ICLK = 2,
FSP_PRIV_CLOCK_PCLKH = 3,
FSP_PRIV_CLOCK_PCLKM = 4,
FSP_PRIV_CLOCK_PCLKL = 5,
FSP_PRIV_CLOCK_PCLKADC = 6,
FSP_PRIV_CLOCK_PCLKGPTL = 7,
FSP_PRIV_CLOCK_PCLKSPI0 = 8,
FSP_PRIV_CLOCK_PCLKSPI1 = 9,
FSP_PRIV_CLOCK_PCLKSPI2 = 10,
FSP_PRIV_CLOCK_PCLKSPI3 = 11,
FSP_PRIV_CLOCK_PCLKSCI0 = 12,
FSP_PRIV_CLOCK_PCLKSCI1 = 13,
FSP_PRIV_CLOCK_PCLKSCI2 = 14,
FSP_PRIV_CLOCK_PCLKSCI3 = 15,
FSP_PRIV_CLOCK_PCLKSCI4 = 16,
FSP_PRIV_CLOCK_PCLKSCI5 = 17,
FSP_PRIV_CLOCK_PCLKCAN = 18,
FSP_PRIV_CLOCK_CKIO = 19,
FSP_PRIV_CLOCK_XSPI0_CLK = 20,
FSP_PRIV_CLOCK_XSPI1_CLK = 21,
} fsp_priv_clock_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
extern const uint32_t g_bsp_system_clock_select[][2];
extern const uint32_t g_bsp_system_clock_select_ckio[][2];
extern const uint32_t g_bsp_system_clock_select_xspi_clk[][2];
extern IRQn_Type g_current_interrupt_num[];
extern uint8_t g_current_interrupt_pointer;
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Return active interrupt vector number value
*
* @return Active interrupt vector number value
**********************************************************************************************************************/
__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
{
/* Return the current interrupt number. */
return g_current_interrupt_num[(g_current_interrupt_pointer - 1U)];
}
/*******************************************************************************************************************//**
* Gets the frequency of a system clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
uint32_t clock_hz = 0;
uint32_t fselcpu0 = R_SYSC_S->SCKCR2_b.FSELCPU0;
switch (clock)
{
case FSP_PRIV_CLOCK_CPU0:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB] << fselcpu0;
break;
}
/* These iclk and pclk cases are intentionally combined. */
case FSP_PRIV_CLOCK_ICLK:
case FSP_PRIV_CLOCK_PCLKH:
case FSP_PRIV_CLOCK_PCLKM:
case FSP_PRIV_CLOCK_PCLKL:
case FSP_PRIV_CLOCK_PCLKADC:
case FSP_PRIV_CLOCK_PCLKGPTL:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB];
break;
}
case FSP_PRIV_CLOCK_PCLKSPI0:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSPI1:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSPI2:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSPI3:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SPI3ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI0:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI1:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI2:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI2ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI3:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI3ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI4:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI4ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKSCI5:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SCI5ASYNCSEL];
break;
}
case FSP_PRIV_CLOCK_PCLKCAN:
{
clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.FSELCANFD];
break;
}
case FSP_PRIV_CLOCK_CKIO:
{
uint32_t ckio = R_SYSC_NS->SCKCR_b.CKIO;
clock_hz = g_bsp_system_clock_select_ckio[ckio][R_SYSC_S->SCKCR2_b.DIVSELSUB];
break;
}
case FSP_PRIV_CLOCK_XSPI0_CLK:
{
uint32_t fselxspi0 = R_SYSC_NS->SCKCR_b.FSELXSPI0;
clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi0][R_SYSC_NS->SCKCR_b.DIVSELXSPI0];
break;
}
case FSP_PRIV_CLOCK_XSPI1_CLK:
{
uint32_t fselxspi1 = R_SYSC_NS->SCKCR_b.FSELXSPI1;
clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi1][R_SYSC_NS->SCKCR_b.DIVSELXSPI1];
break;
}
default:
{
break;
}
}
return clock_hz;
}
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
#endif
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
#ifndef BSP_COMPILER_SUPPORT_H
#define BSP_COMPILER_SUPPORT_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
#include <arm_cmse.h>
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ARMCC_VERSION) /* AC6 compiler */
/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
* memory (ROM) is reserved unnecessarily. */
#define BSP_UNINIT_SECTION_PREFIX ".bss"
#define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#define BSP_TARGET_ARM #pragma arm
#elif defined(__GNUC__) /* GCC compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#define BSP_TARGET_ARM __attribute__((target("arm")))
#elif defined(__ICCARM__) /* IAR compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP "HEAP"
#define BSP_DONT_REMOVE __root
#define BSP_ATTRIBUTE_STACKLESS __stackless
#define BSP_FORCE_INLINE _Pragma("inline=forced")
#define BSP_TARGET_ARM __arm
#endif
#define BSP_SECTION_FIQ_STACK BSP_UNINIT_SECTION_PREFIX ".fiq_stack"
#define BSP_SECTION_IRQ_STACK BSP_UNINIT_SECTION_PREFIX ".irq_stack"
#define BSP_SECTION_ABT_STACK BSP_UNINIT_SECTION_PREFIX ".abt_stack"
#define BSP_SECTION_UND_STACK BSP_UNINIT_SECTION_PREFIX ".und_stack"
#define BSP_SECTION_SYS_STACK BSP_UNINIT_SECTION_PREFIX ".sys_stack"
#define BSP_SECTION_SVC_STACK BSP_UNINIT_SECTION_PREFIX ".svc_stack"
#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
#define BSP_SECTION_ID_CODE ".id_code"
#define BSP_SECTION_LOADER_PARAM ".loader_param"
/* Compiler neutral macros. */
#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
#define BSP_PACKED __attribute__((aligned(1)))
#define BSP_WEAK_REFERENCE __attribute__((weak))
/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
#define BSP_STACK_ALIGNMENT (8)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end of addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#include "bsp_delay.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_DELAY_NS_PER_SECOND (1000000000)
#define BSP_DELAY_NS_PER_US (1000)
#define BSP_DELAY_SIGNIFICANT_DIGITS (10000)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Delay for at least the specified duration in units and return.
* @param[in] delay The number of 'units' to delay.
* @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are:
* BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n
* For example:@n
* At 200 MHz one cycle takes 1/200 microsecond or 5 nanoseconds.@n
* At 800 MHz one cycle takes 1/800 microsecond or 1.25 nanoseconds.@n
* Therefore one run through bsp_prv_software_delay_loop() takes:
* ~ (1.25 * BSP_DELAY_LOOP_CYCLES) or 5 ns.
* A delay of 2 us therefore requires 2000ns/5ns or 400 loops.
*
* The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate.
* @200MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 200000000) = 85 seconds.
* @800MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 800000000) = 21 seconds.
*
* Note that requests for very large delays will be affected by rounding in the calculations and the actual delay
* achieved may be slightly longer. @200 MHz, for example, a request for 85 seconds will be closer to 86 seconds.
*
* Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called
* at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
* overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
*
*
* @note R_BSP_SoftwareDelay() obtains the system clock value by reading the SystemCoreClock variable.
* Therefore, R_BSP_SoftwareDelay() cannot be used until after the SystemCoreClock has been updated.
* The SystemCoreClock is updated by executing SystemCoreClockUpdate() in startup;
* users cannot call R_BSP_SoftwareDelay() inside R_BSP_WarmStart(BSP_WARM_START_RESET) and
* R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK) since they are invoked before SystemCoreClockUpdate() in startup.
*
* @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number
* of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified.
* Approximate overhead for this function is as follows:
* - CR52: 87-94 cycles
*
* @note If more accurate microsecond timing must be performed in software it is recommended to use
* bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE()
* to convert a calculated delay cycle count to a number of software delay loops.
*
* @note Delays may be longer than expected when compiler optimization is turned off.
**********************************************************************************************************************/
void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
{
uint32_t cpu_hz;
uint32_t cycles_requested;
uint32_t ns_per_cycle;
uint32_t loops_required = 0;
uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */
uint64_t ns_64bits;
cpu_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */
/* BSP_DELAY_SIGNIFICANT_DIGITS to keep the decimal point. */
ns_per_cycle = BSP_DELAY_NS_PER_SECOND / (cpu_hz / BSP_DELAY_SIGNIFICANT_DIGITS); /** Get the # of nanoseconds/cycle. */
/* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */
/* division as that pulls in a division library. */
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
ns_64bits = ns_64bits * (uint64_t) BSP_DELAY_SIGNIFICANT_DIGITS;
/* No, we will not overflow.
* Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/
cycles_requested = (uint32_t) (ns_64bits / (uint64_t) ns_per_cycle);
loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES;
}
else
{
/* We did overflow. Try dividing down first.
* Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/
total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)) * BSP_DELAY_SIGNIFICANT_DIGITS;
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
/* No, we will not overflow. */
loops_required = (uint32_t) ns_64bits;
}
else
{
/* We still overflowed, use the max count for cycles */
loops_required = UINT32_MAX;
}
}
/** Only delay if the supplied parameters constitute a delay. */
if (loops_required > (uint32_t) 0)
{
bsp_prv_software_delay_loop(loops_required);
}
}
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
* occur when the loop exits. The 'naked' attribute indicates that the specified function does not need
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
void bsp_prv_software_delay_loop (uint32_t loop_cnt)
{
r_bsp_software_delay_loop(loop_cnt);
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_DELAY_H
#define BSP_DELAY_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if defined(BSP_CFG_CORE_CR52)
#include "cr/bsp_delay_core.h"
#endif
#include "bsp_compiler_support.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */
typedef enum
{
BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds
BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds
BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds
} bsp_delay_units_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void bsp_prv_software_delay_loop(uint32_t loop_cnt);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_EXCEPTIONS_H
#define BSP_EXCEPTIONS_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
volatile uint32_t g_protect_port_counter;
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @defgroup BSP_IO BSP I/O access
* @ingroup RENESAS_COMMON
* @brief This module provides basic read/write/toggle access to port pins and read/write access to port.
*
* @{
**********************************************************************************************************************/
#ifndef BSP_IO_H
#define BSP_IO_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Private definition to set enumeration values. */
#define BSP_IO_PRV_8BIT_MASK (0xFF)
#define BSP_IO_PM_OUTPUT (3U)
/* Key code for writing PRCR register. */
#define BSP_IO_PRV_PRCR_KEY (0xA500U)
#define BSP_IO_REG_PROTECT_GPIO (0x0004U)
/* Difference between safety and non safety I/O port region addresses. */
#define BSP_IO_REGION_ADDRESS_DIFF (R_PORT_SR_BASE - R_PORT_NSR_BASE)
/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
#define BSP_IO_PRV_PORT_OFFSET (8U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Levels that can be set and read for individual pins */
typedef enum e_bsp_io_level
{
BSP_IO_LEVEL_LOW = 0, ///< Low
BSP_IO_LEVEL_HIGH ///< High
} bsp_io_level_t;
/** Direction of individual pins */
typedef enum e_bsp_io_dir
{
BSP_IO_DIRECTION_INPUT = 0, ///< Input
BSP_IO_DIRECTION_OUTPUT ///< Output
} bsp_io_direction_t;
/** Superset list of all possible IO ports. */
typedef enum e_bsp_io_port
{
BSP_IO_PORT_00 = 0x0000, ///< IO port 0
BSP_IO_PORT_01 = 0x0100, ///< IO port 1
BSP_IO_PORT_02 = 0x0200, ///< IO port 2
BSP_IO_PORT_03 = 0x0300, ///< IO port 3
BSP_IO_PORT_04 = 0x0400, ///< IO port 4
BSP_IO_PORT_05 = 0x0500, ///< IO port 5
BSP_IO_PORT_06 = 0x0600, ///< IO port 6
BSP_IO_PORT_07 = 0x0700, ///< IO port 7
BSP_IO_PORT_08 = 0x0800, ///< IO port 8
BSP_IO_PORT_09 = 0x0900, ///< IO port 9
BSP_IO_PORT_10 = 0x0A00, ///< IO port 10
BSP_IO_PORT_11 = 0x0B00, ///< IO port 11
BSP_IO_PORT_12 = 0x0C00, ///< IO port 12
BSP_IO_PORT_13 = 0x0D00, ///< IO port 13
BSP_IO_PORT_14 = 0x0E00, ///< IO port 14
BSP_IO_PORT_15 = 0x0F00, ///< IO port 15
BSP_IO_PORT_16 = 0x1000, ///< IO port 16
BSP_IO_PORT_17 = 0x1100, ///< IO port 17
BSP_IO_PORT_18 = 0x1200, ///< IO port 18
BSP_IO_PORT_19 = 0x1300, ///< IO port 19
BSP_IO_PORT_20 = 0x1400, ///< IO port 20
BSP_IO_PORT_21 = 0x1500, ///< IO port 21
BSP_IO_PORT_22 = 0x1600, ///< IO port 22
BSP_IO_PORT_23 = 0x1700, ///< IO port 23
BSP_IO_PORT_24 = 0x1800, ///< IO port 24
} bsp_io_port_t;
/** Superset list of all possible IO port pins. */
typedef enum e_bsp_io_port_pin
{
BSP_IO_PORT_00_PIN_0 = 0x0000, ///< IO port 0 pin 0
BSP_IO_PORT_00_PIN_1 = 0x0001, ///< IO port 0 pin 1
BSP_IO_PORT_00_PIN_2 = 0x0002, ///< IO port 0 pin 2
BSP_IO_PORT_00_PIN_3 = 0x0003, ///< IO port 0 pin 3
BSP_IO_PORT_00_PIN_4 = 0x0004, ///< IO port 0 pin 4
BSP_IO_PORT_00_PIN_5 = 0x0005, ///< IO port 0 pin 5
BSP_IO_PORT_00_PIN_6 = 0x0006, ///< IO port 0 pin 6
BSP_IO_PORT_00_PIN_7 = 0x0007, ///< IO port 0 pin 7
BSP_IO_PORT_01_PIN_0 = 0x0100, ///< IO port 1 pin 0
BSP_IO_PORT_01_PIN_1 = 0x0101, ///< IO port 1 pin 1
BSP_IO_PORT_01_PIN_2 = 0x0102, ///< IO port 1 pin 2
BSP_IO_PORT_01_PIN_3 = 0x0103, ///< IO port 1 pin 3
BSP_IO_PORT_01_PIN_4 = 0x0104, ///< IO port 1 pin 4
BSP_IO_PORT_01_PIN_5 = 0x0105, ///< IO port 1 pin 5
BSP_IO_PORT_01_PIN_6 = 0x0106, ///< IO port 1 pin 6
BSP_IO_PORT_01_PIN_7 = 0x0107, ///< IO port 1 pin 7
BSP_IO_PORT_02_PIN_0 = 0x0200, ///< IO port 2 pin 0
BSP_IO_PORT_02_PIN_1 = 0x0201, ///< IO port 2 pin 1
BSP_IO_PORT_02_PIN_2 = 0x0202, ///< IO port 2 pin 2
BSP_IO_PORT_02_PIN_3 = 0x0203, ///< IO port 2 pin 3
BSP_IO_PORT_02_PIN_4 = 0x0204, ///< IO port 2 pin 4
BSP_IO_PORT_02_PIN_5 = 0x0205, ///< IO port 2 pin 5
BSP_IO_PORT_02_PIN_6 = 0x0206, ///< IO port 2 pin 6
BSP_IO_PORT_02_PIN_7 = 0x0207, ///< IO port 2 pin 7
BSP_IO_PORT_03_PIN_0 = 0x0300, ///< IO port 3 pin 0
BSP_IO_PORT_03_PIN_1 = 0x0301, ///< IO port 3 pin 1
BSP_IO_PORT_03_PIN_2 = 0x0302, ///< IO port 3 pin 2
BSP_IO_PORT_03_PIN_3 = 0x0303, ///< IO port 3 pin 3
BSP_IO_PORT_03_PIN_4 = 0x0304, ///< IO port 3 pin 4
BSP_IO_PORT_03_PIN_5 = 0x0305, ///< IO port 3 pin 5
BSP_IO_PORT_03_PIN_6 = 0x0306, ///< IO port 3 pin 6
BSP_IO_PORT_03_PIN_7 = 0x0307, ///< IO port 3 pin 7
BSP_IO_PORT_04_PIN_0 = 0x0400, ///< IO port 4 pin 0
BSP_IO_PORT_04_PIN_1 = 0x0401, ///< IO port 4 pin 1
BSP_IO_PORT_04_PIN_2 = 0x0402, ///< IO port 4 pin 2
BSP_IO_PORT_04_PIN_3 = 0x0403, ///< IO port 4 pin 3
BSP_IO_PORT_04_PIN_4 = 0x0404, ///< IO port 4 pin 4
BSP_IO_PORT_04_PIN_5 = 0x0405, ///< IO port 4 pin 5
BSP_IO_PORT_04_PIN_6 = 0x0406, ///< IO port 4 pin 6
BSP_IO_PORT_04_PIN_7 = 0x0407, ///< IO port 4 pin 7
BSP_IO_PORT_05_PIN_0 = 0x0500, ///< IO port 5 pin 0
BSP_IO_PORT_05_PIN_1 = 0x0501, ///< IO port 5 pin 1
BSP_IO_PORT_05_PIN_2 = 0x0502, ///< IO port 5 pin 2
BSP_IO_PORT_05_PIN_3 = 0x0503, ///< IO port 5 pin 3
BSP_IO_PORT_05_PIN_4 = 0x0504, ///< IO port 5 pin 4
BSP_IO_PORT_05_PIN_5 = 0x0505, ///< IO port 5 pin 5
BSP_IO_PORT_05_PIN_6 = 0x0506, ///< IO port 5 pin 6
BSP_IO_PORT_05_PIN_7 = 0x0507, ///< IO port 5 pin 7
BSP_IO_PORT_06_PIN_0 = 0x0600, ///< IO port 6 pin 0
BSP_IO_PORT_06_PIN_1 = 0x0601, ///< IO port 6 pin 1
BSP_IO_PORT_06_PIN_2 = 0x0602, ///< IO port 6 pin 2
BSP_IO_PORT_06_PIN_3 = 0x0603, ///< IO port 6 pin 3
BSP_IO_PORT_06_PIN_4 = 0x0604, ///< IO port 6 pin 4
BSP_IO_PORT_06_PIN_5 = 0x0605, ///< IO port 6 pin 5
BSP_IO_PORT_06_PIN_6 = 0x0606, ///< IO port 6 pin 6
BSP_IO_PORT_06_PIN_7 = 0x0607, ///< IO port 6 pin 7
BSP_IO_PORT_07_PIN_0 = 0x0700, ///< IO port 7 pin 0
BSP_IO_PORT_07_PIN_1 = 0x0701, ///< IO port 7 pin 1
BSP_IO_PORT_07_PIN_2 = 0x0702, ///< IO port 7 pin 2
BSP_IO_PORT_07_PIN_3 = 0x0703, ///< IO port 7 pin 3
BSP_IO_PORT_07_PIN_4 = 0x0704, ///< IO port 7 pin 4
BSP_IO_PORT_07_PIN_5 = 0x0705, ///< IO port 7 pin 5
BSP_IO_PORT_07_PIN_6 = 0x0706, ///< IO port 7 pin 6
BSP_IO_PORT_07_PIN_7 = 0x0707, ///< IO port 7 pin 7
BSP_IO_PORT_08_PIN_0 = 0x0800, ///< IO port 8 pin 0
BSP_IO_PORT_08_PIN_1 = 0x0801, ///< IO port 8 pin 1
BSP_IO_PORT_08_PIN_2 = 0x0802, ///< IO port 8 pin 2
BSP_IO_PORT_08_PIN_3 = 0x0803, ///< IO port 8 pin 3
BSP_IO_PORT_08_PIN_4 = 0x0804, ///< IO port 8 pin 4
BSP_IO_PORT_08_PIN_5 = 0x0805, ///< IO port 8 pin 5
BSP_IO_PORT_08_PIN_6 = 0x0806, ///< IO port 8 pin 6
BSP_IO_PORT_08_PIN_7 = 0x0807, ///< IO port 8 pin 7
BSP_IO_PORT_09_PIN_0 = 0x0900, ///< IO port 9 pin 0
BSP_IO_PORT_09_PIN_1 = 0x0901, ///< IO port 9 pin 1
BSP_IO_PORT_09_PIN_2 = 0x0902, ///< IO port 9 pin 2
BSP_IO_PORT_09_PIN_3 = 0x0903, ///< IO port 9 pin 3
BSP_IO_PORT_09_PIN_4 = 0x0904, ///< IO port 9 pin 4
BSP_IO_PORT_09_PIN_5 = 0x0905, ///< IO port 9 pin 5
BSP_IO_PORT_09_PIN_6 = 0x0906, ///< IO port 9 pin 6
BSP_IO_PORT_09_PIN_7 = 0x0907, ///< IO port 9 pin 7
BSP_IO_PORT_10_PIN_0 = 0x0A00, ///< IO port 10 pin 0
BSP_IO_PORT_10_PIN_1 = 0x0A01, ///< IO port 10 pin 1
BSP_IO_PORT_10_PIN_2 = 0x0A02, ///< IO port 10 pin 2
BSP_IO_PORT_10_PIN_3 = 0x0A03, ///< IO port 10 pin 3
BSP_IO_PORT_10_PIN_4 = 0x0A04, ///< IO port 10 pin 4
BSP_IO_PORT_10_PIN_5 = 0x0A05, ///< IO port 10 pin 5
BSP_IO_PORT_10_PIN_6 = 0x0A06, ///< IO port 10 pin 6
BSP_IO_PORT_10_PIN_7 = 0x0A07, ///< IO port 10 pin 7
BSP_IO_PORT_11_PIN_0 = 0x0B00, ///< IO port 11 pin 0
BSP_IO_PORT_11_PIN_1 = 0x0B01, ///< IO port 11 pin 1
BSP_IO_PORT_11_PIN_2 = 0x0B02, ///< IO port 11 pin 2
BSP_IO_PORT_11_PIN_3 = 0x0B03, ///< IO port 11 pin 3
BSP_IO_PORT_11_PIN_4 = 0x0B04, ///< IO port 11 pin 4
BSP_IO_PORT_11_PIN_5 = 0x0B05, ///< IO port 11 pin 5
BSP_IO_PORT_11_PIN_6 = 0x0B06, ///< IO port 11 pin 6
BSP_IO_PORT_11_PIN_7 = 0x0B07, ///< IO port 11 pin 7
BSP_IO_PORT_12_PIN_0 = 0x0C00, ///< IO port 12 pin 0
BSP_IO_PORT_12_PIN_1 = 0x0C01, ///< IO port 12 pin 1
BSP_IO_PORT_12_PIN_2 = 0x0C02, ///< IO port 12 pin 2
BSP_IO_PORT_12_PIN_3 = 0x0C03, ///< IO port 12 pin 3
BSP_IO_PORT_12_PIN_4 = 0x0C04, ///< IO port 12 pin 4
BSP_IO_PORT_12_PIN_5 = 0x0C05, ///< IO port 12 pin 5
BSP_IO_PORT_12_PIN_6 = 0x0C06, ///< IO port 12 pin 6
BSP_IO_PORT_12_PIN_7 = 0x0C07, ///< IO port 12 pin 7
BSP_IO_PORT_13_PIN_0 = 0x0D00, ///< IO port 13 pin 0
BSP_IO_PORT_13_PIN_1 = 0x0D01, ///< IO port 13 pin 1
BSP_IO_PORT_13_PIN_2 = 0x0D02, ///< IO port 13 pin 2
BSP_IO_PORT_13_PIN_3 = 0x0D03, ///< IO port 13 pin 3
BSP_IO_PORT_13_PIN_4 = 0x0D04, ///< IO port 13 pin 4
BSP_IO_PORT_13_PIN_5 = 0x0D05, ///< IO port 13 pin 5
BSP_IO_PORT_13_PIN_6 = 0x0D06, ///< IO port 13 pin 6
BSP_IO_PORT_13_PIN_7 = 0x0D07, ///< IO port 13 pin 7
BSP_IO_PORT_14_PIN_0 = 0x0E00, ///< IO port 14 pin 0
BSP_IO_PORT_14_PIN_1 = 0x0E01, ///< IO port 14 pin 1
BSP_IO_PORT_14_PIN_2 = 0x0E02, ///< IO port 14 pin 2
BSP_IO_PORT_14_PIN_3 = 0x0E03, ///< IO port 14 pin 3
BSP_IO_PORT_14_PIN_4 = 0x0E04, ///< IO port 14 pin 4
BSP_IO_PORT_14_PIN_5 = 0x0E05, ///< IO port 14 pin 5
BSP_IO_PORT_14_PIN_6 = 0x0E06, ///< IO port 14 pin 6
BSP_IO_PORT_14_PIN_7 = 0x0E07, ///< IO port 14 pin 7
BSP_IO_PORT_15_PIN_0 = 0x0F00, ///< IO port 15 pin 0
BSP_IO_PORT_15_PIN_1 = 0x0F01, ///< IO port 15 pin 1
BSP_IO_PORT_15_PIN_2 = 0x0F02, ///< IO port 15 pin 2
BSP_IO_PORT_15_PIN_3 = 0x0F03, ///< IO port 15 pin 3
BSP_IO_PORT_15_PIN_4 = 0x0F04, ///< IO port 15 pin 4
BSP_IO_PORT_15_PIN_5 = 0x0F05, ///< IO port 15 pin 5
BSP_IO_PORT_15_PIN_6 = 0x0F06, ///< IO port 15 pin 6
BSP_IO_PORT_15_PIN_7 = 0x0F07, ///< IO port 15 pin 7
BSP_IO_PORT_16_PIN_0 = 0x1000, ///< IO port 16 pin 0
BSP_IO_PORT_16_PIN_1 = 0x1001, ///< IO port 16 pin 1
BSP_IO_PORT_16_PIN_2 = 0x1002, ///< IO port 16 pin 2
BSP_IO_PORT_16_PIN_3 = 0x1003, ///< IO port 16 pin 3
BSP_IO_PORT_16_PIN_4 = 0x1004, ///< IO port 16 pin 4
BSP_IO_PORT_16_PIN_5 = 0x1005, ///< IO port 16 pin 5
BSP_IO_PORT_16_PIN_6 = 0x1006, ///< IO port 16 pin 6
BSP_IO_PORT_16_PIN_7 = 0x1007, ///< IO port 16 pin 7
BSP_IO_PORT_17_PIN_0 = 0x1100, ///< IO port 17 pin 0
BSP_IO_PORT_17_PIN_1 = 0x1101, ///< IO port 17 pin 1
BSP_IO_PORT_17_PIN_2 = 0x1102, ///< IO port 17 pin 2
BSP_IO_PORT_17_PIN_3 = 0x1103, ///< IO port 17 pin 3
BSP_IO_PORT_17_PIN_4 = 0x1104, ///< IO port 17 pin 4
BSP_IO_PORT_17_PIN_5 = 0x1105, ///< IO port 17 pin 5
BSP_IO_PORT_17_PIN_6 = 0x1106, ///< IO port 17 pin 6
BSP_IO_PORT_17_PIN_7 = 0x1107, ///< IO port 17 pin 7
BSP_IO_PORT_18_PIN_0 = 0x1200, ///< IO port 18 pin 0
BSP_IO_PORT_18_PIN_1 = 0x1201, ///< IO port 18 pin 1
BSP_IO_PORT_18_PIN_2 = 0x1202, ///< IO port 18 pin 2
BSP_IO_PORT_18_PIN_3 = 0x1203, ///< IO port 18 pin 3
BSP_IO_PORT_18_PIN_4 = 0x1204, ///< IO port 18 pin 4
BSP_IO_PORT_18_PIN_5 = 0x1205, ///< IO port 18 pin 5
BSP_IO_PORT_18_PIN_6 = 0x1206, ///< IO port 18 pin 6
BSP_IO_PORT_18_PIN_7 = 0x1207, ///< IO port 18 pin 7
BSP_IO_PORT_19_PIN_0 = 0x1300, ///< IO port 19 pin 0
BSP_IO_PORT_19_PIN_1 = 0x1301, ///< IO port 19 pin 1
BSP_IO_PORT_19_PIN_2 = 0x1302, ///< IO port 19 pin 2
BSP_IO_PORT_19_PIN_3 = 0x1303, ///< IO port 19 pin 3
BSP_IO_PORT_19_PIN_4 = 0x1304, ///< IO port 19 pin 4
BSP_IO_PORT_19_PIN_5 = 0x1305, ///< IO port 19 pin 5
BSP_IO_PORT_19_PIN_6 = 0x1306, ///< IO port 19 pin 6
BSP_IO_PORT_19_PIN_7 = 0x1307, ///< IO port 19 pin 7
BSP_IO_PORT_20_PIN_0 = 0x1400, ///< IO port 20 pin 0
BSP_IO_PORT_20_PIN_1 = 0x1401, ///< IO port 20 pin 1
BSP_IO_PORT_20_PIN_2 = 0x1402, ///< IO port 20 pin 2
BSP_IO_PORT_20_PIN_3 = 0x1403, ///< IO port 20 pin 3
BSP_IO_PORT_20_PIN_4 = 0x1404, ///< IO port 20 pin 4
BSP_IO_PORT_20_PIN_5 = 0x1405, ///< IO port 20 pin 5
BSP_IO_PORT_20_PIN_6 = 0x1406, ///< IO port 20 pin 6
BSP_IO_PORT_20_PIN_7 = 0x1407, ///< IO port 20 pin 7
BSP_IO_PORT_21_PIN_0 = 0x1500, ///< IO port 21 pin 0
BSP_IO_PORT_21_PIN_1 = 0x1501, ///< IO port 21 pin 1
BSP_IO_PORT_21_PIN_2 = 0x1502, ///< IO port 21 pin 2
BSP_IO_PORT_21_PIN_3 = 0x1503, ///< IO port 21 pin 3
BSP_IO_PORT_21_PIN_4 = 0x1504, ///< IO port 21 pin 4
BSP_IO_PORT_21_PIN_5 = 0x1505, ///< IO port 21 pin 5
BSP_IO_PORT_21_PIN_6 = 0x1506, ///< IO port 21 pin 6
BSP_IO_PORT_21_PIN_7 = 0x1507, ///< IO port 21 pin 7
BSP_IO_PORT_22_PIN_0 = 0x1600, ///< IO port 22 pin 0
BSP_IO_PORT_22_PIN_1 = 0x1601, ///< IO port 22 pin 1
BSP_IO_PORT_22_PIN_2 = 0x1602, ///< IO port 22 pin 2
BSP_IO_PORT_22_PIN_3 = 0x1603, ///< IO port 22 pin 3
BSP_IO_PORT_22_PIN_4 = 0x1604, ///< IO port 22 pin 4
BSP_IO_PORT_22_PIN_5 = 0x1605, ///< IO port 22 pin 5
BSP_IO_PORT_22_PIN_6 = 0x1606, ///< IO port 22 pin 6
BSP_IO_PORT_22_PIN_7 = 0x1607, ///< IO port 22 pin 7
BSP_IO_PORT_23_PIN_0 = 0x1700, ///< IO port 23 pin 0
BSP_IO_PORT_23_PIN_1 = 0x1701, ///< IO port 23 pin 1
BSP_IO_PORT_23_PIN_2 = 0x1702, ///< IO port 23 pin 2
BSP_IO_PORT_23_PIN_3 = 0x1703, ///< IO port 23 pin 3
BSP_IO_PORT_23_PIN_4 = 0x1704, ///< IO port 23 pin 4
BSP_IO_PORT_23_PIN_5 = 0x1705, ///< IO port 23 pin 5
BSP_IO_PORT_23_PIN_6 = 0x1706, ///< IO port 23 pin 6
BSP_IO_PORT_23_PIN_7 = 0x1707, ///< IO port 23 pin 7
BSP_IO_PORT_24_PIN_0 = 0x1800, ///< IO port 24 pin 0
BSP_IO_PORT_24_PIN_1 = 0x1801, ///< IO port 24 pin 1
BSP_IO_PORT_24_PIN_2 = 0x1802, ///< IO port 24 pin 2
BSP_IO_PORT_24_PIN_3 = 0x1803, ///< IO port 24 pin 3
BSP_IO_PORT_24_PIN_4 = 0x1804, ///< IO port 24 pin 4
BSP_IO_PORT_24_PIN_5 = 0x1805, ///< IO port 24 pin 5
BSP_IO_PORT_24_PIN_6 = 0x1806, ///< IO port 24 pin 6
BSP_IO_PORT_24_PIN_7 = 0x1807, ///< IO port 24 pin 7
} bsp_io_port_pin_t;
/** Offset for pin safety region access */
typedef enum e_bsp_io_region
{
BSP_IO_REGION_NOT_SAFE = 0, ///< Non safety region
BSP_IO_REGION_SAFE = BSP_IO_REGION_ADDRESS_DIFF, ///< Safety region
} bsp_io_region_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
extern volatile uint32_t g_protect_port_counter;
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Set the output level of the pin in the specified region.
*
* @param[in] region The target IO region
* @param[in] pin The pin
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin)
{
/* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
* the right side. */
((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >>
BSP_IO_PRV_PORT_OFFSET] |=
(uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
}
/*******************************************************************************************************************//**
* Clear the output level of the pin in the specified region.
*
* @param[in] region The target IO region
* @param[in] pin The pin
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin)
{
/* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
* the right side. */
((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> BSP_IO_PRV_PORT_OFFSET] &=
(uint8_t) (~(1UL << (pin & BSP_IO_PRV_8BIT_MASK)));
}
/*******************************************************************************************************************//**
* Toggle the output level of the pin in the specified region.
*
* @param[in] region The target IO region
* @param[in] pin The pin
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin)
{
/* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on
* the right side. */
((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >>
BSP_IO_PRV_PORT_OFFSET] ^=
(uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK));
}
/*******************************************************************************************************************//**
* Read the input level of the pin in the specified region.
*
* @param[in] region The target IO region
* @param[in] pin The pin
*
* @retval Current input level
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin)
{
return (uint32_t) ((((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[pin >> BSP_IO_PRV_PORT_OFFSET]) >>
(pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL;
}
/*******************************************************************************************************************//**
* Set the output value of the port in the specified region. All pins in the port must be set to the same IO region to
* use this function.
*
* @param[in] region The target IO region
* @param[in] port The port
* @param[in] set_value The setting value
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value)
{
((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[port >> BSP_IO_PRV_PORT_OFFSET] = set_value;
}
/*******************************************************************************************************************//**
* Read the input value of the port in the specified region. All pins in the port must be set to the same IO region to
* use this function.
*
* @param[in] region The target IO region
* @param[in] port The port
*
* @retval Current input value
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port)
{
return (uint32_t) (((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[port >> BSP_IO_PRV_PORT_OFFSET]);
}
/*******************************************************************************************************************//**
* Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur
* via multiple threads or an ISR re-entering this code.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinAccessEnable (void)
{
#if BSP_CFG_PORT_PROTECT
/** Get the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/** If this is first entry then allow writing of PFS. */
if (0 == g_protect_port_counter)
{
/** Disable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO);
}
/** Increment the protect counter */
g_protect_port_counter++;
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
#endif
}
/*******************************************************************************************************************//**
* Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via
* multiple threads or an ISR re-entering this code.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinAccessDisable (void)
{
#if BSP_CFG_PORT_PROTECT
/** Get the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/** Is it safe to disable PFS register? */
if (0 != g_protect_port_counter)
{
/* Decrement the protect counter */
g_protect_port_counter--;
}
/** Is it safe to disable writing of PFS? */
if (0 == g_protect_port_counter)
{
/** Enable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO));
R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO));
}
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
#endif
}
/*******************************************************************************************************************//**
* Read IO region of the pin.
*
* @param[in] pin The pin
*
* @retval BSP_IO_REGION_SAFE IO region of the pin is safety
* @retval BSP_IO_REGION_NOT_SAFE IO region of the pin is non-safety
*
* This function can be given as an argument to pin/port access functions described below. When used in a function
* starting with R_BSP_Port, any one pin in the port should be given as an argument to this function.
* R_BSP_PinSet(), R_BSP_PinClear(), R_BSP_PinToggle(), R_BSP_FastPinRead(), R_BSP_PortWrite(), R_BSP_PortRead()
*
* @note This function can be used to get the region of a specified pin, but the overhead should be considered if this
* function is executed each time the pin is accessed. When accessing the same pin repeatedly, it is recommended
* that the value obtained by this function be held in a variable beforehand, and the value of the variable be
* used as the region argument of the pin access function.
**********************************************************************************************************************/
__STATIC_INLINE bsp_io_region_t R_BSP_IoRegionGet (bsp_io_port_pin_t pin)
{
/* Casting to a uint32_t type is valid because the range of values represented by uint32_t is not over in the
* calculation process of the right-hand side. */
uint32_t aselp =
((uint32_t) ((R_PTADR->RSELP[pin >> BSP_IO_PRV_PORT_OFFSET]) >> (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL);
if (0U == aselp)
{
return BSP_IO_REGION_SAFE;
}
else
{
return BSP_IO_REGION_NOT_SAFE;
}
}
/** @} (end addtogroup BSP_IO) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Initialize interrupt controller.
*
* @retval None
**********************************************************************************************************************/
void bsp_irq_cfg (void)
{
bsp_irq_core_cfg();
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_IRQ_H
#define BSP_IRQ_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if defined(BSP_CFG_CORE_CR52)
#include "cr/bsp_irq_core.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Sets the ISR context associated with the requested IRQ.
*
* @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
* function.
* @param[in] p_context ISR context for IRQ.
**********************************************************************************************************************/
__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
{
/* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
* being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
r_fsp_irq_context_set(irq, p_context);
}
/*******************************************************************************************************************//**
* Clear the GIC pending interrupt.
*
* @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
{
r_bsp_irq_clear_pending(irq);
}
/*******************************************************************************************************************//**
* Get the GIC pending interrupt.
*
* @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
*
* @return Value indicating the status of the level interrupt.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq)
{
return r_bsp_irq_pending_get(irq);
}
/*******************************************************************************************************************//**
* Sets the interrupt priority and context.
*
* @param[in] irq The IRQ number to configure.
* @param[in] priority GIC priority of the interrupt
* @param[in] p_context The interrupt context is a pointer to data required in the ISR.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
{
r_bsp_irq_cfg(irq, priority);
/* Store the context. The context is recovered in the ISR. */
R_FSP_IsrContextSet(irq, p_context);
}
/*******************************************************************************************************************//**
* Enable the IRQ in the GIC (Without clearing the pending bit).
*
* @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
* Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
{
r_bsp_irq_enable_no_clear(irq);
}
/*******************************************************************************************************************//**
* Enable the IRQ in the GIC (With clearing the pending bit).
*
* @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
* Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
{
/* Clear pending interrupts in the GIC. */
R_BSP_IrqClearPending(irq);
/* Enable the interrupt in the GIC. */
R_BSP_IrqEnableNoClear(irq);
}
/*******************************************************************************************************************//**
* Disables interrupts in the GIC.
*
* @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
{
r_bsp_irq_disable(irq);
}
/*******************************************************************************************************************//**
* Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
*
* @param[in] irq Interrupt number.
* @param[in] priority GIC priority of the interrupt
* @param[in] p_context The interrupt context is a pointer to data required in the ISR.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
{
R_BSP_IrqCfg(irq, priority, p_context);
R_BSP_IrqEnable(irq);
}
/*******************************************************************************************************************//**
* @brief Finds the ISR context associated with the requested IRQ.
*
* @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
* function.
* @return ISR context for IRQ.
**********************************************************************************************************************/
__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
{
/* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
* being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
return gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET];
}
/*******************************************************************************************************************//**
* Sets the interrupt detect type.
*
* @param[in] irq The IRQ number to configure.
* @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
{
r_bsp_irq_detect_type_set(irq, detect_type);
}
/*******************************************************************************************************************//**
* Sets the interrupt Group.
*
* @param[in] irq The IRQ number to configure.
* @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
{
r_bsp_irq_group_set(irq, interrupt_group);
}
/*******************************************************************************************************************//**
* Sets the interrupt mask level.
*
* @param[in] mask_level The interrupt mask level
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level)
{
FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT);
}
/*******************************************************************************************************************//**
* Gets the interrupt mask level.
*
* @return Value indicating the interrupt mask level.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void)
{
return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) &
0x0000001FUL);
}
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* @internal
* @addtogroup BSP_MCU_PRV Internal BSP Documentation
* @ingroup RENESAS_INTERNAL
* @{
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_irq_cfg(void); // Used internally by BSP
/** @} (end addtogroup BSP_MCU_PRV) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_MCU_API_H
#define BSP_MCU_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
typedef struct st_bsp_event_info
{
IRQn_Type irq;
elc_event_t event;
} bsp_event_info_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect);
void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect);
void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units);
void R_BSP_SystemReset(void);
void R_BSP_CPUReset(bsp_reset_t cpu);
void R_BSP_CPUResetRelease(bsp_reset_t cpu);
void R_BSP_ModuleResetEnable(bsp_module_reset_t module_to_enable);
void R_BSP_ModuleResetDisable(bsp_module_reset_t module_to_disable);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_MODULE_H
#define BSP_MODULE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Cancels the module stop state.
*
* @param ip fsp_ip_t enum value for the module to be stopped
* @param channel The channel. Use channel 0 for modules without channels.
**********************************************************************************************************************/
#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
BSP_MSTP_DMY_ ## ip(channel); \
BSP_MSTP_DMY_ ## ip(channel); \
BSP_MSTP_DMY_ ## ip(channel); \
BSP_MSTP_DMY_ ## ip(channel); \
BSP_MSTP_DMY_ ## ip(channel); \
FSP_CRITICAL_SECTION_EXIT;}
/*******************************************************************************************************************//**
* Enables the module stop state.
*
* @param ip fsp_ip_t enum value for the module to be stopped
* @param channel The channel. Use channel 0 for modules without channels.
**********************************************************************************************************************/
#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
FSP_CRITICAL_SECTION_EXIT;}
/** @} (end addtogroup BSP_MCU) */
#define BSP_MSTP_REG_FSP_IP_BSC(channel) R_SYSC_NS->MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_BSC(channel) (1U);
#define BSP_MSTP_DMY_FSP_IP_BSC(channel) R_BSC->SDCR;
#define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_SYSC_NS->MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel));
#define BSP_MSTP_DMY_FSP_IP_XSPI(channel) (0 >= channel) ? R_XSPI0->WRAPCFG : R_XSPI1->WRAPCFG
#define BSP_MSTP_REG_FSP_IP_SCI(channel) *((4U >= channel) ? &R_SYSC_NS->MSTPCRA : &R_SYSC_S->MSTPCRG)
#define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U));
#define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ? R_SCI1->RDR : \
((2 >= \
channel) ? R_SCI2->RDR : ((3 >= \
channel) \
? R_SCI3 \
->RDR : \
((4 \
>= \
channel) \
? R_SCI4 \
->RDR : \
R_SCI5-> \
RDR))))
#define BSP_MSTP_REG_FSP_IP_IIC(channel) *((1U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG)
#define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U << (1U)));
#define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel) ? R_IIC1->ICCR1 \
: R_IIC2->ICCR1)
#define BSP_MSTP_REG_FSP_IP_SPI(channel) *((2U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG)
#define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U << (2U)));
#define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel) ? R_SPI1->SPCKD : \
((2 >= \
channel) ? R_SPI2->SPCKD : R_SPI3 \
->SPCKD))
#define BSP_MSTP_REG_FSP_IP_MTU3(channel) R_SYSC_NS->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_MTU3(channel) (1U);
#define BSP_MSTP_DMY_FSP_IP_MTU3(channel) R_MTU0->TCR;
#define BSP_MSTP_REG_FSP_IP_GPT(channel) *((13U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_SYSC_S->MSTPCRG)
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= channel) ? \
(1U << (2U)) : (1U << (3U))));
#define BSP_MSTP_DMY_FSP_IP_GPT(channel) (6 >= \
channel) ? R_GPT0->GTSTR : ((13 >= \
channel) ? R_GPT7->GTSTR : R_GPT14-> \
GTSTR);
#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_SYSC_NS->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (5U));
#define BSP_MSTP_DMY_FSP_IP_TFU(channel) R_TFU->TRGSTS;
#define BSP_MSTP_REG_FSP_IP_ADC12(channel) R_SYSC_NS->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel));
#define BSP_MSTP_DMY_FSP_IP_ADC12(channel) (0 >= channel) ? R_ADC120->ADCSR : R_ADC121->ADCSR;
#define BSP_MSTP_REG_FSP_IP_DSMIF(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel));
#define BSP_MSTP_DMY_FSP_IP_DSMIF(channel) (0 >= channel) ? R_DSMIF0->DSSEICR : R_DSMIF1->DSSEICR
#define BSP_MSTP_REG_FSP_IP_CMT(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_CMT(channel) (1U << (2U + channel));
#define BSP_MSTP_DMY_FSP_IP_CMT(channel) (0 >= \
channel) ? R_CMT->UNT[0].CMSTR0 : ((1 >= \
channel) ? R_CMT->UNT[1].CMSTR0 \
: R_CMT->UNT[2].CMSTR0)
#define BSP_MSTP_REG_FSP_IP_CMTW(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_CMTW(channel) (1U << (5U + channel));
#define BSP_MSTP_DMY_FSP_IP_CMTW(channel) (0 >= channel) ? R_CMTW0->CMWSTR : R_CMTW1->CMWSTR
#define BSP_MSTP_REG_FSP_IP_TSU(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_TSU(channel) (1U << (7U));
#define BSP_MSTP_DMY_FSP_IP_TSU(channel) R_TSU->TSUSM;
#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (8U));
#define BSP_MSTP_DMY_FSP_IP_DOC(channel) R_DOC->DOCR
#define BSP_MSTP_REG_FSP_IP_CRC(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRD : &R_SYSC_S->MSTPCRG)
#define BSP_MSTP_BIT_FSP_IP_CRC(channel) ((0U == channel) ? (1U << (9U)) : (1U << (4U)));
#define BSP_MSTP_DMY_FSP_IP_CRC(channel) (0 >= channel) ? R_CRC0->CRCDIR : R_CRC1->CRCDIR;
#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (10U));
#define BSP_MSTP_DMY_FSP_IP_CANFD(channel) R_CANFD->CFDGIPV;
#define BSP_MSTP_REG_FSP_IP_CKIO(channel) R_SYSC_NS->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_CKIO(channel) (1U << (11U));
#define BSP_MSTP_DMY_FSP_IP_CKIO(channel) ;
#define BSP_MSTP_REG_FSP_IP_GMAC(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GMAC(channel) (1U);
#define BSP_MSTP_DMY_FSP_IP_GMAC(channel) R_GMAC->MAC_Configuration
#define BSP_MSTP_REG_FSP_IP_ETHSW(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ETHSW(channel) (1U << (1U));
#define BSP_MSTP_DMY_FSP_IP_ETHSW(channel) R_ETHSW->REVISION
#define BSP_MSTP_REG_FSP_IP_ESC(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ESC(channel) (1U << (2U));
#define BSP_MSTP_DMY_FSP_IP_ESC(channel) R_ESC->TYPE;
#define BSP_MSTP_REG_FSP_IP_ETHSS(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ETHSS(channel) (1U << (3U));
#define BSP_MSTP_DMY_FSP_IP_ETHSS(channel) R_ETHSS->PRCMD
#define BSP_MSTP_REG_FSP_IP_ENCIF(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_ENCIF(channel) (1U << (4U));
#define BSP_MSTP_DMY_FSP_IP_ENCIF(channel) ;
#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_SYSC_NS->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (8U));
#define BSP_MSTP_DMY_FSP_IP_USBHS(channel) R_USBHC->HCREVISION;
#define BSP_MSTP_REG_FSP_IP_TRACECLOCK(channel) R_SYSC_S->MSTPCRF
#define BSP_MSTP_BIT_FSP_IP_TRACECLOCK(channel) (1U << (0U));
#define BSP_MSTP_DMY_FSP_IP_TRACECLOCK(channel) ;
#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_SYSC_S->MSTPCRG
#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (5U));
#define BSP_MSTP_DMY_FSP_IP_RTC(channel) R_RTC->RTCA0CTL0;
#define BSP_MSTP_REG_FSP_IP_CLMA(channel) R_SYSC_S->MSTPCRG
#define BSP_MSTP_BIT_FSP_IP_CLMA(channel) ((2U >= channel) ? \
(1U << (9U + channel)) : (1U << (8U)));
#define BSP_MSTP_DMY_FSP_IP_CLMA(channel) (0 >= \
channel) ? R_CLMA0->CTL0 : ((1 >= \
channel) ? R_CLMA1->CTL0 : ((2 >= \
channel) ? \
R_CLMA2-> \
CTL0 : \
R_CLMA3-> \
CTL0));
#define BSP_MSTP_REG_FSP_IP_SHOSTIF(channel) R_SYSC_S->MSTPCRI
#define BSP_MSTP_BIT_FSP_IP_SHOSTIF(channel) (1U << (1U));
#define BSP_MSTP_DMY_FSP_IP_SHOSTIF(channel) ;
#define BSP_MSTP_REG_FSP_IP_PHOSTIF(channel) R_SYSC_S->MSTPCRI
#define BSP_MSTP_BIT_FSP_IP_PHOSTIF(channel) (1U << (0U));
#define BSP_MSTP_DMY_FSP_IP_PHOSTIF(channel) ;
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** Used for holding reference counters for protection bits. */
volatile uint16_t g_protect_counters[] =
{
0U, 0U, 0U, 0U
};
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
static const uint16_t g_prcr_masks[] =
{
0x0001U, /* PRC0. */
0x0002U, /* PRC1. */
0x0004U, /* PRC2. */
0x0008U, /* PRC3. */
};
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Enable register protection. Registers that are protected cannot be written to. Register protection is
* enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
*
* @param[in] regs_to_protect Registers which have write protection enabled.
**********************************************************************************************************************/
void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
{
/* Is it safe to disable write access? */
if (0U != g_protect_counters[regs_to_protect])
{
/* Decrement the protect counter */
g_protect_counters[regs_to_protect]--;
}
/* Is it safe to disable write access? */
if (0U == g_protect_counters[regs_to_protect])
{
/** Enable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
}
}
/*******************************************************************************************************************//**
* Disable register protection. Registers that are protected cannot be written to. Register protection is
* disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
*
* @param[in] regs_to_unprotect Registers which have write protection disabled.
**********************************************************************************************************************/
void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
{
/* If this is first entry then disable protection. */
if (0U == g_protect_counters[regs_to_unprotect])
{
/** Disable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
}
/** Increment the protect counter */
g_protect_counters[regs_to_unprotect]++;
}
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_REGISTER_PROTECTION_H
#define BSP_REGISTER_PROTECTION_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/** The different types of registers that can be protected. */
typedef enum e_bsp_reg_protect
{
/** Enables writing to the registers related to the clock generation circuit. */
BSP_REG_PROTECT_CGC = 0,
/** Enables writing to the registers related to low power consumption and reset. */
BSP_REG_PROTECT_LPC_RESET,
/** Enables writing to the registers related to GPIO. */
BSP_REG_PROTECT_GPIO,
/** Enables writing to the registers related to Non-Safety reg. */
BSP_REG_PROTECT_SYSTEM,
} bsp_reg_protect_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_register_protect_open(void); // Used internally by BSP
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_RESET_MRCTL_BIT_SHIFT_MASK (0x0000001FU)
#define BSP_RESET_MRCTL_SELECT_MASK (0x001F0000U)
#define BSP_RESET_MRCTL_REGION_SELECT_MASK (0x00400000U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Occur the system software reset.
**********************************************************************************************************************/
void R_BSP_SystemReset (void)
{
/* System software reset. */
R_SYSC_S->SWRSYS = BSP_PRV_RESET_KEY;
}
/*******************************************************************************************************************//**
* Occur the CPU software reset.
*
* @param[in] cpu to be reset state.
**********************************************************************************************************************/
void R_BSP_CPUReset (bsp_reset_t cpu)
{
/* CPU0 software reset. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY;
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
__WFI();
FSP_PARAMETER_NOT_USED(cpu);
}
/*******************************************************************************************************************//**
* Release the CPU reset state.
*
* @param[in] cpu to be release reset state.
**********************************************************************************************************************/
void R_BSP_CPUResetRelease (bsp_reset_t cpu)
{
/* Release CPU0 reset state. */
R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_RELEASE_KEY;
FSP_PARAMETER_NOT_USED(cpu);
}
/*******************************************************************************************************************//**
* Enable module reset state.
*
* @param[in] module_to_enable Modules to enable module reset state.
**********************************************************************************************************************/
void R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable)
{
volatile uint32_t mrctl;
uint32_t * p_reg;
/** When MRCTLn register exists in the safety region,
* it is necessary to add an offset of safety region. */
p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
(((module_to_enable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
(module_to_enable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
mrctl = 1U << (module_to_enable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
/** Enable module reset state using MRCTLE register. */
*p_reg |= mrctl;
/** To ensure processing after module reset. */
mrctl = *(volatile uint32_t *) (p_reg);
}
/*******************************************************************************************************************//**
* Disable module reset state.
*
* @param[in] module_to_disable Modules to disable module reset state.
**********************************************************************************************************************/
void R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable)
{
volatile uint32_t mrctl;
uint32_t * p_reg;
/** When MRCTLn register exists in the safety region,
* it is necessary to add an offset of safety region. */
p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
(((module_to_disable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
(module_to_disable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
mrctl = 1U << (module_to_disable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
/** Disable module stop state using MRCTLn register. */
*p_reg &= ~mrctl;
/** In order to secure processing after release from module reset,
* dummy read the same register at least three times.
* Refer to "Notes on Module Reset Control Register Operation" of the RZ microprocessor manual. */
mrctl = *(volatile uint32_t *) (p_reg);
mrctl = *(volatile uint32_t *) (p_reg);
mrctl = *(volatile uint32_t *) (p_reg);
}
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_RESET_H
#define BSP_RESET_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Key code for writing reset register. */
#define BSP_PRV_RESET_KEY (0x4321A501U)
#define BSP_PRV_RESET_RELEASE_KEY (0x00000000U)
/* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4).
* Bit 24 indicates whether MRCTLn register is in the safety region. */
#define BSP_RESET_MRCTLA_SELECT (0x00000000U)
#define BSP_RESET_MRCTLE_SELECT (0x00040000U)
#define BSP_RESET_MRCTLI_SELECT (0x00480000U)
/* MRCTL register bit number. */
#define BSP_RESET_MRCTL_BIT0_SHIFT (0x00000000U)
#define BSP_RESET_MRCTL_BIT1_SHIFT (0x00000001U)
#define BSP_RESET_MRCTL_BIT2_SHIFT (0x00000002U)
#define BSP_RESET_MRCTL_BIT3_SHIFT (0x00000003U)
#define BSP_RESET_MRCTL_BIT4_SHIFT (0x00000004U)
#define BSP_RESET_MRCTL_BIT5_SHIFT (0x00000005U)
#define BSP_RESET_MRCTL_BIT6_SHIFT (0x00000006U)
#define BSP_RESET_MRCTL_BIT7_SHIFT (0x00000007U)
#define BSP_RESET_MRCTL_BIT8_SHIFT (0x00000008U)
#define BSP_RESET_MRCTL_BIT9_SHIFT (0x00000009U)
#define BSP_RESET_MRCTL_BIT10_SHIFT (0x0000000AU)
#define BSP_RESET_MRCTL_BIT11_SHIFT (0x0000000BU)
#define BSP_RESET_MRCTL_BIT12_SHIFT (0x0000000CU)
#define BSP_RESET_MRCTL_BIT13_SHIFT (0x0000000DU)
#define BSP_RESET_MRCTL_BIT14_SHIFT (0x0000000EU)
#define BSP_RESET_MRCTL_BIT15_SHIFT (0x0000000FU)
#define BSP_RESET_MRCTL_BIT16_SHIFT (0x00000010U)
#define BSP_RESET_MRCTL_BIT17_SHIFT (0x00000011U)
#define BSP_RESET_MRCTL_BIT18_SHIFT (0x00000012U)
#define BSP_RESET_MRCTL_BIT19_SHIFT (0x00000013U)
#define BSP_RESET_MRCTL_BIT20_SHIFT (0x00000014U)
#define BSP_RESET_MRCTL_BIT21_SHIFT (0x00000015U)
#define BSP_RESET_MRCTL_BIT22_SHIFT (0x00000016U)
#define BSP_RESET_MRCTL_BIT23_SHIFT (0x00000017U)
#define BSP_RESET_MRCTL_BIT24_SHIFT (0x00000018U)
#define BSP_RESET_MRCTL_BIT25_SHIFT (0x00000019U)
#define BSP_RESET_MRCTL_BIT26_SHIFT (0x0000001AU)
#define BSP_RESET_MRCTL_BIT27_SHIFT (0x0000001BU)
#define BSP_RESET_MRCTL_BIT28_SHIFT (0x0000001CU)
#define BSP_RESET_MRCTL_BIT29_SHIFT (0x0000001DU)
#define BSP_RESET_MRCTL_BIT30_SHIFT (0x0000001EU)
#define BSP_RESET_MRCTL_BIT31_SHIFT (0x0000001FU)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/** CPU to be reset target.*/
typedef enum e_bsp_reset
{
BSP_RESET_CR52_0 = 0, ///< Software reset for CR52_0
} bsp_reset_t;
/** The different types of registers that can control the reset of peripheral modules related to Ethernet. */
typedef enum e_bsp_module_reset
{
/** Enables writing to the registers related to xSPI Unit 0 reset control. */
BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
/** Enables writing to the registers related to xSPI Unit 1 reset control. */
BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
/** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */
BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
/** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */
BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
/** Enables writing to the registers related to ETHSW reset control. */
BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
/** Enables writing to the registers related to ESC (Bus clock domain) reset control. */
BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
/** Enables writing to the registers related to ESC (IP clock domain) reset control. */
BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT),
/** Enables writing to the registers related to Ethernet subsystem register reset control. */
BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT),
/** Enables writing to the registers related to MII converter reset control. */
BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT),
/** Enables writing to the registers related to PHOSTIF reset control. */
BSP_MODULE_RESET_PHOSTIF = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT),
/** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */
BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT),
/** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */
BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT),
/** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */
BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT),
} bsp_module_reset_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#include <sys/types.h>
#include <errno.h>
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
caddr_t _sbrk(int incr);
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* FSP implementation of the standard library _sbrk() function.
* @param[in] inc The number of bytes being asked for by malloc().
*
* @note This function overrides the _sbrk version that exists in the newlib library that is linked with.
* That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and
* worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc()
* only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by
* malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc().
* @retval Address of allocated area if successful, -1 otherwise.
**********************************************************************************************************************/
caddr_t _sbrk (int incr)
{
extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker.
extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker.
uint32_t bytes = (uint32_t) incr;
static char * current_heap_end = 0;
char * current_block_address;
if (current_heap_end == 0)
{
current_heap_end = &_Heap_Begin;
}
current_block_address = current_heap_end;
/* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support
* unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple
* of 4. */
bytes = (bytes + 3U) & (~3U);
if (current_heap_end + bytes > &_Heap_Limit)
{
/** Heap has overflowed */
errno = ENOMEM;
return (caddr_t) -1;
}
current_heap_end += bytes;
return (caddr_t) current_block_address;
}
#endif
/******************************************************************************************************************//**
* @} (end addtogroup BSP_MCU)
*********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef RENESAS_TFU
#define RENESAS_TFU
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* Mathematical Functions includes. */
#ifdef __cplusplus
#include <cmath>
#else
#include <math.h>
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935F
#ifdef __GNUC__ /* and (arm)clang */
#if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus)
/* No form of inline is available, it happens only when -std=c89, gnu89 and
* above are OK */
#warning \
"-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99"
#else
#ifdef __GNUC_GNU_INLINE__
/* gnu89 semantics of inline and extern inline are essentially the exact
* opposite of those in C99 */
#define BSP_TFU_INLINE extern inline __attribute__((always_inline))
#else /* __GNUC_STDC_INLINE__ */
#define BSP_TFU_INLINE static inline __attribute__((always_inline))
#endif
#endif
#elif __ICCARM__
#define BSP_TFU_INLINE
#else
#error "Compiler not supported!"
#endif
#if BSP_CFG_USE_TFU_MATHLIB
#define sinf(x) __sinf(x)
#define cosf(x) __cosf(x)
#define atan2f(y, x) __atan2f(y, x)
#define hypotf(x, y) __hypotf(x, y)
#define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h)
#define sincosf(a, s, c) __sincosf(a, s, c)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Calculates sine of the given angle.
* @param[in] angle The value of an angle in radian.
*
* @retval Sine value of an angle.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE float __sinf (float angle)
{
/* Set the angle to R_TFU->SCDT1 */
R_TFU->SCDT1 = angle;
/* Read sin from R_TFU->SCDT1 */
return R_TFU->SCDT1;
}
/*******************************************************************************************************************//**
* Calculates cosine of the given angle.
* @param[in] angle The value of an angle in radian.
*
* @retval Cosine value of an angle.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE float __cosf (float angle)
{
/* Set the angle to R_TFU->SCDT1 */
R_TFU->SCDT1 = angle;
/* Read cos from R_TFU->SCDT1 */
return R_TFU->SCDT0;
}
/*******************************************************************************************************************//**
* Calculates sine and cosine of the given angle.
* @param[in] angle The value of an angle in radian.
* @param[out] sin Sine value of an angle.
* @param[out] cos Cosine value of an angle.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos)
{
/* Set the angle to R_TFU->SCDT1 */
R_TFU->SCDT1 = angle;
/* Read sin from R_TFU->SCDT1 */
*sin = R_TFU->SCDT1;
/* Read sin from R_TFU->SCDT1 */
*cos = R_TFU->SCDT0;
}
/*******************************************************************************************************************//**
* Calculates the arc tangent based on given X-cordinate and Y-cordinate values.
* @param[in] y_cord Y-Axis cordinate value.
* @param[in] x_cord X-Axis cordinate value.
*
* @retval Arc tangent for given values.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord)
{
/* Set X-cordinate to R_TFU->ATDT0 */
R_TFU->ATDT0 = x_cord;
/* set Y-cordinate to R_TFU->ATDT1 */
R_TFU->ATDT1 = y_cord;
/* Read arctan(y/x) from R_TFU->ATDT1 */
return R_TFU->ATDT1;
}
/*******************************************************************************************************************//**
* Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.
* @param[in] y_cord Y-cordinate value.
* @param[in] x_cord X-cordinate value.
*
* @retval Hypotenuse for given values.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord)
{
/* Set X-coordinate to R_TFU->ATDT0 */
R_TFU->ATDT0 = x_cord;
/* set Y-coordinate to R_TFU->ATDT1 */
R_TFU->ATDT1 = y_cord;
/* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
}
/*******************************************************************************************************************//**
* Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.
* @param[in] y_cord Y-cordinate value.
* @param[in] x_cord X-cordinate value.
* @param[out] atan2 Arc tangent for given values.
* @param[out] hypot Hypotenuse for given values.
**********************************************************************************************************************/
#if __ICCARM__
#pragma inline = forced
#endif
BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot)
{
/* Set X-coordinate to R_TFU->ATDT0 */
R_TFU->ATDT0 = x_cord;
/* set Y-coordinate to R_TFU->ATDT1 */
R_TFU->ATDT1 = y_cord;
/* Read arctan(y/x) from R_TFU->ATDT1 */
*atan2 = R_TFU->ATDT1;
/* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */
*hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR;
}
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif /* RENESAS_TFU */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Powers on and off the L3 cache way.
**********************************************************************************************************************/
void r_bsp_cache_l3_power_ctrl (void)
{
/* Does nothing because CR52 does not have the CLUSTERPWRCTLR register. */
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_CACHE_CORE_H
#define BSP_CACHE_CORE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void r_bsp_cache_l3_power_ctrl(void);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
* occur when the loop exits. The 'naked' attribute indicates that the specified function does not need
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
{
__asm volatile ("sw_delay_loop: \n"
#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
" subs r0, #1 \n" ///< 1 cycle
#elif defined(__GNUC__)
" sub r0, r0, #1 \n" ///< 1 cycle
#endif
" cmp r0, #0 \n" ///< 1 cycle
" bne sw_delay_loop \n" ///< 2 cycles
" bx lr \n"); ///< 2 cycles
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_DELAY_CORE_H
#define BSP_DELAY_CORE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* The number of cycles required per software delay loop. */
#ifndef BSP_DELAY_LOOP_CYCLES
#define BSP_DELAY_LOOP_CYCLES (4)
#endif
/* Calculates the number of delay loops to pass to r_bsp_software_delay_loop to achieve at least the requested cycle
* count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures
* the requested number of loops is at least 1 since r_bsp_software_delay_loop cannot be called with a loop count
* of 0. */
#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop(uint32_t loop_cnt);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/** ELC event definitions. */
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU)
#define BSP_PRV_CLEAR_REG_MAX (13U)
#define BSP_PRV_ALL_BIT_CLEAR (0xFFFFFFFFU)
#define BSP_PRV_ID_MASK (0x000003FFU)
#define BSP_PRV_INTERRUPTABLE_NUM (32U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#if VECTOR_DATA_IRQ_COUNT > 0
extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES];
#endif
extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES];
extern const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX];
/* This table is used to store the context in the ISR. */
void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
/* GIC current interrupt ID and variable. */
IRQn_Type g_current_interrupt_num[BSP_PRV_INTERRUPTABLE_NUM];
uint8_t g_current_interrupt_pointer = 0;
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE =
{
(bsp_interrupt_event_t) 0
};
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Using the vector table information section that has been built by the linker and placed into ROM in the
* .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts
* in the NVIC.
*
**********************************************************************************************************************/
void bsp_irq_core_cfg (void)
{
uint32_t gicd_reg_num;
GICD_Type * GICD;
GICR_CONTROL_TARGET_Type * GICR_TARGET0_IFREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_IFREG = BSP_PRV_GICR_TARGET0_IFREG_ADDRESS;
/* Enable Group1 interrupts from the GIC Distributor to the GIC CPU interface. */
GICD->GICD_CTLR |= 0x00000002UL;
/* Release Processor Sleep state of the target. */
GICR_TARGET0_IFREG->GICR_WAKER = 0x00000000UL;
/* Initialize GICD_ICFGR register for the edge-triggered interrupt. */
for (gicd_reg_num = 0; gicd_reg_num < BSP_NON_SELECTABLE_ICFGR_MAX; gicd_reg_num++)
{
GICD->GICD_ICFGR[gicd_reg_num] = BSP_GICD_ICFGR_INIT[gicd_reg_num];
}
/* Clear the Pending and Active bit for the all interrupts. */
for (gicd_reg_num = 0; gicd_reg_num < BSP_PRV_CLEAR_REG_MAX; gicd_reg_num++)
{
GICD->GICD_ICPENDR[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR;
GICD->GICD_ICACTIVER[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR;
}
__asm volatile ("cpsie i \n" /* Enable IRQ Interrupts */
"cpsie f \n" /* Enable FIQ Interrupts */
"cpsie a \n" /* Enable SError Interrupts */
"isb"); /* Ensuring Context-changing */
}
/*******************************************************************************************************************//**
* This function is called first when an interrupt is generated and branches to each interrupt isr function.
*
* @param[in] id GIC INTID used to identify the interrupt.
**********************************************************************************************************************/
void bsp_common_interrupt_handler (uint32_t id)
{
uint16_t gic_intid;
IRQn_Type irq;
/* Get interrupt ID (GIC INTID). */
gic_intid = (uint16_t) (id & BSP_PRV_ID_MASK);
irq = (IRQn_Type) (gic_intid - BSP_CORTEX_VECTOR_TABLE_ENTRIES);
/* Remain the interrupt number */
g_current_interrupt_num[g_current_interrupt_pointer++] = irq;
__asm volatile ("dmb");
BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE
#if VECTOR_DATA_IRQ_COUNT > 0
if (BSP_CORTEX_VECTOR_TABLE_ENTRIES <= gic_intid)
{
/* Branch to an interrupt handler. */
g_vector_table[irq]();
}
else
#endif
{
/* Branch to an interrupt handler. */
g_sgi_ppi_vector_table[gic_intid]();
}
g_current_interrupt_pointer--;
BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE
}

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_IRQ_CORE_H
#define BSP_IRQ_CORE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES)
#define BSP_PRV_GICD_ADDRESS (GICD0)
#define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS (GICR0_TARGET0_INTREG)
#define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS (GICR0_TARGET0_IFREG)
#define BSP_EVENT_SGI_PPI_ARRAY_NUM (2U)
#define BSP_NON_SELECTABLE_ICFGR_MAX (BSP_VECTOR_TABLE_MAX_ENTRIES / BSP_INTERRUPT_TYPE_OFFSET)
#define BSP_PRV_IRQ_CONFIG_MASK (0x000000FFU)
#define BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK (1UL << 1UL)
#define BSP_PRV_GIC_REG_STRIDE04 (4U)
#define BSP_PRV_GIC_REG_STRIDE16 (16U)
#define BSP_PRV_GIC_REG_STRIDE32 (32U)
#define BSP_PRV_GIC_REG_BITS1 (1U)
#define BSP_PRV_GIC_REG_BITS2 (2U)
#define BSP_PRV_GIC_REG_BITS8 (8U)
#define BSP_PRV_GIC_REG_MASK_1BIT (1U)
#define BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM (-17)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Sets the ISR context associated with the requested IRQ.
*
* @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
* function.
* @param[in] p_context ISR context for IRQ.
**********************************************************************************************************************/
__STATIC_INLINE void r_fsp_irq_context_set (IRQn_Type const irq, void * p_context)
{
/* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
* being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET] = p_context;
}
/*******************************************************************************************************************//**
* Clear the GIC pending interrupt.
*
* @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_clear_pending (IRQn_Type irq)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
GICD->GICD_ICPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] =
(uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
GICR_TARGET0_INTREG->GICR_ICPENDR0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
}
}
/*******************************************************************************************************************//**
* Get the GIC pending interrupt.
*
* @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
*
* @return Value indicating the status of the level interrupt.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t r_bsp_irq_pending_get (IRQn_Type irq)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
uint32_t value = 0;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
uint32_t shift = (_irq % BSP_PRV_GIC_REG_STRIDE32);
value = (GICD->GICD_ISPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT);
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
uint32_t shift = _irq;
value = (GICR_TARGET0_INTREG->GICR_ISPENDR0 >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT);
}
return value;
}
/*******************************************************************************************************************//**
* Sets the interrupt priority and context.
*
* @param[in] irq The IRQ number to configure.
* @param[in] priority GIC priority of the interrupt
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_cfg (IRQn_Type const irq, uint32_t priority)
{
#if (52U == __CORTEX_R)
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
/* Set the interrupt group to 1 (IRQ) */
GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |=
(uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
/* Set the interrupt priority */
GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &=
(uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |=
(priority <<
(BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
/* Set the interrupt group to 1 (IRQ) */
GICR_TARGET0_INTREG->GICR_IGROUPR0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
/* Set the interrupt priority */
GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &=
(uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |=
(priority <<
(BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04))));
}
#endif
}
/*******************************************************************************************************************//**
* Enable the IRQ in the GIC (Without clearing the pending bit).
*
* @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the
* Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_enable_no_clear (IRQn_Type const irq)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
GICD->GICD_ISENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] |=
(uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
GICR_TARGET0_INTREG->GICR_ISENABLER0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
}
}
/*******************************************************************************************************************//**
* Disables interrupts in the GIC.
*
* @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_disable (IRQn_Type const irq)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
GICD->GICD_ICENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] =
(uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32));
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
GICR_TARGET0_INTREG->GICR_ICENABLER0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq);
}
__DSB();
__ISB();
}
/*******************************************************************************************************************//**
* Sets the interrupt detect type.
*
* @param[in] irq The IRQ number to configure.
* @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_detect_type_set (IRQn_Type const irq, uint32_t detect_type)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
if (0 != detect_type)
{
GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] |=
(uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
(BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)));
}
else
{
GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] &=
~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
(BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))));
}
}
else if (irq >= BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM)
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
if (0 != detect_type)
{
GICR_TARGET0_INTREG->GICR_ICFGR1 |=
(uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
(BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)));
}
else
{
GICR_TARGET0_INTREG->GICR_ICFGR1 &=
~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK <<
(BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))));
}
}
else
{
/* The register that sets the SGI interrupt type (GICR_ICFGR0) is read-only, so do not set it. */
}
}
/*******************************************************************************************************************//**
* Sets the interrupt Group.
*
* @param[in] irq The IRQ number to configure.
* @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).
**********************************************************************************************************************/
__STATIC_INLINE void r_bsp_irq_group_set (IRQn_Type const irq, uint32_t interrupt_group)
{
GICD_Type * GICD;
GICR_SGI_PPI_Type * GICR_TARGET0_INTREG;
GICD = BSP_PRV_GICD_ADDRESS;
GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS;
if (irq >= 0)
{
uint32_t _irq = (uint32_t) irq;
GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= (interrupt_group << (_irq % BSP_PRV_GIC_REG_STRIDE32));
}
else
{
uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET);
GICR_TARGET0_INTREG->GICR_IGROUPR0 |= interrupt_group << _irq;
}
}
/*******************************************************************************************************************//**
* @internal
* @addtogroup BSP_MCU_PRV Internal BSP Documentation
* @ingroup RENESAS_INTERNAL
* @{
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_irq_core_cfg(void); // Used internally by BSP
void bsp_common_interrupt_handler(uint32_t id);
/** @} (end addtogroup BSP_MCU_PRV) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_ELC_H
#define BSP_ELC_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU_RZN2L
* @{
**********************************************************************************************************************/
/** Sources of event signals to be linked to other peripherals or the CPU
* @note This list may change based on based on the device.
* */
typedef enum e_elc_event_rzn2l
{
ELC_EVENT_INTCPU0 = (0), // Software interrupt 0
ELC_EVENT_INTCPU1 = (1), // Software interrupt 1
ELC_EVENT_INTCPU2 = (2), // Software interrupt 2
ELC_EVENT_INTCPU3 = (3), // Software interrupt 3
ELC_EVENT_INTCPU4 = (4), // Software interrupt 4
ELC_EVENT_INTCPU5 = (5), // Software interrupt 5
ELC_EVENT_IRQ0 = (6), // External pin interrupt 0
ELC_EVENT_IRQ1 = (7), // External pin interrupt 1
ELC_EVENT_IRQ2 = (8), // External pin interrupt 2
ELC_EVENT_IRQ3 = (9), // External pin interrupt 3
ELC_EVENT_IRQ4 = (10), // External pin interrupt 4
ELC_EVENT_IRQ5 = (11), // External pin interrupt 5
ELC_EVENT_IRQ6 = (12), // External pin interrupt 6
ELC_EVENT_IRQ7 = (13), // External pin interrupt 7
ELC_EVENT_IRQ8 = (14), // External pin interrupt 8
ELC_EVENT_IRQ9 = (15), // External pin interrupt 9
ELC_EVENT_IRQ10 = (16), // External pin interrupt 10
ELC_EVENT_IRQ11 = (17), // External pin interrupt 11
ELC_EVENT_IRQ12 = (18), // External pin interrupt 12
ELC_EVENT_IRQ13 = (19), // External pin interrupt 13
ELC_EVENT_BSC_CMI = (20), // Refresh compare match interrupt
ELC_EVENT_DMAC0_INT0 = (21), // DMAC0 transfer completion 0
ELC_EVENT_DMAC0_INT1 = (22), // DMAC0 transfer completion 1
ELC_EVENT_DMAC0_INT2 = (23), // DMAC0 transfer completion 2
ELC_EVENT_DMAC0_INT3 = (24), // DMAC0 transfer completion 3
ELC_EVENT_DMAC0_INT4 = (25), // DMAC0 transfer completion 4
ELC_EVENT_DMAC0_INT5 = (26), // DMAC0 transfer completion 5
ELC_EVENT_DMAC0_INT6 = (27), // DMAC0 transfer completion 6
ELC_EVENT_DMAC0_INT7 = (28), // DMAC0 transfer completion 7
ELC_EVENT_DMAC1_INT0 = (37), // DMAC1 transfer completion 0
ELC_EVENT_DMAC1_INT1 = (38), // DMAC1 transfer completion 1
ELC_EVENT_DMAC1_INT2 = (39), // DMAC1 transfer completion 2
ELC_EVENT_DMAC1_INT3 = (40), // DMAC1 transfer completion 3
ELC_EVENT_DMAC1_INT4 = (41), // DMAC1 transfer completion 4
ELC_EVENT_DMAC1_INT5 = (42), // DMAC1 transfer completion 5
ELC_EVENT_DMAC1_INT6 = (43), // DMAC1 transfer completion 6
ELC_EVENT_DMAC1_INT7 = (44), // DMAC1 transfer completion 7
ELC_EVENT_CMT0_CMI = (53), // CMT0 Compare match
ELC_EVENT_CMT1_CMI = (54), // CMT1 Compare match
ELC_EVENT_CMT2_CMI = (55), // CMT2 Compare match
ELC_EVENT_CMT3_CMI = (56), // CMT3 Compare match
ELC_EVENT_CMT4_CMI = (57), // CMT4 Compare match
ELC_EVENT_CMT5_CMI = (58), // CMT5 Compare match
ELC_EVENT_CMTW0_CMWI = (59), // CMTW0 Compare match
ELC_EVENT_CMTW0_IC0I = (60), // CMTW0 Input capture of register 0
ELC_EVENT_CMTW0_IC1I = (61), // CMTW0 Input capture of register 1
ELC_EVENT_CMTW0_OC0I = (62), // CMTW0 Output compare of register 0
ELC_EVENT_CMTW0_OC1I = (63), // CMTW0 Output compare of register 1
ELC_EVENT_CMTW1_CMWI = (64), // CMTW1 Compare match
ELC_EVENT_CMTW1_IC0I = (65), // CMTW1 Input capture of register 0
ELC_EVENT_CMTW1_IC1I = (66), // CMTW1 Input capture of register 1
ELC_EVENT_CMTW1_OC0I = (67), // CMTW1 Output compare of register 0
ELC_EVENT_CMTW1_OC1I = (68), // CMTW1 Output compare of register 1
ELC_EVENT_TGIA0 = (69), // MTU0.TGRA input capture/compare match
ELC_EVENT_TGIB0 = (70), // MTU0.TGRB input capture/compare match
ELC_EVENT_TGIC0 = (71), // MTU0.TGRC input capture/compare match
ELC_EVENT_TGID0 = (72), // MTU0.TGRD input capture/compare match
ELC_EVENT_TCIV0 = (73), // MTU0.TCNT overflow
ELC_EVENT_TGIE0 = (74), // MTU0.TGRE compare match
ELC_EVENT_TGIF0 = (75), // MTU0.TGRF compare match
ELC_EVENT_TGIA1 = (76), // MTU1.TGRA input capture/compare match
ELC_EVENT_TGIB1 = (77), // MTU1.TGRB input capture/compare match
ELC_EVENT_TCIV1 = (78), // MTU1.TCNT overflow
ELC_EVENT_TCIU1 = (79), // MTU1.TCNT underflow
ELC_EVENT_TGIA2 = (80), // MTU2.TGRA input capture/compare match
ELC_EVENT_TGIB2 = (81), // MTU2.TGRB input capture/compare match
ELC_EVENT_TCIV2 = (82), // MTU2.TCNT overflow
ELC_EVENT_TCIU2 = (83), // MTU2.TCNT underflow
ELC_EVENT_TGIA3 = (84), // MTU3.TGRA input capture/compare match
ELC_EVENT_TGIB3 = (85), // MTU3.TGRB input capture/compare match
ELC_EVENT_TGIC3 = (86), // MTU3.TGRC input capture/compare match
ELC_EVENT_TGID3 = (87), // MTU3.TGRD input capture/compare match
ELC_EVENT_TCIV3 = (88), // MTU3.TCNT overflow
ELC_EVENT_TGIA4 = (89), // MTU4.TGRA input capture/compare match
ELC_EVENT_TGIB4 = (90), // MTU4.TGRB input capture/compare match
ELC_EVENT_TGIC4 = (91), // MTU4.TGRC input capture/compare match
ELC_EVENT_TGID4 = (92), // MTU4.TGRD input capture/compare match
ELC_EVENT_TCIV4 = (93), // MTU4.TCNT overflow/underflow
ELC_EVENT_TGIU5 = (94), // MTU5.TGRU input capture/compare match
ELC_EVENT_TGIV5 = (95), // MTU5.TGRV input capture/compare match
ELC_EVENT_TGIW5 = (96), // MTU5.TGRW input capture/compare match
ELC_EVENT_TGIA6 = (97), // MTU6.TGRA input capture/compare match
ELC_EVENT_TGIB6 = (98), // MTU6.TGRB input capture/compare match
ELC_EVENT_TGIC6 = (99), // MTU6.TGRC input capture/compare match
ELC_EVENT_TGID6 = (100), // MTU6.TGRD input capture/compare match
ELC_EVENT_TCIV6 = (101), // MTU6.TCNT overflow
ELC_EVENT_TGIA7 = (102), // MTU7.TGRA input capture/compare match
ELC_EVENT_TGIB7 = (103), // MTU7.TGRB input capture/compare match
ELC_EVENT_TGIC7 = (104), // MTU7.TGRC input capture/compare match
ELC_EVENT_TGID7 = (105), // MTU7.TGRD input capture/compare match
ELC_EVENT_TCIV7 = (106), // MTU7.TCNT overflow/underflow
ELC_EVENT_TGIA8 = (107), // MTU8.TGRA input capture/compare match
ELC_EVENT_TGIB8 = (108), // MTU8.TGRB input capture/compare match
ELC_EVENT_TGIC8 = (109), // MTU8.TGRC input capture/compare match
ELC_EVENT_TGID8 = (110), // MTU8.TGRD input capture/compare match
ELC_EVENT_TCIV8 = (111), // MTU8.TCNT overflow
ELC_EVENT_OEI1 = (112), // Output enable interrupt 1
ELC_EVENT_OEI2 = (113), // Output enable interrupt 2
ELC_EVENT_OEI3 = (114), // Output enable interrupt 3
ELC_EVENT_OEI4 = (115), // Output enable interrupt 4
ELC_EVENT_GPT0_CCMPA = (116), // GPT0 GTCCRA input capture/compare match
ELC_EVENT_GPT0_CCMPB = (117), // GPT0 GTCCRB input capture/compare match
ELC_EVENT_GPT0_CMPC = (118), // GPT0 GTCCRC compare match
ELC_EVENT_GPT0_CMPD = (119), // GPT0 GTCCRD compare match
ELC_EVENT_GPT0_CMPE = (120), // GPT0 GTCCRE compare match
ELC_EVENT_GPT0_CMPF = (121), // GPT0 GTCCRF compare match
ELC_EVENT_GPT0_OVF = (122), // GPT0 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT0_UDF = (123), // GPT0 GTCNT underflow
ELC_EVENT_GPT0_DTE = (124), // GPT0 Dead time error
ELC_EVENT_GPT1_CCMPA = (125), // GPT1 GTCCRA input capture/compare match
ELC_EVENT_GPT1_CCMPB = (126), // GPT1 GTCCRB input capture/compare match
ELC_EVENT_GPT1_CMPC = (127), // GPT1 GTCCRC compare match
ELC_EVENT_GPT1_CMPD = (128), // GPT1 GTCCRD compare match
ELC_EVENT_GPT1_CMPE = (129), // GPT1 GTCCRE compare match
ELC_EVENT_GPT1_CMPF = (130), // GPT1 GTCCRF compare match
ELC_EVENT_GPT1_OVF = (131), // GPT1 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT1_UDF = (132), // GPT1 GTCNT underflow
ELC_EVENT_GPT1_DTE = (133), // GPT1 Dead time error
ELC_EVENT_GPT2_CCMPA = (134), // GPT2 GTCCRA input capture/compare match
ELC_EVENT_GPT2_CCMPB = (135), // GPT2 GTCCRB input capture/compare match
ELC_EVENT_GPT2_CMPC = (136), // GPT2 GTCCRC compare match
ELC_EVENT_GPT2_CMPD = (137), // GPT2 GTCCRD compare match
ELC_EVENT_GPT2_CMPE = (138), // GPT2 GTCCRE compare match
ELC_EVENT_GPT2_CMPF = (139), // GPT2 GTCCRF compare match
ELC_EVENT_GPT2_OVF = (140), // GPT2 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT2_UDF = (141), // GPT2 GTCNT underflow
ELC_EVENT_GPT2_DTE = (142), // GPT2 Dead time error
ELC_EVENT_GPT3_CCMPA = (143), // GPT3 GTCCRA input capture/compare match
ELC_EVENT_GPT3_CCMPB = (144), // GPT3 GTCCRB input capture/compare match
ELC_EVENT_GPT3_CMPC = (145), // GPT3 GTCCRC compare match
ELC_EVENT_GPT3_CMPD = (146), // GPT3 GTCCRD compare match
ELC_EVENT_GPT3_CMPE = (147), // GPT3 GTCCRE compare match
ELC_EVENT_GPT3_CMPF = (148), // GPT3 GTCCRF compare match
ELC_EVENT_GPT3_OVF = (149), // GPT3 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT3_UDF = (150), // GPT3 GTCNT underflow
ELC_EVENT_GPT3_DTE = (151), // GPT3 Dead time error
ELC_EVENT_GPT4_CCMPA = (152), // GPT4 GTCCRA input capture/compare match
ELC_EVENT_GPT4_CCMPB = (153), // GPT4 GTCCRB input capture/compare match
ELC_EVENT_GPT4_CMPC = (154), // GPT4 GTCCRC compare match
ELC_EVENT_GPT4_CMPD = (155), // GPT4 GTCCRD compare match
ELC_EVENT_GPT4_CMPE = (156), // GPT4 GTCCRE compare match
ELC_EVENT_GPT4_CMPF = (157), // GPT4 GTCCRF compare match
ELC_EVENT_GPT4_OVF = (158), // GPT4 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT4_UDF = (159), // GPT4 GTCNT underflow
ELC_EVENT_GPT4_DTE = (160), // GPT4 Dead time error
ELC_EVENT_GPT5_CCMPA = (161), // GPT5 GTCCRA input capture/compare match
ELC_EVENT_GPT5_CCMPB = (162), // GPT5 GTCCRB input capture/compare match
ELC_EVENT_GPT5_CMPC = (163), // GPT5 GTCCRC compare match
ELC_EVENT_GPT5_CMPD = (164), // GPT5 GTCCRD compare match
ELC_EVENT_GPT5_CMPE = (165), // GPT5 GTCCRE compare match
ELC_EVENT_GPT5_CMPF = (166), // GPT5 GTCCRF compare match
ELC_EVENT_GPT5_OVF = (167), // GPT5 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT5_UDF = (168), // GPT5 GTCNT underflow
ELC_EVENT_GPT5_DTE = (169), // GPT5 Dead time error
ELC_EVENT_GPT6_CCMPA = (170), // GPT6 GTCCRA input capture/compare match
ELC_EVENT_GPT6_CCMPB = (171), // GPT6 GTCCRB input capture/compare match
ELC_EVENT_GPT6_CMPC = (172), // GPT6 GTCCRC compare match
ELC_EVENT_GPT6_CMPD = (173), // GPT6 GTCCRD compare match
ELC_EVENT_GPT6_CMPE = (174), // GPT6 GTCCRE compare match
ELC_EVENT_GPT6_CMPF = (175), // GPT6 GTCCRF compare match
ELC_EVENT_GPT6_OVF = (176), // GPT6 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT6_UDF = (177), // GPT6 GTCNT underflow
ELC_EVENT_GPT6_DTE = (178), // GPT6 Dead time error
ELC_EVENT_GPT7_CCMPA = (179), // GPT7 GTCCRA input capture/compare match
ELC_EVENT_GPT7_CCMPB = (180), // GPT7 GTCCRB input capture/compare match
ELC_EVENT_GPT7_CMPC = (181), // GPT7 GTCCRC compare match
ELC_EVENT_GPT7_CMPD = (182), // GPT7 GTCCRD compare match
ELC_EVENT_GPT7_CMPE = (183), // GPT7 GTCCRE compare match
ELC_EVENT_GPT7_CMPF = (184), // GPT7 GTCCRF compare match
ELC_EVENT_GPT7_OVF = (185), // GPT7 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT7_UDF = (186), // GPT7 GTCNT underflow
ELC_EVENT_GPT7_DTE = (187), // GPT7 Dead time error
ELC_EVENT_GPT8_CCMPA = (188), // GPT8 GTCCRA input capture/compare match
ELC_EVENT_GPT8_CCMPB = (189), // GPT8 GTCCRB input capture/compare match
ELC_EVENT_GPT8_CMPC = (190), // GPT8 GTCCRC compare match
ELC_EVENT_GPT8_CMPD = (191), // GPT8 GTCCRD compare match
ELC_EVENT_GPT8_CMPE = (192), // GPT8 GTCCRE compare match
ELC_EVENT_GPT8_CMPF = (193), // GPT8 GTCCRF compare match
ELC_EVENT_GPT8_OVF = (194), // GPT8 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT8_UDF = (195), // GPT8 GTCNT underflow
ELC_EVENT_GPT8_DTE = (196), // GPT8 Dead time error
ELC_EVENT_GPT9_CCMPA = (197), // GPT9 GTCCRA input capture/compare match
ELC_EVENT_GPT9_CCMPB = (198), // GPT9 GTCCRB input capture/compare match
ELC_EVENT_GPT9_CMPC = (199), // GPT9 GTCCRC compare match
ELC_EVENT_GPT9_CMPD = (200), // GPT9 GTCCRD compare match
ELC_EVENT_GPT9_CMPE = (201), // GPT9 GTCCRE compare match
ELC_EVENT_GPT9_CMPF = (202), // GPT9 GTCCRF compare match
ELC_EVENT_GPT9_OVF = (203), // GPT9 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT9_UDF = (204), // GPT9 GTCNT underflow
ELC_EVENT_GPT9_DTE = (205), // GPT9 Dead time error
ELC_EVENT_GPT10_CCMPA = (206), // GPT10 GTCCRA input capture/compare match
ELC_EVENT_GPT10_CCMPB = (207), // GPT10 GTCCRB input capture/compare match
ELC_EVENT_GPT10_CMPC = (208), // GPT10 GTCCRC compare match
ELC_EVENT_GPT10_CMPD = (209), // GPT10 GTCCRD compare match
ELC_EVENT_GPT10_CMPE = (210), // GPT10 GTCCRE compare match
ELC_EVENT_GPT10_CMPF = (211), // GPT10 GTCCRF compare match
ELC_EVENT_GPT10_OVF = (212), // GPT10 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT10_UDF = (213), // GPT10 GTCNT underflow
ELC_EVENT_GPT10_DTE = (214), // GPT10 Dead time error
ELC_EVENT_GPT11_CCMPA = (215), // GPT11 GTCCRA input capture/compare match
ELC_EVENT_GPT11_CCMPB = (216), // GPT11 GTCCRB input capture/compare match
ELC_EVENT_GPT11_CMPC = (217), // GPT11 GTCCRC compare match
ELC_EVENT_GPT11_CMPD = (218), // GPT11 GTCCRD compare match
ELC_EVENT_GPT11_CMPE = (219), // GPT11 GTCCRE compare match
ELC_EVENT_GPT11_CMPF = (220), // GPT11 GTCCRF compare match
ELC_EVENT_GPT11_OVF = (221), // GPT11 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT11_UDF = (222), // GPT11 GTCNT underflow
ELC_EVENT_GPT11_DTE = (223), // GPT11 Dead time error
ELC_EVENT_GPT12_CCMPA = (224), // GPT12 GTCCRA input capture/compare match
ELC_EVENT_GPT12_CCMPB = (225), // GPT12 GTCCRB input capture/compare match
ELC_EVENT_GPT12_CMPC = (226), // GPT12 GTCCRC compare match
ELC_EVENT_GPT12_CMPD = (227), // GPT12 GTCCRD compare match
ELC_EVENT_GPT12_CMPE = (228), // GPT12 GTCCRE compare match
ELC_EVENT_GPT12_CMPF = (229), // GPT12 GTCCRF compare match
ELC_EVENT_GPT12_OVF = (230), // GPT12 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT12_UDF = (231), // GPT12 GTCNT underflow
ELC_EVENT_GPT12_DTE = (232), // GPT12 Dead time error
ELC_EVENT_GPT13_CCMPA = (233), // GPT13 GTCCRA input capture/compare match
ELC_EVENT_GPT13_CCMPB = (234), // GPT13 GTCCRB input capture/compare match
ELC_EVENT_GPT13_CMPC = (235), // GPT13 GTCCRC compare match
ELC_EVENT_GPT13_CMPD = (236), // GPT13 GTCCRD compare match
ELC_EVENT_GPT13_CMPE = (237), // GPT13 GTCCRE compare match
ELC_EVENT_GPT13_CMPF = (238), // GPT13 GTCCRF compare match
ELC_EVENT_GPT13_OVF = (239), // GPT13 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT13_UDF = (240), // GPT13 GTCNT underflow
ELC_EVENT_GPT13_DTE = (241), // GPT13 Dead time error
ELC_EVENT_POEG0_GROUP0 = (242), // POEG group A interrupt for channels in LLPP
ELC_EVENT_POEG0_GROUP1 = (243), // POEG group B interrupt for channels in LLPP
ELC_EVENT_POEG0_GROUP2 = (244), // POEG group C interrupt for channels in LLPP
ELC_EVENT_POEG0_GROUP3 = (245), // POEG group D interrupt for channels in LLPP
ELC_EVENT_POEG1_GROUP0 = (246), // POEG group A interrupt for channels in NONSAFETY
ELC_EVENT_POEG1_GROUP1 = (247), // POEG group B interrupt for channels in NONSAFETY
ELC_EVENT_POEG1_GROUP2 = (248), // POEG group C interrupt for channels in NONSAFETY
ELC_EVENT_POEG1_GROUP3 = (249), // POEG group D interrupt for channels in NONSAFETY
ELC_EVENT_GMAC_LPI = (250), // GMAC1 energy efficient
ELC_EVENT_GMAC_PMT = (251), // GMAC1 power management
ELC_EVENT_GMAC_SBD = (252), // GMAC1 general interrupt
ELC_EVENT_ETHSW_INTR = (253), // Ethernet Switch interrupt
ELC_EVENT_ETHSW_DLR = (254), // Ethernet Switch DLR interrupt
ELC_EVENT_ETHSW_PRP = (255), // Ethernet Switch PRP interrupt
ELC_EVENT_ETHSW_IHUB = (256), // Ethernet Switch Integrated Hub interrupt
ELC_EVENT_ETHSW_PTRN0 = (257), // Ethernet Switch RX Pattern Matcher interrupt 0
ELC_EVENT_ETHSW_PTRN1 = (258), // Ethernet Switch RX Pattern Matcher interrupt 1
ELC_EVENT_ETHSW_PTRN2 = (259), // Ethernet Switch RX Pattern Matcher interrupt 2
ELC_EVENT_ETHSW_PTRN3 = (260), // Ethernet Switch RX Pattern Matcher interrupt 3
ELC_EVENT_ETHSW_PTRN4 = (261), // Ethernet Switch RX Pattern Matcher interrupt 4
ELC_EVENT_ETHSW_PTRN5 = (262), // Ethernet Switch RX Pattern Matcher interrupt 5
ELC_EVENT_ETHSW_PTRN6 = (263), // Ethernet Switch RX Pattern Matcher interrupt 6
ELC_EVENT_ETHSW_PTRN7 = (264), // Ethernet Switch RX Pattern Matcher interrupt 7
ELC_EVENT_ETHSW_PTRN8 = (265), // Ethernet Switch RX Pattern Matcher interrupt 8
ELC_EVENT_ETHSW_PTRN9 = (266), // Ethernet Switch RX Pattern Matcher interrupt 9
ELC_EVENT_ETHSW_PTRN10 = (267), // Ethernet Switch RX Pattern Matcher interrupt 10
ELC_EVENT_ETHSW_PTRN11 = (268), // Ethernet Switch RX Pattern Matcher interrupt 11
ELC_EVENT_ETHSW_PTPOUT0 = (269), // Ethernet switch timer pulse output 0
ELC_EVENT_ETHSW_PTPOUT1 = (270), // Ethernet switch timer pulse output 1
ELC_EVENT_ETHSW_PTPOUT2 = (271), // Ethernet switch timer pulse output 2
ELC_EVENT_ETHSW_PTPOUT3 = (272), // Ethernet switch timer pulse output 3
ELC_EVENT_ETHSW_TDMAOUT0 = (273), // Ethernet Switch TDMA timer output 0
ELC_EVENT_ETHSW_TDMAOUT1 = (274), // Ethernet Switch TDMA timer output 1
ELC_EVENT_ETHSW_TDMAOUT2 = (275), // Ethernet Switch TDMA timer output 2
ELC_EVENT_ETHSW_TDMAOUT3 = (276), // Ethernet Switch TDMA timer output 3
ELC_EVENT_ESC_SYNC0 = (277), // EtherCAT Sync0 interrupt
ELC_EVENT_ESC_SYNC1 = (278), // EtherCAT Sync1 interrupt
ELC_EVENT_ESC_CAT = (279), // EtherCAT interrupt
ELC_EVENT_ESC_SOF = (280), // EtherCAT SOF interrupt
ELC_EVENT_ESC_EOF = (281), // EtherCAT EOF interrupt
ELC_EVENT_ESC_WDT = (282), // EtherCAT WDT interrupt
ELC_EVENT_ESC_RST = (283), // EtherCAT RESET interrupt
ELC_EVENT_USB_HI = (284), // USB (Host) interrupt
ELC_EVENT_USB_FI = (285), // USB (Function) interrupt
ELC_EVENT_USB_FDMA0 = (286), // USB (Function) DMA 0 transmit completion
ELC_EVENT_USB_FDMA1 = (287), // USB (Function) DMA 1 transmit completion
ELC_EVENT_SCI0_ERI = (288), // SCI0 Receive error
ELC_EVENT_SCI0_RXI = (289), // SCI0 Receive data full
ELC_EVENT_SCI0_TXI = (290), // SCI0 Transmit data empty
ELC_EVENT_SCI0_TEI = (291), // SCI0 Transmit end
ELC_EVENT_SCI1_ERI = (292), // SCI1 Receive error
ELC_EVENT_SCI1_RXI = (293), // SCI1 Receive data full
ELC_EVENT_SCI1_TXI = (294), // SCI1 Transmit data empty
ELC_EVENT_SCI1_TEI = (295), // SCI1 Transmit end
ELC_EVENT_SCI2_ERI = (296), // SCI2 Receive error
ELC_EVENT_SCI2_RXI = (297), // SCI2 Receive data full
ELC_EVENT_SCI2_TXI = (298), // SCI2 Transmit data empty
ELC_EVENT_SCI2_TEI = (299), // SCI2 Transmit end
ELC_EVENT_SCI3_ERI = (300), // SCI3 Receive error
ELC_EVENT_SCI3_RXI = (301), // SCI3 Receive data full
ELC_EVENT_SCI3_TXI = (302), // SCI3 Transmit data empty
ELC_EVENT_SCI3_TEI = (303), // SCI3 Transmit end
ELC_EVENT_SCI4_ERI = (304), // SCI4 Receive error
ELC_EVENT_SCI4_RXI = (305), // SCI4 Receive data full
ELC_EVENT_SCI4_TXI = (306), // SCI4 Transmit data empty
ELC_EVENT_SCI4_TEI = (307), // SCI4 Transmit end
ELC_EVENT_IIC0_EEI = (308), // IIC0 Transfer error or event generation
ELC_EVENT_IIC0_RXI = (309), // IIC0 Receive data full
ELC_EVENT_IIC0_TXI = (310), // IIC0 Transmit data empty
ELC_EVENT_IIC0_TEI = (311), // IIC0 Transmit end
ELC_EVENT_IIC1_EEI = (312), // IIC1 Transfer error or event generation
ELC_EVENT_IIC1_RXI = (313), // IIC1 Receive data full
ELC_EVENT_IIC1_TXI = (314), // IIC1 Transmit data empty
ELC_EVENT_IIC1_TEI = (315), // IIC1 Transmit end
ELC_EVENT_CAN_RXF = (316), // CANFD RX FIFO interrupt
ELC_EVENT_CAN_GLERR = (317), // CANFD Global error interrupt
ELC_EVENT_CAN0_TX = (318), // CAFND0 Channel TX interrupt
ELC_EVENT_CAN0_CHERR = (319), // CAFND0 Channel CAN error interrupt
ELC_EVENT_CAN0_COMFRX = (320), // CAFND0 Common RX FIFO or TXQ interrupt
ELC_EVENT_CAN1_TX = (321), // CAFND1 Channel TX interrupt
ELC_EVENT_CAN1_CHERR = (322), // CAFND1 Channel CAN error interrupt
ELC_EVENT_CAN1_COMFRX = (323), // CAFND1 Common RX FIFO or TXQ interrupt
ELC_EVENT_SPI0_SPRI = (324), // SPI0 Reception buffer full
ELC_EVENT_SPI0_SPTI = (325), // SPI0 Transmit buffer empty
ELC_EVENT_SPI0_SPII = (326), // SPI0 SPI idle
ELC_EVENT_SPI0_SPEI = (327), // SPI0 errors
ELC_EVENT_SPI0_SPCEND = (328), // SPI0 Communication complete
ELC_EVENT_SPI1_SPRI = (329), // SPI1 Reception buffer full
ELC_EVENT_SPI1_SPTI = (330), // SPI1 Transmit buffer empty
ELC_EVENT_SPI1_SPII = (331), // SPI1 SPI idle
ELC_EVENT_SPI1_SPEI = (332), // SPI1 errors
ELC_EVENT_SPI1_SPCEND = (333), // SPI1 Communication complete
ELC_EVENT_SPI2_SPRI = (334), // SPI2 Reception buffer full
ELC_EVENT_SPI2_SPTI = (335), // SPI2 Transmit buffer empty
ELC_EVENT_SPI2_SPII = (336), // SPI2 SPI idle
ELC_EVENT_SPI2_SPEI = (337), // SPI2 errors
ELC_EVENT_SPI2_SPCEND = (338), // SPI2 Communication complete
ELC_EVENT_XSPI0_INT = (339), // xSPI0 Interrupt
ELC_EVENT_XSPI0_INTERR = (340), // xSPI0 Error interrupt
ELC_EVENT_XSPI1_INT = (341), // xSPI1 Interrupt
ELC_EVENT_XSPI1_INTERR = (342), // xSPI1 Error interrupt
ELC_EVENT_DSMIF0_CDRUI = (343), // DSMIF0 current data register update (ORed ch0 to ch2)
ELC_EVENT_DSMIF1_CDRUI = (344), // DSMIF1 current data register update (ORed ch3 to ch5)
ELC_EVENT_ADC0_ADI = (345), // ADC0 A/D scan end interrupt
ELC_EVENT_ADC0_GBADI = (346), // ADC0 A/D scan end interrupt for Group B
ELC_EVENT_ADC0_GCADI = (347), // ADC0 A/D scan end interrupt for Group C
ELC_EVENT_ADC0_CMPAI = (348), // ADC0 Window A compare match
ELC_EVENT_ADC0_CMPBI = (349), // ADC0 Window B compare match
ELC_EVENT_ADC1_ADI = (350), // ADC1 A/D scan end interrupt
ELC_EVENT_ADC1_GBADI = (351), // ADC1 A/D scan end interrupt for Group B
ELC_EVENT_ADC1_GCADI = (352), // ADC1 A/D scan end interrupt for Group C
ELC_EVENT_ADC1_CMPAI = (353), // ADC1 Window A compare match
ELC_EVENT_ADC1_CMPBI = (354), // ADC1 Window B compare match
ELC_EVENT_MBX_INT0 = (372), // Mailbox (Host CPU to Cortex-R52) interrupt 0
ELC_EVENT_MBX_INT1 = (373), // Mailbox (Host CPU to Cortex-R52) interrupt 1
ELC_EVENT_MBX_INT2 = (374), // Mailbox (Host CPU to Cortex-R52) interrupt 2
ELC_EVENT_MBX_INT3 = (375), // Mailbox (Host CPU to Cortex-R52) interrupt 3
ELC_EVENT_CPU0_ERR0 = (384), // Cortex-R52 CPU0 error event 0
ELC_EVENT_CPU0_ERR1 = (385), // Cortex-R52 CPU0 error event 1
ELC_EVENT_PERI_ERR0 = (388), // Peripherals error event 0
ELC_EVENT_PERI_ERR1 = (389), // Peripherals error event 1
ELC_EVENT_SHOST_INT = (390), // SHOSTIF interrupt
ELC_EVENT_PHOST_INT = (391), // PHOSTIF interrupt
ELC_EVENT_INTCPU6 = (392), // Software interrupt 6
ELC_EVENT_INTCPU7 = (393), // Software interrupt 7
ELC_EVENT_IRQ14 = (394), // External pin interrupt 14
ELC_EVENT_IRQ15 = (395), // External pin interrupt 15
ELC_EVENT_GPT14_CCMPA = (396), // GPT14 GTCCRA input capture/compare match
ELC_EVENT_GPT14_CCMPB = (397), // GPT14 GTCCRB input capture/compare match
ELC_EVENT_GPT14_CMPC = (398), // GPT14 GTCCRC compare match
ELC_EVENT_GPT14_CMPD = (399), // GPT14 GTCCRD compare match
ELC_EVENT_GPT14_CMPE = (400), // GPT14 GTCCRE compare match
ELC_EVENT_GPT14_CMPF = (401), // GPT14 GTCCRF compare match
ELC_EVENT_GPT14_OVF = (402), // GPT14 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT14_UDF = (403), // GPT14 GTCNT underflow
ELC_EVENT_GPT15_CCMPA = (404), // GPT15 GTCCRA input capture/compare match
ELC_EVENT_GPT15_CCMPB = (405), // GPT15 GTCCRB input capture/compare match
ELC_EVENT_GPT15_CMPC = (406), // GPT15 GTCCRC compare match
ELC_EVENT_GPT15_CMPD = (407), // GPT15 GTCCRD compare match
ELC_EVENT_GPT15_CMPE = (408), // GPT15 GTCCRE compare match
ELC_EVENT_GPT15_CMPF = (409), // GPT15 GTCCRF compare match
ELC_EVENT_GPT15_OVF = (410), // GPT15 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT15_UDF = (411), // GPT15 GTCNT underflow
ELC_EVENT_GPT16_CCMPA = (412), // GPT16 GTCCRA input capture/compare match
ELC_EVENT_GPT16_CCMPB = (413), // GPT16 GTCCRB input capture/compare match
ELC_EVENT_GPT16_CMPC = (414), // GPT16 GTCCRC compare match
ELC_EVENT_GPT16_CMPD = (415), // GPT16 GTCCRD compare match
ELC_EVENT_GPT16_CMPE = (416), // GPT16 GTCCRE compare match
ELC_EVENT_GPT16_CMPF = (417), // GPT16 GTCCRF compare match
ELC_EVENT_GPT16_OVF = (418), // GPT16 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT16_UDF = (419), // GPT16 GTCNT underflow
ELC_EVENT_GPT17_CCMPA = (420), // GPT17 GTCCRA input capture/compare match
ELC_EVENT_GPT17_CCMPB = (421), // GPT17 GTCCRB input capture/compare match
ELC_EVENT_GPT17_CMPC = (422), // GPT17 GTCCRC compare match
ELC_EVENT_GPT17_CMPD = (423), // GPT17 GTCCRD compare match
ELC_EVENT_GPT17_CMPE = (424), // GPT17 GTCCRE compare match
ELC_EVENT_GPT17_CMPF = (425), // GPT17 GTCCRF compare match
ELC_EVENT_GPT17_OVF = (426), // GPT17 GTCNT overflow (GTPR compare match)
ELC_EVENT_GPT17_UDF = (427), // GPT17 GTCNT underflow
ELC_EVENT_POEG2_GROUP0 = (428), // POEG group A interrupt for channels in SAFETY
ELC_EVENT_POEG2_GROUP1 = (429), // POEG group B interrupt for channels in SAFETY
ELC_EVENT_POEG2_GROUP2 = (430), // POEG group C interrupt for channels in SAFETY
ELC_EVENT_POEG2_GROUP3 = (431), // POEG group D interrupt for channels in SAFETY
ELC_EVENT_RTC_ALM = (432), // Alarm interrupt
ELC_EVENT_RTC_1S = (433), // 1 second interrupt
ELC_EVENT_RTC_PRD = (434), // Fixed interval interrupt
ELC_EVENT_SCI5_ERI = (435), // SCI5 Receive error
ELC_EVENT_SCI5_RXI = (436), // SCI5 Receive data full
ELC_EVENT_SCI5_TXI = (437), // SCI5 Transmit data empty
ELC_EVENT_SCI5_TEI = (438), // SCI5 Transmit end
ELC_EVENT_IIC2_EEI = (439), // IIC2 Transfer error or event generation
ELC_EVENT_IIC2_RXI = (440), // IIC2 Receive data full
ELC_EVENT_IIC2_TXI = (441), // IIC2 Transmit data empty
ELC_EVENT_IIC2_TEI = (442), // IIC2 Transmit end
ELC_EVENT_SPI3_SPRI = (443), // SPI3 Reception buffer full
ELC_EVENT_SPI3_SPTI = (444), // SPI3 Transmit buffer empty
ELC_EVENT_SPI3_SPII = (445), // SPI3 SPI idle
ELC_EVENT_SPI3_SPEI = (446), // SPI3 errors
ELC_EVENT_SPI3_SPCEND = (447), // SPI3 Communication complete
ELC_EVENT_DREQ = (448), // External DMA request
ELC_EVENT_CAN_RF_DMAREQ0 = (449), // CAFND RX FIFO 0 DMA request
ELC_EVENT_CAN_RF_DMAREQ1 = (450), // CAFND RX FIFO 1 DMA request
ELC_EVENT_CAN_RF_DMAREQ2 = (451), // CAFND RX FIFO 2 DMA request
ELC_EVENT_CAN_RF_DMAREQ3 = (452), // CAFND RX FIFO 3 DMA request
ELC_EVENT_CAN_RF_DMAREQ4 = (453), // CAFND RX FIFO 4 DMA request
ELC_EVENT_CAN_RF_DMAREQ5 = (454), // CAFND RX FIFO 5 DMA request
ELC_EVENT_CAN_RF_DMAREQ6 = (455), // CAFND RX FIFO 6 DMA request
ELC_EVENT_CAN_RF_DMAREQ7 = (456), // CAFND RX FIFO 7 DMA request
ELC_EVENT_CAN0_CF_DMAREQ = (457), // CAFND0 First common FIFO DMA request
ELC_EVENT_CAN1_CF_DMAREQ = (458), // CAFND1 First common FIFO DMA request
ELC_EVENT_ADC0_WCMPM = (459), // ADC0 compare match
ELC_EVENT_ADC0_WCMPUM = (460), // ADC0 compare mismatch
ELC_EVENT_ADC1_WCMPM = (461), // ADC1 compare match
ELC_EVENT_ADC1_WCMPUM = (462), // ADC1 compare mismatch
ELC_EVENT_TCIV4_OF = (463), // MTU4.TCNT overflow
ELC_EVENT_TCIV4_UF = (464), // MTU4.TCNT underflow
ELC_EVENT_TCIV7_OF = (465), // MTU7.TCNT overflow
ELC_EVENT_TCIV7_UF = (466), // MTU7.TCNT underflow
ELC_EVENT_IOPORT_GROUP1 = (467), // Input edge detection of input port group 1
ELC_EVENT_IOPORT_GROUP2 = (468), // Input edge detection of input port group 2
ELC_EVENT_IOPORT_SINGLE0 = (469), // Input edge detection of single input port 0
ELC_EVENT_IOPORT_SINGLE1 = (470), // Input edge detection of single input port 1
ELC_EVENT_IOPORT_SINGLE2 = (471), // Input edge detection of single input port 2
ELC_EVENT_IOPORT_SINGLE3 = (472), // Input edge detection of single input port 3
ELC_EVENT_GPT0_ADTRGA = (473), // GPT0 GTADTRA compare match
ELC_EVENT_GPT0_ADTRGB = (474), // GPT0 GTADTRB compare match
ELC_EVENT_GPT1_ADTRGA = (475), // GPT1 GTADTRA compare match
ELC_EVENT_GPT1_ADTRGB = (476), // GPT1 GTADTRB compare match
ELC_EVENT_GPT2_ADTRGA = (477), // GPT2 GTADTRA compare match
ELC_EVENT_GPT2_ADTRGB = (478), // GPT2 GTADTRB compare match
ELC_EVENT_GPT3_ADTRGA = (479), // GPT3 GTADTRA compare match
ELC_EVENT_GPT3_ADTRGB = (480), // GPT3 GTADTRB compare match
ELC_EVENT_GPT4_ADTRGA = (481), // GPT4 GTADTRA compare match
ELC_EVENT_GPT4_ADTRGB = (482), // GPT4 GTADTRB compare match
ELC_EVENT_GPT5_ADTRGA = (483), // GPT5 GTADTRA compare match
ELC_EVENT_GPT5_ADTRGB = (484), // GPT5 GTADTRB compare match
ELC_EVENT_GPT6_ADTRGA = (485), // GPT6 GTADTRA compare match
ELC_EVENT_GPT6_ADTRGB = (486), // GPT6 GTADTRB compare match
ELC_EVENT_GPT7_ADTRGA = (487), // GPT7 GTADTRA compare match
ELC_EVENT_GPT7_ADTRGB = (488), // GPT7 GTADTRB compare match
ELC_EVENT_GPT8_ADTRGA = (489), // GPT8 GTADTRA compare match
ELC_EVENT_GPT8_ADTRGB = (490), // GPT8 GTADTRB compare match
ELC_EVENT_GPT9_ADTRGA = (491), // GPT9 GTADTRA compare match
ELC_EVENT_GPT9_ADTRGB = (492), // GPT9 GTADTRB compare match
ELC_EVENT_GPT10_ADTRGA = (493), // GPT10 GTADTRA compare match
ELC_EVENT_GPT10_ADTRGB = (494), // GPT10 GTADTRB compare match
ELC_EVENT_GPT11_ADTRGA = (495), // GPT11 GTADTRA compare match
ELC_EVENT_GPT11_ADTRGB = (496), // GPT11 GTADTRB compare match
ELC_EVENT_GPT12_ADTRGA = (497), // GPT12 GTADTRA compare match
ELC_EVENT_GPT12_ADTRGB = (498), // GPT12 GTADTRB compare match
ELC_EVENT_GPT13_ADTRGA = (499), // GPT13 GTADTRA compare match
ELC_EVENT_GPT13_ADTRGB = (500), // GPT13 GTADTRB compare match
ELC_EVENT_NONE
} elc_event_t;
/** @} (end addtogroup BSP_MCU_RZN2L) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_FEATURE_H
#define BSP_FEATURE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKADC)
#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
#define BSP_FEATURE_ADC_HAS_PGA (1U)
#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U)
#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
#define BSP_FEATURE_ADC_REGISTER_MASK_TYPE (1U)
#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU)
#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_SLOPE (4000U)
#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x000F) // 0 to 3 in unit 0
#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x00FF) // 0 to 7 in unit 1
#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
#define BSP_FEATURE_BSP_IRQ_PRIORITY_MASK (0xF8U)
#define BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT (3U)
#define BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED (1U)
#define BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED (1U)
#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
#define BSP_FEATURE_CAN_CLOCK (0U)
#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
#define BSP_FEATURE_CAN_NUM_CHANNELS (2U)
#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U)
#define BSP_FEATURE_CGC_HAS_BCLK (1U)
#define BSP_FEATURE_CGC_HAS_FCLK (1U)
#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
#define BSP_FEATURE_CGC_HAS_FLWT (1U)
#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U)
#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
#define BSP_FEATURE_CGC_HAS_PLL (1U)
#define BSP_FEATURE_CGC_HAS_PLL2 (0U)
#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U)
#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
#define BSP_FEATURE_CGC_LOCO_CONTROL_ADDRESS (0x81280070U)
#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
#define BSP_FEATURE_CGC_PLL1_CONTROL_ADDRESS (0x81280050U)
#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U)
#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U)
#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U)
#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0U)
#define BSP_FEATURE_CMT_VALID_CHANNEL_MASK (0x3FU)
#define BSP_FEATURE_CMTW_VALID_CHANNEL_MASK (0x3U)
#define BSP_FEATURE_CRC_VALID_CHANNEL_MASK (0x3U)
#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
#define BSP_FEATURE_DMAC_MAX_UNIT (2U)
#define BSP_FEATURE_DMAC_UNIT0_ERROR_NUM (5U)
#define BSP_FEATURE_DSMIF_CHANNEL_STATUS (1U)
#define BSP_FEATURE_DSMIF_DATA_FORMAT_SEL (0U)
#define BSP_FEATURE_DSMIF_ERROR_STATUS_CLR (5U)
#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_CONTROL (1U)
#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_ISR (1U)
#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_NOTIFY (0U)
#define BSP_FEATURE_DSMIF_OVERCURRENT_ERROR_STATUS (1U)
#define BSP_FEATURE_DSMIF_OVERCURRENT_NOTIFY_STATUS (0U)
#define BSP_FEATURE_ELC_ELC_SSEL_NUM (19)
#define BSP_FEATURE_ELC_EVENT_MASK_NUM (4U)
#define BSP_FEATURE_ELC_PERIPHERAL_0_MASK (0xFFFFFFFFU) // ELC event source no.0 to 31 available on this MCU
#define BSP_FEATURE_ELC_PERIPHERAL_1_MASK (0x007FF9FFU) // ELC event source no.32 to 63 available on this MCU.
#define BSP_FEATURE_ELC_PERIPHERAL_2_MASK (0x00000000U) // ELC event source no.64 to 95 available on this MCU.
#define BSP_FEATURE_ELC_PERIPHERAL_3_MASK (0x00000000U) // ELC event source no.96 to 127 available on this MCU.
#define BSP_FEATURE_ELC_PERIPHERAL_TYPE (1U)
#define BSP_FEATURE_ESC_MAX_PORTS (3U)
#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
#define BSP_FEATURE_ETHER_PHY_MAX_CHANNELS (3U)
#define BSP_FEATURE_ETHSS_MAX_PORTS (3U)
#define BSP_FEATURE_ETHSS_SWITCH_MODE_BIT_MASK (3U)
#define BSP_FEATURE_ETHSW_MAX_CHANNELS (1U)
#define BSP_FEATURE_ETHSW_SUPPORTED (1U)
#define BSP_FEATURE_GMAC_MAX_CHANNELS (1U)
#define BSP_FEATURE_GMAC_MAX_PORTS (3U)
#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFF)
#define BSP_FEATURE_GPT_LLPP_BASE_CHANNEL (0) // LLPP channel: ch0-6
#define BSP_FEATURE_GPT_LLPP_CHANNEL_MASK (0x0007F)
#define BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL (7) // Non-safety channel: ch7-13
#define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_MASK (0x0007F)
#define BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL (14) // safety channel: ch14-17
#define BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK (0x0000F)
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFF)
#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0)
#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF)
#define BSP_FEATURE_ICU_ERROR_PERI_ERR_REG_NUM (2U)
#define BSP_FEATURE_ICU_ERROR_PERI_ERR0_REG_MASK (0xFFFFFEFFU)
#define BSP_FEATURE_ICU_ERROR_PERI_ERR1_REG_MASK (0x19FFA3FFU)
#define BSP_FEATURE_ICU_ERROR_PERIPHERAL_TYPE (1U)
#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU)
#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U)
#define BSP_FEATURE_IIC_SAFETY_CHANNEL (2U)
#define BSP_FEATURE_IIC_SAFETY_CHANNEL_BASE_ADDRESS (R_IIC2_BASE)
#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07)
#define BSP_FEATURE_IOPORT_ELC_PORTS (4U)
#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, {2, 5}}
#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U)
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U)
#define BSP_FEATURE_LPM_HAS_STCONR (1U)
#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U)
#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU)
#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU)
#define BSP_FEATURE_MTU3_MAX_CHANNELS (9U)
#define BSP_FEATURE_MTU3_UVW_MAX_CHANNELS (3U)
#define BSP_FEATURE_MTU3_VALID_CHANNEL_MASK (0x01FF)
#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U)
#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U)
#define BSP_FEATURE_POE3_ERROR_SIGNAL_TYPE (1U)
#define BSP_FEATURE_POE3_PIN_SELECT_TYPE (1U)
#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
#define BSP_FEATURE_POEG_ERROR_SIGNAL_TYPE (1U)
#define BSP_FEATURE_POEG_GROUP_OFSSET_ADDRESS (0x400)
#define BSP_FEATURE_POEG_LLPP_UNIT (0U)
#define BSP_FEATURE_POEG_MAX_UNIT (2U)
#define BSP_FEATURE_POEG_NONSAFETY_UNIT (1U)
#define BSP_FEATURE_POEG_SAFETY_UNIT (2U)
#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS)
#define BSP_FEATURE_SCI_CHANNELS (0x3FU)
#define BSP_FEATURE_SCI_SAFETY_CHANNEL (5U)
#define BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS (R_SCI5_BASE)
#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03FU)
#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU)
#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
#define BSP_FEATURE_SEM_SUPPORTED (0U)
#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U)
#define BSP_FEATURE_SPI_HAS_SPCR3 (0U)
#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
#define BSP_FEATURE_SPI_MAX_CHANNEL (4U)
#define BSP_FEATURE_SPI_SAFETY_CHANNEL (3U)
#define BSP_FEATURE_SPI_SAFETY_CHANNEL_BASE_ADDRESS (R_SPI3_BASE)
#define BSP_FEATURE_TFU_SUPPORTED (1U)
#define BSP_FEATURE_XSPI_CHANNELS (0x03U)
#define BSP_FEATURE_XSPI_NUM_CHIP_SELECT (2U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU_RZN2L
* @{
**********************************************************************************************************************/
/** Array of GICD_ICFGR initialization value. */
const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX] =
{
0xAAAAAAAAUL, /* Event No. 0 to 15 */
0x000000AAUL, /* Event No. 16 to 31 */
0x00000000UL, /* Event No. 32 to 47 */
0xAAAAA800UL, /* Event No. 48 to 63 */
0xAAAAAAAAUL, /* Event No. 64 to 79 */
0xAAAAAAAAUL, /* Event No. 80 to 95 */
0xAAAAAAAAUL, /* Event No. 96 to 111 */
0xAAAAAA00UL, /* Event No. 112 to 127 */
0xAAAAAAAAUL, /* Event No. 128 to 143 */
0xAAAAAAAAUL, /* Event No. 144 to 159 */
0xAAAAAAAAUL, /* Event No. 160 to 175 */
0xAAAAAAAAUL, /* Event No. 176 to 191 */
0xAAAAAAAAUL, /* Event No. 192 to 207 */
0xAAAAAAAAUL, /* Event No. 208 to 223 */
0xAAAAAAAAUL, /* Event No. 224 to 239 */
0x0000000AUL, /* Event No. 240 to 255 */
0xA8000000UL, /* Event No. 256 to 271 */
0xA82A2AAAUL, /* Event No. 272 to 287 */
0x28282828UL, /* Event No. 288 to 303 */
0x00282828UL, /* Event No. 304 to 319 */
0xA82A0A00UL, /* Event No. 320 to 335 */
0xA0AA8020UL, /* Event No. 336 to 351 */
0x00000002UL, /* Event No. 352 to 367 */
0x00000000UL, /* Event No. 368 to 383 */
0xAAAA0A0AUL, /* Event No. 384 to 399 */
0xAAAAAAAAUL, /* Event No. 400 to 415 */
0x00AAAAAAUL, /* Event No. 416 to 431 */
0x828A0A2AUL, /* Event No. 432 to 447 */
};
const uint32_t BSP_GICR_SGI_PPI_ICFGR_INIT[BSP_EVENT_SGI_PPI_ARRAY_NUM] =
{
0xAAAAAAAAUL, /* event SGI */
0x00020000UL, /* event PPI */
};
/** @} (end addtogroup BSP_MCU_RZN2L) */
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if !(BSP_CFG_RAM_EXECUTION)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_LOADER_PARAM_MAX (19)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* Parameter Information for the Loader. */
BSP_DONT_REMOVE const uint32_t g_bsp_loader_param[BSP_LOADER_PARAM_MAX] BSP_PLACE_IN_SECTION(BSP_SECTION_LOADER_PARAM) =
{
BSP_CFG_CACHE_FLG,
BSP_CFG_CS0BCR_V_WRAPCFG_V,
BSP_CFG_CS0WCR_V_COMCFG_V,
BSP_CFG_DUMMY0_BMCFG_V,
BSP_CFG_BSC_FLG_xSPI_FLG,
BSP_CFG_LDR_ADDR_NML,
BSP_CFG_LDR_SIZE_NML,
BSP_CFG_DEST_ADDR_NML,
BSP_CFG_DUMMY1,
BSP_CFG_DUMMY2,
BSP_CFG_DUMMY3_CSSCTL_V,
BSP_CFG_DUMMY4_LIOCFGCS0_V,
BSP_CFG_DUMMY5,
BSP_CFG_DUMMY6,
BSP_CFG_DUMMY7,
BSP_CFG_DUMMY8,
BSP_CFG_DUMMY9,
BSP_CFG_DUMMY10_ACCESS_SPEED,
BSP_CFG_CHECK_SUM
};
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BSP_MCU
* @defgroup BSP_MCU_RZN2L RZN2L
* @includedoc config_bsp_rzn2l_fsp.html
* @{
**********************************************************************************************************************/
/** @} (end defgroup BSP_MCU_RZN2L) */
#ifndef BSP_MCU_INFO_H
#define BSP_MCU_INFO_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP MCU Specific Includes. */
#include "bsp_elc.h"
#include "bsp_feature.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
typedef elc_event_t bsp_interrupt_event_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "r_ioport_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* "PORT" in ASCII, used to determine if the module is open */
#define IOPORT_OPEN (0x504F5254U)
#define IOPORT_CLOSED (0x00000000U)
/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
#define IOPORT_PRV_PORT_OFFSET (8U)
#define IOPORT_PRV_PORT_BITS (0xFF00U)
#define IOPORT_PRV_PIN_BITS (0x00FFU)
#define IOPORT_PRV_8BIT_MASK (0x00FFU)
/* Added definitions */
#define IOPORT_PIN_NUM_MUX (8U)
#define IOPORT_REGION_SEL_SAFE (0U)
#define IOPORT_REGION_SEL_NSAFE (1U)
#define IOPORT_RSEL_MASK (0x01U)
#define IOPORT_PM_BIT_MASK (0x0003U)
#define IOPORT_PFC_BIT_MASK (0x0000000FU)
#define IOPORT_DRTCL_BIT_MASK (0x000000FFU)
#define IOPORT_ELC_PEL_MASK (0x80)
#define IOOPRT_ELC_PGC_MASK (0x88)
#define IOPORT_ELC_PEL_PSM_HIGH (0x20)
/* Switch IOPORT register region either safety or non safety */
#define IOPORT_PRV_PORT_ADDRESS(region_sel) (region_sel == 1 ? (R_PORT_NSR) : (R_PORT_SR))
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
typedef struct st_ioport_cfg_data
{
uint32_t p_reg : 1;
uint32_t pm_reg : 2;
uint32_t pmc_reg : 1;
uint32_t pfc_reg : 4;
uint32_t drct_reg : 6;
uint32_t rsel_reg : 1;
uint32_t reserved : 17;
} ioport_cfg_data_t;
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
static void r_ioport_pins_config(const ioport_cfg_t * p_cfg);
static void r_ioport_pin_set(bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data);
static void r_ioport_event_config(const ioport_extend_cfg_t * p_extend_cfg_data);
/***********************************************************************************************************************
* Private global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Global Variables
**********************************************************************************************************************/
/* IOPort Implementation of IOPort Driver */
const ioport_api_t g_ioport_on_ioport =
{
.open = R_IOPORT_Open,
.close = R_IOPORT_Close,
.pinsCfg = R_IOPORT_PinsCfg,
.pinCfg = R_IOPORT_PinCfg,
.pinEventInputRead = R_IOPORT_PinEventInputRead,
.pinEventOutputWrite = R_IOPORT_PinEventOutputWrite,
.pinRead = R_IOPORT_PinRead,
.pinWrite = R_IOPORT_PinWrite,
.portDirectionSet = R_IOPORT_PortDirectionSet,
.portEventInputRead = R_IOPORT_PortEventInputRead,
.portEventOutputWrite = R_IOPORT_PortEventOutputWrite,
.portRead = R_IOPORT_PortRead,
.portWrite = R_IOPORT_PortWrite,
};
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Initializes internal driver data, then calls pin configuration function to configure pins.
*
* @retval FSP_SUCCESS Pin configuration data written to the multiple registers
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_ALREADY_OPEN Module is already open.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
{
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ASSERT(NULL != p_cfg);
FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
#endif
/* Set driver status to open */
p_instance_ctrl->open = IOPORT_OPEN;
p_instance_ctrl->p_cfg = p_cfg;
r_ioport_pins_config(p_cfg);
r_ioport_event_config(p_cfg->p_extend);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Resets IOPORT registers. Implements @ref ioport_api_t::close
*
* @retval FSP_SUCCESS The IOPORT was successfully uninitialized
* @retval FSP_ERR_ASSERTION p_ctrl was NULL
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl)
{
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Set state to closed */
p_instance_ctrl->open = IOPORT_CLOSED;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Configures the functions of multiple pins by loading configuration data into the multiple registers.
* Implements @ref ioport_api_t::pinsCfg.
*
* This function initializes the supplied list of the multiple registers with the supplied values. This data can be generated
* by the Pins tab of the RZ/N2L Configuration editor or manually by the developer. Different pin configurations can be
* loaded for different situations such as low power modes and testing.
*
* @retval FSP_SUCCESS Pin configuration data written to the multiple registers
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_cfg);
FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
r_ioport_pins_config(p_cfg);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg.
*
* @retval FSP_SUCCESS Pin configured
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different pins.
* This function will change the configuration of the pin with the new configuration. For example it is not possible
* with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To
* achieve this the original settings with the required change will need to be written using this function.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
R_BSP_PinAccessEnable();
r_ioport_pin_set(pin, (ioport_cfg_data_t *) &cfg);
R_BSP_PinAccessDisable();
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the level on a pin. Implements @ref ioport_api_t::pinRead.
*
* The level for the specifed pin will be reterned by PINm register.
*
* @retval FSP_SUCCESS Pin read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
* @note This function is re-entrant for different pins.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_pin_value);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
*p_pin_value = (bsp_io_level_t) R_BSP_FastPinRead(R_BSP_IoRegionGet(pin), pin);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value on an IO port. Implements @ref ioport_api_t::portRead.
*
* The specified port will be read, and the levels for all the pins will be returned by PINm register.
* Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds
* to pin 7, bit 6 to pin 6, and so on.
*
* @retval FSP_SUCCESS Port read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
* @note This function is re-entrant for different ports.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_port_value);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
R_PORT_COMMON_Type * p_ioport_regs;
ioport_size_t safe_value;
ioport_size_t nsafe_value;
/* Get port number */
uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
/* Get the RSELP register value */
ioport_size_t rselp_value = (ioport_size_t) R_PTADR->RSELP[port_num];
/* Get the port register address in non safety region */
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Read the specified port states in non safety region */
nsafe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & rselp_value);
/* Get the port register address in safety region */
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
/* Read the specified port states in safety region */
safe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & ~(rselp_value));
/* Read the specified port states */
*p_port_value = nsafe_value | safe_value;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite.
*
* The output value will be written to the specified port. Each bit in the value parameter corresponds to a bit
* on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
* Each bit in the mask parameter corresponds to a pin on the port.
*
* Only the bits with the corresponding bit in the mask value set will be updated.
* For example, value = 0x00FF, mask = 0x0003 results in only bits 0 and 1 being updated.
*
* @retval FSP_SUCCESS Port written to
* @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointerd
*
* @note This function is re-entrant for different ports. This function makes use of the Pm register to atomically
* modify the levels on the specified pins on a port.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
R_PORT_COMMON_Type * p_ioport_regs;
ioport_size_t temp_value;
ioport_size_t write_mask;
/* mask value: lower word is valid, upper word is invalid */
mask &= IOPORT_PRV_8BIT_MASK;
/* Get port number */
uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
/* Get the RSELP register value */
ioport_size_t rselp_value = R_PTADR->RSELP[port_num];
/* Set value to non safety region register */
write_mask = rselp_value & mask;
if (write_mask)
{
/* Get the port register address */
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Output data store of the specified pins sets to low output */
temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask));
/* Write output data to P register of the specified pins */
p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask));
}
/* Set value to safety region register */
write_mask = (ioport_size_t) ((~rselp_value) & mask);
if (write_mask)
{
/* Get the port register address */
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
/* Output data store of the specified pins sets to low output */
temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask));
/* Write output data to P register of the specified pins */
p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask));
}
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite.
*
* @retval FSP_SUCCESS Pin written to
* @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opene
* @retval FSP_ERR_ASSERTION NULL pointerd
*
* @note This function is re-entrant for different pins. This function makes use of the Pm register to atomically
* modify the level on the specified pin on a port.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
R_PORT_COMMON_Type * p_ioport_regs;
/* Get port and pin number */
uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
/* Get the port register address */
p_ioport_regs = (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) &
IOPORT_RSEL_MASK)));
/* Set output level to P register of the specified pin */
if (BSP_IO_LEVEL_LOW == level)
{
p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num));
}
else
{
p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num);
}
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet().
*
* Multiple pins on a port can be set to inputs or outputs at once.
* Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to
* pin 7, bit 6 to pin 6, and so on. If a mask bit is set to 1 then the corresponding pin will be changed to
* an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of
* the pin will not be changed.
*
* @retval FSP_SUCCESS Port direction updated
* @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different ports.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask)
{
uint32_t pin_num;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask > (uint16_t) 0, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* mask value: lower word is valid, upper word is invalid */
mask &= IOPORT_PRV_8BIT_MASK;
for (pin_num = 0U; pin_num < IOPORT_PIN_NUM_MUX; pin_num++)
{
if (mask & (1U << pin_num))
{
/* Get port number */
uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET;
/* Get the port register address */
R_PORT_COMMON_Type * p_ioport_regs =
IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) &
IOPORT_RSEL_MASK));
/* Set */
uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U)));
/* Set the direction value */
uint16_t temp_value = (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
p_ioport_regs->PM[port_num] = temp_value | set_bits;
}
}
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead().
*
* The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port.
* For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
*
* The port event data is captured in response to a trigger from the ELC. This function enables this data to be read.
* Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
*
* @retval FSP_SUCCESS Port read
* @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data)
{
uint8_t portgroup = 0U;
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_event_data);
FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend;
/* Get register address */
R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Get port group number for the specified port */
if (BSP_IO_PORT_16 == port)
{
portgroup = 0U;
}
else if (BSP_IO_PORT_18 == port)
{
portgroup = 1U;
}
else
{
/* Do Nothing */
}
/* Read current value of buffer value from ELC_PDBF register for the specified port group */
*p_event_data =
(uint16_t) (p_ioport_regs->ELC_PDBF[portgroup].BY & elc_cfg->port_group_input_cfg[portgroup].pin_select);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead.
*
* The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read.
* Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
*
* @retval FSP_SUCCESS Pin read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event)
{
uint8_t portgroup = 0U;
uint8_t portvalue;
uint8_t mask;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_pin_event);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) ||
(port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET),
FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Get port and pin number */
uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin);
uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
/* Get register address */
R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Get port group number for the specified port */
if (BSP_IO_PORT_16 == port_num)
{
portgroup = 0U;
}
else if (BSP_IO_PORT_18 == port_num)
{
portgroup = 1U;
}
else
{
/* Do Nothing */
}
/* Read current value of buffer value from ELC_PDBF register for the specified port group */
portvalue = p_ioport_regs->ELC_PDBF[portgroup].BY;
mask = (uint8_t) (1U << pin_num);
if ((portvalue & mask) == mask)
{
*p_pin_event = BSP_IO_LEVEL_HIGH;
}
else
{
*p_pin_event = BSP_IO_LEVEL_LOW;
}
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* This function writes the set and reset event output data for a port. Implements
* @ref ioport_api_t::portEventOutputWrite.
*
* Using the event system enables a port state to be stored by this function in advance of being output on the port.
* The output to the port will occur when the ELC event occurs.
*
* The input value will be written to the specified port when an ELC event configured for that port occurs.
* Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7,
* bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port.
*
* @retval FSP_SUCCESS Port event data written
* @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value)
{
uint8_t portgroup = 0U;
ioport_size_t temp_value;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
R_BSP_PinAccessEnable(); // Unlock Register Write Protection
/* Get register address */
R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Get port group number for the specified port */
if (BSP_IO_PORT_16 == port)
{
portgroup = 0U;
}
else if (BSP_IO_PORT_18 == port)
{
portgroup = 1U;
}
else
{
/* Do Nothing */
}
temp_value = p_ioport_regs->ELC_PDBF[portgroup].BY;
temp_value &= (ioport_size_t) (~mask_value);
p_ioport_regs->ELC_PDBF[portgroup].BY = (uint8_t) (temp_value | event_data);
R_BSP_PinAccessDisable(); // Lock Register Write Protection
return FSP_SUCCESS;
}
/**********************************************************************************************************************//**
* This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite.
*
* Using the event system enables a pin state to be stored by this function in advance of being output on the pin.
* The output to the pin will occur when the ELC event occurs.
*
* @retval FSP_SUCCESS Pin event data written
* @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
{
uint8_t singleport = 0U;
uint8_t cnt;
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) ||
(port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET),
FSP_ERR_INVALID_ARGUMENT);
#endif
const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend;
R_BSP_PinAccessEnable(); // Unlock Register Write Protection
/* Get register address */
R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
for (cnt = 0; cnt < IOPORT_SINGLE_PORT_NUM; cnt++)
{
if ((bsp_io_port_pin_t) elc_cfg->single_port_cfg[cnt].port_num == pin)
{
singleport = cnt;
}
}
if (BSP_IO_LEVEL_HIGH == pin_value)
{
p_ioport_regs->ELC_PEL[singleport] |= (uint8_t) IOPORT_ELC_PEL_PSM_HIGH;
}
else
{
p_ioport_regs->ELC_PEL[singleport] &= (uint8_t) (~IOPORT_ELC_PEL_PSM_HIGH);
}
R_BSP_PinAccessDisable(); // Lock Register Write Protection
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* @} (end addtogroup IOPORT)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Configures pins.
*
* @param[in] p_cfg Pin configuration data
**********************************************************************************************************************/
void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
{
uint16_t pin_count;
ioport_cfg_t * p_pin_data;
p_pin_data = (ioport_cfg_t *) p_cfg;
R_BSP_PinAccessEnable(); // Unlock Register Write Protection
for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++)
{
r_ioport_pin_set(p_pin_data->p_pin_cfg_data[pin_count].pin,
(ioport_cfg_data_t *) &p_pin_data->p_pin_cfg_data[pin_count].pin_cfg);
}
R_BSP_PinAccessDisable(); // Lock Register Write Protection
}
/*******************************************************************************************************************//**
* Writes to the specified pin's multiple registers
*
* @param[in] pin Pin to write parameter data for
* @param[in] p_cfg_data Value to be written to the multiple registers
*
**********************************************************************************************************************/
static void r_ioport_pin_set (bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data)
{
R_PORT_COMMON_Type * p_ioport_regs;
uint32_t temp_value;
/* Get port and pin number */
uint32_t port = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET;
uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin);
/* Setting for Safety region or Non safety region */
if (p_cfg_data->rsel_reg == 1U) // Setting for Non safety region
{
R_PTADR->RSELP[port] |= (uint8_t) (1U << pin_num);
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
}
else // Setting for Safety region
{
R_PTADR->RSELP[port] &= (uint8_t) (~(1U << pin_num));
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE);
}
/* Setting DRCTL register */
if (3U >= pin_num)
{
temp_value = p_ioport_regs->DRCTL[port].L & ~(IOPORT_DRTCL_BIT_MASK << (pin_num * 8U));
p_ioport_regs->DRCTL[port].L = temp_value | (uint32_t) (p_cfg_data->drct_reg << (pin_num * 8U));
}
else if (3U < pin_num)
{
temp_value = p_ioport_regs->DRCTL[port].H & ~(IOPORT_DRTCL_BIT_MASK << ((pin_num - 4U) * 8U));
p_ioport_regs->DRCTL[port].H = temp_value | (uint32_t) (p_cfg_data->drct_reg << ((pin_num - 4U) * 8U));
}
else
{
/* Do Nothing */
}
/* Setting for GPIO or peripheral */
if (1U == p_cfg_data->pmc_reg) // Setting for peripheral
{
temp_value = p_ioport_regs->PFC[port] & ~(IOPORT_PFC_BIT_MASK << (pin_num * 4U));
p_ioport_regs->PFC[port] = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 4U)); // Setting PFC register
/* Setting peripheral for port mode */
p_ioport_regs->PMC[port] |= (uint8_t) (p_cfg_data->pmc_reg << pin_num); // Setting PMC register
}
else // Setting for GPIO
{
/* Setting GPIO for port mode */
p_ioport_regs->PMC[port] &= (uint8_t) (~(1U << pin_num)); // Setting PMC register
/* Setting for input or output */
if (1U == p_cfg_data->pm_reg) // Setting for input
{
/* Setting PM register. */
/* 01b: Input */
temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (1U << (pin_num * 2U)));
}
else if (1U < p_cfg_data->pm_reg) // Setting for two kinds of Output
{
/* Setting P register */
if (0U == p_cfg_data->p_reg) // Low output setting
{
p_ioport_regs->P[port] &= (uint8_t) (~(1U << pin_num));
}
else if (1U == p_cfg_data->p_reg) // High output setting
{
p_ioport_regs->P[port] |= (uint8_t) (1U << pin_num);
}
else
{
/* Do Nothing */
}
/* Setting PM register. */
/* 10b: Output */
/* 11b: Output(output data is input to input buffer) */
temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U)));
p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (p_cfg_data->pm_reg << (pin_num * 2U)));
}
else
{
/* Do Nothing */
}
}
}
/*******************************************************************************************************************//**
* Writes to the specified pin's multiple registers to generate event link function
*
* @param[in] p_extend_cfg_data Value to be written to the multiple registers
*
**********************************************************************************************************************/
static void r_ioport_event_config (const ioport_extend_cfg_t * p_extend_cfg_data)
{
uint8_t event_num;
uint8_t temp_value = 0x00;
uint8_t single_enable = 0x00;
uint8_t group_enable = 0x00;
R_PORT_COMMON_Type * p_ioport_regs;
ioport_extend_cfg_t * ex_cfg;
ex_cfg = (ioport_extend_cfg_t *) p_extend_cfg_data;
R_BSP_PinAccessEnable(); // Unlock Register Write Protection
/* Get register address */
p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE);
/* Single port configuration */
for (event_num = 0U; event_num < IOPORT_SINGLE_PORT_NUM; event_num++)
{
uint8_t port =
(uint8_t) ((ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET);
uint8_t pin_num = (uint8_t) ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PIN_BITS;
temp_value = p_ioport_regs->ELC_PEL[event_num] & IOPORT_ELC_PEL_MASK;
/* Port selection */
if ((BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) == port)
{
temp_value |= 1U << 3;
}
else if ((BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET) == port)
{
temp_value |= 1U << 4;
}
else
{
/* Do Nothing */
}
temp_value |= pin_num; // Pin number setting
/* When the pin specified as single input port, Set edge detection */
/* When the pin specified as single output port, Set output operation */
if (IOPORT_EVENT_DIRECTION_INPUT == ex_cfg->single_port_cfg[event_num].direction)
{
temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].edge_detection << 5); // Edge detection
/* Edge detection enable */
p_ioport_regs->ELC_DPTC |= (uint8_t) (1U << event_num);
}
else
{
temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].operation << 5); // Output operation
}
/* Set to ELC port setting register */
p_ioport_regs->ELC_PEL[event_num] = temp_value;
/* Single port event link function enable */
if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->single_port_cfg[event_num].event_control)
{
single_enable |= (uint8_t) (1U << event_num);
}
}
/* Port group configuration */
for (event_num = 0U; event_num < IOPORT_PORT_GROUP_NUM; event_num++)
{
/* Pin selection */
uint8_t group_pin = ex_cfg->port_group_input_cfg[event_num].pin_select |
ex_cfg->port_group_output_cfg[event_num].pin_select;
p_ioport_regs->ELC_PGR[event_num] = group_pin;
if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->port_group_input_cfg[event_num].event_control)
{
/* Input port group control */
temp_value = p_ioport_regs->ELC_PGC[event_num] & IOOPRT_ELC_PGC_MASK;
temp_value |= ex_cfg->port_group_input_cfg[event_num].edge_detection; // Edge detection
temp_value |= (uint8_t) (ex_cfg->port_group_input_cfg[event_num].overwrite_control << 2U); // Overwrite setting
/* Buffer register initialization */
p_ioport_regs->ELC_PDBF[event_num].BY = ex_cfg->port_group_input_cfg[event_num].buffer_init_value;
/* Input port group event link function enable */
group_enable |= (uint8_t) (1U << event_num);
}
/* Output port group operation */
temp_value |= (uint8_t) (ex_cfg->port_group_output_cfg[event_num].operation << 4);
/* Set to port group control register */
p_ioport_regs->ELC_PGC[event_num] = temp_value;
}
/* Set to ELC port event control register */
p_ioport_regs->ELC_ELSR2 = (uint8_t) ((single_enable << 4) | (group_enable << 2));
R_BSP_PinAccessDisable(); // Lock Register Write Protection
}

1934
bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_sci_uart/r_sci_uart.c Normal file
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1158
bsp/renesas/rzn2l_rsk/rzn_cfg.txt Normal file
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19
bsp/renesas/rzn2l_rsk/rzn_cfg/SConscript Normal file
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@ -0,0 +1,19 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src = Glob('*.c')
CPPPATH = [cwd+'/fsp_cfg', cwd + '/fsp_cfg/bsp']
group += DefineGroup('rz_cfg', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

25
bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/board_cfg.h Normal file
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/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
#include "../../../rzn/board/rzn2l_rsk/board.h"
#define BSP_CFG_XSPI0_X1_BOOT (1)
#define BSP_CFG_CACHE_FLG (0x00000000)
#define BSP_CFG_CS0BCR_V_WRAPCFG_V (0x00000000)
#define BSP_CFG_CS0WCR_V_COMCFG_V (0x00000000)
#define BSP_CFG_DUMMY0_BMCFG_V (0x00000000)
#define BSP_CFG_BSC_FLG_xSPI_FLG (0x00000000)
#define BSP_CFG_LDR_ADDR_NML (0x6000004C)
#define BSP_CFG_LDR_SIZE_NML (0x00006000)
#define BSP_CFG_DEST_ADDR_NML (0x00102000)
#define BSP_CFG_DUMMY1 (0x00000000)
#define BSP_CFG_DUMMY2 (0x00000000)
#define BSP_CFG_DUMMY3_CSSCTL_V (0x0000003F)
#define BSP_CFG_DUMMY4_LIOCFGCS0_V (0x00070000)
#define BSP_CFG_DUMMY5 (0x00000000)
#define BSP_CFG_DUMMY6 (0x00000000)
#define BSP_CFG_DUMMY7 (0x00000000)
#define BSP_CFG_DUMMY8 (0x00000000)
#define BSP_CFG_DUMMY9 (0x00000000)
#define BSP_CFG_DUMMY10_ACCESS_SPEED (0x00000006)
#define BSP_CFG_CHECK_SUM (0xE0A8)
#endif /* BOARD_CFG_H_ */

37
bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h Normal file
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@ -0,0 +1,37 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define FSP_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#undef FSP_NOT_DEFINED
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PORT_PROTECT (1)
#define BSP_CFG_SOFT_RESET_SUPPORTED (0)
#define BSP_CFG_EARLY_INIT (0)
#define BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0)
#if BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED
#define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE
#define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE
#else
#define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE
#define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE
#endif
#endif /* BSP_CFG_H_ */

14
bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h Normal file
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@ -0,0 +1,14 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_STACK_FIQ_BYTES (0x400)
#define BSP_CFG_STACK_IRQ_BYTES (0x400)
#define BSP_CFG_STACK_ABT_BYTES (0x400)
#define BSP_CFG_STACK_UND_BYTES (0x400)
#define BSP_CFG_STACK_SYS_BYTES (0x400)
#define BSP_CFG_STACK_SVC_BYTES (0x400)
#define BSP_CFG_HEAP_BYTES (0x2000)
#define BSP_CFG_C_RUNTIME_INIT (1)
#define BSP_CFG_USE_TFU_MATHLIB ((1))
#endif /* BSP_MCU_DEVICE_CFG_H_ */

552
bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h Normal file
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@ -0,0 +1,552 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_MEMORY_CFG_H_
#define BSP_MCU_DEVICE_MEMORY_CFG_H_
#define BSP_CFG_MPU0_READ0 (0)
#define BSP_CFG_MPU0_WRITE0 (0)
#define BSP_CFG_MPU0_STADD0 (0x00000000)
#define BSP_CFG_MPU0_ENDADD0 (0x00000C00)
#define BSP_CFG_MPU0_READ1 (0)
#define BSP_CFG_MPU0_WRITE1 (0)
#define BSP_CFG_MPU0_STADD1 (0x00000000)
#define BSP_CFG_MPU0_ENDADD1 (0x00000C00)
#define BSP_CFG_MPU0_READ2 (0)
#define BSP_CFG_MPU0_WRITE2 (0)
#define BSP_CFG_MPU0_STADD2 (0x00000000)
#define BSP_CFG_MPU0_ENDADD2 (0x00000C00)
#define BSP_CFG_MPU0_READ3 (0)
#define BSP_CFG_MPU0_WRITE3 (0)
#define BSP_CFG_MPU0_STADD3 (0x00000000)
#define BSP_CFG_MPU0_ENDADD3 (0x00000C00)
#define BSP_CFG_MPU0_READ4 (0)
#define BSP_CFG_MPU0_WRITE4 (0)
#define BSP_CFG_MPU0_STADD4 (0x00000000)
#define BSP_CFG_MPU0_ENDADD4 (0x00000C00)
#define BSP_CFG_MPU0_READ5 (0)
#define BSP_CFG_MPU0_WRITE5 (0)
#define BSP_CFG_MPU0_STADD5 (0x00000000)
#define BSP_CFG_MPU0_ENDADD5 (0x00000C00)
#define BSP_CFG_MPU0_READ6 (0)
#define BSP_CFG_MPU0_WRITE6 (0)
#define BSP_CFG_MPU0_STADD6 (0x00000000)
#define BSP_CFG_MPU0_ENDADD6 (0x00000C00)
#define BSP_CFG_MPU0_READ7 (0)
#define BSP_CFG_MPU0_WRITE7 (0)
#define BSP_CFG_MPU0_STADD7 (0x00000000)
#define BSP_CFG_MPU0_ENDADD7 (0x00000C00)
#define BSP_CFG_MPU1_READ0 (0)
#define BSP_CFG_MPU1_WRITE0 (0)
#define BSP_CFG_MPU1_STADD0 (0x00000000)
#define BSP_CFG_MPU1_ENDADD0 (0x00000C00)
#define BSP_CFG_MPU1_READ1 (0)
#define BSP_CFG_MPU1_WRITE1 (0)
#define BSP_CFG_MPU1_STADD1 (0x00000000)
#define BSP_CFG_MPU1_ENDADD1 (0x00000C00)
#define BSP_CFG_MPU1_READ2 (0)
#define BSP_CFG_MPU1_WRITE2 (0)
#define BSP_CFG_MPU1_STADD2 (0x00000000)
#define BSP_CFG_MPU1_ENDADD2 (0x00000C00)
#define BSP_CFG_MPU1_READ3 (0)
#define BSP_CFG_MPU1_WRITE3 (0)
#define BSP_CFG_MPU1_STADD3 (0x00000000)
#define BSP_CFG_MPU1_ENDADD3 (0x00000C00)
#define BSP_CFG_MPU1_READ4 (0)
#define BSP_CFG_MPU1_WRITE4 (0)
#define BSP_CFG_MPU1_STADD4 (0x00000000)
#define BSP_CFG_MPU1_ENDADD4 (0x00000C00)
#define BSP_CFG_MPU1_READ5 (0)
#define BSP_CFG_MPU1_WRITE5 (0)
#define BSP_CFG_MPU1_STADD5 (0x00000000)
#define BSP_CFG_MPU1_ENDADD5 (0x00000C00)
#define BSP_CFG_MPU1_READ6 (0)
#define BSP_CFG_MPU1_WRITE6 (0)
#define BSP_CFG_MPU1_STADD6 (0x00000000)
#define BSP_CFG_MPU1_ENDADD6 (0x00000C00)
#define BSP_CFG_MPU1_READ7 (0)
#define BSP_CFG_MPU1_WRITE7 (0)
#define BSP_CFG_MPU1_STADD7 (0x00000000)
#define BSP_CFG_MPU1_ENDADD7 (0x00000C00)
#define BSP_CFG_MPU2_READ0 (0)
#define BSP_CFG_MPU2_WRITE0 (0)
#define BSP_CFG_MPU2_STADD0 (0x00000000)
#define BSP_CFG_MPU2_ENDADD0 (0x00000C00)
#define BSP_CFG_MPU2_READ1 (0)
#define BSP_CFG_MPU2_WRITE1 (0)
#define BSP_CFG_MPU2_STADD1 (0x00000000)
#define BSP_CFG_MPU2_ENDADD1 (0x00000C00)
#define BSP_CFG_MPU2_READ2 (0)
#define BSP_CFG_MPU2_WRITE2 (0)
#define BSP_CFG_MPU2_STADD2 (0x00000000)
#define BSP_CFG_MPU2_ENDADD2 (0x00000C00)
#define BSP_CFG_MPU2_READ3 (0)
#define BSP_CFG_MPU2_WRITE3 (0)
#define BSP_CFG_MPU2_STADD3 (0x00000000)
#define BSP_CFG_MPU2_ENDADD3 (0x00000C00)
#define BSP_CFG_MPU2_READ4 (0)
#define BSP_CFG_MPU2_WRITE4 (0)
#define BSP_CFG_MPU2_STADD4 (0x00000000)
#define BSP_CFG_MPU2_ENDADD4 (0x00000C00)
#define BSP_CFG_MPU2_READ5 (0)
#define BSP_CFG_MPU2_WRITE5 (0)
#define BSP_CFG_MPU2_STADD5 (0x00000000)
#define BSP_CFG_MPU2_ENDADD5 (0x00000C00)
#define BSP_CFG_MPU2_READ6 (0)
#define BSP_CFG_MPU2_WRITE6 (0)
#define BSP_CFG_MPU2_STADD6 (0x00000000)
#define BSP_CFG_MPU2_ENDADD6 (0x00000C00)
#define BSP_CFG_MPU2_READ7 (0)
#define BSP_CFG_MPU2_WRITE7 (0)
#define BSP_CFG_MPU2_STADD7 (0x00000000)
#define BSP_CFG_MPU2_ENDADD7 (0x00000C00)
#define BSP_CFG_MPU3_READ0 (0)
#define BSP_CFG_MPU3_WRITE0 (0)
#define BSP_CFG_MPU3_STADD0 (0x00000000)
#define BSP_CFG_MPU3_ENDADD0 (0x00000000)
#define BSP_CFG_MPU3_READ1 (0)
#define BSP_CFG_MPU3_WRITE1 (0)
#define BSP_CFG_MPU3_STADD1 (0x00000000)
#define BSP_CFG_MPU3_ENDADD1 (0x00000000)
#define BSP_CFG_MPU3_READ2 (0)
#define BSP_CFG_MPU3_WRITE2 (0)
#define BSP_CFG_MPU3_STADD2 (0x00000000)
#define BSP_CFG_MPU3_ENDADD2 (0x00000000)
#define BSP_CFG_MPU3_READ3 (0)
#define BSP_CFG_MPU3_WRITE3 (0)
#define BSP_CFG_MPU3_STADD3 (0x00000000)
#define BSP_CFG_MPU3_ENDADD3 (0x00000000)
#define BSP_CFG_MPU3_READ4 (0)
#define BSP_CFG_MPU3_WRITE4 (0)
#define BSP_CFG_MPU3_STADD4 (0x00000000)
#define BSP_CFG_MPU3_ENDADD4 (0x00000000)
#define BSP_CFG_MPU3_READ5 (0)
#define BSP_CFG_MPU3_WRITE5 (0)
#define BSP_CFG_MPU3_STADD5 (0x00000000)
#define BSP_CFG_MPU3_ENDADD5 (0x00000000)
#define BSP_CFG_MPU3_READ6 (0)
#define BSP_CFG_MPU3_WRITE6 (0)
#define BSP_CFG_MPU3_STADD6 (0x00000000)
#define BSP_CFG_MPU3_ENDADD6 (0x00000000)
#define BSP_CFG_MPU3_READ7 (0)
#define BSP_CFG_MPU3_WRITE7 (0)
#define BSP_CFG_MPU3_STADD7 (0x00000000)
#define BSP_CFG_MPU3_ENDADD7 (0x00000000)
#define BSP_CFG_MPU4_READ0 (0)
#define BSP_CFG_MPU4_WRITE0 (0)
#define BSP_CFG_MPU4_STADD0 (0x00000000)
#define BSP_CFG_MPU4_ENDADD0 (0x00000000)
#define BSP_CFG_MPU4_READ1 (0)
#define BSP_CFG_MPU4_WRITE1 (0)
#define BSP_CFG_MPU4_STADD1 (0x00000000)
#define BSP_CFG_MPU4_ENDADD1 (0x00000000)
#define BSP_CFG_MPU4_READ2 (0)
#define BSP_CFG_MPU4_WRITE2 (0)
#define BSP_CFG_MPU4_STADD2 (0x00000000)
#define BSP_CFG_MPU4_ENDADD2 (0x00000000)
#define BSP_CFG_MPU4_READ3 (0)
#define BSP_CFG_MPU4_WRITE3 (0)
#define BSP_CFG_MPU4_STADD3 (0x00000000)
#define BSP_CFG_MPU4_ENDADD3 (0x00000000)
#define BSP_CFG_MPU4_READ4 (0)
#define BSP_CFG_MPU4_WRITE4 (0)
#define BSP_CFG_MPU4_STADD4 (0x00000000)
#define BSP_CFG_MPU4_ENDADD4 (0x00000000)
#define BSP_CFG_MPU4_READ5 (0)
#define BSP_CFG_MPU4_WRITE5 (0)
#define BSP_CFG_MPU4_STADD5 (0x00000000)
#define BSP_CFG_MPU4_ENDADD5 (0x00000000)
#define BSP_CFG_MPU4_READ6 (0)
#define BSP_CFG_MPU4_WRITE6 (0)
#define BSP_CFG_MPU4_STADD6 (0x00000000)
#define BSP_CFG_MPU4_ENDADD6 (0x00000000)
#define BSP_CFG_MPU4_READ7 (0)
#define BSP_CFG_MPU4_WRITE7 (0)
#define BSP_CFG_MPU4_STADD7 (0x00000000)
#define BSP_CFG_MPU4_ENDADD7 (0x00000000)
#define BSP_CFG_MPU6_READ0 (0)
#define BSP_CFG_MPU6_WRITE0 (0)
#define BSP_CFG_MPU6_STADD0 (0x00000000)
#define BSP_CFG_MPU6_ENDADD0 (0x00000C00)
#define BSP_CFG_MPU6_READ1 (0)
#define BSP_CFG_MPU6_WRITE1 (0)
#define BSP_CFG_MPU6_STADD1 (0x00000000)
#define BSP_CFG_MPU6_ENDADD1 (0x00000C00)
#define BSP_CFG_MPU6_READ2 (0)
#define BSP_CFG_MPU6_WRITE2 (0)
#define BSP_CFG_MPU6_STADD2 (0x00000000)
#define BSP_CFG_MPU6_ENDADD2 (0x00000C00)
#define BSP_CFG_MPU6_READ3 (0)
#define BSP_CFG_MPU6_WRITE3 (0)
#define BSP_CFG_MPU6_STADD3 (0x00000000)
#define BSP_CFG_MPU6_ENDADD3 (0x00000C00)
#define BSP_CFG_MPU6_READ4 (0)
#define BSP_CFG_MPU6_WRITE4 (0)
#define BSP_CFG_MPU6_STADD4 (0x00000000)
#define BSP_CFG_MPU6_ENDADD4 (0x00000C00)
#define BSP_CFG_MPU6_READ5 (0)
#define BSP_CFG_MPU6_WRITE5 (0)
#define BSP_CFG_MPU6_STADD5 (0x00000000)
#define BSP_CFG_MPU6_ENDADD5 (0x00000C00)
#define BSP_CFG_MPU6_READ6 (0)
#define BSP_CFG_MPU6_WRITE6 (0)
#define BSP_CFG_MPU6_STADD6 (0x00000000)
#define BSP_CFG_MPU6_ENDADD6 (0x00000C00)
#define BSP_CFG_MPU6_READ7 (0)
#define BSP_CFG_MPU6_WRITE7 (0)
#define BSP_CFG_MPU6_STADD7 (0x00000000)
#define BSP_CFG_MPU6_ENDADD7 (0x00000C00)
#define BSP_CFG_MPU7_READ0 (0)
#define BSP_CFG_MPU7_WRITE0 (0)
#define BSP_CFG_MPU7_STADD0 (0x00000000)
#define BSP_CFG_MPU7_ENDADD0 (0x00000000)
#define BSP_CFG_MPU7_READ1 (0)
#define BSP_CFG_MPU7_WRITE1 (0)
#define BSP_CFG_MPU7_STADD1 (0x00000000)
#define BSP_CFG_MPU7_ENDADD1 (0x00000000)
#define BSP_CFG_MPU7_READ2 (0)
#define BSP_CFG_MPU7_WRITE2 (0)
#define BSP_CFG_MPU7_STADD2 (0x00000000)
#define BSP_CFG_MPU7_ENDADD2 (0x00000000)
#define BSP_CFG_MPU7_READ3 (0)
#define BSP_CFG_MPU7_WRITE3 (0)
#define BSP_CFG_MPU7_STADD3 (0x00000000)
#define BSP_CFG_MPU7_ENDADD3 (0x00000000)
#define BSP_CFG_MPU7_READ4 (0)
#define BSP_CFG_MPU7_WRITE4 (0)
#define BSP_CFG_MPU7_STADD4 (0x00000000)
#define BSP_CFG_MPU7_ENDADD4 (0x00000000)
#define BSP_CFG_MPU7_READ5 (0)
#define BSP_CFG_MPU7_WRITE5 (0)
#define BSP_CFG_MPU7_STADD5 (0x00000000)
#define BSP_CFG_MPU7_ENDADD5 (0x00000000)
#define BSP_CFG_MPU7_READ6 (0)
#define BSP_CFG_MPU7_WRITE6 (0)
#define BSP_CFG_MPU7_STADD6 (0x00000000)
#define BSP_CFG_MPU7_ENDADD6 (0x00000000)
#define BSP_CFG_MPU7_READ7 (0)
#define BSP_CFG_MPU7_WRITE7 (0)
#define BSP_CFG_MPU7_STADD7 (0x00000000)
#define BSP_CFG_MPU7_ENDADD7 (0x00000000)
#define BSP_CFG_MPU8_READ0 (0)
#define BSP_CFG_MPU8_WRITE0 (0)
#define BSP_CFG_MPU8_STADD0 (0x00000000)
#define BSP_CFG_MPU8_ENDADD0 (0x00000000)
#define BSP_CFG_MPU8_READ1 (0)
#define BSP_CFG_MPU8_WRITE1 (0)
#define BSP_CFG_MPU8_STADD1 (0x00000000)
#define BSP_CFG_MPU8_ENDADD1 (0x00000000)
#define BSP_CFG_MPU8_READ2 (0)
#define BSP_CFG_MPU8_WRITE2 (0)
#define BSP_CFG_MPU8_STADD2 (0x00000000)
#define BSP_CFG_MPU8_ENDADD2 (0x00000000)
#define BSP_CFG_MPU8_READ3 (0)
#define BSP_CFG_MPU8_WRITE3 (0)
#define BSP_CFG_MPU8_STADD3 (0x00000000)
#define BSP_CFG_MPU8_ENDADD3 (0x00000000)
#define BSP_CFG_MPU8_READ4 (0)
#define BSP_CFG_MPU8_WRITE4 (0)
#define BSP_CFG_MPU8_STADD4 (0x00000000)
#define BSP_CFG_MPU8_ENDADD4 (0x00000000)
#define BSP_CFG_MPU8_READ5 (0)
#define BSP_CFG_MPU8_WRITE5 (0)
#define BSP_CFG_MPU8_STADD5 (0x00000000)
#define BSP_CFG_MPU8_ENDADD5 (0x00000000)
#define BSP_CFG_MPU8_READ6 (0)
#define BSP_CFG_MPU8_WRITE6 (0)
#define BSP_CFG_MPU8_STADD6 (0x00000000)
#define BSP_CFG_MPU8_ENDADD6 (0x00000000)
#define BSP_CFG_MPU8_READ7 (0)
#define BSP_CFG_MPU8_WRITE7 (0)
#define BSP_CFG_MPU8_STADD7 (0x00000000)
#define BSP_CFG_MPU8_ENDADD7 (0x00000000)
#define BSP_CFG_CPU_MPU_ATTR0_TYPE (BSP_TYPE_NORMAL_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR0_INNER (BSP_WRITE_BACK_NON_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR0_INNER_READ (BSP_READ_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE (BSP_WRITE_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR0_OUTER (BSP_WRITE_BACK_NON_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR0_OUTER_READ (BSP_READ_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE (BSP_WRITE_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
#define BSP_CFG_CPU_MPU_ATTR1_TYPE (BSP_TYPE_NORMAL_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR1_INNER (BSP_WRITE_NON_THROUGH)
#define BSP_CFG_CPU_MPU_ATTR1_INNER_READ (BSP_READ_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE (BSP_WRITE_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR1_OUTER (BSP_WRITE_NON_THROUGH)
#define BSP_CFG_CPU_MPU_ATTR1_OUTER_READ (BSP_READ_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE (BSP_WRITE_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
#define BSP_CFG_CPU_MPU_ATTR2_TYPE (BSP_TYPE_NORMAL_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR2_INNER (BSP_WRITE_NON_THROUGH)
#define BSP_CFG_CPU_MPU_ATTR2_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR2_OUTER (BSP_WRITE_NON_THROUGH)
#define BSP_CFG_CPU_MPU_ATTR2_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
#define BSP_CFG_CPU_MPU_ATTR3_TYPE (BSP_TYPE_NORMAL_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR3_INNER (BSP_NON_CACHEABLE)
#define BSP_CFG_CPU_MPU_ATTR3_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR3_OUTER (BSP_NON_CACHEABLE)
#define BSP_CFG_CPU_MPU_ATTR3_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
#define BSP_CFG_CPU_MPU_ATTR4_TYPE (BSP_TYPE_DEVICE_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR4_INNER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR4_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR4_OUTER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR4_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE (BSP_DEVICE_NGNRNE)
#define BSP_CFG_CPU_MPU_ATTR5_TYPE (BSP_TYPE_DEVICE_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR5_INNER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR5_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR5_OUTER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR5_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE (BSP_DEVICE_NGNRE)
#define BSP_CFG_CPU_MPU_ATTR6_TYPE (BSP_TYPE_DEVICE_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR6_INNER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR6_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR6_OUTER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR6_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE (BSP_DEVICE_NGRE)
#define BSP_CFG_CPU_MPU_ATTR7_TYPE (BSP_TYPE_DEVICE_MEMORY)
#define BSP_CFG_CPU_MPU_ATTR7_INNER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR7_INNER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR7_OUTER (BSP_WRITE_THROUGH_TRANSIENT)
#define BSP_CFG_CPU_MPU_ATTR7_OUTER_READ (BSP_READ_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE)
#define BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE (BSP_DEVICE_GRE)
/* Region00 : ATCM */
#define BSP_CFG_EL1_MPU_REGION00_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION00_LIMIT (0x0001FFFF)
#define BSP_CFG_EL1_MPU_REGION00_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION00_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION00_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION00_ATTRINDEX (BSP_ATTRINDEX3)
#define BSP_CFG_EL1_MPU_REGION00_ENABLE (BSP_REGION_ENABLE)
/* Region01 : BTCM */
#define BSP_CFG_EL1_MPU_REGION01_BASE (0x00100000)
#define BSP_CFG_EL1_MPU_REGION01_LIMIT (0x0011FFFF)
#define BSP_CFG_EL1_MPU_REGION01_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION01_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION01_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION01_ATTRINDEX (BSP_ATTRINDEX3)
#define BSP_CFG_EL1_MPU_REGION01_ENABLE (BSP_REGION_ENABLE)
/* Region02 : System RAM */
#define BSP_CFG_EL1_MPU_REGION02_BASE (0x10000000)
#define BSP_CFG_EL1_MPU_REGION02_LIMIT (0x1017FFFF)
#define BSP_CFG_EL1_MPU_REGION02_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION02_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION02_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION02_ATTRINDEX (BSP_ATTRINDEX1)
#define BSP_CFG_EL1_MPU_REGION02_ENABLE (BSP_REGION_ENABLE)
/* Region03 : Mirror area of System RAM */
#define BSP_CFG_EL1_MPU_REGION03_BASE (0x30000000)
#define BSP_CFG_EL1_MPU_REGION03_LIMIT (0x3017FFFF)
#define BSP_CFG_EL1_MPU_REGION03_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION03_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION03_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION03_ATTRINDEX (BSP_ATTRINDEX3)
#define BSP_CFG_EL1_MPU_REGION03_ENABLE (BSP_REGION_ENABLE)
/* Region04 : Mirror area of external address space */
#define BSP_CFG_EL1_MPU_REGION04_BASE (0x40000000)
#define BSP_CFG_EL1_MPU_REGION04_LIMIT (0x5FFFFFFF)
#define BSP_CFG_EL1_MPU_REGION04_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION04_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION04_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION04_ATTRINDEX (BSP_ATTRINDEX3)
#define BSP_CFG_EL1_MPU_REGION04_ENABLE (BSP_REGION_ENABLE)
/* Region05 : External address space */
#define BSP_CFG_EL1_MPU_REGION05_BASE (0x60000000)
#define BSP_CFG_EL1_MPU_REGION05_LIMIT (0x7FFFFFFF)
#define BSP_CFG_EL1_MPU_REGION05_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION05_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION05_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION05_ATTRINDEX (BSP_ATTRINDEX1)
#define BSP_CFG_EL1_MPU_REGION05_ENABLE (BSP_REGION_ENABLE)
/* Region06 : Non-Safety Peripheral */
#define BSP_CFG_EL1_MPU_REGION06_BASE (0x80000000)
#define BSP_CFG_EL1_MPU_REGION06_LIMIT (0x80FFFFFF)
#define BSP_CFG_EL1_MPU_REGION06_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION06_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION06_XN (BSP_EXECUTE_NEVER)
#define BSP_CFG_EL1_MPU_REGION06_ATTRINDEX (BSP_ATTRINDEX5)
#define BSP_CFG_EL1_MPU_REGION06_ENABLE (BSP_REGION_ENABLE)
/* Region07 : Safety Peripheral */
#define BSP_CFG_EL1_MPU_REGION07_BASE (0x81000000)
#define BSP_CFG_EL1_MPU_REGION07_LIMIT (0x81FFFFFF)
#define BSP_CFG_EL1_MPU_REGION07_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION07_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION07_XN (BSP_EXECUTE_NEVER)
#define BSP_CFG_EL1_MPU_REGION07_ATTRINDEX (BSP_ATTRINDEX5)
#define BSP_CFG_EL1_MPU_REGION07_ENABLE (BSP_REGION_ENABLE)
/* Region08 : LLPP Peripheral */
#define BSP_CFG_EL1_MPU_REGION08_BASE (0x90000000)
#define BSP_CFG_EL1_MPU_REGION08_LIMIT (0x901FFFFF)
#define BSP_CFG_EL1_MPU_REGION08_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION08_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION08_XN (BSP_EXECUTE_NEVER)
#define BSP_CFG_EL1_MPU_REGION08_ATTRINDEX (BSP_ATTRINDEX5)
#define BSP_CFG_EL1_MPU_REGION08_ENABLE (BSP_REGION_ENABLE)
/* Region09 : GIC0 */
#define BSP_CFG_EL1_MPU_REGION09_BASE (0x94000000)
#define BSP_CFG_EL1_MPU_REGION09_LIMIT (0x941FFFFF)
#define BSP_CFG_EL1_MPU_REGION09_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION09_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION09_XN (BSP_EXECUTE_NEVER)
#define BSP_CFG_EL1_MPU_REGION09_ATTRINDEX (BSP_ATTRINDEX4)
#define BSP_CFG_EL1_MPU_REGION09_ENABLE (BSP_REGION_ENABLE)
/* Region10 : Debug Private */
#define BSP_CFG_EL1_MPU_REGION10_BASE (0xC0000000)
#define BSP_CFG_EL1_MPU_REGION10_LIMIT (0xC0FFFFFF)
#define BSP_CFG_EL1_MPU_REGION10_SH (BSP_OUTER_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION10_AP (BSP_EL1RW_EL0RW)
#define BSP_CFG_EL1_MPU_REGION10_XN (BSP_EXECUTE_NEVER)
#define BSP_CFG_EL1_MPU_REGION10_ATTRINDEX (BSP_ATTRINDEX4)
#define BSP_CFG_EL1_MPU_REGION10_ENABLE (BSP_REGION_ENABLE)
/* Region11 : Not Used */
#define BSP_CFG_EL1_MPU_REGION11_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION11_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION11_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION11_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION11_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION11_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION11_ENABLE (BSP_REGION_DISABLE)
/* Region12 : Not Used */
#define BSP_CFG_EL1_MPU_REGION12_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION12_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION12_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION12_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION12_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION12_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION12_ENABLE (BSP_REGION_DISABLE)
/* Region13 : Not Used */
#define BSP_CFG_EL1_MPU_REGION13_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION13_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION13_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION13_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION13_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION13_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION13_ENABLE (BSP_REGION_DISABLE)
/* Region14 : Not Used */
#define BSP_CFG_EL1_MPU_REGION14_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION14_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION14_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION14_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION14_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION14_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION14_ENABLE (BSP_REGION_DISABLE)
/* Region15 : Not Used */
#define BSP_CFG_EL1_MPU_REGION15_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION15_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION15_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION15_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION15_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION15_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION15_ENABLE (BSP_REGION_DISABLE)
/* Region16 : Not Used */
#define BSP_CFG_EL1_MPU_REGION16_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION16_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION16_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION16_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION16_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION16_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION16_ENABLE (BSP_REGION_DISABLE)
/* Region17 : Not Used */
#define BSP_CFG_EL1_MPU_REGION17_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION17_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION17_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION17_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION17_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION17_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION17_ENABLE (BSP_REGION_DISABLE)
/* Region18 : Not Used */
#define BSP_CFG_EL1_MPU_REGION18_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION18_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION18_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION18_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION18_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION18_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION18_ENABLE (BSP_REGION_DISABLE)
/* Region19 : Not Used */
#define BSP_CFG_EL1_MPU_REGION19_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION19_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION19_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION19_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION19_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION19_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION19_ENABLE (BSP_REGION_DISABLE)
/* Region20 : Not Used */
#define BSP_CFG_EL1_MPU_REGION20_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION20_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION20_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION20_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION20_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION20_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION20_ENABLE (BSP_REGION_DISABLE)
/* Region21 : Not Used */
#define BSP_CFG_EL1_MPU_REGION21_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION21_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION21_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION21_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION21_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION21_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION21_ENABLE (BSP_REGION_DISABLE)
/* Region22 : Not Used */
#define BSP_CFG_EL1_MPU_REGION22_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION22_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION22_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION22_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION22_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION22_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION22_ENABLE (BSP_REGION_DISABLE)
/* Region23 : Not Used */
#define BSP_CFG_EL1_MPU_REGION23_BASE (0x00000000)
#define BSP_CFG_EL1_MPU_REGION23_LIMIT (0x00000000)
#define BSP_CFG_EL1_MPU_REGION23_SH (BSP_NON_SHAREABLE)
#define BSP_CFG_EL1_MPU_REGION23_AP (BSP_EL1RW_EL0NO)
#define BSP_CFG_EL1_MPU_REGION23_XN (BSP_EXECUTE_ENABLE)
#define BSP_CFG_EL1_MPU_REGION23_ATTRINDEX (BSP_ATTRINDEX0)
#define BSP_CFG_EL1_MPU_REGION23_ENABLE (BSP_REGION_DISABLE)
#define BSP_CFG_SCTLR_BR_BIT (BSP_BG_REGION_DISABLE)
#define BSP_CFG_SCTLR_I_BIT (BSP_ICACHE_ENABLE)
#define BSP_CFG_SCTLR_C_BIT (BSP_DATACACHE_ENABLE)
#endif /* BSP_MCU_DEVICE_MEMORY_CFG_H_ */

12
bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h Normal file
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@ -0,0 +1,12 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R9A07G084M04GBG
#define BSP_ATCM_SIZE_BYTES (131072)
#define BSP_BTCM_SIZE_BYTES (131072)
#define BSP_SYSTEM_RAM_SIZE_BYTES (1572864)
#define BSP_PACKAGE_FBGA
#define BSP_PACKAGE_PINS (225)
#define BSP_CFG_CORE_CR52 (0)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

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