springcute
/
rt-thread
mirror of https://github.com/RT-Thread/rt-thread.git
2
0
Fork 3
Code Issues Releases Wiki Activity

Merge pull request #181 from grissiom/rm48x50-next 

Rm48x50 next
This commit is contained in:
Bernard Xiong 2013-10-22 16:22:02 -07:00
parent ac5da68db7 377c6e6cc9
commit a3bf5e2d9b
38 changed files with 1381 additions and 6753 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bsp/rm48x50/HALCoGen/SConscript Normal file
View File

@ -0,0 +1,14 @@
import copy
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('source/*.c')
src += Glob('source/*.S')
CPPPATH = [cwd + '/include/']
group = DefineGroup('HALCoGen', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

98
bsp/rm48x50/HALCoGen/source/dabort.asm
View File

@ -1,98 +0,0 @@
;-------------------------------------------------------------------------------
; dabort.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Run Memory Test
.ref custom_dabort
.def _dabort
.asmfunc
_dabort
stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack
ldr r12, esmsr3 ; ESM Group3 status register
ldr r0, [r12]
tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM
bne ramErrorFound
tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM
bne ramErrorFound
noRAMerror
tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM
bne flashErrorFound
bl custom_dabort ; custom data abort handler required
; If this custom handler is written in assembly, all registers used in the routine
; and the link register must be saved on to the stack upon entry, and restored before
; return from the routine.
ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack
subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted
ramErrorFound
ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW
ldr r2, [r1]
tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled
beq ramErrorReal
mov r2, #0x20
str r2, [r1, #0x10] ; clear RAM error status register
ldr r1, ram2ctrl
str r2, [r1, #0x10] ; clear RAM error status register
mov r2, #0x28
str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
ramErrorReal
b ramErrorReal ; branch here forever as continuing operation is not recommended
flashErrorFound
ldr r1, flashbase
ldr r2, [r1, #0x6C] ; read FDIAGCTRL register
mov r2, r2, lsr #16
tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled
beq flashErrorReal
mov r2, #1
mov r2, r2, lsl #8
str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag
mov r2, #0x80
str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error
mov r2, #5
str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires
ldmfd r13!, {r0 - r12, lr}
subs pc, lr, #4 ; branch to instruction after the one that caused the abort
; this is the case because the data abort was caused intentionally
; and we do not want to cause the same data abort again.
flashErrorReal
b flashErrorReal ; branch here forever as continuing operation is not recommended
esmsr3 .word 0xFFFFF520
ramctrl .word 0xFFFFF800
ram2ctrl .word 0xFFFFF900
ram1errstat .word 0xFFFFF810
ram2errstat .word 0xFFFFF910
flashbase .word 0xFFF87000
.endasmfunc

713
bsp/rm48x50/HALCoGen/source/esm.c
View File

@ -1,713 +0,0 @@
/** @file esm.c
* @brief Esm Driver Source File
* @date 29.May.2013
* @version 03.05.02
*
* This file contains:
* - API Functions
* .
* which are relevant for the Esm driver.
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "esm.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @fn void esmInit(void)
* @brief Initializes Esm Driver
*
* This function initializes the Esm driver.
*
*/
/* USER CODE BEGIN (2) */
/* USER CODE END */
void esmInit(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** - Disable error pin channels */
esmREG->EPENACLR1 = 0xFFFFFFFFU;
esmREG->EPENACLR4 = 0xFFFFFFFFU;
/** - Disable interrupts */
esmREG->INTENACLR1 = 0xFFFFFFFFU;
esmREG->INTENACLR4 = 0xFFFFFFFFU;
/** - Clear error status flags */
esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS2EMU = 0xFFFFFFFFU;
esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;
esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS5EMU = 0xFFFFFFFFU;
esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;
/** - Setup LPC preload */
esmREG->LTCPRELOAD = 16384U - 1U;
/** - Reset error pin */
if (esmREG->EPSTATUS == 0U)
{
esmREG->KEY = 0x00000005U;
}
else
{
esmREG->KEY = 0x00000000U;
}
/** - Clear interrupt level */
esmREG->INTLVLCLR1 = 0xFFFFFFFFU;
esmREG->INTLVLCLR4 = 0xFFFFFFFFU;
/** - Set interrupt level */
esmREG->INTLVLSET1 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
esmREG->INTLVLSET4 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
/** - Enable error pin channels */
esmREG->EPENASET1 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
esmREG->EPENASET4 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
/** - Enable interrupts */
esmREG->INTENASET1 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
esmREG->INTENASET4 = (0U << 31U)
| (0U << 30U)
| (0U << 29U)
| (0U << 28U)
| (0U << 27U)
| (0U << 26U)
| (0U << 25U)
| (0U << 24U)
| (0U << 23U)
| (0U << 22U)
| (0U << 21U)
| (0U << 20U)
| (0U << 19U)
| (0U << 18U)
| (0U << 17U)
| (0U << 16U)
| (0U << 15U)
| (0U << 14U)
| (0U << 13U)
| (0U << 12U)
| (0U << 11U)
| (0U << 10U)
| (0U << 9U)
| (0U << 8U)
| (0U << 7U)
| (0U << 6U)
| (0U << 5U)
| (0U << 4U)
| (0U << 3U)
| (0U << 2U)
| (0U << 1U)
| (0U);
/* USER CODE BEGIN (4) */
/* USER CODE END */
}
/** @fn uint32 esmError(void)
* @brief Return Error status
*
* @return The error status
*
* Returns the error status.
*/
uint32 esmError(void)
{
uint32 status;
/* USER CODE BEGIN (5) */
/* USER CODE END */
status = esmREG->EPSTATUS;
/* USER CODE BEGIN (6) */
/* USER CODE END */
return status;
}
/** @fn void esmEnableError(uint64 channels)
* @brief Enable Group 1 Channels Error Signals propagation
*
* @param[in] channels - Channel mask
*
* Enable Group 1 Channels Error Signals propagation to the error pin.
*/
void esmEnableError(uint64 channels)
{
/* USER CODE BEGIN (7) */
/* USER CODE END */
esmREG->EPENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->EPENASET1 = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (8) */
/* USER CODE END */
}
/** @fn void esmDisableError(uint64 channels)
* @brief Disable Group 1 Channels Error Signals propagation
*
* @param[in] channels - Channel mask
*
* Disable Group 1 Channels Error Signals propagation to the error pin.
*/
void esmDisableError(uint64 channels)
{
/* USER CODE BEGIN (9) */
/* USER CODE END */
esmREG->EPENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->EPENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
/** @fn void esmTriggerErrorPinReset(void)
* @brief Trigger error pin reset and switch back to normal operation
*
* Trigger error pin reset and switch back to normal operation.
*/
void esmTriggerErrorPinReset(void)
{
/* USER CODE BEGIN (11) */
/* USER CODE END */
esmREG->KEY = 5U;
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
/** @fn void esmActivateNormalOperation(void)
* @brief Activate normal operation
*
* Activates normal operation mode.
*/
void esmActivateNormalOperation(void)
{
/* USER CODE BEGIN (13) */
/* USER CODE END */
esmREG->KEY = 0U;
/* USER CODE BEGIN (14) */
/* USER CODE END */
}
/** @fn void esmEnableInterrupt(uint64 channels)
* @brief Enable Group 1 Channels Interrupts
*
* @param[in] channels - Channel mask
*
* Enable Group 1 Channels Interrupts.
*/
void esmEnableInterrupt(uint64 channels)
{
/* USER CODE BEGIN (15) */
/* USER CODE END */
esmREG->INTENASET4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->INTENASET1 = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
/** @fn void esmDisableInterrupt(uint64 channels)
* @brief Disable Group 1 Channels Interrupts
*
* @param[in] channels - Channel mask
*
* Disable Group 1 Channels Interrupts.
*/
void esmDisableInterrupt(uint64 channels)
{
/* USER CODE BEGIN (17) */
/* USER CODE END */
esmREG->INTENACLR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->INTENACLR1 = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
* @brief Set Group 1 Channels Interrupt Levels
*
* @param[in] channels - Channel mask
* @param[in] flags - Level mask: - 0: Low priority interrupt
* - 1: High priority interrupt
*
* Set Group 1 Channels Interrupts levels.
*/
void esmSetInterruptLevel(uint64 channels, uint64 flags)
{
/* USER CODE BEGIN (19) */
/* USER CODE END */
esmREG->INTLVLCLR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFU);
esmREG->INTLVLSET4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
esmREG->INTLVLCLR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFU);
esmREG->INTLVLSET1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
/* USER CODE BEGIN (20) */
/* USER CODE END */
}
/** @fn void esmClearStatus(uint32 group, uint64 channels)
* @brief Clear Group error status
*
* @param[in] group - Error group
* @param[in] channels - Channel mask
*
* Clear Group error status.
*/
void esmClearStatus(uint32 group, uint64 channels)
{
/* USER CODE BEGIN (21) */
/* USER CODE END */
esmREG->ESTATUS4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->ESTATUS1[group] = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
/** @fn void esmClearStatusBuffer(uint64 channels)
* @brief Clear Group 2 error status buffer
*
* @param[in] channels - Channel mask
*
* Clear Group 2 error status buffer.
*/
void esmClearStatusBuffer(uint64 channels)
{
/* USER CODE BEGIN (23) */
/* USER CODE END */
esmREG->ESTATUS5EMU = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
esmREG->ESTATUS2EMU = (uint32)(channels & 0xFFFFFFFFU);
/* USER CODE BEGIN (24) */
/* USER CODE END */
}
/** @fn void esmSetCounterPreloadValue(uint32 value)
* @brief Set counter preload value
*
* @param[in] value - Counter preload value
*
* Set counter preload value.
*/
void esmSetCounterPreloadValue(uint32 value)
{
/* USER CODE BEGIN (25) */
/* USER CODE END */
esmREG->LTCPRELOAD = value & 0xC000U;
/* USER CODE BEGIN (26) */
/* USER CODE END */
}
/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
* @brief Return Error status
*
* @param[in] group - Error group
* @param[in] channels - Error Channels
*
* @return The channels status of selected group
*
* Returns the channels status of selected group.
*/
uint64 esmGetStatus(uint32 group, uint64 channels)
{
uint64 status;
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
status = (((uint64)esmREG->ESTATUS4[group] << 32U) | (uint64)esmREG->ESTATUS1[group]) & channels;
/* USER CODE BEGIN (28) */
/* USER CODE END */
return status;
}
/** @fn uint64 esmGetStatusBuffer(uint64 channels)
* @brief Return Group 2 channel x Error status buffer
*
* @param[in] channels - Error Channels
*
* @return The channels status
*
* Returns the group 2 buffered status of selected channels.
*/
uint64 esmGetStatusBuffer(uint64 channels)
{
uint64 status;
/* USER CODE BEGIN (29) */
/* USER CODE END */
/*SAFETYMCUSW 51 S MR:12.3 <REVIEWED> "Needs shifting for 64-bit value" */
status = (((uint64)esmREG->ESTATUS5EMU << 32U) | (uint64)esmREG->ESTATUS2EMU) & channels;
/* USER CODE BEGIN (30) */
/* USER CODE END */
return status;
}
/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
* @brief Return ESM Self test status
*
* @return ESM Self test status
*
* Returns the ESM Self test status.
*/
esmSelfTestFlag_t esmEnterSelfTest(void)
{
esmSelfTestFlag_t status;
/* USER CODE BEGIN (31) */
/* USER CODE END */
if(((esmREG->EPSTATUS & 0x1U) == 0x0U) && (esmREG->KEY == 0x0U))
{
status = esmSelfTest_NotStarted;
}
else
{
esmREG->KEY = 0xAU;
status = esmSelfTest_Active;
if((esmREG->EPSTATUS & 0x1U) != 0x0U)
{
status = esmSelfTest_Failed;
}
esmREG->KEY = 0x5U;
}
/* USER CODE BEGIN (32) */
/* USER CODE END */
return status;
}
/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
* @brief Return ESM Self test status
*
* Returns the ESM Self test status.
*/
esmSelfTestFlag_t esmSelfTestStatus(void)
{
esmSelfTestFlag_t status;
/* USER CODE BEGIN (33) */
/* USER CODE END */
if((esmREG->EPSTATUS & 0x1U) == 0x0U)
{
if(esmREG->KEY == 0x5U)
{
status = esmSelfTest_Active;
}
else
{
status = esmSelfTest_Failed;
}
}
else
{
status = esmSelfTest_Passed;
}
/* USER CODE BEGIN (34) */
/* USER CODE END */
return status;
}
/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration registers
*
* @param[in] *config_reg: pointer to the struct to which the initial or current
* value of the configuration registers need to be stored
* @param[in] type: whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored
* in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored
* in the struct pointed by config_reg
*
* This function will copy the initial or current value (depending on the parameter 'type')
* of the configuration registers to the struct pointed by config_reg
*
*/
void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_EPENASET1 = ESM_EPENASET1_CONFIGVALUE;
config_reg->CONFIG_INTENASET1 = ESM_INTENASET1_CONFIGVALUE;
config_reg->CONFIG_INTLVLSET1 = ESM_INTLVLSET1_CONFIGVALUE;
config_reg->CONFIG_LTCPRELOAD = ESM_LTCPRELOAD_CONFIGVALUE;
config_reg->CONFIG_KEY = ESM_KEY_CONFIGVALUE;
config_reg->CONFIG_EPENASET4 = ESM_EPENASET4_CONFIGVALUE;
config_reg->CONFIG_INTENASET4 = ESM_INTENASET4_CONFIGVALUE;
config_reg->CONFIG_INTLVLSET4 = ESM_INTLVLSET4_CONFIGVALUE;
}
else
{
config_reg->CONFIG_EPENASET1 = esmREG->EPENASET1;
config_reg->CONFIG_INTENASET1 = esmREG->INTENASET1;
config_reg->CONFIG_INTLVLSET1 = esmREG->INTLVLSET1;
config_reg->CONFIG_LTCPRELOAD = esmREG->LTCPRELOAD;
config_reg->CONFIG_KEY = esmREG->KEY;
config_reg->CONFIG_EPENASET4 = esmREG->EPENASET4;
config_reg->CONFIG_INTENASET4 = esmREG->INTENASET4;
config_reg->CONFIG_INTLVLSET4 = esmREG->INTLVLSET4;
}
}
/* USER CODE BEGIN (35) */
/* USER CODE END */
/** @fn void esmHighInterrupt(void)
* @brief High Level Interrupt for ESM
*/
#pragma CODE_STATE(esmHighInterrupt, 32)
#pragma INTERRUPT(esmHighInterrupt, FIQ)
void esmHighInterrupt(void)
{
sint32 vec = esmREG->INTOFFH - 1U;
/* USER CODE BEGIN (36) */
/* USER CODE END */
if (vec >= 96U)
{
esmREG->ESTATUS4[1U] = 1U << (vec-96U);
esmGroup2Notification(vec-64U);
}
else if (vec >= 64U)
{
esmREG->ESTATUS4[0U] = 1U << (vec-64U);
esmGroup1Notification(vec-32U);
}
else if (vec >= 32U)
{
esmREG->ESTATUS1[1U] = 1U << (vec-32U);
esmGroup2Notification(vec-32U);
}
else if (vec >= 0U)
{
esmREG->ESTATUS1[0U] = 1U << vec;
esmGroup1Notification(vec);
}
else
{
esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
}
/* USER CODE BEGIN (37) */
/* USER CODE END */
}
/* USER CODE BEGIN (41) */
/* USER CODE END */

125
bsp/rm48x50/HALCoGen/source/notification.c
View File

@ -1,125 +0,0 @@
/** @file notification.c
* @brief User Notification Definition File
* @date 29.May.2013
* @version 03.05.02
*
* This file defines empty notification routines to avoid
* linker errors, Driver expects user to define the notification.
* The user needs to either remove this file and use their custom
* notification function or place their code sequence in this file
* between the provided USER CODE BEGIN and USER CODE END.
*
*/
/* Include Files */
#include "esm.h"
#include "sys_selftest.h"
#include "gio.h"
#include "sci.h"
#include "rti.h"
#include "sys_dma.h"
/* USER CODE BEGIN (0) */
#include <stdint.h>
/* USER CODE END */
void esmGroup1Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (1) */
/* USER CODE END */
}
/* USER CODE BEGIN (2) */
/* USER CODE END */
void esmGroup2Notification(uint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
/* USER CODE BEGIN (6) */
/* USER CODE END */
void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
void rtiNotification(uint32 notification)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (9) */
sciSendByte(scilinREG, 'I');
/* USER CODE END */
}
/* USER CODE BEGIN (10) */
/* USER CODE END */
void gioNotification(gioPORT_t *port, sint32 bit)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
void sciNotification(sciBASE_t *sci, uint32 flags)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (29) */
if (sci == scilinREG && flags == SCI_RX_INT)
{
}
/* USER CODE END */
}
/* USER CODE BEGIN (30) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* USER CODE BEGIN (47) */
/* USER CODE END */
/* USER CODE BEGIN (50) */
/* USER CODE END */
/* USER CODE BEGIN (53) */
/* USER CODE END */
void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (54) */
/* USER CODE END */
}
/* USER CODE BEGIN (55) */
/* USER CODE END */
/* USER CODE BEGIN (56) */
/* USER CODE END */

121
bsp/rm48x50/HALCoGen/source/pinmux.c
View File

@ -1,121 +0,0 @@
/** @file pinmux.c
* @brief PINMUX Driver Inmplmentation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* Include Files */
#include "pinmux.h"
#define PINMUX_SET(REG, BALLID, MUX) \
pinMuxReg->PINMMR##REG## = (pinMuxReg->PINMMR##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)
#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)
#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
#define PINMUX_ETHERNET_SELECT(interface) \
pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
/* USER CODE BEGIN (0) */
/* USER CODE END */
void muxInit(void){
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Enable Pin Muxing */
kickerReg->KICKER0 = 0x83E70B13U;
kickerReg->KICKER1 = 0x95A4F1E0U;
/* USER CODE BEGIN (2) */
/* USER CODE END */
pinMuxReg->PINMMR0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;
pinMuxReg->PINMMR1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;
pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
pinMuxReg->PINMMR3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;
pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;
pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;
pinMuxReg->PINMMR7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_ETMDATA_30;
pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;
pinMuxReg->PINMMR9 = (~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U| PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;
pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;
pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;
pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
pinMuxReg->PINMMR15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
pinMuxReg->PINMMR16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;
pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;
pinMuxReg->PINMMR18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
pinMuxReg->PINMMR19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;
pinMuxReg->PINMMR20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;
pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;
pinMuxReg->PINMMR23 = (~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U |(~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U| PINMUX_BALL_C6_EMIF_ADDR_8;
pinMuxReg->PINMMR24 = (~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U | (~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR25 = (~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U|(~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U|(~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U;
pinMuxReg->PINMMR26 = (~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U|(~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U|PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
pinMuxReg->PINMMR28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA;
PINMUX_GATE_EMIF_CLK_ENABLE(OFF);
PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
PINMUX_ALT_ADC_TRIGGER_SELECT(1);
PINMUX_ETHERNET_SELECT(RMII);
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Disable Pin Muxing */
kickerReg->KICKER0 = 0x00000000U;
kickerReg->KICKER1 = 0x00000000U;
/* USER CODE BEGIN (4) */
/* USER CODE END */
}
/* USER CODE BEGIN (5) */
/* USER CODE END */

28
bsp/rm48x50/HALCoGen/source/rti.c
View File

@ -764,31 +764,3 @@ void rtiGetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type)
}
}
/* USER CODE BEGIN (82) */
/* USER CODE END */
/** @fn void rtiCompare3Interrupt(void)
* @brief RTI1 Compare 3 Interrupt Handler
*
* RTI1 Compare 3 interrupt handler
*
*/
void rtiCompare3Interrupt(void)
{
/* USER CODE BEGIN (83) */
/* USER CODE END */
rtiREG1->INTFLAG = 8U;
rtiNotification(rtiNOTIFICATION_COMPARE3);
/* USER CODE BEGIN (84) */
/* USER CODE END */
}

549
bsp/rm48x50/HALCoGen/source/sci.c
View File

@ -1,549 +0,0 @@
/** @file sci.c
* @brief SCI Driver Implementation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* USER CODE END */
#include "sci.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @struct g_sciTransfer
* @brief Interrupt mode globals
*
*/
static struct g_sciTransfer
{
uint32 mode;
uint32 length;
uint8 * data;
} g_sciTransfer_t[2U];
/** @fn void sciInit(void)
* @brief Initializes the SCI Driver
*
* This function initializes the SCI module.
*/
void sciInit(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @b initialize @b SCILIN */
/** - bring SCI out of reset */
scilinREG->GCR0 = 1U;
/** - Disable all interrupts */
scilinREG->CLRINT = 0xFFFFFFFFU;
scilinREG->CLRINTLVL = 0xFFFFFFFFU;
/** - global control 1 */
scilinREG->GCR1 = (1U << 25U) /* enable transmit */
| (1U << 24U) /* enable receive */
| (1U << 5U) /* internal clock (device has no clock pin) */
| ((1U-1U) << 4U) /* number of stop bits */
| (0U << 3U) /* even parity, otherwise odd */
| (0U << 2U) /* enable parity */
| (1U << 1U); /* asynchronous timing mode */
/** - set baudrate */
scilinREG->BRS = 53U; /* baudrate */
/** - transmission length */
scilinREG->FORMAT = 8U - 1U; /* length */
/** - set SCI pins functional mode */
scilinREG->FUN = (1U << 2U) /* tx pin */
| (1U << 1U) /* rx pin */
| (0U); /* clk pin */
/** - set SCI pins default output value */
scilinREG->DOUT = (0U << 2U) /* tx pin */
| (0U << 1U) /* rx pin */
| (0U); /* clk pin */
/** - set SCI pins output direction */
scilinREG->DIR = (0U << 2U) /* tx pin */
| (0U << 1U) /* rx pin */
| (0U); /* clk pin */
/** - set SCI pins open drain enable */
scilinREG->ODR = (0U << 2U) /* tx pin */
| (0U << 1U) /* rx pin */
| (0U); /* clk pin */
/** - set SCI pins pullup/pulldown enable */
scilinREG->PD = (0U << 2U) /* tx pin */
| (0U << 1U) /* rx pin */
| (0U); /* clk pin */
/** - set SCI pins pullup/pulldown select */
scilinREG->PSL = (1U << 2U) /* tx pin */
| (1U << 1U) /* rx pin */
| (1U); /* clk pin */
/** - set interrupt level */
scilinREG->SETINTLVL = (0U << 26U) /* Framing error */
| (0U << 25U) /* Overrun error */
| (0U << 24U) /* Parity error */
| (0U << 9U) /* Receive */
| (0U << 8U) /* Transmit */
| (0U << 1U) /* Wakeup */
| (0U); /* Break detect */
/** - set interrupt enable */
scilinREG->SETINT = (0U << 26U) /* Framing error */
| (0U << 25U) /* Overrun error */
| (0U << 24U) /* Parity error */
| (1U << 9U) /* Receive */
| (0U << 1U) /* Wakeup */
| (0U); /* Break detect */
/** - initialize global transfer variables */
g_sciTransfer_t[1U].mode = 0U << 8U;
g_sciTransfer_t[1U].length = 0U;
/** - Finaly start SCILIN */
scilinREG->GCR1 |= (1U << 7U);
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port)
* @brief Change functional behavior of pins at runtime.
* @param[in] sci - sci module base address
* @param[in] port - Value to write to FUN register
*
* Change the value of the PCFUN register at runtime, this allows to
* dynamically change the functionality of the SCI pins between functional
* and GIO mode.
*/
void sciSetFunctional(sciBASE_t *sci, uint32 port)
{
/* USER CODE BEGIN (4) */
/* USER CODE END */
sci->FUN = port;
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
* @brief Change baudrate at runtime.
* @param[in] sci - sci module base address
* @param[in] baud - baudrate in Hz
*
* Change the SCI baudrate at runtime.
*/
void sciSetBaudrate(sciBASE_t *sci, uint32 baud)
{
float64 vclk = 100.000 * 1000000.0;
uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U;
/* USER CODE BEGIN (6) */
/* USER CODE END */
/*SAFETYMCUSW 96 S MR:6.1 <REVIEWED> "Calculations including int and float cannot be avoided" */
sci->BRS = ((uint32)((vclk /(f*baud) + 0.5)) - 1U) & 0x00FFFFFFU;
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
/** @fn uint32 sciIsTxReady(sciBASE_t *sci)
* @brief Check if Tx buffer empty
* @param[in] sci - sci module base address
*
* @return The TX ready flag
*
* Checks to see if the Tx buffer ready flag is set, returns
* 0 is flags not set otherwise will return the Tx flag itself.
*/
uint32 sciIsTxReady(sciBASE_t *sci)
{
/* USER CODE BEGIN (8) */
/* USER CODE END */
return sci->FLR & SCI_TX_INT;
}
/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte)
* @brief Send Byte
* @param[in] sci - sci module base address
* @param[in] byte - byte to transfer
*
* Sends a single byte in polling mode, will wait in the
* routine until the transmit buffer is empty before sending
* the byte. Use sciIsTxReady to check for Tx buffer empty
* before calling sciSendByte to avoid waiting.
*/
void sciSendByte(sciBASE_t *sci, uint8 byte)
{
/* USER CODE BEGIN (9) */
/* USER CODE END */
while ((sci->FLR & SCI_TX_INT) == 0U)
{
} /* Wait */
sci->TD = byte;
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
* @brief Send Data
* @param[in] sci - sci module base address
* @param[in] length - number of data words to transfer
* @param[in] data - pointer to data to send
*
* Send a block of data pointed to by 'data' and 'length' bytes
* long. If interrupts have been enabled the data is sent using
* interrupt mode, otherwise polling mode is used. In interrupt
* mode transmission of the first byte is started and the routine
* returns immediately, sciSend must not be called again until the
* transfer is complete, when the sciNotification callback will
* be called. In polling mode, sciSend will not return until
* the transfer is complete.
*
* @note if data word is less than 8 bits, then the data must be left
* aligned in the data byte.
*/
void sciSend(sciBASE_t *sci, uint32 length, uint8 * data)
{
uint32 index = sci == sciREG ? 0U : 1U;
/* USER CODE BEGIN (11) */
/* USER CODE END */
if ((g_sciTransfer_t[index].mode & SCI_TX_INT) != 0U)
{
/* we are in interrupt mode */
g_sciTransfer_t[index].length = length;
g_sciTransfer_t[index].data = data;
/* start transmit by sending first byte */
sci->TD = *g_sciTransfer_t[index].data++ ;
sci->SETINT = SCI_TX_INT;
}
else
{
/* send the data */
while (length-- > 0U)
{
while ((sci->FLR & SCI_TX_INT) == 0U)
{
} /* Wait */
sci->TD = *data++;
}
}
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
/** @fn uint32 sciIsRxReady(sciBASE_t *sci)
* @brief Check if Rx buffer full
* @param[in] sci - sci module base address
*
* @return The Rx ready flag
*
* Checks to see if the Rx buffer full flag is set, returns
* 0 is flags not set otherwise will return the Rx flag itself.
*/
uint32 sciIsRxReady(sciBASE_t *sci)
{
/* USER CODE BEGIN (13) */
/* USER CODE END */
return sci->FLR & SCI_RX_INT;
}
/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci)
* @brief Check if Idle Period is Detected
* @param[in] sci - sci module base address
*
* @return The Idle flag
*
* Checks to see if the SCI Idle flag is set, returns 0 is flags
* not set otherwise will return the Ilde flag itself.
*/
uint32 sciIsIdleDetected(sciBASE_t *sci)
{
/* USER CODE BEGIN (14) */
/* USER CODE END */
return sci->FLR & SCI_IDLE;
}
/** @fn uint32 sciRxError(sciBASE_t *sci)
* @brief Return Rx Error flags
* @param[in] sci - sci module base address
*
* @return The Rx error flags
*
* Returns the Rx framing, overrun and parity errors flags,
* also clears the error flags before returning.
*/
uint32 sciRxError(sciBASE_t *sci)
{
uint32 status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT);
/* USER CODE BEGIN (15) */
/* USER CODE END */
sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
return status;
}
/** @fn uint32 sciReceiveByte(sciBASE_t *sci)
* @brief Receive Byte
* @param[in] sci - sci module base address
*
* @return Received byte
*
* Receives a single byte in polling mode. If there is
* not a byte in the receive buffer the routine will wait
* until one is received. Use sciIsRxReady to check to
* see if the buffer is full to avoid waiting.
*/
uint32 sciReceiveByte(sciBASE_t *sci)
{
/* USER CODE BEGIN (16) */
/* USER CODE END */
while ((sci->FLR & SCI_RX_INT) == 0U)
{
} /* Wait */
return (sci->RD & 0x000000FFU);
}
/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
* @brief Receive Data
* @param[in] sci - sci module base address
* @param[in] length - number of data words to transfer
* @param[in] data - pointer to data buffer
*
* Receive a block of 'length' bytes long and place it into the
* data buffer pointed to by 'data'. If interrupts have been
* enabled the data is received using interrupt mode, otherwise
* polling mode is used. In interrupt mode receive is setup and
* the routine returns immediately, sciReceive must not be called
* again until the transfer is complete, when the sciNotification
* callback will be called. In polling mode, sciReceive will not
* return until the transfer is complete.
*/
void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data)
{
/* USER CODE BEGIN (17) */
/* USER CODE END */
if ((sci->SETINT & SCI_RX_INT) == SCI_RX_INT)
{
/* we are in interrupt mode */
uint32 index = sci == sciREG ? 0U : 1U;
/* clear error flags */
sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;
g_sciTransfer_t[index].length = length;
g_sciTransfer_t[index].data = data;
}
else
{
while (length-- > 0U)
{
while ((sci->FLR & SCI_RX_INT) == 0U)
{
} /* Wait */
*data++ = (uint8)(sci->RD & 0x000000FFU);
}
}
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
* @brief Enable Loopback mode for self test
* @param[in] sci - sci module base address
* @param[in] Loopbacktype - Digital or Analog
*
* This function enables the Loopback mode for self test.
*/
void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype)
{
/* USER CODE BEGIN (19) */
/* USER CODE END */
/* Clear Loopback incase enabled already */
sci->IODFTCTRL = 0U;
/* Enable Loopback either in Analog or Digital Mode */
sci->IODFTCTRL = 0x00000A00U
| (Loopbacktype << 1U);
/* USER CODE BEGIN (20) */
/* USER CODE END */
}
/** @fn void sciDisableLoopback(sciBASE_t *sci)
* @brief Enable Loopback mode for self test
* @param[in] sci - sci module base address
*
* This function disable the Loopback mode.
*/
void sciDisableLoopback(sciBASE_t *sci)
{
/* USER CODE BEGIN (21) */
/* USER CODE END */
/* Disable Loopback Mode */
sci->IODFTCTRL = 0x00000500U;
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags)
* @brief Enable interrupts
* @param[in] sci - sci module base address
* @param[in] flags - Interrupts to be enabled, can be ored value of:
* SCI_FE_INT - framing error,
* SCI_OE_INT - overrun error,
* SCI_PE_INT - parity error,
* SCI_RX_INT - receive buffer ready,
* SCI_TX_INT - transmit buffer ready,
* SCI_WAKE_INT - wakeup,
* SCI_BREAK_INT - break detect
*/
void sciEnableNotification(sciBASE_t *sci, uint32 flags)
{
uint32 index = sci == sciREG ? 0U : 1U;
/* USER CODE BEGIN (23) */
/* USER CODE END */
g_sciTransfer_t[index].mode |= (flags & SCI_TX_INT);
sci->SETINT = (flags & (~(SCI_TX_INT)));
/* USER CODE BEGIN (24) */
/* USER CODE END */
}
/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags)
* @brief Disable interrupts
* @param[in] sci - sci module base address
* @param[in] flags - Interrupts to be disabled, can be ored value of:
* SCI_FE_INT - framing error,
* SCI_OE_INT - overrun error,
* SCI_PE_INT - parity error,
* SCI_RX_INT - receive buffer ready,
* SCI_TX_INT - transmit buffer ready,
* SCI_WAKE_INT - wakeup,
* SCI_BREAK_INT - break detect
*/
void sciDisableNotification(sciBASE_t *sci, uint32 flags)
{
uint32 index = sci == sciREG ? 0U : 1U;
/* USER CODE BEGIN (25) */
/* USER CODE END */
g_sciTransfer_t[index].mode &= ~(flags & SCI_TX_INT);
sci->CLRINT = (flags & (~SCI_TX_INT));
/* USER CODE BEGIN (26) */
/* USER CODE END */
}
/** @fn void linHighLevelInterrupt(void)
* @brief Level 0 Interrupt for SCILIN
*/
void linHighLevelInterrupt(void)
{
uint32 vec = scilinREG->INTVECT0;
/* USER CODE BEGIN (35) */
/* USER CODE END */
switch (vec)
{
case 1U:
sciNotification(scilinREG, SCI_WAKE_INT);
break;
case 3U:
sciNotification(scilinREG, SCI_PE_INT);
break;
case 6U:
sciNotification(scilinREG, SCI_FE_INT);
break;
case 7U:
sciNotification(scilinREG, SCI_BREAK_INT);
break;
case 9U:
sciNotification(scilinREG, SCI_OE_INT);
break;
case 11U:
/* receive */
{ uint32 byte = (scilinREG->RD & 0x000000FFU);
if (g_sciTransfer_t[1U].length > 0U)
{
*g_sciTransfer_t[1U].data++ = byte;
g_sciTransfer_t[1U].length--;
if (g_sciTransfer_t[1U].length == 0U)
{
sciNotification(scilinREG, SCI_RX_INT);
}
}
}
break;
case 12U:
/* transmit */
if (--g_sciTransfer_t[1U].length > 0U)
{
scilinREG->TD = *g_sciTransfer_t[1U].data++;
}
else
{
scilinREG->CLRINT = SCI_TX_INT;
sciNotification(scilinREG, SCI_TX_INT);
}
break;
default:
/* phantom interrupt, clear flags and return */
scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;
break;
}
/* USER CODE BEGIN (36) */
/* USER CODE END */
}
/* USER CODE BEGIN (37) */
/* USER CODE END */

322
bsp/rm48x50/HALCoGen/source/sys_dma.c
View File

@ -1,322 +0,0 @@
/** @file dma.c
* @brief DMA Driver Inmplmentation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_dma.h"
/** @fn void dmaEnable(void)
* @brief enables DMA module
*
* This function brings DMA out of reset
*/
void dmaEnable(void)
{
dmaREG->GCTRL = 0x00000001U; /* reset dma */
dmaREG->GCTRL |= 0x00010000U; /* enable dma */
dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */
}
/** @fn void dmaDisable(void)
* @brief disables DMA module
*
* This function disables DMA module
*/
void dmaDisable(void)
{
/* Wait until DMA's external bus has completed data transfer */
while((dmaREG->GCTRL & DMA_GCTRL_BUSBUSY) != 0U)
{
} /* Wait */
/* Disable DMA module */
dmaREG->GCTRL = 0U;
}
/** @fn void dmaReqAssign(uint32 channel,uint32 reqline)
* @brief Initializes the DMA Driver
* @param[in] channel DMA channel
* @param[in] reqline DMA request line
*
* This function assigns dma request lines to channels
*/
void dmaReqAssign(uint32 channel,uint32 reqline)
{
register uint32 i=0U,j=0U;
i = channel >> 2U; /* Find the register to configure */
j = channel -(i<<2U); /* Find the offset of the type */
j = 3U-j; /* reverse the byte order */
j = j<<3U; /* find the bit location */
/* mapping channel 'i' to request line 'j' */
dmaREG->DREQASI[i] &= ~(0xffU<<j);
dmaREG->DREQASI[i] |= (reqline<<j);
}
/** @fn uint32 dmaGetReq(uint32 channel)
* @brief Gets the request line number mapped to the selected channel
* @param[in] channel DMA channel
*
* This function returns the request line number mapped to the selected channel
*/
uint32 dmaGetReq(uint32 channel)
{
register uint32 i=0U,j=0U;
i = channel >> 2U; /* Find the register to configure */
j = channel -(i<<2U); /* Find the offset of the type */
j = 3U-j; /* reverse the byte order */
j = j<<3U; /* find the bit location */
return ((dmaREG->DREQASI[i] >> j) &0xffU);
}
/** @fn void dmaSetCtrlPacket(uint32 channel)
* @brief Initializes the DMA Driver
*
* This function sets control packet
*/
void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT)
{
register uint32 i=0U,j=0U;
dmaRAMREG->PCP[channel].ISADDR = g_dmaCTRLPKT.SADD;
dmaRAMREG->PCP[channel].IDADDR = g_dmaCTRLPKT.DADD;
dmaRAMREG->PCP[channel].ITCOUNT = (g_dmaCTRLPKT.FRCNT << 16U) | g_dmaCTRLPKT.ELCNT;
dmaRAMREG->PCP[channel].CHCTRL = (g_dmaCTRLPKT.RDSIZE << 14U) | (g_dmaCTRLPKT.WRSIZE << 12U) | (g_dmaCTRLPKT.TTYPE << 8U)| \
(g_dmaCTRLPKT.ADDMODERD << 3U ) | (g_dmaCTRLPKT.ADDMODEWR << 1U ) | (g_dmaCTRLPKT.AUTOINIT);
dmaRAMREG->PCP[channel].CHCTRL |= (g_dmaCTRLPKT.CHCTRL << 16U);
dmaRAMREG->PCP[channel].EIOFF = (g_dmaCTRLPKT.ELDOFFSET << 16U) | (g_dmaCTRLPKT.ELSOFFSET);
dmaRAMREG->PCP[channel].FIOFF = (g_dmaCTRLPKT.FRDOFFSET << 16U) | (g_dmaCTRLPKT.FRSOFFSET);
i = channel >> 3U; /* Find the register to write */
j = channel -(i << 3U); /* Find the offset of the 4th bit */
j = 7U -j; /* Reverse the order of the 4th bit offset */
j = j<<2U; /* Find the bit location of the 4th bit to write */
dmaREG->PAR[i] &= ~(0xfU<<j);
dmaREG->PAR[i] |= (g_dmaCTRLPKT.PORTASGN<<j);
}
/** @fn void dmaSetChEnable(uint32 channel,uint32 type)
* @brief Enable channel
* @param[in] channel DMA channel
* @param[in] type Type of triggering
* - DMA_HW: Enables the selected DMA channel for hardware triggering
* - DMA_SW: Enables the selected DMA channel for software triggering
*
* This function enables the DMA channel for hardware or software triggering
*/
void dmaSetChEnable(uint32 channel,uint32 type)
{
if(type == DMA_HW)
{
dmaREG->HWCHENAS = (1U << channel);
}
else if(type == DMA_SW)
{
dmaREG->SWCHENAS = (1U << channel);
}
else
{
/** Empty */
}
}
/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
* @brief Assign Priority to the channel
* @param[in] channel DMA channel
* @param[in] priority Priority queue to which channel needs to be assigned
* - LOWPRIORITY : The selected channel will be assigned to low priority queue
* - HIGHPRIORITY: The selected channel will be assigned to high priority queue
*
* This function assigns the selected priority to the selected channel
*/
void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority)
{
if (priority == LOWPRIORITY)
{
dmaREG->CHPRIOR |= 1U << channel;
}
else
{
dmaREG->CHPRIOS |= 1U << channel;
}
}
/** @fn void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
* @brief Enable selected interrupt
* @param[in] channel DMA channel
* @param[in] inttype Interrupt to be enabled
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
* - BER: Bus Error Interrupt will be disabled for the selected channel
*
* This function enables the selected interrupt for the selected channel
*/
void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype)
{
dmaREG->GCHIENAS = 1 << channel;
switch (inttype)
{
case FTC: dmaREG->FTCINTENAS |= 1U << channel;
break;
case LFS: dmaREG->LFSINTENAS |= 1U << channel;
break;
case HBC: dmaREG->HBCINTENAS |= 1U << channel;
break;
case BTC: dmaREG->BTCINTENAS |= 1U << channel;
break;
default :
break;
}
}
/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
* @brief Disable selected interrupt
* @param[in] channel DMA channel
* @param[in] inttype Interrupt to be disabled
* - FTC: Frame Transfer Complete Interrupt will be disabled for the selected channel
* - LFS: Last Frame Transfer Started Interrupt will be disabled for the selected channel
* - HBC: First Half Of Block Complete Interrupt will be disabled for the selected channel
* - BTC: Block transfer complete Interrupt will be disabled for the selected channel
* - BER: Bus Error Interrupt will be disabled for the selected channel
*
* This function disables the selected interrupt for the selected channel
*/
void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype)
{
switch (inttype)
{
case FTC: dmaREG->FTCINTENAR |= 1U << channel;
break;
case LFS: dmaREG->LFSINTENAR |= 1U << channel;
break;
case HBC: dmaREG->HBCINTENAR |= 1U << channel;
break;
case BTC: dmaREG->BTCINTENAR |= 1U << channel;
break;
default :
break;
}
}
/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
* @brief Configure start and end address of the region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
* @param[in] start_add Start address of the the region
* @param[in] end_add End address of the region
*
* This function configure start and end address of the selected region
*/
void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add)
{
dmaREG->DMAMPR[region].STARTADD = start_add;
dmaREG->DMAMPR[region].ENDADD = end_add;
}
/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
* @brief Enable the selected region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
* @param[in] access Access permission of the selected region
* - FULLACCESS
* - READONLY
* - WRITEONLY
* - NOACCESS
* @param[in] intenable Interrupt to be enabled or not
* - INTERRUPT_ENABLE : Enable interrupt for the selected region
* - INTERRUPT_DISABLE: Disable interrupt for the selected region
*
* This function enables the selected region with selected access permission with or without interrupt enable
*/
void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable)
{
/* Enable the region */
dmaREG->DMAMPCTRL |= 1U << (region*8U);
/* Set access permission for the region */
dmaREG->DMAMPCTRL |= access << ((region*8U) + 1U);
/* Enable or Disable interrupt */
dmaREG->DMAMPCTRL |= intenable << ((region*8U) + 3U);
}
/** @fn void dmaDisableRegion(dmaREGION_t region)
* @brief Disable the selected region
* @param[in] region Memory Region
* - DMA_REGION0
* - DMA_REGION1
* - DMA_REGION2
* - DMA_REGION3
*
* This function disables the selected region(no address checking done).
*/
void dmaDisableRegion(dmaREGION_t region)
{
dmaREG->DMAMPCTRL &= ~(1U << (region*8U));
}
/** @fn void dmaEnableParityCheck(void)
* @brief Enable Parity Check
*
* This function enables parit check
*/
void dmaEnableParityCheck(void)
{
dmaREG->DMAPCR = 0x5U;
}
/** @fn void dmaDisableParityCheck(void)
* @brief Disable Parity Check
*
* This function disables parity check
*/
void dmaDisableParityCheck(void)
{
dmaREG->DMAPCR = 0xAU;
}

82
bsp/rm48x50/HALCoGen/source/sys_main.c
View File

@ -1,82 +0,0 @@
/** @file sys_main.c
* @brief Application main file
* @date 29.May.2013
* @version 03.05.02
*
* This file contains an empty main function,
* which can be used for the application.
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* we will use our own main and get rid off everything from HALCoGen here */
#if 0
#include <stdint.h>
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
#include "system.h"
/* USER CODE BEGIN (1) */
/* Include HET header file - types, definitions and function declarations for system driver */
#include "het.h"
#include "esm.h"
#include "sci.h"
#include "rti.h"
/* Task1 */
void vTaskDelay(int t)
{
for (; t; t--)
{
int i;
for(i = 100000;i ; i--)
{
}
}
}
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
uint8_t sci_buf;
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
/* Set high end timer GIO port hetPort pin direction to all output */
gioSetDirection(hetPORT1, 0xFFFFFFFF);
sciInit();
rtiInit();
rtiStartCounter(rtiCOUNTER_BLOCK1);
rtiEnableNotification(rtiNOTIFICATION_COMPARE3);
_enable_IRQ();
sciReceive(scilinREG, 1, &sci_buf);
for(;;)
{
gioSetBit(hetPORT1, 17, gioGetBit(hetPORT1, 17) ^ 1);
/* Taggle HET[1] with timer tick */
/*sciSendByte(scilinREG, 'b');*/
vTaskDelay(100);
/*sciSendByte(scilinREG, 'a');*/
}
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
#endif
/* USER CODE END */

403
bsp/rm48x50/HALCoGen/source/sys_mpu.asm
View File

@ -1,403 +0,0 @@
;-------------------------------------------------------------------------------
; sys_mpu.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initalize Mpu
.def _mpuInit_
.asmfunc
_mpuInit_
stmfd sp!, {r0}
; Disable mpu
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
; Disable background region
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
; Setup region 1
mov r0, #0
mcr p15, #0, r0, c6, c2, #0
ldr r0, r1Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1000
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 2
mov r0, #1
mcr p15, #0, r0, c6, c2, #0
ldr r0, r2Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0600
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region
mov r0, #2
mcr p15, #0, r0, c6, c2, #0
ldr r0, r3Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 4
mov r0, #3
mcr p15, #0, r0, c6, c2, #0
ldr r0, r4Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 5
mov r0, #4
mcr p15, #0, r0, c6, c2, #0
ldr r0, r5Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0000
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 6
mov r0, #5
mcr p15, #0, r0, c6, c2, #0
ldr r0, r6Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0000
orr r0, r0, #0x0300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 7
mov r0, #6
mcr p15, #0, r0, c6, c2, #0
ldr r0, r7Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1200
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 8
mov r0, #7
mcr p15, #0, r0, c6, c2, #0
ldr r0, r8Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 9
mov r0, #8
mcr p15, #0, r0, c6, c2, #0
ldr r0, r9Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 10
mov r0, #9
mcr p15, #0, r0, c6, c2, #0
ldr r0, r10Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0010
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))
mcr p15, #0, r0, c6, c1, #2
; Setup region 11
mov r0, #10
mcr p15, #0, r0, c6, c2, #0
ldr r0, r11Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1100
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0))
mcr p15, #0, r0, c6, c1, #2
; Setup region 12
mov r0, #11
mcr p15, #0, r0, c6, c2, #0
ldr r0, r12Base
mcr p15, #0, r0, c6, c1, #0
mov r0, #0x0008
orr r0, r0, #0x1300
mcr p15, #0, r0, c6, c1, #4
movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0))
mcr p15, #0, r0, c6, c1, #2
; Enable mpu background region
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
; Enable mpu
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
r1Base .word 0x00000000
r2Base .word 0x00000000
r3Base .word 0x08000000
r4Base .word 0x08400000
r5Base .word 0x60000000
r6Base .word 0x80000000
r7Base .word 0xF0000000
r8Base .word 0xFC000000
r9Base .word 0xFE000000
r10Base .word 0xFF000000
r11Base .word 0x08001000
r12Base .word 0x20000000
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Mpu
.def _mpuEnable_
.asmfunc
_mpuEnable_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Mpu
.def _mpuDisable_
.asmfunc
_mpuDisable_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
dsb
mcr p15, #0, r0, c1, c0, #0
isb
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Mpu background region
.def _mpuEnableBackgroundRegion_
.asmfunc
_mpuEnableBackgroundRegion_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Mpu background region
.def _mpuDisableBackgroundRegion_
.asmfunc
_mpuDisableBackgroundRegion_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x20000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Returns number of implemented Mpu regions
.def _mpuGetNumberOfRegions_
.asmfunc
_mpuGetNumberOfRegions_
mrc p15, #0, r0, c0, c0, #4
uxtb r0, r0, ROR #8
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Returns the type of the implemented mpu regions
.def _mpuAreRegionsSeparate_
.asmfunc
_mpuAreRegionsSeparate_
mrc p15, #0, r0, c0, c0, #4
uxtb r0, r0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set mpu region number
.def _mpuSetRegion_
.asmfunc
_mpuSetRegion_
mcr p15, #0, r0, c6, c2, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get mpu region number
.def _mpuGetRegion_
.asmfunc
_mpuGetRegion_
mrc p15, #0, r0, c6, c2, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set base address
.def _mpuSetRegionBaseAddress_
.asmfunc
_mpuSetRegionBaseAddress_
mcr p15, #0, r0, c6, c1, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get base address
.def _mpuGetRegionBaseAddress_
.asmfunc
_mpuGetRegionBaseAddress_
mrc p15, #0, r0, c6, c1, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set type and permission
.def _mpuSetRegionTypeAndPermission_
.asmfunc
_mpuSetRegionTypeAndPermission_
orr r0, r0, r1
mcr p15, #0, r0, c6, c1, #4
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get type
.def _mpuGetRegionType_
.asmfunc
_mpuGetRegionType_
mrc p15, #0, r0, c6, c1, #4
bic r0, r0, #0xFF00
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get permission
.def _mpuGetRegionPermission_
.asmfunc
_mpuGetRegionPermission_
mrc p15, #0, r0, c6, c1, #4
bic r0, r0, #0xFF
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set region size register value
.def _mpuSetRegionSizeRegister_
.asmfunc
_mpuSetRegionSizeRegister_
mcr p15, #0, r0, c6, c1, #2
bx lr
.endasmfunc
;-------------------------------------------------------------------------------

602
bsp/rm48x50/HALCoGen/source/sys_pcr.c
View File

@ -1,602 +0,0 @@
/** @file sys_pcr.c
* @brief PCR Driver Implementation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_pcr.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* USER CODE BEGIN (1) */
/* USER CODE END */
/** @fn void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
* @brief Set the peripheral protection of the selected frame
* @param[in] peripheral_Frame - Peripheral frame to be protected
*
* This function sets the protection for the selected frame.
*/
void peripheral_Frame_Protection_Set(peripheral_Frame_Select_t peripheral_Frame)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
uint32 chip_select_grp;
uint32 Quarant_selct;
chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
if (chip_select_grp >= 3U)
{
pcrREG->PPROTSET3 = Quarant_selct;
}
else if (chip_select_grp >= 2U)
{
pcrREG->PPROTSET2 = Quarant_selct;
}
else if (chip_select_grp >= 1U)
{
pcrREG->PPROTSET1 = Quarant_selct;
}
else
{
pcrREG->PPROTSET0 = Quarant_selct;
}
/* USER CODE BEGIN (3) */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
/** @fn void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
* @brief Clear the peripheral protection of the selected frame
* @param[in] peripheral_Frame - Peripheral frame to be out of protection
*
* This function clears the protection set for the selected frame.
*/
void peripheral_Frame_Protection_Clr(peripheral_Frame_Select_t peripheral_Frame)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
uint32 chip_select_grp;
uint32 Quarant_selct;
chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
if (chip_select_grp >= 3U)
{
pcrREG->PPROTCLR3 = Quarant_selct;
}
else if (chip_select_grp >= 2U)
{
pcrREG->PPROTCLR2 = Quarant_selct;
}
else if (chip_select_grp >= 1U)
{
pcrREG->PPROTCLR1 = Quarant_selct;
}
else
{
pcrREG->PPROTCLR0 = Quarant_selct;
}
/* USER CODE BEGIN (6) */
/* USER CODE END */
}
/* USER CODE BEGIN (7) */
/* USER CODE END */
/** @fn void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
* @brief Take the selected peripheral to powerdown
* @param[in] peripheral_Frame - Peripheral frame to be taken to powerdown
*
* This function will set the selected peripheral frame to powerdown.
*/
void peripheral_Frame_Powerdown_Set(peripheral_Frame_Select_t peripheral_Frame)
{
/* USER CODE BEGIN (8) */
/* USER CODE END */
uint32 chip_select_grp;
uint32 Quarant_selct;
chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
if (chip_select_grp >= 3U)
{
pcrREG->PSPWRDWNSET3 = Quarant_selct;
}
else if (chip_select_grp >= 2U)
{
pcrREG->PSPWRDWNSET2 = Quarant_selct;
}
else if (chip_select_grp >= 1U)
{
pcrREG->PSPWRDWNSET1 = Quarant_selct;
}
else
{
pcrREG->PSPWRDWNSET0 = Quarant_selct;
}
/* USER CODE BEGIN (9) */
/* USER CODE END */
}
/* USER CODE BEGIN (10) */
/* USER CODE END */
/** @fn void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
* @brief Bring the selected peripheral frame out of powerdown
* @param[in] peripheral_Frame - Peripheral frame to be taken out of powerdown
*
* This function will bring the selected peripheral frame out of powerdown.
*/
void peripheral_Frame_Powerdown_Clr(peripheral_Frame_Select_t peripheral_Frame)
{
/* USER CODE BEGIN (11) */
/* USER CODE END */
uint32 chip_select_grp;
uint32 Quarant_selct;
chip_select_grp = (peripheral_Frame.Peripheral_CS >> 3U);
Quarant_selct = (uint32)(peripheral_Frame.Peripheral_Quadrant << ((peripheral_Frame.Peripheral_CS & 7U) << 2U));
if (chip_select_grp >= 3U)
{
pcrREG->PSPWRDWNCLR3 = Quarant_selct;
}
else if (chip_select_grp >= 2U)
{
pcrREG->PSPWRDWNCLR2 = Quarant_selct;
}
else if (chip_select_grp >= 1U)
{
pcrREG->PSPWRDWNCLR1 = Quarant_selct;
}
else
{
pcrREG->PSPWRDWNCLR0 = Quarant_selct;
}
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
/* USER CODE BEGIN (13) */
/* USER CODE END */
/** @fn void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
* @brief Set the peripheral memory protection of the selected frame
* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be protected
*
* This function sets the protection for the selected peripheral memory frame.
*/
void peripheral_Mem_Frame_Prot_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
{
/* USER CODE BEGIN (14) */
/* USER CODE END */
uint32 chip_select_grp;
chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
if (chip_select_grp >= 1U)
{
pcrREG->PMPROTSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
}
else
{
pcrREG->PMPROTSET0 = (1U << peripheral_Memory_Frame_CS);
}
/* USER CODE BEGIN (15) */
/* USER CODE END */
}
/* USER CODE BEGIN (16) */
/* USER CODE END */
/** @fn void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
* @brief Clear the peripheral memory protection of the selected frame
* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be cleared from protection
*
* This function clears the protection set for the selected peripheral memory frame.
*/
void peripheral_Mem_Frame_Prot_Clr(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
{
/* USER CODE BEGIN (17) */
/* USER CODE END */
uint32 chip_select_grp;
chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
if (chip_select_grp >= 1U)
{
pcrREG->PMPROTCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
}
else
{
pcrREG->PMPROTCLR0 = (1U << peripheral_Memory_Frame_CS);
}
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
/* USER CODE BEGIN (19) */
/* USER CODE END */
/** @fn void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
* @brief Take the selected peripheral memory frame to powerdown
* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken to powerdown
*
* This function will set the selected peripheral memory frame to powerdown.
*/
void peripheral_Mem_Frame_Pwrdwn_Set(peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
{
/* USER CODE BEGIN (20) */
/* USER CODE END */
uint32 chip_select_grp;
chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
if (chip_select_grp >= 1U)
{
pcrREG->PSPWRDWNSET1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
}
else
{
pcrREG->PSPWRDWNSET0 = (1U << peripheral_Memory_Frame_CS);
}
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
/* USER CODE BEGIN (22) */
/* USER CODE END */
/** @fn void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
* @brief Bring the selected peripheral Memory frame out of powerdown
* @param[in] peripheral_Memory_Frame_CS - Peripheral memory frame to be taken out of powerdown
*
* This function will bring the selected peripheral memory frame out of powerdown.
*/
void peripheral_Mem_Frame_Pwrdwn_Clr (peripheral_MemoryFrame_CS_t peripheral_Memory_Frame_CS)
{
/* USER CODE BEGIN (23) */
/* USER CODE END */
uint32 chip_select_grp;
chip_select_grp = (peripheral_Memory_Frame_CS >> 5U);
if (chip_select_grp >= 1U)
{
pcrREG->PSPWRDWNCLR1 = (1U << (peripheral_Memory_Frame_CS & 0xFU));
}
else
{
pcrREG->PSPWRDWNCLR0 = (1U << peripheral_Memory_Frame_CS);
}
/* USER CODE BEGIN (24) */
/* USER CODE END */
}
/* USER CODE BEGIN (25) */
/* USER CODE END */
/** @fn void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
* @brief Set the peripheral protection of all the selected frames
* @param[in] peripheral_Quad_CS - All Peripheral frames to be protected
*
* This function sets the protection for all the selected frames.
*/
void peripheral_Protection_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
{
/* USER CODE BEGIN (26) */
/* USER CODE END */
pcrREG->PPROTSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
pcrREG->PPROTSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
pcrREG->PPROTSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
pcrREG->PPROTSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
/* USER CODE BEGIN (27) */
/* USER CODE END */
}
/* USER CODE BEGIN (28) */
/* USER CODE END */
/** @fn void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
* @brief Clear the peripheral protection of all the selected frames
* @param[in] peripheral_Quad_CS - All Peripheral frames to be out of protection.
*
* This function clears the protection set for all the selected frame.
*/
void peripheral_Protection_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
{
/* USER CODE BEGIN (29) */
/* USER CODE END */
pcrREG->PPROTCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
pcrREG->PPROTCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
pcrREG->PPROTCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
pcrREG->PPROTCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
/* USER CODE BEGIN (30) */
/* USER CODE END */
}
/* USER CODE BEGIN (31) */
/* USER CODE END */
/** @fn void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
* @brief Take all the selected peripheral frame to powerdown
* @param[in] peripheral_Quad_CS - Peripheral frames to be taken to powerdown
*
* This function will set all the selected peripheral frame to powerdown.
*/
void peripheral_Powerdown_Set(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
{
/* USER CODE BEGIN (32) */
/* USER CODE END */
pcrREG->PSPWRDWNSET0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
pcrREG->PSPWRDWNSET1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
pcrREG->PSPWRDWNSET2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
pcrREG->PSPWRDWNSET3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
/* USER CODE BEGIN (33) */
/* USER CODE END */
}
/* USER CODE BEGIN (34) */
/* USER CODE END */
/** @fn void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
* @brief Bring all the selected peripheral frame out of powerdown
* @param[in] peripheral_Quad_CS - Peripheral frames to be taken out of powerdown
*
* This function will bring all the selected peripheral frame out of powerdown.
*/
void peripheral_Powerdown_Clr(peripheral_Quad_ChipSelect_t peripheral_Quad_CS)
{
/* USER CODE BEGIN (35) */
/* USER CODE END */
pcrREG->PSPWRDWNCLR0 = peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7;
pcrREG->PSPWRDWNCLR1 = peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15;
pcrREG->PSPWRDWNCLR2 = peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23;
pcrREG->PSPWRDWNCLR3 = peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31;
/* USER CODE BEGIN (36) */
/* USER CODE END */
}
/* USER CODE BEGIN (37) */
/* USER CODE END */
/** @fn void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
* @brief Set the peripheral memory protection of all the selected frame
* @param[in] peripheral_Memory_CS - Peripheral memory frames to be protected
*
* This function sets the protection for all the selected peripheral memory frame.
*/
void peripheral_Memory_Protection_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
{
/* USER CODE BEGIN (38) */
/* USER CODE END */
pcrREG->PMPROTSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
pcrREG->PMPROTSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
/* USER CODE BEGIN (39) */
/* USER CODE END */
}
/* USER CODE BEGIN (40) */
/* USER CODE END */
/** @fn void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
* @brief Clear the peripheral memory protection of all the selected frame
* @param[in] peripheral_Memory_CS - Peripheral memory frames to be cleared from protection
*
* This function clears the protection set for all the selected peripheral memory frame.
*/
void peripheral_Memory_Protection_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
{
/* USER CODE BEGIN (41) */
/* USER CODE END */
pcrREG->PMPROTCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
pcrREG->PMPROTCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
/* USER CODE BEGIN (42) */
/* USER CODE END */
}
/* USER CODE BEGIN (43) */
/* USER CODE END */
/** @fn void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
* @brief Take all the selected peripheral memory frame to powerdown
* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken to powerdown
*
* This function will set all the selected peripheral memory frame to powerdown.
*/
void peripheral_Memory_Powerdown_Set(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
{
/* USER CODE BEGIN (44) */
/* USER CODE END */
pcrREG->PSPWRDWNSET0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
pcrREG->PSPWRDWNSET1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
/* USER CODE BEGIN (45) */
/* USER CODE END */
}
/* USER CODE BEGIN (46) */
/* USER CODE END */
/** @fn void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
* @brief Bring all the selected peripheral Memory frame out of powerdown
* @param[in] peripheral_Memory_CS - Peripheral memory frames to be taken out of powerdown
*
* This function will bring all the selected peripheral memory frame out of powerdown.
*/
void peripheral_Memory_Powerdown_Clr(peripheral_Memory_ChipSelect_t peripheral_Memory_CS)
{
/* USER CODE BEGIN (47) */
/* USER CODE END */
pcrREG->PSPWRDWNCLR0 = peripheral_Memory_CS.Peripheral_Mem_CS0_31;
pcrREG->PSPWRDWNCLR1 = peripheral_Memory_CS.Peripheral_Mem_CS32_63;
/* USER CODE BEGIN (48) */
/* USER CODE END */
}
/* USER CODE BEGIN (49) */
/* USER CODE END */
/** @fn peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void)
* @brief Get the powerdown status of the peripheral frames.
* @return Peripheral frames power down status
*
* This function gets the powerdown status of the peripheral frames.
*/
peripheral_Quad_ChipSelect_t peripheral_Powerdown_Status(void)
{
/* USER CODE BEGIN (50) */
/* USER CODE END */
peripheral_Quad_ChipSelect_t peripheral_Quad_CS;
peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7 = pcrREG->PSPWRDWNSET0;
peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15 = pcrREG->PSPWRDWNSET1;
peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23 = pcrREG->PSPWRDWNSET2;
peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31 = pcrREG->PSPWRDWNSET3;
/* USER CODE BEGIN (51) */
/* USER CODE END */
return peripheral_Quad_CS;
}
/* USER CODE BEGIN (52) */
/* USER CODE END */
/** @fn peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void)
* @brief Get the protection status of the peripheral frames
* @return Peripheral frames protection status
*
* This function gets the protection status of the peripheral frames.
*/
peripheral_Quad_ChipSelect_t peripheral_Protection_Status(void)
{
/* USER CODE BEGIN (53) */
/* USER CODE END */
peripheral_Quad_ChipSelect_t peripheral_Quad_CS;
peripheral_Quad_CS.Peripheral_Quad0_3_CS0_7 = pcrREG->PPROTSET0;
peripheral_Quad_CS.Peripheral_Quad4_7_CS8_15 = pcrREG->PPROTSET1;
peripheral_Quad_CS.Peripheral_Quad8_11_CS16_23 = pcrREG->PPROTSET2;
peripheral_Quad_CS.Peripheral_Quad12_15_CS24_31 = pcrREG->PPROTSET3;
/* USER CODE BEGIN (54) */
/* USER CODE END */
return peripheral_Quad_CS;
}
/* USER CODE BEGIN (55) */
/* USER CODE END */
/** @fn peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void)
* @brief Get the protection set of all the peripheral Memory frame
* @return Peripheral memory frames protection status
*
* This function gets the protection status of all the peripheral Memory frame.
*/
peripheral_Memory_ChipSelect_t peripheral_Memory_Protection_Status(void)
{
/* USER CODE BEGIN (56) */
/* USER CODE END */
peripheral_Memory_ChipSelect_t peripheral_Memory_CS;
peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PMPROTSET0;
peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PMPROTSET1;
/* USER CODE BEGIN (57) */
/* USER CODE END */
return peripheral_Memory_CS;
}
/* USER CODE BEGIN (58) */
/* USER CODE END */
/** @fn peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void)
* @brief Get the powerdown status of all the peripheral Memory frame
* @return Peripheral memory frames powerdown status
*
* This function gets the powerdown status of all the peripheral Memory frame.
*/
peripheral_Memory_ChipSelect_t Periipheral_Memory_Powerdown_Status(void)
{
/* USER CODE BEGIN (59) */
/* USER CODE END */
peripheral_Memory_ChipSelect_t peripheral_Memory_CS;
peripheral_Memory_CS.Peripheral_Mem_CS0_31 = pcrREG->PSPWRDWNSET0;
peripheral_Memory_CS.Peripheral_Mem_CS32_63 = pcrREG->PSPWRDWNSET1;
/* USER CODE BEGIN (60) */
/* USER CODE END */
return peripheral_Memory_CS;
}
/* USER CODE BEGIN (61) */
/* USER CODE END */

32
bsp/rm48x50/HALCoGen/source/sys_phantom.c
View File

@ -1,32 +0,0 @@
/** @file sys_phantom.c
* @brief Phantom Interrupt Source File
* @date 29.May.2013
* @version 03.05.02
*
* This file contains:
* - Phantom Interrupt Handler
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_common.h"
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Phantom Interrupt Handler */
/* USER CODE BEGIN (1) */
/* USER CODE END */
#pragma CODE_STATE(phantomInterrupt, 32)
#pragma INTERRUPT(phantomInterrupt, IRQ)
void phantomInterrupt(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
}
/* USER CODE BEGIN (3) */
/* USER CODE END */

348
bsp/rm48x50/HALCoGen/source/sys_pmm.c
View File

@ -1,348 +0,0 @@
/** @file sys_pmm.c
* @brief PCR Driver Implementation File
* @date 29.May.2013
* @version 03.05.02
*
*/
/* (c) Texas Instruments 2009-2013, All rights reserved. */
#include "sys_pmm.h"
/** @fn void pmmInit(void)
* @brief Initializes the PMM Driver
*
* This function initializes the PMM module.
*/
void pmmInit(void)
{
/*Disable clocks to all logic domains*/
pmmREG->PDCLKDISREG = 0xFU;
/*Enable or disable clock to pmctrl_wakeup block and automatic clock wake up*/
pmmREG->GLOBALCTRL1 = (0U << 8U) | (0U << 0U); /*from GUI*/
/*Power on the logic power domains*/
pmmREG->LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
/*Power on the memory-only power domains*/
pmmREG->MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
/*wait till Logic Power Domain PD2 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD2] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD3 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD3] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD4 turns OFF*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD4] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
{
}/* Wait */
/*wait till Logic Power Domain PD5 turns ON*/
while((pmmREG->LOGICPDPWRSTAT[PMM_LOGICPD5] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD1 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD1] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD2 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD2] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
/*wait till Memory Only Power Domain RAM_PD3 turns ON*/
while((pmmREG->MEMPDPWRSTAT[PMM_MEMPD3] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
{
/* Enable clocks for the selected logic domain */
pmmREG->PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
}
}
/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
* @brief Turns on Logic Power Domain
* @param[in] logicPD - Power Domain to be turned on
* - PMM_LOGICPD2: Power domain PD2 will be turned on
* - PMM_LOGICPD3: Power domain PD3 will be turned on
* - PMM_LOGICPD4: Power domain PD4 will be turned on
* - PMM_LOGICPD5: Power domain PD5 will be turned on
*
* This function turns on the selected Logic Power Domain
*
*/
void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD)
{
if (logicPD != PMM_LOGICPD1)
{
/* Power on the domain */
if (logicPD == PMM_LOGICPD2)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
}
else if (logicPD == PMM_LOGICPD3)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
}
else if (logicPD == PMM_LOGICPD4)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
}
else
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0x5U << 0U);
}
/* Wait until the power domain turns on */
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
if ((pmmREG->GLOBALCTRL1 & PMM_GLOBALCTRL1_AUTOCLKWAKEENA) == 0U)
{
/* Enable clocks to the power domain */
pmmREG->PDCLKDISCLRREG = 1U << (uint32)logicPD;
}
}
}
/** @fn void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
* @brief Turns on Memory Power Domain
* @param[in] memPD - Power Domain to be tured on
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned on
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned on
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned on
*
* This function turns on the selected Memory Power Domain
*
*/
void pmmTurnONMemPowerDomain(pmm_MemPD_t memPD)
{
/* Power on the domain */
if (memPD == PMM_MEMPD1)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0x5U << 24U);
}
else if (memPD == PMM_MEMPD2)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0x5U << 16U);
}
else
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0x5U << 8U);
}
/*Wait until the power domain turns on*/
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
}/* Wait */
}
/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
* @brief Turns off Logic Power Domain
* @param[in] logicPD - Power Domain to be tured off
* - PMM_LOGICPD2: Power domain PD2 will be turned off
* - PMM_LOGICPD3: Power domain PD3 will be turned off
* - PMM_LOGICPD4: Power domain PD4 will be turned off
* - PMM_LOGICPD5: Power doamin PD5 will be turned off
*
* This function turns off the selected Logic Power Domain
*
*/
void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD)
{
if (logicPD != PMM_LOGICPD1)
{
/* Disable all clocks to the power domain */
pmmREG->PDCLKDISSETREG = 1U << (uint32)logicPD;
/* Power down the domain */
if (logicPD == PMM_LOGICPD2)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
}
else if (logicPD == PMM_LOGICPD3)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
}
else if (logicPD == PMM_LOGICPD4)
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
}
else
{
pmmREG->LOGICPDPWRCTRL0 = (pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U) | (0xAU << 0U);
}
/* Wait until the power domain turns off */
while((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_LOGICPDPWRSTAT) != 0U)
{
}/* Wait */
}
}
/** @fn void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
* @brief Turns off Memory Power Domain
* @param[in] memPD - Power Domain to be tured off
* - PMM_MEMPD1: Power domain RAM_PD1 will be turned off
* - PMM_MEMPD2: Power domain RAM_PD2 will be turned off
* - PMM_MEMPD3: Power domain RAM_PD3 will be turned off
*
* This function turns off the selected Memory Power Domain
*
*/
void pmmTurnOFFMemPowerDomain(pmm_MemPD_t memPD)
{
/* Power down the domain */
if (memPD == PMM_MEMPD1)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xF0FFFFFFU) | (0xAU << 24U);
}
else if (memPD == PMM_MEMPD2)
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFF0FFFFU) | (0xAU << 16U);
}
else
{
pmmREG->MEMPDPWRCTRL0 = (pmmREG->MEMPDPWRCTRL0 & 0xFFFFF0FFU) | (0xAU << 8U);
}
/*Wait until the power domain turns off*/
while((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_MEMPDPWRSTAT) != 0U)
{
}/* Wait */
}
/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
* @brief Check if the power domain is active or not
* @param[in] logicPD - Power Domain to be be checked
* - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not
* - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not
* - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not
* - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not
* @return The function will return:
* - TRUE : When the selected power domain is in Active state.
* - FALSE: When the selected power domain is in OFF state.
*
* This function checks whether the selected power domain is active or not.
*
*/
boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD)
{
boolean status;
if ((pmmREG->LOGICPDPWRSTAT[logicPD] & PMM_LOGICPDPWRSTAT_DOMAINON) == 0U)
{
status = FALSE;
}
else
{
status = TRUE;
}
return status;
}
/** @fn boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
* @brief Check if the power domain is active or not
* @param[in] memPD - Power Domain to be tured off
* - PMM_MEMPD1: Checks whether Power domain RAM_PD1 is active or not
* - PMM_MEMPD2: Checks whether Power domain RAM_PD2 is active or not
* - PMM_MEMPD3: Checks whether Power domain RAM_PD3 is active or not
* @return The function will return:
* - TRUE : When the selected power domain is in Active state.
* - FALSE: When the selected power domain is in OFF state.
*
* This function checks whether the selected power domain is active or not.
*
*/
boolean pmmIsMemPowerDomainActive(pmm_MemPD_t memPD)
{
boolean status;
if ((pmmREG->MEMPDPWRSTAT[memPD] & PMM_MEMPDPWRSTAT_DOMAINON) == 0U)
{
status = FALSE;
}
else
{
status = TRUE;
}
return status;
}
/** @fn void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
* @brief Get the initial or current values of the configuration register
* @param[in] *config_reg - pointer to the struct to which the initial or current value of the configuration registers need to be stored
* @param[in] type - whether initial or current value of the configuration registers need to be stored
* - InitialValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* - CurrentValue: initial value of the configuration registers will be stored in the struct pointed by config_reg
* This function will copy the initial or current value (depending on the parameter 'type') of the configuration registers to the struct pointed by config_reg
*/
void pmmGetConfigValue(pmm_config_reg_t *config_reg, config_value_type_t type)
{
if (type == InitialValue)
{
config_reg->CONFIG_LOGICPDPWRCTRL0 = PMM_LOGICPDPWRCTRL0_CONFIGVALUE;
config_reg->CONFIG_MEMPDPWRCTRL0 = PMM_MEMPDPWRCTRL0_CONFIGVALUE;
config_reg->CONFIG_PDCLKDISREG = PMM_PDCLKDISREG_CONFIGVALUE;
config_reg->CONFIG_GLOBALCTRL1 = PMM_GLOBALCTRL1_CONFIGVALUE;
}
else
{
config_reg->CONFIG_LOGICPDPWRCTRL0 = pmmREG->LOGICPDPWRCTRL0;
config_reg->CONFIG_MEMPDPWRCTRL0 = pmmREG->MEMPDPWRCTRL0;
config_reg->CONFIG_PDCLKDISREG = pmmREG->PDCLKDISREG;
config_reg->CONFIG_GLOBALCTRL1 = pmmREG->GLOBALCTRL1;
}
}
/** @fn void pmmSetMode(pmm_Mode_t mode)
* @brief Set PSCON Compare Block Mode
* @param[in] mode - PSCON Compare Block mode
* - LockStep : PSCON compare block is set to Lock-Step mode
* - SelfTest : PSCON compare block is set to Self-Test mode
* - ErrorForcing : PSCON compare block is set to Error-Forcing mode
* - SelfTestErrorForcing : PSCON compare block is set to Self-Test-Error-Forcing mode
*
* This function sets the PSCON Compare block to the selected mode
*
*/
void pmmSetMode(pmm_Mode_t mode)
{
/* Set PSCON Compare Block Mode */
pmmREG->PRCKEYREG = mode;
}
/** @fn boolean pmmPerformSelfTest(void)
* @brief Perform self test and return the result
*
* @return The function will return
* - TRUE if PSCON compare block passed self-test
* - FALSE if PSCON compare block failed in self-test
*
* This function checks whether PSCON compare block passed the self-test or not.
*
*/
boolean pmmPerformSelfTest(void)
{
boolean status = TRUE;
/*Enter self-test mode*/
pmmREG->PRCKEYREG = SelfTest;
/*Wait till self test is completed*/
while ((pmmREG->LPDDCSTAT1 & 0xFU) != 0xFU)
{
}/* Wait */
while ((pmmREG->MPDDCSTAT1 & 0x7U) != 0x7U)
{
}/* Wait */
/*Check whether self-test passed or not*/
if ((pmmREG->LPDDCSTAT2 & 0xFU) != 0U)
{
status = FALSE;
}
if ((pmmREG->MPDDCSTAT2 & 0x7U) != 0U)
{
status = FALSE;
}
/*Enter lock-step mode*/
pmmREG->PRCKEYREG = LockStep;
return status;
}

223
bsp/rm48x50/HALCoGen/source/sys_pmu.asm
View File

@ -1,223 +0,0 @@
;-------------------------------------------------------------------------------
; sys_pmu.asm
;
; (c) Texas Instruments 2009-2013, All rights reserved.
;
.text
.arm
;-------------------------------------------------------------------------------
; Initialize Pmu
; Note: It will reset all counters
.def _pmuInit_
.asmfunc
_pmuInit_
stmfd sp!, {r0}
; set control register
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #(1 << 4) + 6 + 1
mcr p15, #0, r0, c9, c12, #0
; clear flags
mov r0, #0
sub r1, r1, #1
mcr p15, #0, r0, c9, c12, #3
; select counter 0 event
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
; select counter 1 event
mov r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
; select counter 2 event
mov r0, #2
mcr p15, #0, r0, c9, c12, #5 ; select counter
mov r0, #0x11
mcr p15, #0, r0, c9, c13, #1 ; select event
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Counters Global [Cycle, Event [0..2]]
; Note: It will reset all counters
.def _pmuEnableCountersGlobal_
.asmfunc
_pmuEnableCountersGlobal_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #7
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Counters Global [Cycle, Event [0..2]]
.def _pmuDisableCountersGlobal_
.asmfunc
_pmuDisableCountersGlobal_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
bic r0, r0, #1
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Cycle Counter
.def _pmuResetCycleCounter_
.asmfunc
_pmuResetCycleCounter_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #4
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Event Counters [0..2]
.def _pmuResetEventCounters_
.asmfunc
_pmuResetEventCounters_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #2
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Reset Cycle Counter abd Event Counters [0..2]
.def _pmuResetCounters_
.asmfunc
_pmuResetCounters_
stmfd sp!, {r0}
mrc p15, #0, r0, c9, c12, #0
orr r0, r0, #6
mcr p15, #0, r0, c9, c12, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Start Counters [Cycle, 0..2]
.def _pmuStartCounters_
.asmfunc
_pmuStartCounters_
mcr p15, #0, r0, c9, c12, #1
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Stop Counters [Cycle, 0..2]
.def _pmuStopCounters_
.asmfunc
_pmuStopCounters_
mcr p15, #0, r0, c9, c12, #2
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Set Count event
.def _pmuSetCountEvent_
.asmfunc
_pmuSetCountEvent_
lsr r0, r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mcr p15, #0, r1, c9, c13, #1 ; select event
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Cycle Count
.def _pmuGetCycleCount_
.asmfunc
_pmuGetCycleCount_
mrc p15, #0, r0, c9, c13, #0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Event Counter Count Value
.def _pmuGetEventCount_
.asmfunc
_pmuGetEventCount_
lsr r0, r0, #1
mcr p15, #0, r0, c9, c12, #5 ; select counter
mrc p15, #0, r0, c9, c13, #2 ; read event counter
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get Overflow Flags
.def _pmuGetOverflow_
.asmfunc
_pmuGetOverflow_
mrc p15, #0, r0, c9, c12, #3 ; read overflow
mov r1, #0
sub r1, r1, #1
mcr p15, #0, r1, c9, c12, #3 ; clear flags
bx lr
.endasmfunc
;-------------------------------------------------------------------------------

2178
bsp/rm48x50/HALCoGen/source/sys_selftest.c
View File

File diff suppressed because it is too large Load Diff

515
bsp/rm48x50/HALCoGen/source/sys_startup.c
View File

@ -1,4 +1,4 @@
/** @file sys_startup.c
/** @file sys_startup.c
* @brief Startup Source File
* @date 29.May.2013
* @version 03.05.02
@ -15,10 +15,6 @@
/* (c) Texas Instruments 2009-2013, All rights reserved. */
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "sys_common.h"
@ -29,22 +25,13 @@
#include "esm.h"
#include "mibspi.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/* Type Definitions */
typedef void (*handler_fptr)(const uint8 * in, uint8 * out);
/* USER CODE BEGIN (2) */
/* USER CODE END */
/* External Functions */
/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
/*SAFETYMCUSW 122 S MR:20.11 <REVIEWED> "Startup code(exit and abort need to be present)" */
/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 298 S MR: <REVIEWED> "Startup code(handler pointers)" */
/*SAFETYMCUSW 299 S MR: <REVIEWED> "Startup code(typedef for handler pointers in library )" */
@ -55,6 +42,7 @@ typedef void (*handler_fptr)(const uint8 * in, uint8 * out);
/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
#ifdef __TI_COMPILER_VERSION__
#pragma WEAK(__TI_Handler_Table_Base)
#pragma WEAK(__TI_Handler_Table_Limit)
#pragma WEAK(__TI_CINIT_Base)
@ -67,42 +55,37 @@ extern uint32 __TI_CINIT_Limit;
extern uint32 __TI_PINIT_Base;
extern uint32 __TI_PINIT_Limit;
extern uint32 * __binit__;
#endif
extern void main(void);
extern void exit(void);
extern void muxInit(void);
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Startup Routine */
/* USER CODE BEGIN (4) */
/* USER CODE END */
/** @fn void memoryInit(uint32 ram)
* @brief Memory Initialization Driver
*
* This function is called to perform Memory initialization of selected RAM's.
*/
void memoryInit(uint32 ram)
{
/* Enable Memory Hardware Initialization */
systemREG1->MINITGCR = 0xAU;
#pragma CODE_STATE(_c_int00, 32)
#pragma INTERRUPT(_c_int00, RESET)
/* Enable Memory Hardware Initialization for selected RAM's */
systemREG1->MSINENA = ram;
/* Wait until Memory Hardware Initialization complete */
while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U)
{
}/* Wait */
/* Disable Memory Hardware Initialization */
systemREG1->MINITGCR = 0x5U;
}
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
*
* Errata Description:
* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
@ -112,80 +95,40 @@ void _c_int00(void)
{
_esmCcmErrorsClear_();
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (11) */
/* USER CODE END */
_errata_CORTEXR4_66_();
_errata_CORTEXR4_57_();
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
* to identify the cause of the CPU reset. */
/* check for power-on reset condition */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* USER CODE BEGIN (13) */
/* USER CODE END */
_errata_CORTEXR4_66_();
/* USER CODE BEGIN (14) */
/* USER CODE END */
_errata_CORTEXR4_57_();
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
/* Reset caused due
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Clear the Watchdog reset flag in Exception Status register */
/* Add user code here to handle watchdog violation. */
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
@ -193,136 +136,23 @@ void _c_int00(void)
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->ESTATUS1[2]) != 0U)
{
/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
/* USER CODE BEGIN (24) */
/* USER CODE END */
for(;;)
{
}/* Wait */
/* USER CODE BEGIN (25) */
/* USER CODE END */
}
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* Run a diagnostic check on the memory self-test controller.
* This function chooses a RAM test algorithm and runs it on an on-chip ROM.
* The memory self-test is expected to fail. The function ensures that the PBIST controller
* is capable of detecting and indicating a memory self-test failure.
*/
pbistSelfCheck();
/* USER CODE BEGIN (31) */
/* USER CODE END */
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
while((!pbistIsTestCompleted()) == TRUE)
{
}/* Wait */
/* USER CODE BEGIN (33) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
{
memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
}
else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
{
memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
}
else
{
/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
/* USER CODE BEGIN (34) */
/* USER CODE END */
for(;;)
{
}/* Wait */
/* USER CODE BEGIN (35) */
/* USER CODE END */
}
}
/* USER CODE BEGIN (36) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (37) */
/* USER CODE END */
/* Initialize CPU RAM.
* This function uses the system module's hardware for auto-initialization of memories and their
* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
@ -331,273 +161,53 @@ void _c_int00(void)
*/
memoryInit(0x1U);
/* USER CODE BEGIN (38) */
/* USER CODE END */
/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
_coreEnableRamEcc_();
/* USER CODE BEGIN (39) */
/* USER CODE END */
/* Start PBIST on all dual-port memories */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
PBIST test perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
pbistRun( 0x00000000U
| 0x00000000U
| 0x00000800U
| 0x00000200U
| 0x00000040U
| 0x00000080U
| 0x00000100U
| 0x00000004U
| 0x00000008U
| 0x00000010U
| 0x00000400U
| 0x00020000U
| 0x00001000U
| 0x00040000U
| 0x00002000U
| 0x00080000U
| 0x00004000U
| 0x00000000U
| 0x00000000U
,(uint32) PBIST_March13N_DP);
/* USER CODE BEGIN (40) */
/* USER CODE END */
/* Test the CPU ECC mechanism for RAM accesses.
* The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
* in the ECC causes a data abort exception. The data abort handler is written to look for
* deliberately caused exception and to return the code execution to the instruction
* following the one that caused the abort.
*/
checkB0RAMECC();
tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100U);
checkB1RAMECC();
tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100U);
/* USER CODE BEGIN (41) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
while((!pbistIsTestCompleted()) == TRUE)
{
}/* Wait */
/* USER CODE BEGIN (44) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* USER CODE BEGIN (45) */
/* USER CODE END */
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
{
memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U),(uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
}
else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
{
memoryPort1TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA1, (uint32)pbistREG->FSRDL1);
}
else
{
/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
/* USER CODE BEGIN (46) */
/* USER CODE END */
for(;;)
{
}/* Wait */
/* USER CODE BEGIN (47) */
/* USER CODE END */
}
}
/* USER CODE BEGIN (48) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (56) */
/* USER CODE END */
/* Release the MibSPI1 modules from local reset.
* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
*/
mibspiREG1->GCR0 = 0x1U;
/* Release the MibSPI3 modules from local reset.
* This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
*/
mibspiREG3->GCR0 = 0x1U;
/* Release the MibSPI5 modules from local reset.
* This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
*/
mibspiREG5->GCR0 = 0x1U;
/* USER CODE BEGIN (57) */
/* USER CODE END */
/* Initialize all on-chip SRAMs except for MibSPIx RAMs
* The MibSPIx modules have their own auto-initialization mechanism which is triggered
* as soon as the modules are brought out of local reset.
*/
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
*/
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
memoryInit( (1U << 1U)
| (1U << 2U)
| (1U << 5U)
| (1U << 6U)
| (1U << 10U)
| (1U << 8U)
| (1U << 14U)
| (1U << 3U)
| (1U << 4U)
| (1U << 15U)
| (1U << 16U)
| (0U << 13U) );
/* Test the parity protection mechanism for peripheral RAMs
NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
/* USER CODE BEGIN (58) */
/* USER CODE END */
het1ParityCheck();
/* USER CODE BEGIN (59) */
/* USER CODE END */
htu1ParityCheck();
/* USER CODE BEGIN (60) */
/* USER CODE END */
het2ParityCheck();
/* USER CODE BEGIN (61) */
/* USER CODE END */
htu2ParityCheck();
/* USER CODE BEGIN (62) */
/* USER CODE END */
adc1ParityCheck();
/* USER CODE BEGIN (63) */
/* USER CODE END */
adc2ParityCheck();
/* USER CODE BEGIN (64) */
/* USER CODE END */
can1ParityCheck();
/* USER CODE BEGIN (65) */
/* USER CODE END */
can2ParityCheck();
/* USER CODE BEGIN (66) */
/* USER CODE END */
can3ParityCheck();
/* USER CODE BEGIN (67) */
/* USER CODE END */
vimParityCheck();
/* USER CODE BEGIN (68) */
/* USER CODE END */
dmaParityCheck();
/* USER CODE BEGIN (69) */
/* USER CODE END */
/* Initialize all on-chip SRAMs except for MibSPIx RAMs The MibSPIx modules
* have their own auto-initialization mechanism which is triggered as soon
* as the modules are brought out of local reset. */
/* The system module auto-init will hang on the MibSPI RAM if the module is
* still in local reset. */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories
* and their channel numbers. Memory Initialization is perfomed only on
* the user selected memories in HALCoGen's GUI SAFETY INIT tab. */
memoryInit((1U << 1U) | (1U << 2U) | (1U << 5U) | (1U << 6U)
| (1U << 10U) | (1U << 8U) | (1U << 14U) | (1U << 3U)
| (1U << 4U) | (1U << 15U) | (1U << 16U) | (0U << 13U) );
while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
{
}/* Wait */
/* wait for MibSPI1 RAM to complete initialization */
while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI3 RAM to complete initialization */
{
}/* Wait */
/* wait for MibSPI3 RAM to complete initialization */
while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
{
}/* Wait */
/* wait for MibSPI5 RAM to complete initialization */
/* USER CODE BEGIN (70) */
/* USER CODE END */
mibspi1ParityCheck();
/* USER CODE BEGIN (71) */
/* USER CODE END */
mibspi3ParityCheck();
/* USER CODE BEGIN (72) */
/* USER CODE END */
mibspi5ParityCheck();
/* USER CODE BEGIN (73) */
/* USER CODE END */
/* USER CODE BEGIN (74) */
/* USER CODE END */
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (75) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
vimInit();
#ifdef __GNUC__
data_init();
#elif defined(__TI_COMPILER_VERSION__)
/* initialize copy table */
if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU)
{
@ -633,20 +243,7 @@ void _c_int00(void)
p();
}
}
/* USER CODE BEGIN (76) */
/* USER CODE END */
#endif
/* call the application */
main();
/* USER CODE BEGIN (77) */
/* USER CODE END */
exit();
/* USER CODE BEGIN (78) */
/* USER CODE END */
}
/* USER CODE BEGIN (79) */
/* USER CODE END */

148
bsp/rm48x50/HALCoGen/source/sys_vim.c
View File

@ -30,140 +30,6 @@ typedef volatile struct vimRam
#define vimRAM ((vimRAM_t *)0xFFF82000U)
static const t_isrFuncPTR s_vim_init[129] =
{
&phantomInterrupt,
&esmHighInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&rtiCompare3Interrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&linHighLevelInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
&phantomInterrupt,
};
void vimParityErrorHandler(void);
/** @fn void vimInit(void)
* @brief Initializes VIM module
*
@ -172,18 +38,8 @@ void vimParityErrorHandler(void);
void vimInit(void)
{
/* Initialize VIM table */
{
uint32 i;
for (i = 0U; i < (VIM_CHANNELS + 1U); i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* Set Fall-Back Address Parity Error Register */
VIM_FBPARERR = (uint32)&vimParityErrorHandler;
/*VIM_FBPARERR = (uint32)&vimParityErrorHandler;*/
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
@ -627,6 +483,7 @@ void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type)
}
#if 0
#pragma CODE_STATE(vimParityErrorHandler, 32)
#pragma INTERRUPT(vimParityErrorHandler, IRQ)
@ -674,3 +531,4 @@ void vimParityErrorHandler(void)
}
}
}
#endif

7
bsp/rm48x50/HALCoGen/source/system.c
View File

@ -282,7 +282,7 @@ void systemInit(void)
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheck();
//efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
@ -294,17 +294,18 @@ void systemInit(void)
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
//muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
#if 0
/* Wait for eFuse controller self-test to complete and check results */
if ((!checkefcSelfTest()) !=0U) /* eFuse controller ECC logic self-test failed */
{
efcClass2Error(); /* device operation is not reliable */
}
#endif
/* USER CODE BEGIN (20) */
/* USER CODE END */

12
bsp/rm48x50/SConscript Normal file
View File

@ -0,0 +1,12 @@
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

31
bsp/rm48x50/SConstruct Normal file
View File

@ -0,0 +1,31 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-rm48x50.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
if env['PLATFORM'] == 'win32':
env['ASCOM'] = '$AS $ASFLAGS $CCFLAGS $_CCCOMCOM -o $TARGET $SOURCES'
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
Depends(TARGET, 'rm48x50.ld')
# make a building
DoBuilding(TARGET, objs)

9
bsp/rm48x50/application/SConscript Normal file
View File

@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

24
bsp/rm48x50/application/startup.c
View File

@ -19,7 +19,7 @@
#ifdef RT_USING_FINSH
#include <finsh.h>
extern void finsh_system_init(void);
extern int finsh_system_init(void);
#endif
#include <board.h>
@ -43,6 +43,28 @@ extern unsigned char * const system_data_end;
#endif
#define MEMEND 0x08040000
void rt_hw_pmu_enable_cnt(void)
{
unsigned long tmp;
__asm (" MRC p15, #0, r0, c9, c12, #0");
__asm (" ORR r0, r0, #0x09\n");
__asm (" MCR p15, #0, r0, c9, c12, #0\n");
__asm (" MOV r0, #1\n");
__asm (" RBIT r0, r0\n");
__asm (" MCR p15, #0, r0, c9, c12, #1\n");
}
void rt_hw_pmu_setcnt(unsigned long val)
{
__asm (" MCR p15, #0, r0, c9, c13, #0");
}
unsigned long rt_hw_pmu_getcnt(void)
{
__asm (" MRC p15, #0, r0, c9, c13, #0");
}
/**
* This function will startup RT-Thread RTOS.
*/

9
bsp/rm48x50/drivers/SConscript
View File

@ -6,15 +6,6 @@ from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_LWIP') == False:
src_need_remove = ['dm9000.c'] # need remove file list.
SrcRemove(src, src_need_remove)
if GetDepend('RT_USING_DFS') == False:
src_need_remove = ['sd.c'] # need remove file list.
SrcRemove(src, src_need_remove)
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)

2
bsp/rm48x50/drivers/board.h
View File

@ -20,7 +20,7 @@
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
void rt_hw_board_init(void);
void rt_hw_led_set(rt_uint32_t led);
void rt_hw_led_set(int led);
void rt_hw_led_flash(void);
#ifdef RT_USING_FINSH

144
bsp/rm48x50/rm48x50.ld Normal file
View File

@ -0,0 +1,144 @@
/*
* linker script for RM48x50 with GNU ld
* Grissiom 2013-10-20
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 3M
DATA (rw) : ORIGIN = 0x08000000, LENGTH = 256k
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(system_vectors)
SECTIONS
{
.text :
{
__text_start = .;
*(.vectors)
*(.text)
*(.text.*)
__rodata_start = .;
*(.rodata)
*(.rodata.*)
__rodata_end = .;
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.v4_bx)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initialization */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
__text_end = .;
} > CODE = 0
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
} > CODE
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
__data_end = .;
__noinit_start = .;
.noinit :
{
. = ALIGN(4);
*(.bss.noinit)
} > DATA
__noinit_stop = .;
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} > DATA
__bss_end = .;
/* Stabs debugging sections.
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
*/
_end = .;
}

6
bsp/rm48x50/rtconfig.h
View File

@ -19,7 +19,7 @@
// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
#define IDLE_THREAD_STACK_SIZE 512
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
//#define RT_DEBUG
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
@ -27,7 +27,7 @@
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK
//#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
@ -131,7 +131,7 @@
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
#define RT_USING_LWIP
//#define RT_USING_LWIP
// <bool name="RT_USING_LWIP141" description="Using lwIP 1.4.1 version" default="true" />
#define RT_USING_LWIP141
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />

103
bsp/rm48x50/rtconfig.py Normal file
View File

@ -0,0 +1,103 @@
import os
# toolchains options
ARCH='arm'
CPU='cortex-r4'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files\GNU Tools ARM Embedded\4.7 2013q3\bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil'
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support IAR yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -Wall -march=armv7-r -mfloat-abi=hard'+\
' -ftree-vectorize -ffast-math -mfpu=vfpv3-d16 '+\
' -ffunction-sections -fdata-sections '
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-rm48x50.map,-cref,-u,system_vectors -T rm48x50.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 '
AFLAGS += ' -g -gdwarf-2'
else:
CFLAGS += ' -O3 -g -gdwarf-2'
AFLAGS += ' -g -gdwarf-2'
POST_ACTION = SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMP'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-beaglebone.map --scatter beaglebone_ram.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' --cpu DARMP'
CFLAGS = ''
AFLAGS = ''
LFLAGS = ' --config beaglebone_ram.icf'
EXEC_PATH += '/arm/bin/'
RT_USING_MINILIBC = False
POST_ACTION = ''

39
libcpu/arm/cortex-r4/RM48x50.h
View File

@ -1,39 +0,0 @@
#ifndef RM48X50_H
#define RM48X50_H
#include <system.h>
#include <sys_vim.h>
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
struct rt_hw_register
{
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long sp;
unsigned long lr;
unsigned long pc;
unsigned long cpsr;
unsigned long ORIG_r0;
};
#endif /* end of include guard: RM48X50_H */

48
libcpu/arm/cortex-r4/armv7.h Normal file
View File

@ -0,0 +1,48 @@
#ifndef __ARMV7_H__
#define __ARMV7_H__
#ifndef VFP_DATA_NR
#define VFP_DATA_NR 32
#endif
/* the exception stack without VFP registers */
struct rt_hw_exp_stack
{
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long sp;
unsigned long lr;
unsigned long pc;
unsigned long cpsr;
};
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define MONITORMODE 0x16
#define ABORTMODE 0x17
#define HYPMODE 0x1b
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
#define T_Bit (1<<5)
#define F_Bit (1<<6)
#define I_Bit (1<<7)
#define A_Bit (1<<8)
#define E_Bit (1<<9)
#define J_Bit (1<<24)
#endif

255
libcpu/arm/cortex-r4/context_gcc.S Normal file
View File

@ -0,0 +1,255 @@
/*
* File : context_ccs.asm
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-20 Bernard first version
* 2011-07-22 Bernard added thumb mode porting
* 2013-05-24 Grissiom port to CCS
* 2013-05-26 Grissiom optimize for ARMv7
* 2013-10-20 Grissiom port to GCC
*/
#include <rtconfig.h>
.text
.arm
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl rt_hw_trap_irq
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, cpsr
CPSID IF
BX lr
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR cpsr_c, r0
BX lr
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* r0 --> from
* r1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
STMDB sp!, {lr} @ push pc (lr should be pushed in place of PC)
STMDB sp!, {r0-r12, lr} @ push lr & register file
MRS r4, cpsr
TST lr, #0x01
ORRNE r4, r4, #0x20 @ it's thumb code
STMDB sp!, {r4} @ push cpsr
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS r4, fpexc
TST r4, #0x40000000
BEQ __no_vfp_frame1
VSTMDB sp!, {d0-d15}
VMRS r5, fpscr
@ TODO: add support for Common VFPv3.
@ Save registers like FPINST, FPINST2
STMDB sp!, {r5}
__no_vfp_frame1:
STMDB sp!, {r4}
#endif
STR sp, [r0] @ store sp in preempted tasks TCB
LDR sp, [r1] @ get new task stack pointer
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
LDMIA sp!, {r0} @ get fpexc
VMSR fpexc, r0 @ restore fpexc
TST r0, #0x40000000
BEQ __no_vfp_frame2
LDMIA sp!, {r1} @ get fpscr
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame2:
#endif
LDMIA sp!, {r4} @ pop new task cpsr to spsr
MSR spsr_cxsf, r4
LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
/*
* void rt_hw_context_switch_to(rt_uint32 to)
* r0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
LDR sp, [r0] @ get new task stack pointer
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
LDMIA sp!, {r0} @ get fpexc
VMSR fpexc, r0
TST r0, #0x40000000
BEQ __no_vfp_frame_to
LDMIA sp!, {r1} @ get fpscr
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_to:
#endif
LDMIA sp!, {r4} @ pop new task cpsr to spsr
MSR spsr_cxsf, r4
LDMIA sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@
*/
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
LDR r2, =rt_thread_switch_interrupt_flag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1 @ set rt_thread_switch_interrupt_flag to 1
STR r3, [r2]
LDR r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
STR r0, [r2]
_reswitch:
LDR r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
STR r1, [r2]
BX lr
.globl IRQ_Handler
IRQ_Handler:
STMDB sp!, {r0-r12,lr}
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS r0, fpexc
TST r0, #0x40000000
BEQ __no_vfp_frame_str_irq
VSTMDB sp!, {d0-d15}
VMRS r1, fpscr
@ TODO: add support for Common VFPv3.
@ Save registers like FPINST, FPINST2
STMDB sp!, {r1}
__no_vfp_frame_str_irq:
STMDB sp!, {r0}
#endif
BL rt_interrupt_enter
BL rt_hw_trap_irq
BL rt_interrupt_leave
@ if rt_thread_switch_interrupt_flag set, jump to
@ rt_hw_context_switch_interrupt_do and don't return
LDR r0, =rt_thread_switch_interrupt_flag
LDR r1, [r0]
CMP r1, #1
BEQ rt_hw_context_switch_interrupt_do
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
LDMIA sp!, {r0} @ get fpexc
VMSR fpexc, r0
TST r0, #0x40000000
BEQ __no_vfp_frame_ldr_irq
LDMIA sp!, {r1} @ get fpscr
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_ldr_irq:
#endif
LDMIA sp!, {r0-r12,lr}
SUBS pc, lr, #4
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_hw_context_switch_interrupt_do
rt_hw_context_switch_interrupt_do:
MOV r1, #0 @ clear flag
STR r1, [r0]
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
LDMIA sp!, {r0} @ get fpexc
VMSR fpexc, r0
TST r0, #0x40000000
BEQ __no_vfp_frame_do1
LDMIA sp!, {r1} @ get fpscr
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_do1:
#endif
LDMIA sp!, {r0-r12,lr} @ reload saved registers
STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC
@ mode so there is no need to update SP.
SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
SUB r2, lr, #4 @ save old task's pc to r2
MRS r3, spsr @ get cpsr of interrupt thread
@ switch to SVC mode and no interrupt
CPSID IF, #0x13
STMDB sp!, {r2} @ push old task's pc
STMDB sp!, {r4-r12,lr} @ push old task's lr,r12-r4
LDMIA r1!, {r4-r7} @ restore r0-r3 of the interrupted thread
STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to
@ r0-r3 because we just want to transfer the data and don't
@ use them here.
STMDB sp!, {r3} @ push old task's cpsr
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
VMRS r0, fpexc
TST r0, #0x40000000
BEQ __no_vfp_frame_do2
VSTMDB sp!, {d0-d15}
VMRS r1, fpscr
@ TODO: add support for Common VFPv3.
@ Save registers like FPINST, FPINST2
STMDB sp!, {r1}
__no_vfp_frame_do2:
STMDB sp!, {r0}
#endif
LDR r4, =rt_interrupt_from_thread
LDR r5, [r4]
STR sp, [r5] @ store sp in preempted tasks's TCB
LDR r6, =rt_interrupt_to_thread
LDR r6, [r6]
LDR sp, [r6] @ get new task's stack pointer
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
LDMIA sp!, {r0} @ get fpexc
VMSR fpexc, r0
TST r0, #0x40000000
BEQ __no_vfp_frame_do3
LDMIA sp!, {r1} @ get fpscr
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_do3:
#endif
LDMIA sp!, {r4} @ pop new task's cpsr to spsr
MSR spsr_cxsf, r4
LDMIA sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr

7
libcpu/arm/cortex-r4/cpu.c
View File

@ -39,6 +39,7 @@ void rt_hw_cpu_shutdown()
while (1);
}
#ifdef __TI_COMPILER_VERSION__
#ifdef RT_USING_CPU_FFS
int __rt_ffs(int value)
{
@ -52,7 +53,6 @@ int __rt_ffs(int value)
}
#endif
#ifdef __TI_COMPILER_VERSION__
void rt_hw_cpu_icache_enable()
{
__asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
@ -90,5 +90,10 @@ void rt_hw_cpu_dcache_disable()
__asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
}
#elif __GNUC__
int __rt_ffs(int value)
{
return __builtin_ffs(value);
}
#endif
/*@}*/

6
libcpu/arm/cortex-r4/interrupt.c
View File

@ -15,7 +15,11 @@
#include <rtthread.h>
#include <rthw.h>
#include "RM48x50.h"
#include <sys_vim.h>
#include <system.h>
#include "armv7.h"
#define MAX_HANDLERS 96

6
libcpu/arm/cortex-r4/stack.c
View File

@ -13,7 +13,8 @@
* 2013-05-24 Grissiom port to RM48x50
*/
#include <rtthread.h>
#include "RM48x50.h"
#include "armv7.h"
/**
* @addtogroup RM48x50
*/
@ -57,10 +58,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
else
*(--stk) = SVCMODE; /* arm mode */
#ifdef __TI_VFP_SUPPORT__
#if defined(__TI_VFP_SUPPORT__) || (defined (__VFP_FP__) && !defined(__SOFTFP__))
#ifndef RT_VFP_LAZY_STACKING
{
#define VFP_DATA_NR 32
int i;
for (i = 0; i < VFP_DATA_NR; i++)

332
bsp/rm48x50/HALCoGen/source/sys_core.asm → libcpu/arm/cortex-r4/start_ccs.asm
View File

@ -7,17 +7,14 @@
.text
.arm
.ref _c_int00
.def _reset
.asmfunc
_reset
;-------------------------------------------------------------------------------
; Initialize CPU Registers
.def _coreInitRegisters_
.asmfunc
_coreInitRegisters_
; After reset, the CPU is in the Supervisor mode (M = 10011)
; After reset, the CPU is in the Supervisor mode (M = 10011)
mov r0, lr
mov r1, #0x0000
mov r2, #0x0000
@ -33,7 +30,7 @@ _coreInitRegisters_
mov r12, #0x0000
mov r13, #0x0000
mrs r1, cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch to FIQ mode (M = 10001)
cps #17
mov lr, r0
@ -43,27 +40,27 @@ _coreInitRegisters_
mov r11, #0x0000
mov r12, #0x0000
mrs r1, cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch to IRQ mode (M = 10010)
cps #18
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch to Abort mode (M = 10111)
cps #23
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch to Undefined Instruction Mode (M = 11011)
cps #27
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch to System Mode ( Shares User Mode registers ) (M = 11111)
cps #31
mov lr, r0
mrs r1,cpsr
msr spsr_cxsf, r1
msr spsr_cxsf, r1
; Switch back to Supervisor Mode (M = 10011)
cps #19
@ -94,27 +91,9 @@ _coreInitRegisters_
fmdrr d14, r1, r1
fmdrr d15, r1, r1
.endif
bl next1
next1
bl next2
next2
bl next3
next3
bl next4
next4
bx r0
.endasmfunc
;-------------------------------------------------------------------------------
; Initialize Stack Pointers
.def _coreInitStackPointer_
.asmfunc
_coreInitStackPointer_
cps #17
ldr sp, fiqSp
cps #18
@ -127,8 +106,19 @@ _coreInitStackPointer_
ldr sp, userSp
cps #19
ldr sp, svcSp
bx lr
bl next1
next1
bl next2
next2
bl next3
next3
bl next4
next4
ldr lr, int00ad
bx lr
int00ad .word _c_int00
userSp .word 0x08000000+0x00001000
svcSp .word 0x08000000+0x00001000+0x00000100
fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
@ -138,90 +128,6 @@ undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+
.endasmfunc
;-------------------------------------------------------------------------------
; Get CPSR Value
.def _getCPSRValue_
.asmfunc
_getCPSRValue_
mrs r0, CPSR
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Take CPU to IDLE state
.def _gotoCPUIdle_
.asmfunc
_gotoCPUIdle_
WFI
nop
nop
nop
nop
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable VFP Unit
.def _coreEnableVfp_
.asmfunc
_coreEnableVfp_
mrc p15, #0x00, r0, c1, c0, #0x02
orr r0, r0, #0xF00000
mcr p15, #0x00, r0, c1, c0, #0x02
mov r0, #0x40000000
fmxr fpexc, r0
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Event Bus Export
.def _coreEnableEventBusExport_
.asmfunc
_coreEnableEventBusExport_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c9, c12, #0x00
orr r0, r0, #0x10
mcr p15, #0x00, r0, c9, c12, #0x00
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable Event Bus Export
.def _coreDisableEventBusExport_
.asmfunc
_coreDisableEventBusExport_
stmfd sp!, {r0}
mrc p15, #0x00, r0, c9, c12, #0x00
bic r0, r0, #0x10
mcr p15, #0x00, r0, c9, c12, #0x00
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable RAM ECC Support
@ -234,7 +140,7 @@ _coreEnableRamEcc_
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -252,7 +158,7 @@ _coreDisableRamEcc_
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -271,7 +177,7 @@ _coreEnableFlashEcc_
orr r0, r0, #0x02000000
dmb
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -289,30 +195,11 @@ _coreDisableFlashEcc_
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x02000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable Offset via Vic controller
.def _coreEnableIrqVicOffset_
.asmfunc
_coreEnableIrqVicOffset_
stmfd sp!, {r0}
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x01000000
mcr p15, #0, r0, c1, c0, #0
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Get data fault status register
@ -338,7 +225,7 @@ _coreClearDataFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #0
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -369,7 +256,7 @@ _coreClearInstructionFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #1
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -400,7 +287,7 @@ _coreClearDataFaultAddress_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #0
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -431,7 +318,7 @@ _coreClearInstructionFaultAddress_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #2
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -462,7 +349,7 @@ _coreClearAuxiliaryDataFault_
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c1, #0
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
@ -492,64 +379,11 @@ _coreClearAuxiliaryInstructionFault_
stmfd sp!, {r0}
mov r0, #0
mrc p15, #0, r0, c5, c1, #1
ldmfd sp!, {r0}
ldmfd sp!, {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable interrupts - R4 IRQ & FIQ
.def _disable_interrupt_
.asmfunc
_disable_interrupt_
cpsid if
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable FIQ interrupt
.def _disable_FIQ_interrupt_
.asmfunc
_disable_FIQ_interrupt_
cpsid f
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Disable FIQ interrupt
.def _disable_IRQ_interrupt_
.asmfunc
_disable_IRQ_interrupt_
cpsid i
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Enable interrupts - R4 IRQ & FIQ
.def _enable_interrupt_
.asmfunc
_enable_interrupt_
cpsie if
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Clear ESM CCM errorss
@ -558,7 +392,7 @@ _enable_interrupt_
_esmCcmErrorsClear_
stmfd sp!, {r0-r2}
stmfd sp!, {r0-r2}
ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
ldr r2, ESMSR1_ERR_CLR
str r2, [r0] ; clear the ESMSR1 register
@ -581,7 +415,7 @@ _esmCcmErrorsClear_
ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
ldr r2, CCMR4_ERR_CLR
str r2, [r0] ; clear the CCMR4 status register
ldmfd sp!, {r0-r2}
ldmfd sp!, {r0-r2}
bx lr
ESMSR1_REG .word 0xFFFFF518
@ -598,16 +432,16 @@ ESMSSR2_ERR_CLR .word 0x00000004
VIM_INT_CLR .word 0x00000001
VIM_INTREQ .word 0xFFFFFE20
.endasmfunc
.endasmfunc
;-------------------------------------------------------------------------------
; Work Around for Errata CORTEX-R4#57:
;
; Errata Description:
;
; Errata Description:
; Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
; Workaround:
; Disable out-of-order single-precision floating point
; multiply-accumulate instruction completion
; Disable out-of-order single-precision floating point
; multiply-accumulate instruction completion
.def _errata_CORTEXR4_57_
.asmfunc
@ -615,22 +449,22 @@ VIM_INTREQ .word 0xFFFFFE20
_errata_CORTEXR4_57_
push {r0}
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
mrc p15, #0, r0, c15, c0, #0 ; Read Secondary Auxiliary Control Register
orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
mcr p15, #0, r0, c15, c0, #0 ; Write Secondary Auxiliary Control Register
pop {r0}
bx lr
.endasmfunc
;-------------------------------------------------------------------------------
; Work Around for Errata CORTEX-R4#66:
;
; Errata Description:
; Register Corruption During A Load-Multiple Instruction At
;
; Errata Description:
; Register Corruption During A Load-Multiple Instruction At
; an Exception Vector
; Workaround:
; Disable out-of-order completion for divide instructions in
; Auxiliary Control register
; Disable out-of-order completion for divide instructions in
; Auxiliary Control register
.def _errata_CORTEXR4_66_
.asmfunc
@ -639,12 +473,73 @@ _errata_CORTEXR4_66_
push {r0}
mrc p15, #0, r0, c1, c0, #1 ; Read Auxiliary Control register
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
; for divide instructions.)
mcr p15, #0, r0, c1, c0, #1 ; Write Auxiliary Control register
pop {r0}
pop {r0}
bx lr
.endasmfunc
.def turnon_VFP
.asmfunc
turnon_VFP
; Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
.endasmfunc
_push_svc_reg .macro
sub sp, sp, #17 * 4 ;/* Sizeof(struct rt_hw_exp_stack) */
stmia sp, {r0 - r12} ;/* Calling r0-r12 */
mov r0, sp
mrs r6, spsr ;/* Save CPSR */
str lr, [r0, #15*4] ;/* Push PC */
str r6, [r0, #16*4] ;/* Push CPSR */
cps #0x13
str sp, [r0, #13*4] ;/* Save calling SP */
str lr, [r0, #14*4] ;/* Save calling PC */
.endm
.ref rt_hw_trap_svc
.def vector_svc
.asmfunc
vector_svc:
_push_svc_reg
bl rt_hw_trap_svc
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_pabt
.def vector_pabort
.asmfunc
vector_pabort:
_push_svc_reg
bl rt_hw_trap_pabt
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_dabt
.def vector_dabort
.asmfunc
vector_dabort:
_push_svc_reg
bl rt_hw_trap_dabt
sub pc, pc, #-4
.endasmfunc
.ref rt_hw_trap_resv
.def vector_resv
.asmfunc
vector_resv:
_push_svc_reg
bl rt_hw_trap_resv
sub pc, pc, #-4
.endasmfunc
;-------------------------------------------------------------------------------
; C++ construct table pointers
@ -654,7 +549,4 @@ _errata_CORTEXR4_66_
__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
;-------------------------------------------------------------------------------

482
libcpu/arm/cortex-r4/start_gcc.S Normal file
View File

@ -0,0 +1,482 @@
@-------------------------------------------------------------------------------
@ sys_core.asm
@
@ (c) Texas Instruments 2009-2013, All rights reserved.
@
#include <rtconfig.h>
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
.equ UND_Stack_Size, 0x00000000
.equ SVC_Stack_Size, 0x00000100
.equ ABT_Stack_Size, 0x00000000
.equ FIQ_Stack_Size, 0x00000000
.equ IRQ_Stack_Size, 0x00000100
.equ USR_Stack_Size, 0x00000100
.section .bss.noinit
/* stack */
.globl stack_start
.globl stack_top
stack_start:
.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
.long 0
.endr
stack_top:
.section .text, "ax"
.text
.arm
.globl _c_int00
.globl _reset
_reset:
@-------------------------------------------------------------------------------
@ Initialize CPU Registers
@ After reset, the CPU is in the Supervisor mode (M = 10011)
cpsid if, #19
#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
@ Turn on FPV coprocessor
mrc p15, #0x00, r2, c1, c0, #0x02
orr r2, r2, #0xF00000
mcr p15, #0x00, r2, c1, c0, #0x02
fmrx r2, fpexc
orr r2, r2, #0x40000000
fmxr fpexc, r2
#endif
@-------------------------------------------------------------------------------
@ Initialize Stack Pointers
ldr r0, =stack_top
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #Mode_UND|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #UND_Stack_Size
@ Enter Abort Mode and set its Stack Pointer
msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #ABT_Stack_Size
@ Enter FIQ Mode and set its Stack Pointer
msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #FIQ_Stack_Size
@ Enter IRQ Mode and set its Stack Pointer
msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #IRQ_Stack_Size
@ Enter Supervisor Mode and set its Stack Pointer
msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #SVC_Stack_Size
@ Enter User Mode and set its Stack Pointer
mov sp, r0
sub sl, sp, #USR_Stack_Size
bl next1
next1:
bl next2
next2:
bl next3
next3:
bl next4
next4:
ldr lr, =_c_int00
bx lr
.globl data_init
data_init:
/* copy .data to SRAM */
ldr r1, =_sidata /* .data start in image */
ldr r2, =_edata /* .data end in image */
ldr r3, =_sdata /* sram data start */
data_loop:
ldr r0, [r1, #0]
str r0, [r3]
add r1, r1, #4
add r3, r3, #4
cmp r3, r2 /* check if data to clear */
blo data_loop /* loop until done */
/* clear .bss */
mov r0,#0 /* get a zero */
ldr r1,=__bss_start /* bss start */
ldr r2,=__bss_end /* bss end */
bss_loop:
cmp r1,r2 /* check if data to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
blo bss_loop /* loop until done */
/* call C++ constructors of global objects */
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r3, ip, lr}
mov lr, pc
bx r2
ldmfd sp!, {r0-r3, ip, lr}
b ctor_loop
ctor_end:
bx lr
@-------------------------------------------------------------------------------
@ Enable RAM ECC Support
.globl _coreEnableRamEcc_
_coreEnableRamEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Disable RAM ECC Support
.globl _coreDisableRamEcc_
_coreDisableRamEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x0C000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Enable Flash ECC Support
.globl _coreEnableFlashEcc_
_coreEnableFlashEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
orr r0, r0, #0x02000000
dmb
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Disable Flash ECC Support
.globl _coreDisableFlashEcc_
_coreDisableFlashEcc_:
stmfd sp!, {r0}
mrc p15, #0x00, r0, c1, c0, #0x01
bic r0, r0, #0x02000000
mcr p15, #0x00, r0, c1, c0, #0x01
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get data fault status register
.globl _coreGetDataFault_
_coreGetDataFault_:
mrc p15, #0, r0, c5, c0, #0
bx lr
@-------------------------------------------------------------------------------
@ Clear data fault status register
.globl _coreClearDataFault_
_coreClearDataFault_:
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #0
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get instruction fault status register
.globl _coreGetInstructionFault_
_coreGetInstructionFault_:
mrc p15, #0, r0, c5, c0, #1
bx lr
@-------------------------------------------------------------------------------
@ Clear instruction fault status register
.globl _coreClearInstructionFault_
_coreClearInstructionFault_:
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c0, #1
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get data fault address register
.globl _coreGetDataFaultAddress_
_coreGetDataFaultAddress_:
mrc p15, #0, r0, c6, c0, #0
bx lr
@-------------------------------------------------------------------------------
@ Clear data fault address register
.globl _coreClearDataFaultAddress_
_coreClearDataFaultAddress_:
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #0
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get instruction fault address register
.globl _coreGetInstructionFaultAddress_
_coreGetInstructionFaultAddress_:
mrc p15, #0, r0, c6, c0, #2
bx lr
@-------------------------------------------------------------------------------
@ Clear instruction fault address register
.globl _coreClearInstructionFaultAddress_
_coreClearInstructionFaultAddress_:
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c6, c0, #2
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get auxiliary data fault status register
.globl _coreGetAuxiliaryDataFault_
_coreGetAuxiliaryDataFault_:
mrc p15, #0, r0, c5, c1, #0
bx lr
@-------------------------------------------------------------------------------
@ Clear auxiliary data fault status register
.globl _coreClearAuxiliaryDataFault_
_coreClearAuxiliaryDataFault_:
stmfd sp!, {r0}
mov r0, #0
mcr p15, #0, r0, c5, c1, #0
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Get auxiliary instruction fault status register
.globl _coreGetAuxiliaryInstructionFault_
_coreGetAuxiliaryInstructionFault_:
mrc p15, #0, r0, c5, c1, #1
bx lr
@-------------------------------------------------------------------------------
@ Clear auxiliary instruction fault status register
.globl _coreClearAuxiliaryInstructionFault_
_coreClearAuxiliaryInstructionFault_:
stmfd sp!, {r0}
mov r0, #0
mrc p15, #0, r0, c5, c1, #1
ldmfd sp!, {r0}
bx lr
@-------------------------------------------------------------------------------
@ Clear ESM CCM errorss
.globl _esmCcmErrorsClear_
_esmCcmErrorsClear_:
stmfd sp!, {r0-r2}
ldr r0, ESMSR1_REG @ load the ESMSR1 status register address
ldr r2, ESMSR1_ERR_CLR
str r2, [r0] @ clear the ESMSR1 register
ldr r0, ESMSR2_REG @ load the ESMSR2 status register address
ldr r2, ESMSR2_ERR_CLR
str r2, [r0] @ clear the ESMSR2 register
ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address
ldr r2, ESMSSR2_ERR_CLR
str r2, [r0] @ clear the ESMSSR2 register
ldr r0, ESMKEY_REG @ load the ESMKEY register address
mov r2, #0x5 @ load R2 with 0x5
str r2, [r0] @ clear the ESMKEY register
ldr r0, VIM_INTREQ @ load the INTREQ register address
ldr r2, VIM_INT_CLR
str r2, [r0] @ clear the INTREQ register
ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address
ldr r2, CCMR4_ERR_CLR
str r2, [r0] @ clear the CCMR4 status register
ldmfd sp!, {r0-r2}
bx lr
ESMSR1_REG: .word 0xFFFFF518
ESMSR2_REG: .word 0xFFFFF51C
ESMSR3_REG: .word 0xFFFFF520
ESMKEY_REG: .word 0xFFFFF538
ESMSSR2_REG: .word 0xFFFFF53C
CCMR4_STAT_REG: .word 0xFFFFF600
ERR_CLR_WRD: .word 0xFFFFFFFF
CCMR4_ERR_CLR: .word 0x00010000
ESMSR1_ERR_CLR: .word 0x80000000
ESMSR2_ERR_CLR: .word 0x00000004
ESMSSR2_ERR_CLR: .word 0x00000004
VIM_INT_CLR: .word 0x00000001
VIM_INTREQ: .word 0xFFFFFE20
@-------------------------------------------------------------------------------
@ Work Around for Errata CORTEX-R4#57:
@
@ Errata Description:
@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
@ Workaround:
@ Disable out-of-order single-precision floating point
@ multiply-accumulate instruction completion
.globl _errata_CORTEXR4_57_
_errata_CORTEXR4_57_:
push {r0}
mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
pop {r0}
bx lr
@-------------------------------------------------------------------------------
@ Work Around for Errata CORTEX-R4#66:
@
@ Errata Description:
@ Register Corruption During A Load-Multiple Instruction At
@ an Exception Vector
@ Workaround:
@ Disable out-of-order completion for divide instructions in
@ Auxiliary Control register
.globl _errata_CORTEXR4_66_
_errata_CORTEXR4_66_:
push {r0}
mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
@ for divide instructions.)
mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
pop {r0}
bx lr
.globl turnon_VFP
turnon_VFP:
@ Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
.macro push_svc_reg
sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
stmia sp, {r0 - r12} @/* Calling r0-r12 */
mov r0, sp
mrs r6, spsr @/* Save CPSR */
str lr, [r0, #15*4] @/* Push PC */
str r6, [r0, #16*4] @/* Push CPSR */
cps #Mode_SVC
str sp, [r0, #13*4] @/* Save calling SP */
str lr, [r0, #14*4] @/* Save calling PC */
.endm
.globl vector_svc
vector_svc:
push_svc_reg
bl rt_hw_trap_svc
b .
.globl vector_pabort
vector_pabort:
push_svc_reg
bl rt_hw_trap_pabt
b .
.globl vector_dabort
vector_dabort:
push_svc_reg
bl rt_hw_trap_dabt
b .
.globl vector_resv
vector_resv:
push_svc_reg
bl rt_hw_trap_resv
b .

46
libcpu/arm/cortex-r4/trap.c
View File

@ -15,8 +15,10 @@
#include <rtthread.h>
#include <rthw.h>
#include "RM48x50.h"
//#define BSP_INT_DEBUG
#include <sys_vim.h>
#include "armv7.h"
/**
* @addtogroup RM48x50
@ -28,7 +30,7 @@
*
* @param regs the registers point
*/
void rt_hw_show_register (struct rt_hw_register *regs)
void rt_hw_show_register (struct rt_hw_exp_stack *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
@ -40,14 +42,14 @@ void rt_hw_show_register (struct rt_hw_register *regs)
}
/**
* When ARM7TDMI comes across an instruction which it cannot handle,
* When comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
void rt_hw_trap_udef(struct rt_hw_exp_stack *regs)
{
rt_kprintf("undefined instruction\n");
rt_hw_show_register(regs);
@ -65,12 +67,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*
* @note never invoke this function in application
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
void rt_hw_trap_svc(struct rt_hw_exp_stack *regs)
{
rt_kprintf("software interrupt\n");
rt_hw_show_register(regs);
if (rt_thread_self() != RT_NULL)
rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
@ -82,12 +85,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*
* @note never invoke this function in application
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
{
rt_kprintf("prefetch abort\n");
rt_hw_show_register(regs);
if (rt_thread_self() != RT_NULL)
rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
@ -99,12 +103,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
*
* @note never invoke this function in application
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
{
rt_kprintf("Data Abort ");
rt_hw_show_register(regs);
if (rt_thread_self() != RT_NULL)
rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
@ -115,19 +120,16 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
*
* @note never invoke this function in application
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
{
rt_kprintf("not used\n");
rt_kprintf("Reserved trap\n");
rt_hw_show_register(regs);
if (rt_thread_self() != RT_NULL)
rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/*
*#pragma CODE_STATE(rt_hw_trap_irq, 32)
*#pragma INTERRUPT(rt_hw_trap_irq, IRQ)
*/
extern rt_isr_handler_t isr_table[];
void rt_hw_trap_irq(void)
{

34
bsp/rm48x50/HALCoGen/source/sys_intvecs.asm → libcpu/arm/cortex-r4/vector_ccs.asm
View File

@ -10,35 +10,25 @@
;-------------------------------------------------------------------------------
; import reference for interrupt routines
.ref _c_int00
.ref _dabort
.ref _reset
.ref turnon_VFP
.ref vector_svc
.ref vector_pabort
.ref vector_dabort
.ref vector_resv
.ref IRQ_Handler
.def resetEntry
;-------------------------------------------------------------------------------
; interrupt vectors
.def resetEntry
resetEntry
b _c_int00
b _reset
b turnon_VFP
svcEntry
b svcEntry
prefetchEntry
b prefetchEntry
b _dabort
reservedEntry
b reservedEntry
b vector_svc
b vector_pabort
b vector_dabort
b vector_resv
b IRQ_Handler
ldr pc,[pc,#-0x1b0]
.sect ".text"
turnon_VFP
; Enable FPV
STMDB sp!, {r0}
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
LDMIA sp!, {r0}
subs pc, lr, #4
;-------------------------------------------------------------------------------

31
libcpu/arm/cortex-r4/vector_gcc.S Normal file
View File

@ -0,0 +1,31 @@
@-------------------------------------------------------------------------------
@ sys_intvecs.asm
@
@ (c) Texas Instruments 2009-2013, All rights reserved.
@
.section .vectors, "ax"
.code 32
@-------------------------------------------------------------------------------
@ import reference for interrupt routines
.globl _reset
.globl turnon_VFP
.globl vector_svc
.globl vector_pabort
.globl vector_dabort
.globl vector_resv
.globl IRQ_Handler
.globl system_vectors
system_vectors:
b _reset
b turnon_VFP
b vector_svc
b vector_pabort
b vector_dabort
b vector_resv
b IRQ_Handler
ldr pc,[pc,#-0x1b0]