diff --git a/bsp/bf533/application.c b/bsp/bf533/application.c new file mode 100644 index 0000000000..1e3573d60f --- /dev/null +++ b/bsp/bf533/application.c @@ -0,0 +1,41 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#include "application.h" +#include "board.h" +#include "rtthread.h" + +void app_init_entry(void *parg) +{ + parg = parg; + + rt_hw_core_timer_init();//start system tick in first thread. + + rt_hw_isr_install(); +} + + +void rt_application_init(void) +{ + rt_thread_t led_thread; + +#ifdef RT_USING_HEAP + led_thread = rt_thread_create("init", app_init_entry, RT_NULL, 512, 200, 20); +#endif + + if (led_thread != RT_NULL) + { + rt_thread_startup(led_thread); + } +} diff --git a/bsp/bf533/application.h b/bsp/bf533/application.h new file mode 100644 index 0000000000..1d0f995099 --- /dev/null +++ b/bsp/bf533/application.h @@ -0,0 +1,28 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#ifndef __APPLICATION_H__ +#define __APPLICATION_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +void rt_application_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __APPLICATION_H__ */ diff --git a/bsp/bf533/board.c b/bsp/bf533/board.c new file mode 100644 index 0000000000..87daa517b9 --- /dev/null +++ b/bsp/bf533/board.c @@ -0,0 +1,257 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#include "board.h" +#include "rtconfig.h" +#include "rtdef.h" +#include "rthw.h" +#include "serial.h" + +#include +#include +#include +#include +#include +#include +#include + +#define IVG_CLR(index) (index > 0 ? ((0xFFFFFFF0 << (index * 0x04)) | \ + (0xFFFFFFF0 >> ((0x08 - index) * 0x04))):0xFFFFFFF0) +#define IVG_SET(index,ivg) ((((ivg) - 0x07) & 0x0F) << (index * 0x04)) + +#define UART0 ((struct uartport *)pUART_THR) +struct serial_int_rx uart0_int_rx; +struct serial_device uart0 = +{ + UART0, + &uart0_int_rx, + RT_NULL +}; +struct rt_device uart0_device; + +/** + * This function is to set the EBIU(EXTERNAL BUS INTERFACE UNIT). + */ +static void rt_hw_ebiu_init(void) +{ + *pEBIU_AMBCTL0 = 0xffc2ffc2; + + *pEBIU_AMBCTL1 = 0xffc2ffc3; + + *pEBIU_AMGCTL = 0x010f; +} + +/** + * This is the timer interrupt service routine. + */ +EX_INTERRUPT_HANDLER(rt_hw_timer_handler) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function is called to initialize system tick source (typically a + * timer generating interrupts every 1 to 100 mS). + * We decided to use Core Timer as the tick interrupt source. + */ +void rt_hw_core_timer_init(void) +{ + *pTCNTL = 1; // Turn on timer, TMPWR + *pTSCALE = 0x00; + *pTCOUNT = CCLKSPEED / RT_TICK_PER_SECOND; + *pTPERIOD = CCLKSPEED / RT_TICK_PER_SECOND; + register_handler(ik_timer,rt_hw_timer_handler); + *pTCNTL = 0x07; // Start Timer and set Auto-reload +} + +void rt_hw_interrupt_init(void) +{ + extern rt_uint32_t rt_interrupt_from_thread; + extern rt_uint32_t rt_interrupt_to_thread; + extern rt_uint32_t rt_thread_switch_interrupt_flag; + extern rt_uint8_t rt_interrupt_nest; + extern void interrupt_thread_switch(void); + + register_handler(ik_ivg14,interrupt_thread_switch); //context_vdsp.S + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +static void rt_hw_pll_init(void) +{ + unsigned long imask; + + sysreg_write(reg_SYSCFG, 0x32); + + *pSIC_IWR = 0x01; + + *pPLL_CTL = SET_MSEL(SPEED_MULTIPLE); + + // PLL Re-programming Sequence. + // Core is idle'ed to allow the PPL to re-lock. + imask = cli(); + idle(); + sti(imask); + *pVR_CTL = 0x00FB; + + // PLL Re-programming Sequence. + // Core is idle'ed to allow the PPL to re-lock. + imask = cli(); + idle(); + sti(imask); + + *pPLL_DIV = BUS_DIVISOR; +} + +/** + * This function is called to initialize external sdram. + */ +static void rt_hw_exdram_init(void) +{ + // Initalize EBIU control registers to enable all banks + *pEBIU_AMBCTL1 = 0xFFFFFF02; + ssync(); + + *pEBIU_AMGCTL = 0x00FF; + ssync(); + + // Check if already enabled + if (SDRS != ((*pEBIU_SDSTAT) & SDRS)) + { + return; + } + + //SDRAM Refresh Rate Control Register + *pEBIU_SDRRC = 0x01A0; + + //SDRAM Memory Bank Control Register + *pEBIU_SDBCTL = 0x0025; //1.7 64 MB + + //SDRAM Memory Global Control Register + *pEBIU_SDGCTL = 0x0091998D;//0x998D0491 + + ssync(); +} + +short uart_set_bitrate(unsigned long bit_rate) +{ + unsigned short int divisor; + + switch (bit_rate) + { + case 1200: + case 2400: + case 4800: + case 9600: + case 19200: + case 28800: + case 38400: + case 57600: + case 115200: + case 125000: + divisor = (unsigned short int) ((float) SCLKSPEED / ((float) bit_rate * 16.0f) + 0.5f); + + *(pUART_LCR) |= DLAB; // Enable access to DLL and DLH registers + *(pUART_DLL) = divisor & 0xFF; + *(pUART_DLH) = divisor >> 8; + *(pUART_LCR) &= ~DLAB; // clear DLAB bit + + break; + + default: // baud rate not supported + break; + } + + return 0; +} + +void rt_hw_uart_init(void) +{ + // Apply UART configuration 8 bit data, No parity, 1 stop bit + *pUART_LCR = 0x0000; // Reset value + *pUART_LCR = WLS(8); + + // Ensure that Loopback mode is disabled by clearing LOOP_ENA bit + *pUART_MCR = 0x0000; //Reset value + + uart_set_bitrate(19200);// Set communication baudrate 115200 + + *pUART_IER = ERBFI; + + // Enable UART clock + *pUART_GCTL = UCEN; +} + +int uart_put_char(const char c) +{ + while (!(*pUART_LSR & THRE)) + { + /* wait */ + } + + *pUART_THR = c; + + return c; +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + if (*str == '\n') + uart_put_char('\r'); + uart_put_char(*str++); + } +} + +EX_INTERRUPT_HANDLER(uart_rx_isr) +{ + rt_interrupt_enter(); + + rt_hw_serial_isr(&uart0_device); + + rt_interrupt_leave(); +} + +void rt_hw_isr_install(void) +{ + *pSIC_IWR = 0xFFFFFFFF; + *pSIC_IMASK = 0x00000000; + + *pSIC_IAR1 &= IVG_CLR(IAR1_DMA6_UARTRX_IVG); + *pSIC_IAR1 |= IVG_SET(IAR1_DMA6_UARTRX_IVG,ik_ivg9); + register_handler(ik_ivg9,uart_rx_isr); + *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/* ¿ªÖÐ¶Ï */ +} + +void rt_hw_board_init(void) +{ + rt_hw_pll_init(); + + rt_hw_ebiu_init(); + + rt_hw_exdram_init(); + + rt_hw_uart_init(); +} diff --git a/bsp/bf533/board.h b/bsp/bf533/board.h new file mode 100644 index 0000000000..01cbf6c954 --- /dev/null +++ b/bsp/bf533/board.h @@ -0,0 +1,94 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define CLKIN 33333000LL +#define SPEED_MULTIPLE 16 +#define BUS_DIVISOR 4 +#define CCLKSPEED (CLKIN * SPEED_MULTIPLE) +#define SCLKSPEED (CLKIN * BUS_DIVISOR) +#define CLOCKS_PER_SECD CCLKSPEED +#define SCLOCKS_PER_SEC SCLKSPEED + +//SIC_IMASK¼Ä´æÆ÷ +#define PLL_WAKEUP_INT_MASK 0x00000001 +#define DMA_ERROR_INT_MASK 0x00000002 +#define PPI_ERROR_INT_MASK 0x00000004 +#define SPORT0_ERROR_INT_MASK 0x00000008 +#define SPORT1_ERROR_INT_MASK 0x00000010 +#define SPI_ERROR_INT_MASK 0x00000020 +#define UART_ERROR_INT_MASK 0x00000040 +#define RTC_INT_MASK 0x00000080 +#define DMA0_PPI_INT_MASK 0x00000100 +#define DMA1_SPORT0_RX_INT_MASK 0x00000200 +#define DMA2_SPORT0_TX_INT_MASK 0x00000400 +#define DMA3_SPORT1_RX_INT_MASK 0x00000800 +#define DMA4_SPORT1_TX_INT_MASK 0x00001000 +#define DMA5_SPI_INT_MASK 0x00002000 +#define DMA6_UART_RX_INT_MASK 0x00004000 +#define DMA7_UART_TX_INT_MASK 0x00008000 +#define TIMER0_INT_MASK 0x00010000 +#define TIMER1_INT_MASK 0x00020000 +#define TIMER2_INT_MASK 0x00040000 +#define PF_INTA_MASK 0x00080000 +#define PF_INTB_MASK 0x00100000 +#define MEM_DMA_STREAM0_MASK 0x00200000 +#define MEM_DMA_STREAM1_MASK 0x00400000 +#define SOFT_WATCHDOG_TMER_MASK 0x00800000 + +//SIC_IAR0 +#define IAR0_PLL_WAKEUP_INT_IVG 0x00 +#define IAR0_DMA_ERROR_INT_IVG 0x01 +#define IAR0_PPI_ERROR_INT_IVG 0x02 +#define IAR0_SPORT0_ERROR_INT_IVG 0x03 +#define IAR0_SPORT1_ERROR_INT_IVG 0x04 +#define IAR0_SPI_ERROR_INT_IVG 0x05 +#define IAR0_UART_ERROR_INT_IVG 0x06 +#define IAR0_RTC_INT_IVG 0x07 + +//SIC_IAR1 +#define IAR1_DMA0_PPI_INT_IVG 0x00 +#define IAR1_DMA1_SPORT0RX_IVG 0x01 +#define IAR1_DMA2_SPORT0TX_IVG 0x02 +#define IAR1_DMA3_SPORT1RX_IVG 0x03 +#define IAR1_DMA4_SPORT1TX_IVG 0x04 +#define IAR1_DMA5_SPI_INT_IVG 0x05 +#define IAR1_DMA6_UARTRX_IVG 0x06 +#define IAR1_DMA7_UARTTX_IVG 0x07 + +//SIC_IAR2 +#define IAR2_TIMER0_INT_IVG 0x00 +#define IAR2_TIMER1_INT_IVG 0x01 +#define IAR2_TIMER2_INT_IVG 0x02 +#define IAR2_PF_A_INT_IVG 0x03 +#define IAR2_PF_B_INT_IVG 0x04 +#define IAR2_MEM_DMA_STREAM0_INT_IVG 0x05 +#define IAR2_MEM_DMA_STREAM1_INT_IVG 0x06 +#define IAR2_SWATCHDOG_TIMER_INT_IVG 0x07 + +#ifdef __cplusplus +extern "C" { +#endif + +void rt_hw_core_timer_init(void); +void rt_hw_board_init(void); +void rt_hw_isr_install(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H_ */ diff --git a/bsp/bf533/rtconfig.h b/bsp/bf533/rtconfig.h new file mode 100644 index 0000000000..def2b6272c --- /dev/null +++ b/bsp/bf533/rtconfig.h @@ -0,0 +1,243 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +//add by mojingxian.defualt idle stack is too small. +#define IDLE_THREAD_STACK_SIZE 512 + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 32 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 256 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 1000 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +/* #define RT_DEBUG */ +/* #define RT_THREAD_DEBUG */ + +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* Using Software Timer */ +//#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 8 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_TICK_PER_SECOND 1000 + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* Using SLAB Allocator */ +//#define RT_USING_SLAB + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE + +/* Using Module System */ +//#define RT_USING_MODULE +#define RT_USING_LIBDL + +/* SECTION: Console options */ +#define RT_USING_CONSOLE + +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_STACK_SIZE 1024 + +/* SECTION: a runtime libc library */ +/* a runtime libc library */ +//#define RT_USING_NEWLIB +//#define RT_USING_PTHREADS + +/* SECTION: C++ support */ +/* Using C++ support */ +/* #define RT_USING_CPLUSPLUS */ + +/* SECTION: Device filesystem support */ +/* using DFS support */ +//#define RT_USING_DFS +#define RT_USING_DFS_ELMFAT +/* use long file name feature */ +#define RT_DFS_ELM_USE_LFN 1 +/* the max number of file length */ +#define RT_DFS_ELM_MAX_LFN 128 +/* #define RT_USING_DFS_YAFFS2 */ +/* #define RT_USING_DFS_UFFS */ +#define RT_USING_DFS_DEVFS + +/* #define RT_USING_DFS_NFS */ +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" + +#define DFS_USING_WORKDIR + +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 4 +/* the max number of opened files */ +#define DFS_FD_MAX 16 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 + +/* Enable freemodbus protocal stack*/ +/* #define RT_USING_MODBUS */ + +/* SECTION: lwip, a lighwight TCP/IP protocol stack */ +/* Using lighweight TCP/IP protocol stack */ +/* #define RT_USING_LWIP */ +//#define RT_LWIP_DNS + +/* Trace LwIP protocol */ +/* #define RT_LWIP_DEBUG */ + +/* Enable ICMP protocol */ +#define RT_LWIP_ICMP + +/* Enable IGMP protocol */ +#define RT_LWIP_IGMP + +/* Enable UDP protocol */ +#define RT_LWIP_UDP + +/* Enable TCP protocol */ +#define RT_LWIP_TCP + +/* the number of simulatenously active TCP connections*/ +#define RT_LWIP_TCP_PCB_NUM 5 + +/* TCP sender buffer space */ +#define RT_LWIP_TCP_SND_BUF 1024*8 + +/* TCP receive window. */ +#define RT_LWIP_TCP_WND 1024*8 + +/* Enable SNMP protocol */ +/* #define RT_LWIP_SNMP */ + +/* Using DHCP */ +/* #define RT_LWIP_DHCP */ + +/* ip address of target */ +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 + +/* gateway address of target */ +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 + +/* mask address of target */ +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 + +/* the number of blocks for pbuf */ +#define RT_LWIP_PBUF_NUM 16 + +/* the number of simultaneously queued TCP */ +#define RT_LWIP_TCP_SEG_NUM 40 + +/* thread priority of tcpip thread */ +#define RT_LWIP_TCPTHREAD_PRIORITY 128 + +/* mail box size of tcpip thread to wait for */ +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32 + +/* thread stack size of tcpip thread */ +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 + +/* thread priority of ethnetif thread */ +#define RT_LWIP_ETHTHREAD_PRIORITY 144 + +/* mail box size of ethnetif thread to wait for */ +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32 + +/* thread stack size of ethnetif thread */ +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 + +/* SECTION: RTGUI support */ +/* using RTGUI support */ +#define RT_USING_RTGUI + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 16 +/* support 16 weight font */ +#define RTGUI_USING_FONT16 +/* support 16 weight font */ +#define RTGUI_USING_FONT12 +/* support Chinese font */ +#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +/* #define RTGUI_USING_HZ_FILE */ +/* use Chinese bitmap font */ +#define RTGUI_USING_HZ_BMP +/* use small size in RTGUI */ +/* #define RTGUI_USING_SMALL_SIZE */ +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +/* RTGUI image options */ +//#define RTGUI_IMAGE_XPM +//#define RTGUI_IMAGE_JPEG +//#define RTGUI_IMAGE_PNG +//#define RTGUI_IMAGE_BMP + +/* SECTION: FTK support */ +/* using FTK support */ +/* #define RT_USING_FTK */ + +/* + * Note on FTK: + * + * FTK depends : + * #define RT_USING_NEWLIB + * #define DFS_USING_WORKDIR + * + * And the maximal length must great than 64 + * #define RT_DFS_ELM_MAX_LFN 128 + */ + +#endif diff --git a/bsp/bf533/startup.c b/bsp/bf533/startup.c new file mode 100644 index 0000000000..fd6dae9538 --- /dev/null +++ b/bsp/bf533/startup.c @@ -0,0 +1,102 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#include +#include +#include "application.h" +#include "board.h" +#include "serial.h" +#include "finsh.h" + +extern "asm" int rtt_heap_start; +extern "asm" int rtt_heap_end; +extern struct serial_device uart0; +extern struct rt_device uart0_device; + +void rtthread_startup(void) +{ + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)&rtt_heap_start, (void*)&rtt_heap_end); +#endif + +#ifdef RT_USING_MODULE + /* init module system*/ + rt_system_module_init(); +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE + /* register uart0 */ + rt_hw_serial_register(&uart0_device, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); + + /* init all device */ + rt_device_init_all(); + + rt_console_set_device("uart0"); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + extern void finsh_system_init(void); + finsh_system_init(); + finsh_set_device("uart0"); +#endif + + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} diff --git a/bsp/bf533/vdsp/bf533.dpj b/bsp/bf533/vdsp/bf533.dpj new file mode 100644 index 0000000000..5d0e8641e8 --- /dev/null +++ b/bsp/bf533/vdsp/bf533.dpj @@ -0,0 +1,740 @@ + + + + + ADSP-BF533 + .ldr + Loader file + + + + + .\Debug + .\Debug + 0 + + + + + + + + + + + + + + + + + + + + + + + .\Release + .\Release + 12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + .\Debug + .\Debug + + + + + .\Release + .\Release + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bf533/vdsp/bf533.mak b/bsp/bf533/vdsp/bf533.mak new file mode 100644 index 0000000000..b87990da62 --- /dev/null +++ b/bsp/bf533/vdsp/bf533.mak @@ -0,0 +1,244 @@ +# Generated by the VisualDSP++ IDDE + +# Note: Any changes made to this Makefile will be lost the next time the +# matching project file is loaded into the IDDE. If you wish to preserve +# changes, rename this file and run it externally to the IDDE. + +# The syntax of this Makefile is such that GNU Make v3.77 or higher is +# required. + +# The current working directory should be the directory in which this +# Makefile resides. + +# Supported targets: +# bf533_Debug +# bf533_Debug_clean + +# Define this variable if you wish to run this Makefile on a host +# other than the host that created it and VisualDSP++ may be installed +# in a different directory. + +ADI_DSP=C:\Program Files (x86)\Analog Devices\VisualDSP 5.0 + + +# $VDSP is a gmake-friendly version of ADI_DIR + +empty:= +space:= $(empty) $(empty) +VDSP_INTERMEDIATE=$(subst \,/,$(ADI_DSP)) +VDSP=$(subst $(space),\$(space),$(VDSP_INTERMEDIATE)) + +RM=cmd /C del /F /Q + +# +# Begin "bf533_Debug" configuration +# + +ifeq ($(MAKECMDGOALS),bf533_Debug) + +bf533_Debug : ./Debug/bf533.ldr + +./Debug/application.doj :../application.c ../application.h ../board.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\application.c" + $(VDSP)/ccblkfn.exe -c ..\application.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\application.doj -MM + +./Debug/bf533_basiccrt.doj :./bf533_basiccrt.s $(VDSP)/Blackfin/include/cplb.h $(VDSP)/Blackfin/include/defBF532.h $(VDSP)/Blackfin/include/defBF533.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/sys/_adi_platform.h $(VDSP)/Blackfin/include/sys/anomaly_macros_rtl.h $(VDSP)/Blackfin/include/sys/platform.h + @echo ".\bf533_basiccrt.s" + $(VDSP)/easmblkfn.exe .\bf533_basiccrt.s -proc ADSP-BF533 -file-attr ProjectName=bf533 -g -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -o .\Debug\bf533_basiccrt.doj -MM + +./Debug/bf533_heaptab.doj :bf533_heaptab.c + @echo ".\bf533_heaptab.c" + $(VDSP)/ccblkfn.exe -c .\bf533_heaptab.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\bf533_heaptab.doj -MM + +./Debug/board.doj :../board.c ../board.h ../rtconfig.h ../../../include/rtdef.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../libcpu/blackfin/bf53x/serial.h $(VDSP)/Blackfin/include/signal.h $(VDSP)/Blackfin/include/sys/signal_bf.h $(VDSP)/Blackfin/include/sys/platform.h $(VDSP)/Blackfin/include/sys/_adi_platform.h $(VDSP)/Blackfin/include/cdefBF533.h $(VDSP)/Blackfin/include/cdefBF532.h $(VDSP)/Blackfin/include/defBF532.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/cdef_LPBlackfin.h $(VDSP)/Blackfin/include/ccblkfn.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/builtins.h $(VDSP)/Blackfin/include/sys/builtins_support.h $(VDSP)/Blackfin/include/fract_typedef.h $(VDSP)/Blackfin/include/fr2x16_typedef.h $(VDSP)/Blackfin/include/r2x16_typedef.h $(VDSP)/Blackfin/include/raw_typedef.h $(VDSP)/Blackfin/include/sys/anomaly_macros_rtl.h $(VDSP)/Blackfin/include/sys/mc_typedef.h $(VDSP)/Blackfin/include/sysreg.h $(VDSP)/Blackfin/include/string.h $(VDSP)/Blackfin/include/sys/exception.h $(VDSP)/Blackfin/include/stdio.h $(VDSP)/Blackfin/include/sys/stdio_bf.h + @echo "..\board.c" + $(VDSP)/ccblkfn.exe -c ..\board.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\board.doj -MM + +./Debug/clock.doj :../../../src/clock.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\clock.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\clock.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\clock.doj -MM + +./Debug/cmd.doj :../../../components/finsh/cmd.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../components/finsh/finsh.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h + @echo "..\..\..\components\finsh\cmd.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\cmd.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\cmd.doj -MM + +./Debug/context_vdsp.doj :../../../libcpu/blackfin/bf53x/context_vdsp.S + @echo "..\..\..\libcpu\blackfin\bf53x\context_vdsp.S" + $(VDSP)/easmblkfn.exe ..\..\..\libcpu\blackfin\bf53x\context_vdsp.S -proc ADSP-BF533 -file-attr ProjectName=bf533 -g -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -o .\Debug\context_vdsp.doj -MM + +./Debug/cpuport.doj :../../../libcpu/blackfin/bf53x/cpuport.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\libcpu\blackfin\bf53x\cpuport.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\libcpu\blackfin\bf53x\cpuport.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\cpuport.doj -MM + +./Debug/device.doj :../../../src/device.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\device.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\device.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\device.doj -MM + +./Debug/finsh_compiler.doj :../../../components/finsh/finsh_compiler.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_node.h ../../../components/finsh/finsh_error.h ../../../components/finsh/finsh_var.h ../../../components/finsh/finsh_ops.h ../../../components/finsh/finsh_vm.h + @echo "..\..\..\components\finsh\finsh_compiler.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_compiler.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_compiler.doj -MM + +./Debug/finsh_error.doj :../../../components/finsh/finsh_error.c ../../../components/finsh/finsh_error.h ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h + @echo "..\..\..\components\finsh\finsh_error.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_error.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_error.doj -MM + +./Debug/finsh_heap.doj :../../../components/finsh/finsh_heap.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_var.h + @echo "..\..\..\components\finsh\finsh_heap.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_heap.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_heap.doj -MM + +./Debug/finsh_init.doj :../../../components/finsh/finsh_init.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_node.h ../../../components/finsh/finsh_vm.h ../../../components/finsh/finsh_var.h ../../../components/finsh/finsh_parser.h ../../../components/finsh/finsh_error.h ../../../components/finsh/finsh_heap.h + @echo "..\..\..\components\finsh\finsh_init.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_init.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_init.doj -MM + +./Debug/finsh_node.doj :../../../components/finsh/finsh_node.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_node.h ../../../components/finsh/finsh_error.h ../../../components/finsh/finsh_var.h ../../../components/finsh/finsh_heap.h + @echo "..\..\..\components\finsh\finsh_node.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_node.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_node.doj -MM + +./Debug/finsh_ops.doj :../../../components/finsh/finsh_ops.c ../../../components/finsh/finsh_ops.h ../../../components/finsh/finsh_vm.h ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_var.h + @echo "..\..\..\components\finsh\finsh_ops.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_ops.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_ops.doj -MM + +./Debug/finsh_parser.doj :../../../components/finsh/finsh_parser.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_token.h ../../../components/finsh/finsh_node.h ../../../components/finsh/finsh_error.h ../../../components/finsh/finsh_parser.h ../../../components/finsh/finsh_var.h + @echo "..\..\..\components\finsh\finsh_parser.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_parser.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_parser.doj -MM + +./Debug/finsh_token.doj :../../../components/finsh/finsh_token.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_token.h ../../../components/finsh/finsh_error.h + @echo "..\..\..\components\finsh\finsh_token.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_token.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_token.doj -MM + +./Debug/finsh_var.doj :../../../components/finsh/finsh_var.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_var.h + @echo "..\..\..\components\finsh\finsh_var.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_var.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_var.doj -MM + +./Debug/finsh_vm.doj :../../../components/finsh/finsh_vm.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/finsh_vm.h ../../../components/finsh/finsh_var.h ../../../components/finsh/finsh_ops.h + @echo "..\..\..\components\finsh\finsh_vm.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\finsh_vm.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\finsh_vm.doj -MM + +./Debug/idle.doj :../../../src/idle.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\idle.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\idle.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\idle.doj -MM + +./Debug/ipc.doj :../../../src/ipc.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\ipc.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\ipc.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\ipc.doj -MM + +./Debug/irq.doj :../../../src/irq.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\irq.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\irq.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\irq.doj -MM + +./Debug/kservice.doj :../../../src/kservice.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\kservice.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\kservice.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\kservice.doj -MM + +./Debug/mem.doj :../../../src/mem.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../components/finsh/finsh.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h + @echo "..\..\..\src\mem.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\mem.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\mem.doj -MM + +./Debug/mempool.doj :../../../src/mempool.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\mempool.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\mempool.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\mempool.doj -MM + +./Debug/module.doj :../../../src/module.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rtm.h $(VDSP)/Blackfin/include/string.h + @echo "..\..\..\src\module.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\module.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\module.doj -MM + +./Debug/object.doj :../../../src/object.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\object.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\object.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\object.doj -MM + +./Debug/rtm.doj :../../../src/rtm.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/assert.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h $(VDSP)/Blackfin/include/stdio.h $(VDSP)/Blackfin/include/sys/stdio_bf.h + @echo "..\..\..\src\rtm.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\rtm.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\rtm.doj -MM + +./Debug/scheduler.doj :../../../src/scheduler.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\scheduler.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\scheduler.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\scheduler.doj -MM + +./Debug/serial.doj :../../../libcpu/blackfin/bf53x/serial.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../libcpu/blackfin/bf53x/serial.h ../../../include/rthw.h + @echo "..\..\..\libcpu\blackfin\bf53x\serial.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\libcpu\blackfin\bf53x\serial.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\serial.doj -MM + +./Debug/shell.doj :../../../components/finsh/shell.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h ../../../components/finsh/finsh.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h ../../../components/finsh/shell.h + @echo "..\..\..\components\finsh\shell.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\shell.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\shell.doj -MM + +./Debug/slab.doj :../../../src/slab.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h + @echo "..\..\..\src\slab.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\slab.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\slab.doj -MM + +./Debug/startup.doj :../startup.c ../../../include/rthw.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../application.h ../board.h ../../../libcpu/blackfin/bf53x/serial.h ../../../components/finsh/finsh.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h + @echo "..\startup.c" + $(VDSP)/ccblkfn.exe -c ..\startup.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\startup.doj -MM + +./Debug/symbol.doj :../../../components/finsh/symbol.c ../../../components/finsh/finsh.h ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h $(VDSP)/Blackfin/include/ctype.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/string.h + @echo "..\..\..\components\finsh\symbol.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\components\finsh\symbol.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\symbol.doj -MM + +./Debug/thread.doj :../../../src/thread.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\thread.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\thread.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\thread.doj -MM + +./Debug/timer.doj :../../../src/timer.c ../../../include/rtthread.h ../../../include/rtdef.h ../rtconfig.h $(VDSP)/Blackfin/include/stdarg.h $(VDSP)/Blackfin/include/yvals.h ../../../include/rtdebug.h ../../../include/rtservice.h ../../../include/rthw.h + @echo "..\..\..\src\timer.c" + $(VDSP)/ccblkfn.exe -c ..\..\..\src\timer.c -file-attr ProjectName=bf533 -g -structs-do-not-overlap -no-multiline -I ../../../include -I ../ -I ../../../components/finsh -I ../../../libcpu/blackfin/bf53x -I ../../../src -double-size-64 -decls-strong -warn-protos -proc ADSP-BF533 -o .\Debug\timer.doj -MM + +./Debug/bf533.dxe :./bf533_ram.ldf ./Debug/bf533_basiccrt.doj $(VDSP)/Blackfin/lib/bf532_rev_0.5/libprofile532y.dlb ./Debug/application.doj ./Debug/bf533_heaptab.doj ./Debug/board.doj ./Debug/clock.doj ./Debug/cmd.doj ./Debug/context_vdsp.doj ./Debug/cpuport.doj ./Debug/device.doj ./Debug/finsh_compiler.doj ./Debug/finsh_error.doj ./Debug/finsh_heap.doj ./Debug/finsh_init.doj ./Debug/finsh_node.doj ./Debug/finsh_ops.doj ./Debug/finsh_parser.doj ./Debug/finsh_token.doj ./Debug/finsh_var.doj ./Debug/finsh_vm.doj ./Debug/idle.doj ./Debug/ipc.doj ./Debug/irq.doj ./Debug/kservice.doj ./Debug/mem.doj ./Debug/mempool.doj ./Debug/module.doj ./Debug/object.doj ./Debug/rtm.doj ./Debug/scheduler.doj ./Debug/serial.doj ./Debug/shell.doj ./Debug/slab.doj ./Debug/startup.doj ./Debug/symbol.doj ./Debug/thread.doj ./Debug/timer.doj $(VDSP)/Blackfin/lib/cplbtab533.doj $(VDSP)/Blackfin/lib/bf532_rev_0.5/crtn532y.doj $(VDSP)/Blackfin/lib/bf532_rev_0.5/libsmall532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libio532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libc532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libevent532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libx532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libcpp532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libcpprt532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libf64ieee532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libdsp532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libsftflt532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/libetsi532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/Debug/libssl532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/Debug/libdrv532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/Debug/libusb532y.dlb $(VDSP)/Blackfin/lib/bf532_rev_0.5/idle532mty.doj $(VDSP)/Blackfin/lib/bf532_rev_0.5/librt_fileio532y.dlb + @echo "Linking..." + $(VDSP)/ccblkfn.exe .\Debug\application.doj .\Debug\bf533_basiccrt.doj .\Debug\bf533_heaptab.doj .\Debug\board.doj .\Debug\clock.doj .\Debug\cmd.doj .\Debug\context_vdsp.doj .\Debug\cpuport.doj .\Debug\device.doj .\Debug\finsh_compiler.doj .\Debug\finsh_error.doj .\Debug\finsh_heap.doj .\Debug\finsh_init.doj .\Debug\finsh_node.doj .\Debug\finsh_ops.doj .\Debug\finsh_parser.doj .\Debug\finsh_token.doj .\Debug\finsh_var.doj .\Debug\finsh_vm.doj .\Debug\idle.doj .\Debug\ipc.doj .\Debug\irq.doj .\Debug\kservice.doj .\Debug\mem.doj .\Debug\mempool.doj .\Debug\module.doj .\Debug\object.doj .\Debug\rtm.doj .\Debug\scheduler.doj .\Debug\serial.doj .\Debug\shell.doj .\Debug\slab.doj .\Debug\startup.doj .\Debug\symbol.doj .\Debug\thread.doj .\Debug\timer.doj -map .\Debug\bf533.map.xml -L .\Debug -flags-link -MDUSE_FILEIO,-MD__cplusplus,-MDUSER_CRT=ADI_QUOTEbf533_basiccrt.dojADI_QUOTE,-MDUSE_CACHE,-MDUSE_INSTRUCTION_CACHE -flags-link -e -add-debug-libpaths -flags-link -od,.\Debug -o .\Debug\bf533.dxe -proc ADSP-BF533 -flags-link -T,./bf533_ram.ldf -MM + +./Debug/bf533.ldr :./Debug/bf533.dxe + @echo "Creating loader file..." + $(VDSP)/elfloader.exe .\Debug\bf533.dxe -b Flash -f BINARY -Width 16 -init ./bf533_init.dxe -o .\Debug\bf533.ldr -proc ADSP-BF533 -MM + +endif + +ifeq ($(MAKECMDGOALS),bf533_Debug_clean) + +bf533_Debug_clean: + -$(RM) ".\Debug\application.doj" + -$(RM) ".\Debug\bf533_basiccrt.doj" + -$(RM) ".\Debug\bf533_heaptab.doj" + -$(RM) ".\Debug\board.doj" + -$(RM) ".\Debug\clock.doj" + -$(RM) ".\Debug\cmd.doj" + -$(RM) ".\Debug\context_vdsp.doj" + -$(RM) ".\Debug\cpuport.doj" + -$(RM) ".\Debug\device.doj" + -$(RM) ".\Debug\finsh_compiler.doj" + -$(RM) ".\Debug\finsh_error.doj" + -$(RM) ".\Debug\finsh_heap.doj" + -$(RM) ".\Debug\finsh_init.doj" + -$(RM) ".\Debug\finsh_node.doj" + -$(RM) ".\Debug\finsh_ops.doj" + -$(RM) ".\Debug\finsh_parser.doj" + -$(RM) ".\Debug\finsh_token.doj" + -$(RM) ".\Debug\finsh_var.doj" + -$(RM) ".\Debug\finsh_vm.doj" + -$(RM) ".\Debug\idle.doj" + -$(RM) ".\Debug\ipc.doj" + -$(RM) ".\Debug\irq.doj" + -$(RM) ".\Debug\kservice.doj" + -$(RM) ".\Debug\mem.doj" + -$(RM) ".\Debug\mempool.doj" + -$(RM) ".\Debug\module.doj" + -$(RM) ".\Debug\object.doj" + -$(RM) ".\Debug\rtm.doj" + -$(RM) ".\Debug\scheduler.doj" + -$(RM) ".\Debug\serial.doj" + -$(RM) ".\Debug\shell.doj" + -$(RM) ".\Debug\slab.doj" + -$(RM) ".\Debug\startup.doj" + -$(RM) ".\Debug\symbol.doj" + -$(RM) ".\Debug\thread.doj" + -$(RM) ".\Debug\timer.doj" + -$(RM) ".\Debug\bf533.dxe" + -$(RM) ".\Debug\bf533.ldr" + -$(RM) ".\Debug\*.ipa" + -$(RM) ".\Debug\*.opa" + -$(RM) ".\Debug\*.ti" + -$(RM) ".\Debug\*.pgi" + -$(RM) ".\*.rbld" + +endif + + diff --git a/bsp/bf533/vdsp/bf533.pcf b/bsp/bf533/vdsp/bf533.pcf new file mode 100644 index 0000000000..dbc0908871 Binary files /dev/null and b/bsp/bf533/vdsp/bf533.pcf differ diff --git a/bsp/bf533/vdsp/bf533_basiccrt.s b/bsp/bf533/vdsp/bf533_basiccrt.s new file mode 100644 index 0000000000..e48e71bfc6 --- /dev/null +++ b/bsp/bf533/vdsp/bf533_basiccrt.s @@ -0,0 +1,344 @@ +/* MANAGED-BY-SYSTEM-BUILDER */ +/* VisualDSP++ 5.0 Update 6 */ +/* CRT Printer version: 5.6.0.4 */ +/* crtgen.exe version: 5.6.0.4 */ +/* VDSG version: 5.6.0.4 */ + +/* +** bf533_basiccrt.s generated on May 08, 2012 at 10:55:43. +** +** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved. +** This contains Analog Devices Background IP and Development IP as +** defined in the ADI/Intel Collaboration Agreement. +** +** This file is generated automatically based upon the options selected +** in the Startup Code Wizard. Changes to the startup configuration +** should be made by changing the appropriate options rather than +** editing this file. Additional user code to be executed before calling +** main can be inserted between the labels .start_of_user_code1 and +** .end_of_user_code1 or .start_of_user_code2 and .end_of_user_code2. +** This code is preserved if the CRT is re-generated. +** +** Configuration:- +** product_name: VisualDSP++ 5.0 Update 6 +** processor: ADSP-BF533 +** si_revision: automatic +** cplb_init: true +** cplb_ctrl: ( +** CPLB_ENABLE_ICACHE +** CPLB_ENABLE_ICPLBS +** ) +** mem_init: false +** device_init: true +** init_regs: false +** zero_return_regs: false +** use_profiling: false +** use_vdk: false +** set_clock_and_power: false +** +*/ + +///////////////////////////////////////////////////////////////// +// blackfin-edinburgh-core +#include +#include + +///////////////////////////////////////////////////////////////// +// standard +#define IVBh (EVT0 >> 16) +#define IVBl (EVT0 & 0xFFFF) +#define UNASSIGNED_VAL 0x8181 +#define INTERRUPT_BITS 0x400 // just IVG15 +#define SYSCFG_VALUE 0x30 + + .section/DOUBLEANY program; + .file_attr requiredForROMBoot; + .align 2; + +start: + + +/*$VDSG */ +.start_of_user_code_very_beginning: + // Insert additional code to be executed before any other Startup Code here. + // This code is preserved if the CRT is re-generated. +.end_of_user_code_very_beginning: +/*$VDSG */ + +///////////////////////////////////////////////////////////////// +// blackfin-edinburgh-core +#if WA_05000109 + // Avoid Anomaly 05-00-0109 + R1 = SYSCFG_VALUE; + SYSCFG = R1; +#endif + +///////////////////////////////////////////////////////////////// +// standard +#if WA_05000229 + // Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset. + R1 = 0x400; +#if defined(__ADSPBF538__) || defined(__ADSPBF539__) + P0.L = SPI0_CTL & 0xFFFF; + P0.H = SPI0_CTL >> 16; + W[P0] = R1.L; +#else + P0.L = SPI_CTL & 0xFFFF; + P0.H = SPI_CTL >> 16; + W[P0] = R1.L; +#endif + P0.L = DMA5_CONFIG & 0xFFFF; + P0.H = DMA5_CONFIG >> 16; + R1 = 0; + W[P0] = R1.L; +#endif + // Clear loop counters to disable hardware loops + R7 = 0; + LC0 = R7; + LC1 = R7; + + // Clear the DAG Length regs, to force linear addressing + L0 = R7; + L1 = R7; + L2 = R7; + L3 = R7; + + // Clear ITEST_COMMAND and DTEST_COMMAND registers + I0.L = (ITEST_COMMAND & 0xFFFF); + I0.H = (ITEST_COMMAND >> 16); + I1.L = (DTEST_COMMAND & 0xFFFF); + I1.H = (DTEST_COMMAND >> 16); + [I0] = R7; + [I1] = R7; + CSYNC; + + // Initialise the Event Vector table. + P0.H = IVBh; + P0.L = IVBl; + + // Install __unknown_exception_occurred in EVT so that + // there is defined behaviour. + P0 += 2*4; // Skip Emulation and Reset + P1 = 13; + R1.L = __unknown_exception_occurred; + R1.H = __unknown_exception_occurred; + LSETUP (.ivt,.ivt) LC0 = P1; +.ivt: [P0++] = R1; + + // Set IVG15's handler to be the start of the mode-change + // code. Then, before we return from the Reset back to user + // mode, we'll raise IVG15. This will mean we stay in supervisor + // mode, and continue from the mode-change point, but at a + // much lower priority. + P1.H = supervisor_mode; + P1.L = supervisor_mode; + [P0] = P1; + +///////////////////////////////////////////////////////////////// +// cplb-handler +#include "cplb.h" + P1.H = _cplb_hdr; + P1.L = _cplb_hdr; + [P0-48] = P1; // write exception handler +.extern _cplb_hdr; + + +///////////////////////////////////////////////////////////////// +// standard + // Initialise the stack. + // Note: this points just past the end of the section. + // First write should be with [--SP]. + SP.L=ldf_stack_end; + SP.H=ldf_stack_end; + usp = sp; + + // We're still in supervisor mode at the moment, so the FP + // needs to point to the supervisor stack. + FP = SP; + + // Make space for incoming "parameters" for functions + // we call from here: + SP += -12; + + R0 = INTERRUPT_BITS; + R0 <<= 5; // Bits 0-4 not settable. + CALL.X __install_default_handlers; + + R1 = SYSCFG; + R4 = R0; // Save modified list + BITSET(R1,1); + SYSCFG = R1; // Enable the cycle counter + +///////////////////////////////////////////////////////////////// +// blackfin-edinburgh-core +#if WA_05000137 + // Avoid Anomaly 02-00-0137 + // Set the port preferences of DAG0 and DAG1 to be + // different; this gives better performance when + // performing daul-dag operations on SDRAM. + P0.L = DMEM_CONTROL & 0xFFFF; + P0.H = DMEM_CONTROL >> 16; + R0 = [P0]; + BITSET(R0, 12); + BITCLR(R0, 13); + [P0] = R0; + CSYNC; +#endif + + +/*$VDSG */ +.start_of_user_code1: + // Insert additional code to be executed before main here. + // This code is preserved if the CRT is re-generated. +.end_of_user_code1: +/*$VDSG */ + +///////////////////////////////////////////////////////////////// +// cplb-init + // initialise the CPLBs if they're needed. This was not possible + // before we set up the stacks. + R0 = 81; // cplb_ctrl = 81 + CALL.X _cplb_init; +.extern _cplb_init; +.type _cplb_init,STT_FUNC; + + .section/DOUBLEANY data1; +___cplb_ctrl: + .align 4; + .byte4=81; +.global ___cplb_ctrl; +.type ___cplb_ctrl,STT_OBJECT; + .section/DOUBLEANY program; + .align 2; + +///////////////////////////////////////////////////////////////// +// standard + // Enable interrupts + STI R4; // Using the mask from default handlers + RAISE 15; + + // Move the processor into user mode. + P0.L=still_interrupt_in_ipend; + P0.H=still_interrupt_in_ipend; + RETI=P0; + NOP; // Purely to prevent a stall warning + +still_interrupt_in_ipend: + // execute RTI until we've `finished` servicing all + // interrupts of priority higher than IVG15. Normally one + // would expect to only have the reset interrupt in IPEND + // being serviced, but occasionally when debugging this may + // not be the case - if restart is hit when servicing an + // interrupt. + // + // When we clear all bits from IPEND, we'll enter user mode, + // then we'll automatically jump to supervisor_mode to start + // servicing IVG15 (which we will 'service' for the whole + // program, so that the program is in supervisor mode. + // Need to do this to 'finish' servicing the reset interupt. + RTI; + +supervisor_mode: + [--SP] = RETI; // re-enables the interrupt system + R0.L = UNASSIGNED_VAL; + R0.H = UNASSIGNED_VAL; + + // Push a RETS and Old FP onto the stack, for sanity. + [--SP]=R0; + [--SP]=R0; + // Make sure the FP is sensible. + FP = SP; + // Leave space for incoming "parameters" + SP += -12; + + +/*$VDSG */ +.start_of_user_code2: + // Insert additional code to be executed before device initialization here. + // This code is preserved if the CRT is re-generated. +.end_of_user_code2: +/*$VDSG */ + +///////////////////////////////////////////////////////////////// +// device-initialization + // initialise the devices known about for stdio. + CALL.X _init_devtab; +.extern _init_devtab; +.type _init_devtab,STT_FUNC; + +///////////////////////////////////////////////////////////////// +// cplusplus + CALL.X ___ctorloop; // run global scope C++ constructors +.extern ___ctorloop; +.type ___ctorloop,STT_FUNC; + + +/*$VDSG */ +.start_of_user_code3: + // Insert additional code to be executed before main here. + // This code is preserved if the CRT is re-generated. +.end_of_user_code3: +/*$VDSG */ + +///////////////////////////////////////////////////////////////// +// get-args + // Read command-line arguments. + CALL.X __getargv; + r1.l=__Argv; + r1.h=__Argv; + +.extern __getargv; +.type __getargv,STT_FUNC; +.extern __Argv; +.type __Argv,STT_OBJECT; + +///////////////////////////////////////////////////////////////// +// standard + // Call the application program. + CALL.X _main; + +///////////////////////////////////////////////////////////////// +// call-exit + CALL.X _exit; // passing in main's return value +.extern _exit; +.type _exit,STT_FUNC; + +///////////////////////////////////////////////////////////////// +// standard +.start.end: // Required by the linker to know the size of the routine + // that is needed for absolute placement. + +.global start; +.type start,STT_FUNC; +.global .start.end; +.type .start.end,STT_FUNC; +.extern _main; +.type _main,STT_FUNC; +.extern ldf_stack_end; +.extern __unknown_exception_occurred; +.type __unknown_exception_occurred,STT_FUNC; +.extern __install_default_handlers; +.type __install_default_handlers,STT_FUNC; + + +///////////////////////////////////////////////////////////////// +// cplusplus +.section/DOUBLEANY ctor; + .align 4; +___ctor_table: + .byte4=0; +.global ___ctor_table; +.type ___ctor_table,STT_OBJECT; +.section/DOUBLEANY .gdt; + .align 4; +___eh_gdt: +.global ___eh_gdt; + .byte4=0; +.type ___eh_gdt,STT_OBJECT; +.section/DOUBLEANY .frt; + .align 4; +___eh_frt: +.global ___eh_frt; + .byte4=0; +.type ___eh_frt,STT_OBJECT; + diff --git a/bsp/bf533/vdsp/bf533_heaptab.c b/bsp/bf533/vdsp/bf533_heaptab.c new file mode 100644 index 0000000000..d2364a8c74 --- /dev/null +++ b/bsp/bf533/vdsp/bf533_heaptab.c @@ -0,0 +1,85 @@ +/* MANAGED-BY-SYSTEM-BUILDER */ +/* VisualDSP++ 5.0 Update 6 */ +/* LDF Printer version: 5.6.0.4 */ +/* ldfgen.exe version: 5.6.0.4 */ +/* VDSG version: 5.6.0.4 */ + +/* +** User heap source file generated on Feb 23, 2012 at 09:38:46. +** +** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved. +** +** This file is generated automatically based upon the options selected +** in the LDF Wizard. Changes to the LDF configuration should be made by +** changing the appropriate options rather than editing this file. +** +** Configuration:- +** crt_doj: bf533_basiccrt.doj +** processor: ADSP-BF533 +** product_name: VisualDSP++ 5.0 Update 6 +** si_revision: 0.5 +** default_silicon_revision_from_archdef: 0.5 +** cplb_init_cplb_ctrl: 81 +** using_cplusplus: true +** mem_init: false +** use_vdk: false +** use_eh: true +** use_argv: false +** running_from_internal_memory: true +** user_heap_src_file: E:\eclipse\tq2440radio\bsp\bf533\vdsp\bf533_heaptab.c +** libraries_use_stdlib: true +** libraries_use_fileio_libs: false +** libraries_use_ieeefp_emulation_libs: false +** libraries_use_eh_enabled_libs: false +** system_heap: L1 +** system_heap_min_size: 1k +** system_stack: L1 +** system_stack_min_size: 1k +** use_sdram: false +** +*/ + + +#ifdef _MISRA_RULES +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1) +#pragma diag(suppress:misra_rule_2_2) +#pragma diag(suppress:misra_rule_6_3) +#pragma diag(suppress:misra_rule_8_10) +#pragma diag(suppress:misra_rule_10_1_a) +#pragma diag(suppress:misra_rule_11_3) +#pragma diag(suppress:misra_rule_12_7) +#endif /* _MISRA_RULES */ + + + +extern "asm" int ldf_heap_space; +extern "asm" int ldf_heap_length; + + +struct heap_table_t +{ + void *base; + unsigned long length; + long int userid; +}; + +#pragma file_attr("libData=HeapTable") +#pragma section("constdata") +struct heap_table_t heap_table[2] = +{ + + + { &ldf_heap_space, (int) &ldf_heap_length, 0 }, + + + { 0, 0, 0 } +}; + + + +#ifdef _MISRA_RULES +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + diff --git a/bsp/bf533/vdsp/bf533_init.dxe b/bsp/bf533/vdsp/bf533_init.dxe new file mode 100644 index 0000000000..25e3d5af41 Binary files /dev/null and b/bsp/bf533/vdsp/bf533_init.dxe differ diff --git a/bsp/bf533/vdsp/bf533_ram.ldf b/bsp/bf533/vdsp/bf533_ram.ldf new file mode 100644 index 0000000000..beac9dfefd --- /dev/null +++ b/bsp/bf533/vdsp/bf533_ram.ldf @@ -0,0 +1,424 @@ +/* MANAGED-BY-SYSTEM-BUILDER */ +/* VisualDSP++ 5.0 Update 6 */ +/* LDF Printer version: 5.6.0.4 */ +/* ldfgen.exe version: 5.6.0.4 */ +/* VDSG version: 5.6.0.4 */ + +/* +** ADSP-BF533 linker description file generated on Feb 23, 2012 at 09:38:46. +** +** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved. +** +** This file is generated automatically based upon the options selected +** in the LDF Wizard. Changes to the LDF configuration should be made by +** changing the appropriate options rather than editing this file. +** +** Configuration:- +** crt_doj: bf533_basiccrt.doj +** processor: ADSP-BF533 +** product_name: VisualDSP++ 5.0 Update 6 +** si_revision: automatic +** default_silicon_revision_from_archdef: 0.5 +** cplb_init_cplb_ctrl: ( +** CPLB_ENABLE_ICACHE +** CPLB_ENABLE_ICPLBS +** ) +** using_cplusplus: true +** mem_init: false +** use_vdk: false +** use_eh: true +** use_argv: false +** running_from_internal_memory: true +** user_heap_src_file: E:\eclipse\tq2440radio\bsp\bf533\vdsp\bf533_heaptab.c +** libraries_use_stdlib: true +** libraries_use_fileio_libs: false +** libraries_use_ieeefp_emulation_libs: false +** libraries_use_eh_enabled_libs: false +** system_heap: L1 +** system_heap_min_size: 1k +** system_stack: L1 +** system_stack_min_size: 1k +** use_sdram: false +** +*/ + +ARCHITECTURE(ADSP-BF533) + +SEARCH_DIR($ADI_DSP/Blackfin/lib) + + +// Workarounds are enabled, exceptions are disabled. +#define RT_LIB_NAME(x) lib ## x ## y.dlb +#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb +#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb +#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb +#define RT_OBJ_NAME(x) x ## y.doj +#define RT_OBJ_NAME_MT(x) x ## mty.doj + + +$LIBRARIES = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + RT_LIB_NAME_MT(small532) + ,RT_LIB_NAME_MT(io532) + ,RT_LIB_NAME_MT(c532) + ,RT_LIB_NAME_MT(event532) + ,RT_LIB_NAME_MT(x532) + ,RT_LIB_NAME_EH_MT(cpp532) + ,RT_LIB_NAME_EH_MT(cpprt532) + ,RT_LIB_NAME(f64ieee532) + ,RT_LIB_NAME(dsp532) + ,RT_LIB_NAME(sftflt532) + ,RT_LIB_NAME(etsi532) + ,RT_LIB_NAME(ssl532) + ,RT_LIB_NAME(drv532) + ,RT_LIB_NAME(usb532) + ,RT_OBJ_NAME_MT(idle532) + ,RT_LIB_NAME_MT(rt_fileio532) + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + +$OBJECTS = + "bf533_basiccrt.doj" + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + , RT_LIB_NAME(profile532) + , $COMMAND_LINE_OBJECTS + , "cplbtab533.doj" + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + , RT_OBJ_NAME(crtn532) + ; + +$OBJS_LIBS_INTERNAL = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")} + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + +$OBJS_LIBS_NOT_EXTERNAL = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")} + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + +/*$VDSG */ +/* This code is preserved if the LDF is re-generated. */ + + +#define ASYNC0_MEMTYPE RAM +#define ASYNC1_MEMTYPE RAM +#define ASYNC2_MEMTYPE RAM +#define ASYNC3_MEMTYPE RAM + + +/*$VDSG */ + + +MEMORY +{ +/* +** ADSP-BF533 MEMORY MAP. +** +** The known memory spaces are as follows: +** +** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB) +** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB) +** 0xFFB01000 - 0xFFBFFFFF Reserved +** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K) +** 0xFFA14000 - 0xFFAFFFFF Reserved +** 0xFFA10000 - 0xFFA13FFF Code SRAM / cache (16K) +** 0xFFA00000 - 0xFFA0FFFF Code SRAM (64K) +** 0xFF908000 - 0xFF9FFFFF Reserved +** 0xFF904000 - 0xFF907FFF Data Bank B SRAM / cache (16K) +** 0xFF900000 - 0xFF903FFF Data Bank B SRAM (16K) +** 0xFF808000 - 0xFF8FFFFF Reserved +** 0xFF804000 - 0xFF807FFF Data Bank A SRAM / cache (16K) +** 0xFF800000 - 0xFF803FFF Data Bank A SRAM (16K) +** 0xEF000000 - 0xFF7FFFFF Reserved +** 0x20400000 - 0xEEFFFFFF Reserved +** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB) +** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB) +** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB) +** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB) +** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB) +*/ + + MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) } + MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) } + MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0FFFF) WIDTH(8) } + MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) } + MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) } + MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) } + MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) } + MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) } + MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) } + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + +} /* MEMORY */ + +PROCESSOR p0 +{ + OUTPUT($COMMAND_LINE_OUTPUT_FILE) + RESOLVE(start, 0xFFA00000) + KEEP(start, _main) + KEEP_SECTIONS(FSymTab,VSymTab,RTMSymTab) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + SECTIONS + { + /* Workaround for hardware errata 05-00-0189 and 05-00-0310 - + ** "Speculative (and fetches made at boundary of reserved memory + ** space) for instruction or data fetches may cause false + ** protection exceptions" and "False hardware errors caused by + ** fetches at the boundary of reserved memory ". + ** + ** Done by avoiding use of 76 bytes from at the end of blocks + ** that are adjacent to reserved memory. Workaround is enabled + ** for appropriate silicon revisions (-si-revision switch). + */ + RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76) + RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76) + RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76) + RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76) + RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + scratchpad NO_INIT + { + INPUT_SECTION_ALIGN(4) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_SCRATCH + + L1_code + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code)) + INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb)) + INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program)) + INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_CODE + + L1_code_cache + { + INPUT_SECTION_ALIGN(4) + ___l1_code_cache = 1; + } > MEM_L1_CODE_CACHE + + L1_data_a_1 + { + INPUT_SECTION_ALIGN(4) + ___l1_data_cache_a = 0; + INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a)) + INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 1024,4) + } > MEM_L1_DATA_A + + L1_data_a_bsz ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz)) + } > MEM_L1_DATA_A + + L1_data_a_tables + { + INPUT_SECTION_ALIGN(4) + FORCE_CONTIGUITY + INPUT_SECTIONS($OBJECTS(vtbl) $LIBRARIES(vtbl)) + INPUT_SECTIONS($OBJECTS(ctor) $LIBRARIES(ctor)) + INPUT_SECTIONS($OBJECTS(ctorl) $LIBRARIES(ctorl)) + INPUT_SECTIONS($OBJECTS(.frt) $LIBRARIES(.frt)) + INPUT_SECTIONS($OBJECTS(.rtti) $LIBRARIES(.rtti)) + INPUT_SECTIONS($OBJECTS(.gdt) $LIBRARIES(.gdt)) + INPUT_SECTIONS($OBJECTS(.gdtl) $LIBRARIES(.gdtl)) + INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt)) + INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht)) + } > MEM_L1_DATA_A + + L1_data_a + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data)) + INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1)) + INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1)) + INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_DATA_A + + bsz_L1_data_a ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz)) + INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz)) + } > MEM_L1_DATA_A + + L1_data_a_stack_heap + { + INPUT_SECTION_ALIGN(4) + RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4) + ldf_stack_space = heaps_and_stack_in_L1_data_a; + ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_a_length - 4)) & 0xfffffffc; + } > MEM_L1_DATA_A + + L1_data_b_bsz ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz)) + } > MEM_L1_DATA_B + + L1_data_b + { + INPUT_SECTION_ALIGN(4) + ___l1_data_cache_b = 0; + INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b)) + INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 1024,4) + INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data)) + INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1)) + INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1)) + INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata)) + INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt) ) + INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht) ) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_DATA_B + + bsz_L1_data_b ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz)) + INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz)) + } > MEM_L1_DATA_B + + rt_thread_section + { + /* section information for finsh shell */ + INPUT_SECTION_ALIGN(4) + __fsymtab_start = .; + INPUT_SECTIONS($OBJECTS(FSymTab) $LIBRARIES(FSymTab)) + __fsymtab_end = .; + + INPUT_SECTION_ALIGN(4) + __vsymtab_start = .; + INPUT_SECTIONS($OBJECTS(VSymTab) $LIBRARIES(VSymTab)) + __vsymtab_end = .; + + /* section information for modules */ + INPUT_SECTION_ALIGN(4) + __rtmsymtab_start = .; + INPUT_SECTIONS($OBJECTS(RTMSymTab) $LIBRARIES(RTMSymTab)) + __rtmsymtab_end = .; + + RESERVE(heaps_in_L1_data_b_space, heaps_in_L1_data_b_length = 2048,4) + } > MEM_L1_DATA_B + + L1_data_b_stack_heap + { + INPUT_SECTION_ALIGN(4) + ldf_heap_space = heaps_and_stack_in_L1_data_b; + ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_b_length - 4)) & 0xfffffffc; + ldf_heap_length = ldf_heap_end - ldf_heap_space; + + RESERVE_EXPAND(heaps_in_L1_data_b_space, heaps_in_L1_data_b_length , 0, 4) + rtt_heap_start = heaps_in_L1_data_b_space; + rtt_heap_end = (heaps_in_L1_data_b_space + heaps_in_L1_data_b_length - 4) & 0xfffffffc; + rtt_heap_length = rtt_heap_end - rtt_heap_start; + } > MEM_L1_DATA_B + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } /* SECTIONS */ +} /* p0 */ + diff --git a/bsp/bf533/vdsp/bf533_sdram_64M.ldf b/bsp/bf533/vdsp/bf533_sdram_64M.ldf new file mode 100644 index 0000000000..4b23fbfaf6 --- /dev/null +++ b/bsp/bf533/vdsp/bf533_sdram_64M.ldf @@ -0,0 +1,486 @@ +/* MANAGED-BY-SYSTEM-BUILDER */ +/* VisualDSP++ 5.0 Update 6 */ +/* LDF Printer version: 5.6.0.4 */ +/* ldfgen.exe version: 5.6.0.4 */ +/* VDSG version: 5.6.0.4 */ + +/* +** ADSP-BF533 linker description file generated on Feb 22, 2012 at 14:26:29. +** +** Copyright (C) 2000-2008 Analog Devices Inc., All Rights Reserved. +** +** This file is generated automatically based upon the options selected +** in the LDF Wizard. Changes to the LDF configuration should be made by +** changing the appropriate options rather than editing this file. +** +** Configuration:- +** crt_doj: bf533_basiccrt.doj +** processor: ADSP-BF533 +** product_name: VisualDSP++ 5.0 Update 6 +** si_revision: automatic +** default_silicon_revision_from_archdef: 0.5 +** cplb_init_cplb_ctrl: ( +** CPLB_ENABLE_ICACHE +** CPLB_ENABLE_DCACHE +** CPLB_ENABLE_DCACHE2 +** CPLB_ENABLE_CPLBS +** CPLB_ENABLE_ICPLBS +** CPLB_ENABLE_DCPLBS +** ) +** using_cplusplus: true +** mem_init: false +** use_vdk: false +** use_eh: true +** use_argv: false +** running_from_internal_memory: true +** user_heap_src_file: E:\eclipse\3m_dsp\ARZ-3M3B-DSP_base26\rt-thread\bsp\bf533\vdsp\bf533_heaptab.c +** libraries_use_stdlib: true +** libraries_use_fileio_libs: false +** libraries_use_ieeefp_emulation_libs: false +** libraries_use_eh_enabled_libs: false +** system_heap: L1 +** system_heap_min_size: 1k +** system_stack: L1 +** system_stack_min_size: 1k +** use_sdram: true +** use_sdram_size: 64MB +** use_sdram_partitioned: none +** +*/ + +ARCHITECTURE(ADSP-BF533) + +SEARCH_DIR($ADI_DSP/Blackfin/lib) + + +// Workarounds are enabled, exceptions are disabled. +#define RT_LIB_NAME(x) lib ## x ## y.dlb +#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb +#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb +#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb +#define RT_OBJ_NAME(x) x ## y.doj +#define RT_OBJ_NAME_MT(x) x ## mty.doj + + +$LIBRARIES = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + RT_LIB_NAME_MT(small532) + ,RT_LIB_NAME_MT(io532) + ,RT_LIB_NAME_MT(c532) + ,RT_LIB_NAME_MT(event532) + ,RT_LIB_NAME_MT(x532) + ,RT_LIB_NAME_EH_MT(cpp532) + ,RT_LIB_NAME_EH_MT(cpprt532) + ,RT_LIB_NAME(f64ieee532) + ,RT_LIB_NAME(dsp532) + ,RT_LIB_NAME(sftflt532) + ,RT_LIB_NAME(etsi532) + ,RT_LIB_NAME(ssl532) + ,RT_LIB_NAME(drv532) + ,RT_LIB_NAME(usb532) + ,RT_OBJ_NAME_MT(idle532) + ,RT_LIB_NAME_MT(rt_fileio532) + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + +$OBJECTS = + "bf533_basiccrt.doj" + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + , RT_LIB_NAME(profile532) + , $COMMAND_LINE_OBJECTS + , "cplbtab533.doj" + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + , RT_OBJ_NAME(crtn532) + ; + +$OBJS_LIBS_INTERNAL = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")} + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + +$OBJS_LIBS_NOT_EXTERNAL = + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")} + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + ; + + +/*$VDSG */ +/* Text inserted between these $VDSG comments will be preserved */ +/*$VDSG */ + + +/*$VDSG */ +/* This code is preserved if the LDF is re-generated. */ + + +#define ASYNC0_MEMTYPE RAM +#define ASYNC1_MEMTYPE RAM +#define ASYNC2_MEMTYPE RAM +#define ASYNC3_MEMTYPE RAM + + +/*$VDSG */ + + +MEMORY +{ +/* +** ADSP-BF533 MEMORY MAP. +** +** The known memory spaces are as follows: +** +** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB) +** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB) +** 0xFFB01000 - 0xFFBFFFFF Reserved +** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K) +** 0xFFA14000 - 0xFFAFFFFF Reserved +** 0xFFA10000 - 0xFFA13FFF Code SRAM / cache (16K) +** 0xFFA00000 - 0xFFA0FFFF Code SRAM (64K) +** 0xFF908000 - 0xFF9FFFFF Reserved +** 0xFF904000 - 0xFF907FFF Data Bank B SRAM / cache (16K) +** 0xFF900000 - 0xFF903FFF Data Bank B SRAM (16K) +** 0xFF808000 - 0xFF8FFFFF Reserved +** 0xFF804000 - 0xFF807FFF Data Bank A SRAM / cache (16K) +** 0xFF800000 - 0xFF803FFF Data Bank A SRAM (16K) +** 0xEF000000 - 0xFF7FFFFF Reserved +** 0x20400000 - 0xEEFFFFFF Reserved +** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB) +** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB) +** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB) +** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB) +** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB) +*/ + + MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) } + MEM_L1_CODE_CACHE { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) } + MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA0FFFF) WIDTH(8) } + MEM_L1_DATA_B_CACHE { TYPE(RAM) START(0xFF904000) END(0xFF907FFF) WIDTH(8) } + MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF903FFF) WIDTH(8) } + MEM_L1_DATA_A_CACHE { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) } + MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) } + MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) } + MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) } + MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) } + MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) } + MEM_SDRAM0 { TYPE(RAM) START(0x00000004) END(0x03ffffff) WIDTH(8) } + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + +} /* MEMORY */ + +PROCESSOR p0 +{ + OUTPUT($COMMAND_LINE_OUTPUT_FILE) + RESOLVE(start, 0xFFA00000) + KEEP(start, _main) + KEEP_SECTIONS(FSymTab,VSymTab,RTMSymTab) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + SECTIONS + { + /* Workaround for hardware errata 05-00-0189 and 05-00-0310 - + ** "Speculative (and fetches made at boundary of reserved memory + ** space) for instruction or data fetches may cause false + ** protection exceptions" and "False hardware errors caused by + ** fetches at the boundary of reserved memory ". + ** + ** Done by avoiding use of 76 bytes from at the end of blocks + ** that are adjacent to reserved memory. Workaround is enabled + ** for appropriate silicon revisions (-si-revision switch). + */ + RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76) + RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76) + RESERVE(___wab3=MEMORY_END(MEM_L1_DATA_B_CACHE) - 75, ___l3 = 76) + RESERVE(___wab5=MEMORY_END(MEM_L1_DATA_A_CACHE) - 75, ___l5 = 76) + RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76) + RESERVE(___wab9=MEMORY_END(MEM_SDRAM0) - 75, ___l9 = 76) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + scratchpad NO_INIT + { + INPUT_SECTION_ALIGN(4) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + INPUT_SECTIONS($OBJECTS(L1_scratchpad) $LIBRARIES(L1_scratchpad)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_SCRATCH + + L1_code + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(L1_code) $LIBRARIES(L1_code)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code)) + INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb)) + INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(program)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(program)) + INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_CODE + + L1_code_cache + { + INPUT_SECTION_ALIGN(4) + ___l1_code_cache = 1; + } > MEM_L1_CODE_CACHE + + L1_data_a_1 + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(L1_data_a) $LIBRARIES(L1_data_a)) + INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + RESERVE(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length = 1024,4) + } > MEM_L1_DATA_A + + L1_data_a_bsz ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz)) + } > MEM_L1_DATA_A + + L1_data_a_tables + { + INPUT_SECTION_ALIGN(4) + FORCE_CONTIGUITY + INPUT_SECTIONS($OBJECTS(vtbl) $LIBRARIES(vtbl)) + INPUT_SECTIONS($OBJECTS(ctor) $LIBRARIES(ctor)) + INPUT_SECTIONS($OBJECTS(ctorl) $LIBRARIES(ctorl)) + INPUT_SECTIONS($OBJECTS(.frt) $LIBRARIES(.frt)) + INPUT_SECTIONS($OBJECTS(.rtti) $LIBRARIES(.rtti)) + INPUT_SECTIONS($OBJECTS(.gdt) $LIBRARIES(.gdt)) + INPUT_SECTIONS($OBJECTS(.gdtl) $LIBRARIES(.gdtl)) + INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt)) + INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht)) + } > MEM_L1_DATA_A + + L1_data_a + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data)) + INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1)) + INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1)) + INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_DATA_A + + bsz_L1_data_a ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz)) + INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz)) + } > MEM_L1_DATA_A + + L1_data_a_stack_heap + { + INPUT_SECTION_ALIGN(4) + RESERVE_EXPAND(heaps_and_stack_in_L1_data_a, heaps_and_stack_in_L1_data_a_length , 0, 4) + ldf_stack_space = heaps_and_stack_in_L1_data_a; + ldf_stack_end = (ldf_stack_space + (heaps_and_stack_in_L1_data_a_length - 4)) & 0xfffffffc; + } > MEM_L1_DATA_A + + L1_data_a_cache + { + INPUT_SECTION_ALIGN(4) + ___l1_data_cache_a = 1; + } > MEM_L1_DATA_A_CACHE + + L1_data_b_bsz ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS( $OBJECTS(L1_bsz) $LIBRARIES(L1_bsz)) + } > MEM_L1_DATA_B + + L1_data_b + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(L1_data_b) $LIBRARIES(L1_data_b)) + INPUT_SECTIONS($OBJECTS(L1_data) $LIBRARIES(L1_data)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + RESERVE(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length = 1024,4) + INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data)) + INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata)) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(data1)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(data1)) + INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1)) + INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata)) + INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt) ) + INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht) ) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_L1_DATA_B + + bsz_L1_data_b ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJS_LIBS_INTERNAL(bsz)) + INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL(bsz)) + INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz)) + } > MEM_L1_DATA_B + + L1_data_b_stack_heap + { + INPUT_SECTION_ALIGN(4) + RESERVE_EXPAND(heaps_and_stack_in_L1_data_b, heaps_and_stack_in_L1_data_b_length , 0, 4) + ldf_heap_space = heaps_and_stack_in_L1_data_b; + ldf_heap_end = (ldf_heap_space + (heaps_and_stack_in_L1_data_b_length - 4)) & 0xfffffffc; + ldf_heap_length = ldf_heap_end - ldf_heap_space; + } > MEM_L1_DATA_B + + L1_data_b_cache + { + INPUT_SECTION_ALIGN(4) + ___l1_data_cache_b = 1; + } > MEM_L1_DATA_B_CACHE + + sdram + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES(sdram0)) + INPUT_SECTIONS($OBJECTS(sdram0_bank0) $LIBRARIES(sdram0_bank0)) + INPUT_SECTIONS($OBJECTS(sdram0_bank1) $LIBRARIES(sdram0_bank1)) + INPUT_SECTIONS($OBJECTS(sdram0_bank2) $LIBRARIES(sdram0_bank2)) + INPUT_SECTIONS($OBJECTS(sdram0_bank3) $LIBRARIES(sdram0_bank3)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + INPUT_SECTIONS($OBJECTS(noncache_code) $LIBRARIES(noncache_code)) + INPUT_SECTIONS($OBJECTS(program) $LIBRARIES(program)) + INPUT_SECTIONS($OBJECTS(cplb) $LIBRARIES(cplb)) + INPUT_SECTIONS($OBJECTS(cplb_code) $LIBRARIES(cplb_code)) + INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1)) + INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata)) + INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata)) + INPUT_SECTIONS($OBJECTS(cplb_data) $LIBRARIES(cplb_data)) + INPUT_SECTIONS($OBJECTS(.edt) $LIBRARIES(.edt)) + INPUT_SECTIONS($OBJECTS(.cht) $LIBRARIES(.cht)) + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } > MEM_SDRAM0 + + bsz_sdram0 ZERO_INIT + { + INPUT_SECTION_ALIGN(4) + INPUT_SECTIONS($OBJECTS(sdram_bsz) $LIBRARIES(sdram_bsz)) + INPUT_SECTIONS($OBJECTS(bsz) $LIBRARIES(bsz)) + } > MEM_SDRAM0 + + rt_thread_section + { + /* section information for finsh shell */ + INPUT_SECTION_ALIGN(4) + __fsymtab_start = .; + INPUT_SECTIONS($OBJECTS(FSymTab) $LIBRARIES(FSymTab)) + __fsymtab_end = .; + + INPUT_SECTION_ALIGN(4) + __vsymtab_start = .; + INPUT_SECTIONS($OBJECTS(VSymTab) $LIBRARIES(VSymTab)) + __vsymtab_end = .; + + /* section information for modules */ + INPUT_SECTION_ALIGN(4) + __rtmsymtab_start = .; + INPUT_SECTIONS($OBJECTS(RTMSymTab) $LIBRARIES(RTMSymTab)) + __rtmsymtab_end = .; + + RESERVE(heaps_in_sdram_space, heaps_in_sdram_length = 2048,4) + } > MEM_SDRAM0 + + sdram_stack_heap + { + RESERVE_EXPAND(heaps_in_sdram_space, heaps_in_sdram_length , 0, 4) + rtt_heap_start = heaps_in_sdram_space; + rtt_heap_end = (heaps_in_sdram_space + heaps_in_sdram_length - 32) & 0xfffffffc; + rtt_heap_length = rtt_heap_end - rtt_heap_start; + } > MEM_SDRAM0 + + + /*$VDSG */ + /* Text inserted between these $VDSG comments will be preserved */ + /*$VDSG */ + + } /* SECTIONS */ +} /* p0 */ + diff --git a/bsp/bf533/vdsp/mine.dxe b/bsp/bf533/vdsp/mine.dxe new file mode 100644 index 0000000000..93ee3b9da2 Binary files /dev/null and b/bsp/bf533/vdsp/mine.dxe differ diff --git a/libcpu/blackfin/bf53x/context_vdsp.S b/libcpu/blackfin/bf53x/context_vdsp.S new file mode 100644 index 0000000000..b955d9ded7 --- /dev/null +++ b/libcpu/blackfin/bf53x/context_vdsp.S @@ -0,0 +1,165 @@ +/* + * File : context_vdsp.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian First version + */ + +.global _rt_hw_interrupt_disable; +.global _rt_hw_interrupt_enable; +.global _interrupt_thread_switch; + +.extern _rt_interrupt_from_thread; +.extern _rt_interrupt_to_thread; +.extern _rt_thread_switch_interrupt_flag; + +.section/DOUBLE64 program; + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return value in R0. + */ +_rt_hw_interrupt_disable: + CLI R0; + +_rt_hw_interrupt_disable.end: + NOP; + NOP; + NOP; + RTS; + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * R0->level + */ +_rt_hw_interrupt_enable: + STI R0; + +_rt_hw_interrupt_enable.end: + NOP; + NOP; + NOP; + RTS; + +_interrupt_thread_switch: + /* Save context, interrupts disabled by IPEND[4] bit */ + [ -- SP ] = R0; + [ -- SP ] = P1; + [ -- SP ] = RETS; + [ -- SP ] = R1; + [ -- SP ] = R2; + [ -- SP ] = P0; + [ -- SP ] = P2; + [ -- SP ] = ASTAT; + R1 = RETI; /* IPEND[4] is currently set, globally disabling interrupts */ + /* IPEND[4] will stay set when RETI is saved through R1 */ + + [ -- SP ] = R1; + [ -- SP ] = (R7:3, P5:3); + [ -- SP ] = FP; + [ -- SP ] = I0; + [ -- SP ] = I1; + [ -- SP ] = I2; + [ -- SP ] = I3; + [ -- SP ] = B0; + [ -- SP ] = B1; + [ -- SP ] = B2; + [ -- SP ] = B3; + [ -- SP ] = L0; + [ -- SP ] = L1; + [ -- SP ] = L2; + [ -- SP ] = L3; + [ -- SP ] = M0; + [ -- SP ] = M1; + [ -- SP ] = M2; + [ -- SP ] = M3; + R1.L = A0.x; + [ -- SP ] = R1; + R1 = A0.w; + [ -- SP ] = R1; + R1.L = A1.x; + [ -- SP ] = R1; + R1 = A1.w; + [ -- SP ] = R1; + [ -- SP ] = LC0; + R3 = 0; + LC0 = R3; + [ -- SP ] = LC1; + R3 = 0; + LC1 = R3; + [ -- SP ] = LT0; + [ -- SP ] = LT1; + [ -- SP ] = LB0; + [ -- SP ] = LB1; + + /* Context save done so save SP in the TCB */ + P1.h = _rt_interrupt_from_thread; + P1.l = _rt_interrupt_from_thread; + P2 = [ P1 ]; + [ P2 ] = SP; + + /* clear rt_thread_switch_interrupt_flag to 0 */ + P1.h = _rt_thread_switch_interrupt_flag; + P1.l = _rt_thread_switch_interrupt_flag; + R0 = 0; + [ P1 ] = R0; + + /* Get a pointer to the high ready task's TCB */ + P1.h = _rt_interrupt_to_thread; + P1.l = _rt_interrupt_to_thread; + P2 = [ P1 ]; + SP = [ P2 ]; + + /* Restoring CPU context and return to task */ + LB1 = [ SP ++ ]; + LB0 = [ SP ++ ]; + LT1 = [ SP ++ ]; + LT0 = [ SP ++ ]; + LC1 = [ SP ++ ]; + LC0 = [ SP ++ ]; + R0 = [ SP ++ ]; + A1 = R0; + R0 = [ SP ++ ]; + A1.x = R0.L; + R0 = [ SP ++ ]; + A0 = R0; + R0 = [ SP ++ ]; + A0.x = R0.L; + M3 = [ SP ++ ]; + M2 = [ SP ++ ]; + M1 = [ SP ++ ]; + M0 = [ SP ++ ]; + L3 = [ SP ++ ]; + L2 = [ SP ++ ]; + L1 = [ SP ++ ]; + L0 = [ SP ++ ]; + B3 = [ SP ++ ]; + B2 = [ SP ++ ]; + B1 = [ SP ++ ]; + B0 = [ SP ++ ]; + I3 = [ SP ++ ]; + I2 = [ SP ++ ]; + I1 = [ SP ++ ]; + I0 = [ SP ++ ]; + FP = [ SP ++ ]; + (R7:3, P5:3) = [ SP ++ ]; + RETI = [ SP ++ ]; /* IPEND[4] will stay set when RETI popped from stack */ + ASTAT = [ SP ++ ]; + P2 = [ SP ++ ]; + P0 = [ SP ++ ]; + R2 = [ SP ++ ]; + R1 = [ SP ++ ]; + RETS = [ SP ++ ]; + P1 = [ SP ++ ]; + R0 = [ SP ++ ]; + +_interrupt_thread_switch.end: + RTI; + diff --git a/libcpu/blackfin/bf53x/cpuport.c b/libcpu/blackfin/bf53x/cpuport.c new file mode 100644 index 0000000000..91cfaeb403 --- /dev/null +++ b/libcpu/blackfin/bf53x/cpuport.c @@ -0,0 +1,93 @@ +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-02-13 mojingxian first version + */ + +#include + +/* flag in interrupt handling */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * initializes stack of thread + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned char i; + unsigned long *stk; + + stk = (unsigned long *)stack_addr; /* Load stack pointer */ + + /* Simulate a function call to the task with an argument */ + stk -= 3; /* 3 words assigned for incoming args (R0, R1, R2) */ + + /* Now simulating vectoring to an ISR */ + *--stk = (unsigned long)parameter; /* R0 value - caller's incoming argument #1 */ + *--stk = (unsigned long)0; /* P1 value - value irrelevant */ + + *--stk = (unsigned long)texit; /* RETS value - NO task should return with RTS. */ + /* however OS_CPU_Invalid_Task_Return is a safety */ + /* catch-allfor tasks that return with an RTS */ + + *--stk = (unsigned long)parameter; /* R1 value - caller's incoming argument #2 */ + /* (not relevant in current test example) */ + *--stk = (unsigned long)parameter; /* R2 value - caller's incoming argument #3 */ + /* (not relevant in current test example) */ + *--stk = (unsigned long)0; /* P0 value - value irrelevant */ + *--stk = (unsigned long)0; /* P2 value - value irrelevant */ + *--stk = (unsigned long)0; /* ASTAT value - caller's ASTAT value - value */ + /* irrelevant */ + + *--stk = (unsigned long)tentry; /* RETI value- pushing the start address of the task */ + + for (i = 0; i < 35; i++) /* remaining reg values - R7:3, P5:3, */ + { /* 4 words of A1:0(.W,.X), LT0, LT1, */ + *--stk = (unsigned long)0; /* LC0, LC1, LB0, LB1,I3:0, M3:0, L3:0, B3:0, */ + } /* All values irrelevant */ + + return (rt_uint8_t *)stk; /* Return top-of-stack */ +} + +void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + + rt_interrupt_to_thread = to; + asm("raise 14;"); // Raise Interrupt 14 (trap) +} + +void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) +{ + if (rt_thread_switch_interrupt_flag != 1) + { + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = from; + } + + rt_interrupt_to_thread = to; + asm("raise 14;"); // Raise Interrupt 14 (trap) +} + +void rt_hw_context_switch_to(rt_uint32_t to) +{ + rt_thread_switch_interrupt_flag = 1; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = to; + asm("raise 14;"); // Raise Interrupt 14 (trap) +} diff --git a/libcpu/blackfin/bf53x/serial.c b/libcpu/blackfin/bf53x/serial.c new file mode 100644 index 0000000000..e5547fb887 --- /dev/null +++ b/libcpu/blackfin/bf53x/serial.c @@ -0,0 +1,284 @@ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://openlab.rt-thread.com/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2009-04-20 yi.qiu modified according bernard's stm32 version + * 2012-02-17 mojingxian modified for bf53x + */ + +#include + +#include "serial.h" + +/** + * @addtogroup BF53X + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + *ptr = uart->uart_device->rbr_thr & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = '\r'; + } + + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = (*ptr & 0xFF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +/*@}*/ diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h new file mode 100644 index 0000000000..8eef14546b --- /dev/null +++ b/libcpu/blackfin/bf53x/serial.h @@ -0,0 +1,56 @@ +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +typedef struct uartport +{ + volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register + volatile rt_uint16_t reserved0; + volatile rt_uint16_t reserved1; + volatile rt_uint16_t reserved2; + volatile rt_uint16_t reserved3; + volatile rt_uint16_t reserved4; + volatile rt_uint16_t reserved5; + volatile rt_uint16_t reserved6; + volatile rt_uint16_t reserved7; + volatile rt_uint16_t reserved8; + volatile rt_uint16_t lsr; //line status register +}uartport; + +struct serial_device +{ + uartport* uart_device; + + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); + +void rt_hw_serial_isr(rt_device_t device); + +#endif