mirror of https://github.com/l4ka/pistachio.git
- Adopted user-level tracebuffer logic
- Unified asm macros for amd64/ia32 (though not in the same file yet)
This commit is contained in:
Jan Stoess
parent
3cc9e4f474
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f9729fe126
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/*********************************************************************
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*
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* Copyright (C) 2002, Karlsruhe University
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*
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* File path: l4/amd64/tracebuffer.h
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* Description: Functions for accessing the tracebuffer
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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********************************************************************/
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#ifndef __L4__AMD64__TRACEBUFFER_H__
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#define __L4__AMD64__TRACEBUFFER_H__
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#define __L4_TRACEBUFFER_SIZE (4 * 1024 * 1024)
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/* Turn preprocessor symbol definition into string */
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#define MKSTR(sym) MKSTR2(sym)
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#define MKSTR2(sym) #sym
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#if defined(L4_64BIT)
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# define __PLUS32 + 32
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#else
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# define __PLUS32
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#endif
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/*
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* A tracebuffer record indicates the type of event, the time of the
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* event, the current thread, a number of event specific parameters,
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* and potentially the current performance counters.
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*/
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typedef struct
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{
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struct {
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L4_Word_t utype : 16;
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L4_Word_t __pad0 : 16 __PLUS32;
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L4_Word_t cpu : 16;
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L4_Word_t __pad1 : 16 __PLUS32;
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} X;
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L4_Word_t tsc;
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L4_Word_t thread;
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L4_Word_t pmc0;
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L4_Word_t pmc1;
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L4_Word_t str;
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L4_Word_t data[9];
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} L4_TraceRecord_t;
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/*
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* Access to performance monitoring counters
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*/
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/*
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* Access to stack pointer, timestamp, and performance monitoring counters
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*/
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#define __L4_TBUF_RDTSC " rdtsc \n" \
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" shl $32, %%rdx \n" \
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" movl %%eax, %%edx \n" \
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" mov %2, %%fs:2*%c9(%0) \n"
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#if defined(L4_PERFMON)
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#define __L4_TBUF_RDPMC_0 " rdpmc \n" \
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" shl $32, %%rdx \n" \
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" movl %%eax, %%edx \n" \
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" mov %2, %%fs:4*%c9(%0) \n"
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#define __L4_TBUF_RDPMC_1 " rdpmc \n" \
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" shl $32, %%rdx \n" \
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" movl %%eax, %%edx \n" \
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" mov %2, %%fs:5*%c9(%0) \n"
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# if !defined(L4_CONFIG_CPU_AMD64_P4)
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# define __L4_TBUF_PMC_SEL_0 " xorl %%ecx, %%ecx \n"
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# define __L4_TBUF_PMC_SEL_1 " inc %%ecx \n"
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# elif defined(L4_CONFIG_CPU_AMD64_P4)
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# define __L4_TBUF_PMC_SEL_0 " movl $12, %%ecx \n"
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# define __L4_TBUF_PMC_SEL_1 " add $2, %%ecx \n"
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# endif
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#else
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# define __L4_TBUF_PMC_SEL_0 " xor %3, %3 \n"
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# define __L4_TBUF_PMC_SEL_1
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# define __L4_TBUF_RDPMC_0 " mov %3, %%fs:4*%c9(%0) \n"
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# define __L4_TBUF_RDPMC_1 " mov %3, %%fs:5$c9(%9)\n"
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#endif
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/*
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* Make sure cmpxchg is atomic
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*/
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#if defined(L4_CONFIG_SMP)
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# define __L4_TBUF_LOCK "lock;"
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#else
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# define __L4_TBUF_LOCK
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#endif
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/*
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* Tracebuffer access macros
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*/
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#define __L4_TBUF_INCREASE_COUNTER(ctr) \
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do { \
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asm volatile ( \
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__L4_TBUF_LOCK \
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" inc %%fs:8*%c1(%0) \n" \
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: \
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: \
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"r" ((ctr & 0x7) * 4), \
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"i" (sizeof(L4_Word_t))); \
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} while (0)
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#define __L4_TBUF_GET_NEXT_RECORD(tid, event) \
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({ \
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L4_Word_t _dummy, _addr; \
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asm volatile ( \
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/* Check wheter to filter the event */ \
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" mov %%fs:2*%c9, %3 \n" \
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" and %1, %3 \n" \
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" xor %%fs:3*%c9, %3 \n" \
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" jnz 2f \n" \
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\
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/* Get record offset into EDI */ \
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"1: mov %%fs:1*%c9, %3 \n" \
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" mov %8, %0 \n" \
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" mov %0, %2 \n" \
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" add %3, %0 \n" \
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" and $"MKSTR(__L4_TRACEBUFFER_SIZE-1)", %0 \n" \
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" cmovz %2, %0 \n" \
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__L4_TBUF_LOCK \
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" cmpxchg %0, %%fs:1*%c9 \n" \
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" jnz 1b \n" \
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\
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/* Store type, cpu, thread, counters */ \
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" movl %%ecx, %%fs:(%0) \n" \
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" mov %%gs:0, %1 \n" \
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" mov "MKSTR(4 *__L4_TCR_PROCESSOR_NO)"(%1), %2\n" \
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" movl %%edx, %%fs:4(%0) \n" \
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" mov "MKSTR(4 *__L4_TCR_MY_GLOBAL_ID)"(%1), %2\n" \
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" movl %%edx, %%fs:3*%c9(%0) \n" \
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__L4_TBUF_RDTSC \
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__L4_TBUF_PMC_SEL_0 \
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__L4_TBUF_RDPMC_0 \
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__L4_TBUF_PMC_SEL_1 \
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__L4_TBUF_RDPMC_1 \
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"2: \n" \
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: \
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"=D" (_addr), /* 0 */ \
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"=c" (_dummy), /* 1 */ \
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"=d" (_dummy), /* 2 */ \
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"=a" (_dummy) /* 3 */ \
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: \
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"0" (0), /* 4 */ \
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"1" (event & 0xffff), /* 5 */ \
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"2" (0), /* 6 */ \
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"3" (0), /* 7 */ \
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"i" (sizeof (L4_TraceRecord_t)), /* 8 */ \
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"i" (sizeof(L4_Word_t)) /* 9 */ \
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); \
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_addr; \
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})
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/**
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* Record (format) string into event buffer.
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*
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* @param addr offset of event record
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* @param offset string to be recorded
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*/
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#define __L4_TBUF_STORE_STR(addr, str) \
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do { \
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asm volatile ( \
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"mov %0, %%fs:6*%c2(%1)\n" \
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: \
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: \
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"r" (str), \
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"D" (addr), \
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"i" (sizeof(L4_Word_t))); \
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} while (0)
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/**
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* Record arguments into event buffer at indicated location.
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*
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* @param addr offset of event record
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* @param offset offset within event record
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* @param item value to be recorded
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*/
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#define __L4_TBUF_STORE_DATA(addr, offset, item) \
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do { \
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L4_Word_t _dummy; \
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asm volatile ( \
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"mov %2, %%fs:(%1)\n" \
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: \
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"=D" (_dummy) \
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: \
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"0" (addr + (7 + offset) * sizeof(L4_Word_t)), \
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"r" (item)); \
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} while (0)
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#endif /* !__L4__AMD64__TRACEBUFFER_H__ */
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