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Allow compilation in pure c.

This commit is contained in:
Jan Stoess 2010-07-12 19:47:30 +02:00
parent 452b9b8f16
commit f85d2ee02f
5 changed files with 72 additions and 73 deletions
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16
user/include/l4/ia32/arch.h
View File

@ -254,7 +254,7 @@ L4_INLINE void L4_GPRegsCtrlXferItemSet(L4_GPRegsCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
L4_INLINE void L4_MsgAppendGPRegsCtrlXferItem (L4_Msg_t * msg, L4_GPRegsCtrlXferItem_t *c)
@ -319,7 +319,7 @@ L4_INLINE void L4_CRegsCtrlXferItemSet(L4_CRegsCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
@ -382,7 +382,7 @@ L4_INLINE void L4_DRegsCtrlXferItemSet(L4_DRegsCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
@ -439,7 +439,7 @@ L4_INLINE void L4_SegCtrlXferItemSet(L4_SegCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
L4_INLINE void L4_MsgAppendSegCtrlXferItem (L4_Msg_t * msg, L4_SegCtrlXferItem_t *c)
@ -493,7 +493,7 @@ L4_INLINE void L4_DTRCtrlXferItemSet(L4_DTRCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
L4_INLINE void L4_MsgAppendDTRCtrlXferItem (L4_Msg_t * msg, L4_DTRCtrlXferItem_t *c)
@ -555,7 +555,7 @@ L4_INLINE void L4_NonRegExcCtrlXferItemInit(L4_NonRegExcCtrlXferItem_t *c)
L4_INLINE void L4_NonRegExcCtrlXferItemSet(L4_NonRegExcCtrlXferItem_t *c, L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
L4_INLINE void L4_MsgAppendNonRegExcCtrlXferItem(L4_Msg_t *msg, L4_NonRegExcCtrlXferItem_t *c)
@ -610,7 +610,7 @@ L4_INLINE void L4_ExecCtrlXferItemSet(L4_ExecCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}
@ -678,7 +678,7 @@ L4_INLINE void L4_OtherRegsCtrlXferItemSet(L4_OtherRegsCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1<<reg);
c->item.X.mask |= (1<<reg);
}

29
user/include/l4/message.h
View File

@ -458,21 +458,20 @@ typedef union {
L4_Word_t id:8;
L4_Word_t __type:3;
L4_Word_t C:1;
};
#else
struct {
L4_Word_t C:1;
L4_Word_t __type:3;
L4_Word_t id:8;
L4_Word_t mask:20 __PLUS32;
};
#endif
} X;
} L4_CtrlXferItem_t;
L4_INLINE L4_Bool_t L4_IsCtrlXferItem (L4_CtrlXferItem_t * s)
{
return (s->__type == 6);
return (s->X.__type == 6);
}
#if defined(__cplusplus)
@ -486,18 +485,18 @@ L4_INLINE L4_Bool_t L4_CtrlXferItem (L4_CtrlXferItem_t * s)
L4_INLINE void L4_CtrlXferItemInit (L4_CtrlXferItem_t *c, L4_Word_t id)
{
c->raw[0] = 0;
c->__type = 0x06;
c->id = id;
c->mask = 0;
c->X.__type = 0x06;
c->X.id = id;
c->X.mask = 0;
}
L4_INLINE void L4_FaultConfCtrlXferItemInit (L4_CtrlXferItem_t *c, L4_Word_t fault_id, L4_Word_t fault_mask)
{
c->raw[0] = 0;
c->__type = 0x06;
c->id = fault_id;
c->mask = fault_mask;
c->X.__type = 0x06;
c->X.id = fault_id;
c->X.mask = fault_mask;
}
@ -720,7 +719,7 @@ L4_INLINE void L4_MsgAppendStringItem (L4_Msg_t * msg,
L4_INLINE void L4_MsgAppendCtrlXferItem (L4_Msg_t * msg, L4_CtrlXferItem_t *c)
{
L4_Word_t reg=0, num=0, mask = c->mask;
L4_Word_t reg=0, num=0, mask = c->X.mask;
/*
* Add regs according to mask
@ -748,7 +747,7 @@ L4_INLINE void L4_AppendFaultConfCtrlXferItems(L4_Msg_t *msg, L4_Word64_t fault_
fault_id_mask_low>>=__L4_Lsb(fault_id_mask_low)+1,fault_id+=__L4_Lsb(fault_id_mask_low)+1)
{
L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
item.C = 1;
item.X.C = 1;
L4_MsgAppendWord(msg, item.raw[0]);
}
@ -757,11 +756,11 @@ L4_INLINE void L4_AppendFaultConfCtrlXferItems(L4_Msg_t *msg, L4_Word64_t fault_
fault_id_mask_high>>=__L4_Lsb(fault_id_mask_high)+1,fault_id+=__L4_Lsb(fault_id_mask_high)+1)
{
L4_FaultConfCtrlXferItemInit(&item, fault_id, fault_mask);
item.C = 1;
item.X.C = 1;
L4_MsgAppendWord(msg, item.raw[0]);
}
item.C = C;
item.X.C = C;
msg->msg[msg->tag.X.u + msg->tag.X.t] = item.raw[0];
}
@ -801,7 +800,7 @@ L4_INLINE void L4_MsgPutStringItem (L4_Msg_t * msg, L4_Word_t t,
L4_INLINE void L4_MsgPutCtrlXferItem (L4_Msg_t * msg, L4_Word_t t, L4_CtrlXferItem_t *c)
{
L4_Word_t reg=0, num=0, mask = c->mask;
L4_Word_t reg=0, num=0, mask = c->X.mask;
/*
* Put regs according to mask
@ -856,7 +855,7 @@ L4_INLINE L4_Word_t L4_MsgGetCtrlXferItem (L4_Msg_t * msg, L4_Word_t mr, L4_Ctrl
/* Store item */
c->raw[0] = msg->msg[mr];
mask = c->mask;
mask = c->X.mask;
/*
* Store regs according to mask
* */

18
user/include/l4/powerpc/arch.h
View File

@ -189,7 +189,7 @@ L4_INLINE void L4_GPRegsCtrlXferItemSet(L4_GPRegsCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendGPRegsCtrlXferItem (L4_Msg_t * msg, L4_GPRegsCtrlXferItem_t *c)
@ -246,7 +246,7 @@ L4_INLINE void L4_GPRegsXCtrlXferItemSet(L4_GPRegsXCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendGPRegsXCtrlXferItem (L4_Msg_t * msg, L4_GPRegsXCtrlXferItem_t *c)
@ -333,7 +333,7 @@ L4_INLINE void L4_TLBCtrlXferItemSet(L4_TLBCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs[reg / 4].reg[reg % 4] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendTLBCtrlXferItem (L4_Msg_t * msg, L4_TLBCtrlXferItem_t *c)
@ -400,7 +400,7 @@ L4_INLINE void L4_ExceptCtrlXferItemSet(L4_ExceptCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendExceptCtrlXferItem (L4_Msg_t * msg, L4_ExceptCtrlXferItem_t *c)
@ -451,7 +451,7 @@ L4_INLINE void L4_IvorCtrlXferItemSet(L4_IvorCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendIvorCtrlXferItem (L4_Msg_t * msg, L4_IvorCtrlXferItem_t *c)
@ -508,7 +508,7 @@ L4_INLINE void L4_TimerCtrlXferItemSet(L4_TimerCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendTimerCtrlXferItem (L4_Msg_t * msg, L4_TimerCtrlXferItem_t *c)
@ -560,7 +560,7 @@ L4_INLINE void L4_ConfigCtrlXferItemSet(L4_ConfigCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendConfigCtrlXferItem (L4_Msg_t * msg, L4_ConfigCtrlXferItem_t *c)
@ -621,7 +621,7 @@ L4_INLINE void L4_ConfigCtrlXferItemSet(L4_DebugCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendDebugCtrlXferItem (L4_Msg_t * msg, L4_DebugCtrlXferItem_t *c)
@ -678,7 +678,7 @@ L4_INLINE void L4_CacheCtrlXferItemSet(L4_CacheCtrlXferItem_t *c,
L4_Word_t reg, L4_Word_t val)
{
c->regs.reg[reg] = val;
c->item.mask |= (1ul << reg);
c->item.X.mask |= (1ul << reg);
}
L4_INLINE void L4_MsgAppendCacheCtrlXferItem (L4_Msg_t * msg, L4_CacheCtrlXferItem_t *c)

2
user/include/l4/powerpc/specials.h
View File

@ -39,7 +39,7 @@ L4_INLINE int __L4_Msb( L4_Word_t w )
{
int zeros;
asm volatile ("cntlzw %0, %1" : "=r" (zeros) : "r" (w) );
__asm__ __volatile__ ("cntlzw %0, %1" : "=r" (zeros) : "r" (w) );
return 31-zeros;
}

80
user/include/l4/powerpc/syscalls.h
View File

@ -3,7 +3,7 @@
* Copyright (C) 1999-2010, Karlsruhe University
* Copyright (C) 2008-2009, Volkmar Uhlig, IBM Corporation
*
* File path: include/l4/powerpc/syscalls.h
* File path: l4/powerpc/syscalls.h
* Description:
*
* Redistribution and use in source and binary forms, with or without
@ -106,7 +106,7 @@ L4_INLINE L4_ThreadId_t L4_ExchangeRegisters(
L4_ThreadId_t *old_pager
)
{
register L4_Word_t r3 asm("r3") = dest.raw;
register L4_Word_t r3 __asm__("r3") = dest.raw;
struct {
L4_Word_t control;
@ -168,11 +168,11 @@ L4_INLINE L4_Word_t L4_ThreadControl(
L4_ThreadId_t Pager,
void * UtcbLocation)
{
register L4_Word_t r3 asm("r3") = dest.raw;
register L4_Word_t r4 asm("r4") = SpaceSpecifier.raw;
register L4_Word_t r5 asm("r5") = Scheduler.raw;
register L4_Word_t r6 asm("r6") = Pager.raw;
register void * r7 asm("r7") = UtcbLocation;
register L4_Word_t r3 __asm__("r3") = dest.raw;
register L4_Word_t r4 __asm__("r4") = SpaceSpecifier.raw;
register L4_Word_t r5 __asm__("r5") = Scheduler.raw;
register L4_Word_t r6 __asm__("r6") = Pager.raw;
register void * r7 __asm__("r7") = UtcbLocation;
__asm__ __volatile__ (
"mtctr %5 ;"
@ -194,8 +194,8 @@ extern __L4_SystemClock_t __L4_SystemClock;
L4_INLINE L4_Clock_t L4_SystemClock( void )
{
register L4_Word_t r3 asm("r3");
register L4_Word_t r4 asm("r4");
register L4_Word_t r3 __asm__("r3");
register L4_Word_t r4 __asm__("r4");
__asm__ __volatile__ (
"mtctr %2 ;"
@ -217,7 +217,7 @@ extern __L4_ThreadSwitch_t __L4_ThreadSwitch;
L4_INLINE void L4_ThreadSwitch( L4_ThreadId_t dest )
{
register L4_Word_t r3 asm("r3") = dest.raw;
register L4_Word_t r3 __asm__("r3") = dest.raw;
__asm__ __volatile__ (
"mtctr %1 ;"
@ -244,11 +244,11 @@ L4_INLINE L4_Word_t L4_Schedule(
L4_Word_t * old_TimeControl
)
{
register L4_Word_t r3 asm("r3") = dest.raw;
register L4_Word_t r4 asm("r4") = TimeControl;
register L4_Word_t r5 asm("r5") = ProcessorControl;
register L4_Word_t r6 asm("r6") = prio;
register L4_Word_t r7 asm("r7") = PreemptionControl;
register L4_Word_t r3 __asm__("r3") = dest.raw;
register L4_Word_t r4 __asm__("r4") = TimeControl;
register L4_Word_t r5 __asm__("r5") = ProcessorControl;
register L4_Word_t r6 __asm__("r6") = prio;
register L4_Word_t r7 __asm__("r7") = PreemptionControl;
__asm__ __volatile__ (
"mtctr %2 ;"
@ -276,11 +276,11 @@ L4_INLINE L4_MsgTag_t L4_Ipc(
L4_ThreadId_t *from
)
{
register L4_Word_t r15 asm("r15") = to.raw;
register L4_Word_t r16 asm("r16") = FromSpecifier.raw;
register L4_Word_t r17 asm("r17") = Timeouts;
register L4_Word_t r15 __asm__("r15") = to.raw;
register L4_Word_t r16 __asm__("r16") = FromSpecifier.raw;
register L4_Word_t r17 __asm__("r17") = Timeouts;
asm volatile (
__asm__ __volatile__ (
"lwz %%r0, 36 (%%r2) ;"
"lwz %%r3, 4 (%%r2) ;"
"lwz %%r4, 8 (%%r2) ;"
@ -335,11 +335,11 @@ L4_INLINE L4_MsgTag_t L4_Lipc(
L4_ThreadId_t *from
)
{
register L4_Word_t r15 asm("r15") = to.raw;
register L4_Word_t r16 asm("r16") = FromSpecifier.raw;
register L4_Word_t r17 asm("r17") = Timeouts;
register L4_Word_t r15 __asm__("r15") = to.raw;
register L4_Word_t r16 __asm__("r16") = FromSpecifier.raw;
register L4_Word_t r17 __asm__("r17") = Timeouts;
asm volatile (
__asm__ __volatile__ (
"lwz %%r0, 36 (%%r2) ;"
"lwz %%r3, 4 (%%r2) ;"
"lwz %%r4, 8 (%%r2) ;"
@ -389,7 +389,7 @@ extern __L4_Unmap_t __L4_Unmap;
L4_INLINE void L4_Unmap( L4_Word_t control )
{
asm volatile (
__asm__ __volatile__ (
"mr %%r15, %1 ;"
"mtctr %0 ;"
@ -439,11 +439,11 @@ L4_INLINE L4_Word_t L4_SpaceControl(
L4_Word_t *old_control
)
{
register L4_Word_t r3 asm("r3") = SpaceSpecifier.raw;
register L4_Word_t r4 asm("r4") = control;
register L4_Word_t r5 asm("r5") = KernelInterfacePageArea.raw;
register L4_Word_t r6 asm("r6") = UtcbArea.raw;
register L4_Word_t r7 asm("r7") = redirector.raw;
register L4_Word_t r3 __asm__("r3") = SpaceSpecifier.raw;
register L4_Word_t r4 __asm__("r4") = control;
register L4_Word_t r5 __asm__("r5") = KernelInterfacePageArea.raw;
register L4_Word_t r6 __asm__("r6") = UtcbArea.raw;
register L4_Word_t r7 __asm__("r7") = redirector.raw;
__asm__ __volatile__ (
"mtctr %5 ;"
@ -472,10 +472,10 @@ L4_INLINE L4_Word_t L4_ProcessorControl(
L4_Word_t voltage
)
{
register L4_Word_t r3 asm("r3") = ProcessorNo;
register L4_Word_t r4 asm("r4") = InternalFrequency;
register L4_Word_t r5 asm("r5") = ExternalFrequency;
register L4_Word_t r6 asm("r6") = voltage;
register L4_Word_t r3 __asm__("r3") = ProcessorNo;
register L4_Word_t r4 __asm__("r4") = InternalFrequency;
register L4_Word_t r5 __asm__("r5") = ExternalFrequency;
register L4_Word_t r6 __asm__("r6") = voltage;
__asm__ __volatile__ (
"mtctr %4 ;"
@ -500,14 +500,14 @@ L4_INLINE L4_Word_t L4_MemoryControl(
const L4_Word_t attributes[4]
)
{
register L4_Word_t r15 asm("r15") = control;
register L4_Word_t r16 asm("r16") = attributes[0];
register L4_Word_t r17 asm("r17") = attributes[1];
register L4_Word_t r18 asm("r18") = attributes[2];
register L4_Word_t r19 asm("r19") = attributes[3];
register L4_Word_t r3 asm("r3");
register L4_Word_t r15 __asm__("r15") = control;
register L4_Word_t r16 __asm__("r16") = attributes[0];
register L4_Word_t r17 __asm__("r17") = attributes[1];
register L4_Word_t r18 __asm__("r18") = attributes[2];
register L4_Word_t r19 __asm__("r19") = attributes[3];
register L4_Word_t r3 __asm__("r3");
asm volatile (
__asm__ __volatile__ (
"lwz %%r0, 36 (%%r2) ;"
"lwz %%r3, 4 (%%r2) ;"
"lwz %%r4, 8 (%%r2) ;"