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Removed unmaintained architectures and platforms. 

Revert them back in later if needed.
This commit is contained in:
Espen Skoglund 2007-07-06 16:36:48 +02:00
parent 705fa0247a
commit a0a8042f2a
701 changed files with 26 additions and 103728 deletions
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/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* Logically, this code should be part of libopcode but since some of
the operand insertion/extraction functions help bfd to implement
relocations, this code is included as part of cpu-ia64.c. This
avoids circular dependencies between libopcode and libbfd and also
obviates the need for applications to link in libopcode when all
they really want is libbfd.
--davidm Mon Apr 13 22:14:02 1998 */
/* changes by ud3 marked with //ud3 */
#include "ia64-opc.h" //ud3
#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
static const char*
ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
return "internal error---this shouldn't happen";
}
static const char*
ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
return "internal error---this shouldn't happen";
}
static const char*
ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
return 0;
}
static const char*
ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
return 0;
}
static const char*
ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value >= 1u << self->field[0].bits)
return "register number out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((1u << self->field[0].bits) - 1));
return 0;
}
static const char*
ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn new = 0;
int i;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
value >>= self->field[i].bits;
}
if (value)
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_U_64_BIT value = 0;
int i, bits = 0, total = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
value |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
*valuep = value;
return 0;
}
static const char*
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value & 0x7)
return "value not an integer multiple of 8";
return ins_immu (self, value >> 3, code);
}
static const char*
ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
result = ext_immu (self, code, valuep);
if (result)
return result;
*valuep = *valuep << 3;
return 0;
}
static const char*
ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code, int scale)
{
BFD_HOST_64_BIT svalue = value, sign_bit = 0;
ia64_insn new = 0;
int i;
svalue >>= scale;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
svalue >>= self->field[i].bits;
}
if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
ia64_insn *valuep, int scale)
{
int i, bits = 0, total = 0, shift;
BFD_HOST_64_BIT val = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
val |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
/* sign extend: */
shift = 8*sizeof (val) - total;
val = (val << shift) >> shift;
*valuep = (val << scale);
return 0;
}
static const char*
ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 0);
}
static const char*
ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *res = ext_imms_scaled (self, code, valuep, 0);
++*valuep;
return res;
}
static const char*
ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 1);
}
static const char*
ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 1);
}
static const char*
ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 4);
}
static const char*
ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 4);
}
static const char*
ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 16);
}
static const char*
ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 16);
}
static const char*
ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
return ins_immu (self, value ^ mask, code);
}
static const char*
ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
ia64_insn mask;
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
result = ext_immu (self, code, valuep);
if (!result)
{
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
*valuep ^= mask;
}
return result;
}
static const char*
ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
return "count out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
return 0;
}
static const char*
ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value > 2)
return "count must be in range 1..3";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
return 0;
}
static const char*
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
switch (value)
{
case 0: value = 0; break;
case 7: value = 1; break;
case 15: value = 2; break;
case 16: value = 3; break;
default: return "count must be 0, 7, 15, or 16";
}
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
ia64_insn value;
value = (code >> self->field[0].shift) & 0x3;
switch (value)
{
case 0: value = 0; break;
case 1: value = 7; break;
case 2: value = 15; break;
case 3: value = 16; break;
}
*valuep = value;
return 0;
}
static const char*
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
BFD_HOST_64_BIT val = value;
BFD_HOST_U_64_BIT sign = 0;
if (val < 0)
{
sign = 0x4;
value = -value;
}
switch (value)
{
case 1: value = 3; break;
case 4: value = 2; break;
case 8: value = 1; break;
case 16: value = 0; break;
default: return "count must be +/- 1, 4, 8, or 16";
}
*code |= (sign | value) << self->field[0].shift;
return 0;
}
static const char*
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_64_BIT val;
int negate;
val = (code >> self->field[0].shift) & 0x7;
negate = val & 0x4;
switch (val & 0x3)
{
case 0: val = 16; break;
case 1: val = 8; break;
case 2: val = 4; break;
case 3: val = 1; break;
}
if (negate)
val = -val;
*valuep = val;
return 0;
}
#define CST IA64_OPND_CLASS_CST
#define REG IA64_OPND_CLASS_REG
#define IND IA64_OPND_CLASS_IND
#define ABS IA64_OPND_CLASS_ABS
#define REL IA64_OPND_CLASS_REL
#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
{
/* constants: */
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
/* register operands: */
{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
"an application register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
"a branch register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
"a branch register"},
{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
"a control register"},
{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
"a general register r0-r3" },
/* indirect operands: */
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
"a cpuid register" },
{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
"a dbr register" },
{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
"a dtr register" },
{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
"an itr register" },
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
"an ibr register" },
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
"an indirect memory address" },
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
"an msr register" },
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
"a pkr register" },
{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
"a pmc register" },
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
"a pmd register" },
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
"an rr register" },
/* immediate operands: */
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
"a 2-bit count (1-4)" },
{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
"a 2-bit count (1-3)" },
{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
"a count (0, 7, 15, or 16)" },
{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
"a 6-bit count (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
"a 1-bit integer (-1, 0)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
"a 2-bit unsigned (0-3)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
"a frame size (register count)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
"a local register count" },
{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
"a rotating register count (integer multiple of 8)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-128-127)" },
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-127-128)" },
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
"a 9-bit unsigned (0-511)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
"a 14-bit integer (-8192-8191)" },
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
"a 17-bit integer (-65536-65535)" },
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
"a 21-bit unsigned" },
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
"a 22-bit signed integer" },
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
"a 24-bit unsigned" },
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
"a 62-bit unsigned" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
"a 64-bit unsigned" },
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
"an increment (+/- 1, 4, 8, or 16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
"a 4-bit length (1-16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
"a 6-bit length (1-64)" },
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
"an 8-bit mix type" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
"a 6-bit bit pos (0-63)" },
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
"a branch target" },
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
"a branch target" },
};

7436
contrib/disas/ia64-asmtab.c
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File diff suppressed because it is too large Load Diff

148
contrib/disas/ia64-asmtab.h
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@ -1,148 +0,0 @@
/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
Copyright 1999, 2000 Free Software Foundation, Inc.
Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef IA64_ASMTAB_H
#define IA64_ASMTAB_H
#include "opcode/ia64.h"
/* The primary opcode table is made up of the following: */
struct ia64_main_table
{
/* The entry in the string table that corresponds to the name of this
opcode. */
unsigned short name_index;
/* The type of opcode; corresponds to the TYPE field in
struct ia64_opcode. */
unsigned char opcode_type;
/* The number of outputs for this opcode. */
unsigned char num_outputs;
/* The base insn value for this opcode. It may be modified by completers. */
ia64_insn opcode;
/* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
ia64_insn mask;
/* The operands of this instruction. Corresponds to the OPERANDS field
in struct ia64_opcode. */
unsigned char operands[5];
/* The flags for this instruction. Corresponds to the FLAGS field in
struct ia64_opcode. */
short flags;
/* The tree of completers for this instruction; this is an offset into
completer_table. */
short completers;
};
/* Each instruction has a set of possible "completers", or additional
suffixes that can alter the instruction's behavior, and which has
potentially different dependencies.
The completer entries modify certain bits in the instruction opcode.
Which bits are to be modified are marked by the BITS, MASK and
OFFSET fields. The completer entry may also note dependencies for the
opcode.
These completers are arranged in a DAG; the pointers are indexes
into the completer_table array. The completer DAG is searched by
find_completer () and ia64_find_matching_opcode ().
Note that each completer needs to be applied in turn, so that if we
have the instruction
cmp.lt.unc
the completer entries for both "lt" and "unc" would need to be applied
to the opcode's value.
Some instructions do not require any completers; these contain an
empty completer entry. Instructions that require a completer do
not contain an empty entry.
Terminal completers (those completers that validly complete an
instruction) are marked by having the TERMINAL_COMPLETER flag set.
Only dependencies listed in the terminal completer for an opcode are
considered to apply to that opcode instance. */
struct ia64_completer_table
{
/* The bit value that this completer sets. */
unsigned int bits;
/* And its mask. 1s are bits that are to be modified in the
instruction. */
unsigned int mask;
/* The entry in the string table that corresponds to the name of this
completer. */
unsigned short name_index;
/* An alternative completer, or -1 if this is the end of the chain. */
short alternative;
/* A pointer to the DAG of completers that can potentially follow
this one, or -1. */
short subentries;
/* The bit offset in the instruction where BITS and MASK should be
applied. */
unsigned char offset : 7;
unsigned char terminal_completer : 1;
/* Index into the dependency list table */
short dependencies;
};
/* This contains sufficient information for the disassembler to resolve
the complete name of the original instruction. */
struct ia64_dis_names
{
/* COMPLETER_INDEX represents the tree of completers that make up
the instruction. The LSB represents the top of the tree for the
specified instruction.
A 0 bit indicates to go to the next alternate completer via the
alternative field; a 1 bit indicates that the current completer
is part of the instruction, and to go down the subentries index.
We know we've reached the final completer when we run out of 1
bits.
There is always at least one 1 bit. */
unsigned int completer_index : 20;
/* The index in the main_table[] array for the instruction. */
unsigned short insn_index : 11;
/* If set, the next entry in this table is an alternate possibility
for this instruction encoding. Which one to use is determined by
the instruction type and other factors (see opcode_verify ()). */
unsigned int next_flag : 1;
/* The disassembly priority of this entry among instructions. */
unsigned short priority;
};
#endif

274
contrib/disas/ia64-dis.c
View File

@ -1,274 +0,0 @@
/* ia64-dis.c -- Disassemble ia64 instructions
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/* search for comments by ud3 */
//ud3 #include <assert.h>
//ud3 #include <string.h>
//ud3 #include "dis-asm.h"
#include "opcode/ia64.h"
#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
/* Disassemble ia64 instruction. */
/* Return the instruction type for OPCODE found in unit UNIT. */
static enum ia64_insn_type
unit_to_type (ia64_insn opcode, enum ia64_unit unit)
{
enum ia64_insn_type type;
int op;
op = IA64_OP (opcode);
if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
{
type = IA64_TYPE_A;
}
else
{
switch (unit)
{
case IA64_UNIT_I:
type = IA64_TYPE_I; break;
case IA64_UNIT_M:
type = IA64_TYPE_M; break;
case IA64_UNIT_B:
type = IA64_TYPE_B; break;
case IA64_UNIT_F:
type = IA64_TYPE_F; break;
case IA64_UNIT_L:
case IA64_UNIT_X:
type = IA64_TYPE_X; break;
default:
type = -1;
}
}
return type;
}
int
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
{
ia64_insn t0, t1, slot[3], template, s_bit, insn;
int slotnum, j, status, need_comma, retval, slot_multiplier;
const struct ia64_operand *odesc;
const struct ia64_opcode *idesc;
const char *err, *str, *tname;
BFD_HOST_U_64_BIT value;
bfd_byte bundle[16];
enum ia64_unit unit;
char regname[16];
if (info->bytes_per_line == 0)
info->bytes_per_line = 6;
info->display_endian = info->endian;
slot_multiplier = info->bytes_per_line;
retval = slot_multiplier;
slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
if (slotnum > 2)
return -1;
memaddr -= (memaddr & 0xf);
status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* bundles are always in little-endian byte order */
t0 = bfd_getl64 (bundle);
t1 = bfd_getl64 (bundle + 8);
s_bit = t0 & 1;
template = (t0 >> 1) & 0xf;
slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
tname = ia64_templ_desc[template].name;
if (slotnum == 0)
(*info->fprintf_func) (info->stream, "[%s] ", tname);
else
(*info->fprintf_func) (info->stream, " ", tname);
unit = ia64_templ_desc[template].exec_unit[slotnum];
if (template == 2 && slotnum == 1)
{
/* skip L slot in MLI template: */
slotnum = 2;
retval += slot_multiplier;
}
insn = slot[slotnum];
if (unit == IA64_UNIT_NIL)
goto decoding_failed;
idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
if (idesc == NULL)
goto decoding_failed;
/* print predicate, if any: */
if ((idesc->flags & IA64_OPCODE_NO_PRED)
|| (insn & 0x3f) == 0)
(*info->fprintf_func) (info->stream, " ");
else
(*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
/* now the actual instruction: */
(*info->fprintf_func) (info->stream, "%s", idesc->name);
if (idesc->operands[0])
(*info->fprintf_func) (info->stream, " ");
need_comma = 0;
for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
{
odesc = elf64_ia64_operands + idesc->operands[j];
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
{
/* special case of 64 bit immediate load: */
value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
| (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
| (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
}
else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
{
/* 62-bit immediate for nop.x/break.x */
value = ((slot[1] & 0x1ffffffffffLL) << 21)
| (((insn >> 36) & 0x1) << 20)
| ((insn >> 6) & 0xfffff);
}
else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
{
/* 60-bit immedate for long branches. */
value = (((insn >> 13) & 0xfffff)
| (((insn >> 36) & 1) << 59)
| (slot[1] << 20)) << 4;
}
else
{
err = (*odesc->extract) (odesc, insn, &value);
if (err)
{
(*info->fprintf_func) (info->stream, "%s", err);
goto done;
}
}
switch (odesc->class)
{
case IA64_OPND_CLASS_CST:
(*info->fprintf_func) (info->stream, "%s", odesc->str);
break;
case IA64_OPND_CLASS_REG:
if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
{
switch (value)
{
case 0: case 1: case 2: case 3:
case 4: case 5: case 6: case 7:
sprintf (regname, "ar.k%u", (unsigned int) value);
break;
case 16: strcpy (regname, "ar.rsc"); break;
case 17: strcpy (regname, "ar.bsp"); break;
case 18: strcpy (regname, "ar.bspstore"); break;
case 19: strcpy (regname, "ar.rnat"); break;
case 32: strcpy (regname, "ar.ccv"); break;
case 36: strcpy (regname, "ar.unat"); break;
case 40: strcpy (regname, "ar.fpsr"); break;
case 44: strcpy (regname, "ar.itc"); break;
case 64: strcpy (regname, "ar.pfs"); break;
case 65: strcpy (regname, "ar.lc"); break;
case 66: strcpy (regname, "ar.ec"); break;
default:
sprintf (regname, "ar%u", (unsigned int) value);
break;
}
(*info->fprintf_func) (info->stream, "%s", regname);
}
else
(*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_IND:
(*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_ABS:
str = 0;
if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
switch (value)
{
case 0x0: str = "@brcst"; break;
case 0x8: str = "@mix"; break;
case 0x9: str = "@shuf"; break;
case 0xa: str = "@alt"; break;
case 0xb: str = "@rev"; break;
}
if (str)
(*info->fprintf_func) (info->stream, "%s", str);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
(*info->fprintf_func) (info->stream, "%lld", value);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
(*info->fprintf_func) (info->stream, "%llu", value);
else
(*info->fprintf_func) (info->stream, "0x%llx", value);
break;
case IA64_OPND_CLASS_REL:
(*info->print_address_func) (memaddr + value, info);
break;
}
need_comma = 1;
if (j + 1 == idesc->num_outputs)
{
(*info->fprintf_func) (info->stream, "=");
need_comma = 0;
}
}
if (slotnum + 1 == ia64_templ_desc[template].group_boundary
|| ((slotnum == 2) && s_bit))
(*info->fprintf_func) (info->stream, ";;");
done:
//ud3 ia64_free_opcode ((struct ia64_opcode *)idesc);
failed:
if (slotnum == 2)
retval += 16 - 3*slot_multiplier;
return retval;
decoding_failed:
(*info->fprintf_func) (info->stream, " data8 %#011llx", insn);
goto failed;
}

773
contrib/disas/ia64-opc.c
View File

@ -1,773 +0,0 @@
/* ia64-opc.c -- Functions to access the compacted opcode table
Copyright 1999, 2000 Free Software Foundation, Inc.
Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/* changes by ud3 marked with //ud3 */
//ud3 #include "ansidecl.h"
//ud3 #include "libiberty.h"
//ud3 #include "sysdep.h"
#include "ia64-asmtab.h"
#include "ia64-asmtab.c"
static void get_opc_prefix PARAMS ((const char **, char *));
static short int find_string_ent PARAMS ((const char *));
static short int find_main_ent PARAMS ((short int));
static short int find_completer PARAMS ((short int, short int, const char *));
static ia64_insn apply_completer PARAMS ((ia64_insn, int));
static int extract_op_bits PARAMS ((int, int, int));
static int extract_op PARAMS ((int, int *, unsigned int *));
static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type));
static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type));
static struct ia64_opcode *make_ia64_opcode
PARAMS ((ia64_insn, const char *, int, int));
static struct ia64_opcode *ia64_find_matching_opcode
PARAMS ((const char *, short int));
const struct ia64_templ_desc ia64_templ_desc[16] =
{
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */
{ 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },
{ 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" },
{ 0, { 0, }, "-3-" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */
{ 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" },
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */
{ 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" },
{ 0, { 0, }, "-a-" },
{ 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */
{ 0, { 0, }, "-d-" },
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" },
{ 0, { 0, }, "-f-" },
};
#if 0 //ud3
/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST.
PTR will be adjusted to point to the start of the next portion
of the opcode, or at the NUL character. */
static void
get_opc_prefix (ptr, dest)
const char **ptr;
char *dest;
{
char *c = strchr (*ptr, '.');
if (c != NULL)
{
memcpy (dest, *ptr, c - *ptr);
dest[c - *ptr] = '\0';
*ptr = c + 1;
}
else
{
int l = strlen (*ptr);
memcpy (dest, *ptr, l);
dest[l] = '\0';
*ptr += l;
}
}
/* Find the index of the entry in the string table corresponding to
STR; return -1 if one does not exist. */
static short
find_string_ent (str)
const char *str;
{
short start = 0;
short end = sizeof (ia64_strings) / sizeof (const char *);
short i = (start + end) / 2;
if (strcmp (str, ia64_strings[end - 1]) > 0)
{
return -1;
}
while (start <= end)
{
int c = strcmp (str, ia64_strings[i]);
if (c < 0)
{
end = i - 1;
}
else if (c == 0)
{
return i;
}
else
{
start = i + 1;
}
i = (start + end) / 2;
}
return -1;
}
/* Find the opcode in the main opcode table whose name is STRINGINDEX, or
return -1 if one does not exist. */
static short
find_main_ent (nameindex)
short nameindex;
{
short start = 0;
short end = sizeof (main_table) / sizeof (struct ia64_main_table);
short i = (start + end) / 2;
if (nameindex < main_table[0].name_index
|| nameindex > main_table[end - 1].name_index)
{
return -1;
}
while (start <= end)
{
if (nameindex < main_table[i].name_index)
{
end = i - 1;
}
else if (nameindex == main_table[i].name_index)
{
while (i > 0 && main_table[i - 1].name_index == nameindex)
{
i--;
}
return i;
}
else
{
start = i + 1;
}
i = (start + end) / 2;
}
return -1;
}
/* Find the index of the entry in the completer table that is part of
MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
return -1 if one does not exist. */
static short
find_completer (main_ent, prev_completer, name)
short main_ent;
short prev_completer;
const char *name;
{
short name_index = find_string_ent (name);
if (name_index < 0)
{
return -1;
}
if (prev_completer == -1)
{
prev_completer = main_table[main_ent].completers;
}
else
{
prev_completer = completer_table[prev_completer].subentries;
}
while (prev_completer != -1)
{
if (completer_table[prev_completer].name_index == name_index)
{
return prev_completer;
}
prev_completer = completer_table[prev_completer].alternative;
}
return -1;
}
#endif //ud3
/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and
return the result. */
static ia64_insn
apply_completer (opcode, completer_index)
ia64_insn opcode;
int completer_index;
{
ia64_insn mask = completer_table[completer_index].mask;
ia64_insn bits = completer_table[completer_index].bits;
int shiftamt = (completer_table[completer_index].offset & 63);
mask = mask << shiftamt;
bits = bits << shiftamt;
opcode = (opcode & ~mask) | bits;
return opcode;
}
/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in
the dis_table array, and return its value. (BITOFFSET is numbered
starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the
first byte in OP_POINTER.) */
static int
extract_op_bits (op_pointer, bitoffset, bits)
int op_pointer;
int bitoffset;
int bits;
{
int res = 0;
op_pointer += (bitoffset / 8);
if (bitoffset % 8)
{
unsigned int op = dis_table[op_pointer++];
int numb = 8 - (bitoffset % 8);
int mask = (1 << numb) - 1;
int bata = (bits < numb) ? bits : numb;
int delta = numb - bata;
res = (res << bata) | ((op & mask) >> delta);
bitoffset += bata;
bits -= bata;
}
while (bits >= 8)
{
res = (res << 8) | (dis_table[op_pointer++] & 255);
bits -= 8;
}
if (bits > 0)
{
unsigned int op = (dis_table[op_pointer++] & 255);
res = (res << bits) | (op >> (8 - bits));
}
return res;
}
/* Examine the state machine entry at OP_POINTER in the dis_table
array, and extract its values into OPVAL and OP. The length of the
state entry in bits is returned. */
static int
extract_op (op_pointer, opval, op)
int op_pointer;
int *opval;
unsigned int *op;
{
int oplen = 5;
*op = dis_table[op_pointer];
if ((*op) & 0x40)
{
opval[0] = extract_op_bits (op_pointer, oplen, 5);
oplen += 5;
}
switch ((*op) & 0x30)
{
case 0x10:
{
opval[1] = extract_op_bits (op_pointer, oplen, 8);
oplen += 8;
opval[1] += op_pointer;
break;
}
case 0x20:
{
opval[1] = extract_op_bits (op_pointer, oplen, 16);
if (! (opval[1] & 32768))
{
opval[1] += op_pointer;
}
oplen += 16;
break;
}
case 0x30:
{
oplen--;
opval[2] = extract_op_bits (op_pointer, oplen, 12);
oplen += 12;
opval[2] |= 32768;
break;
}
}
if (((*op) & 0x08) && (((*op) & 0x30) != 0x30))
{
opval[2] = extract_op_bits (op_pointer, oplen, 16);
oplen += 16;
if (! (opval[2] & 32768))
{
opval[2] += op_pointer;
}
}
return oplen;
}
/* Returns a non-zero value if the opcode in the main_table list at
PLACE matches OPCODE and is of type TYPE. */
static int
opcode_verify (opcode, place, type)
ia64_insn opcode;
int place;
enum ia64_insn_type type;
{
if (main_table[place].opcode_type != type)
{
return 0;
}
if (main_table[place].flags
& (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
{
const struct ia64_operand *o1, *o2;
ia64_insn f2, f3;
if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3)
{
o1 = elf64_ia64_operands + IA64_OPND_F2;
o2 = elf64_ia64_operands + IA64_OPND_F3;
(*o1->extract) (o1, opcode, &f2);
(*o2->extract) (o2, opcode, &f3);
if (f2 != f3)
return 0;
}
else
{
ia64_insn len, count;
/* length must equal 64-count: */
o1 = elf64_ia64_operands + IA64_OPND_LEN6;
o2 = elf64_ia64_operands + main_table[place].operands[2];
(*o1->extract) (o1, opcode, &len);
(*o2->extract) (o2, opcode, &count);
if (len != 64 - count)
return 0;
}
}
return 1;
}
/* Find an instruction entry in the ia64_dis_names array that matches
opcode OPCODE and is of type TYPE. Returns either a positive index
into the array, or a negative value if an entry for OPCODE could
not be found. Checks all matches and returns the one with the highest
priority. */
static int
locate_opcode_ent (opcode, type)
ia64_insn opcode;
enum ia64_insn_type type;
{
int currtest[41];
int bitpos[41];
int op_ptr[41];
int currstatenum = 0;
short found_disent = -1;
short found_priority = -1;
currtest[currstatenum] = 0;
op_ptr[currstatenum] = 0;
bitpos[currstatenum] = 40;
while (1)
{
int op_pointer = op_ptr[currstatenum];
unsigned int op;
int currbitnum = bitpos[currstatenum];
int oplen;
int opval[3];
int next_op;
int currbit;
oplen = extract_op (op_pointer, opval, &op);
bitpos[currstatenum] = currbitnum;
/* Skip opval[0] bits in the instruction. */
if (op & 0x40)
{
currbitnum -= opval[0];
}
/* The value of the current bit being tested. */
currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0;
next_op = -1;
/* We always perform the tests specified in the current state in
a particular order, falling through to the next test if the
previous one failed. */
switch (currtest[currstatenum])
{
case 0:
currtest[currstatenum]++;
if (currbit == 0 && (op & 0x80))
{
/* Check for a zero bit. If this test solely checks for
a zero bit, we can check for up to 8 consecutive zero
bits (the number to check is specified by the lower 3
bits in the state code.)
If the state instruction matches, we go to the very
next state instruction; otherwise, try the next test. */
if ((op & 0xf8) == 0x80)
{
int count = op & 0x7;
int x;
for (x = 0; x <= count; x++)
{
int i =
opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0;
if (i)
{
break;
}
}
if (x > count)
{
next_op = op_pointer + ((oplen + 7) / 8);
currbitnum -= count;
break;
}
}
else if (! currbit)
{
next_op = op_pointer + ((oplen + 7) / 8);
break;
}
}
/* FALLTHROUGH */
case 1:
/* If the bit in the instruction is one, go to the state
instruction specified by opval[1]. */
currtest[currstatenum]++;
if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30))
{
next_op = opval[1];
break;
}
/* FALLTHROUGH */
case 2:
/* Don't care. Skip the current bit and go to the state
instruction specified by opval[2].
An encoding of 0x30 is special; this means that a 12-bit
offset into the ia64_dis_names[] array is specified. */
currtest[currstatenum]++;
if ((op & 0x08) || ((op & 0x30) == 0x30))
{
next_op = opval[2];
break;
}
}
/* If bit 15 is set in the address of the next state, an offset
in the ia64_dis_names array was specified instead. We then
check to see if an entry in the list of opcodes matches the
opcode we were given; if so, we have succeeded. */
if ((next_op >= 0) && (next_op & 32768))
{
short disent = next_op & 32767;
short priority = -1;
if (next_op > 65535)
{
abort ();
}
/* Run through the list of opcodes to check, trying to find
one that matches. */
while (disent >= 0)
{
int place = ia64_dis_names[disent].insn_index;
priority = ia64_dis_names[disent].priority;
if (opcode_verify (opcode, place, type)
&& priority > found_priority)
{
break;
}
if (ia64_dis_names[disent].next_flag)
{
disent++;
}
else
{
disent = -1;
}
}
if (disent >= 0)
{
found_disent = disent;
found_priority = priority;
}
/* Try the next test in this state, regardless of whether a match
was found. */
next_op = -2;
}
/* next_op == -1 is "back up to the previous state".
next_op == -2 is "stay in this state and try the next test".
Otherwise, transition to the state indicated by next_op. */
if (next_op == -1)
{
currstatenum--;
if (currstatenum < 0)
{
return found_disent;
}
}
else if (next_op >= 0)
{
currstatenum++;
bitpos[currstatenum] = currbitnum - 1;
op_ptr[currstatenum] = next_op;
currtest[currstatenum] = 0;
}
}
}
/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
static struct ia64_opcode __ia64_opcode; //ud3
static struct ia64_opcode *
make_ia64_opcode (opcode, name, place, depind)
ia64_insn opcode;
const char *name;
int place;
int depind;
{
#if 0 //ud3
struct ia64_opcode *res =
(struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode));
res->name = xstrdup (name);
#else
struct ia64_opcode *res = &__ia64_opcode;
res->name = name;
#endif //ud3
res->type = main_table[place].opcode_type;
res->num_outputs = main_table[place].num_outputs;
res->opcode = opcode;
res->mask = main_table[place].mask;
res->operands[0] = main_table[place].operands[0];
res->operands[1] = main_table[place].operands[1];
res->operands[2] = main_table[place].operands[2];
res->operands[3] = main_table[place].operands[3];
res->operands[4] = main_table[place].operands[4];
res->flags = main_table[place].flags;
res->ent_index = place;
res->dependencies = &op_dependencies[depind];
return res;
}
/* Determine the ia64_opcode entry for the opcode specified by INSN
and TYPE. If a valid entry is not found, return NULL. */
struct ia64_opcode *
ia64_dis_opcode (insn, type)
ia64_insn insn;
enum ia64_insn_type type;
{
int disent = locate_opcode_ent (insn, type);
if (disent < 0)
{
return NULL;
}
else
{
unsigned int cb = ia64_dis_names[disent].completer_index;
static char name[128];
int place = ia64_dis_names[disent].insn_index;
int ci = main_table[place].completers;
ia64_insn tinsn = main_table[place].opcode;
strcpy (name, ia64_strings [main_table[place].name_index]);
while (cb)
{
if (cb & 1)
{
int cname = completer_table[ci].name_index;
tinsn = apply_completer (tinsn, ci);
if (ia64_strings[cname][0] != '\0')
{
strcat (name, ".");
strcat (name, ia64_strings[cname]);
}
if (cb != 1)
{
ci = completer_table[ci].subentries;
}
}
else
{
ci = completer_table[ci].alternative;
}
if (ci < 0)
{
abort ();
}
cb = cb >> 1;
}
if (tinsn != (insn & main_table[place].mask))
{
abort ();
}
return make_ia64_opcode (insn, name, place,
completer_table[ci].dependencies);
}
}
#if 0 //ud3
/* Search the main_opcode table starting from PLACE for an opcode that
matches NAME. Return NULL if one is not found. */
static struct ia64_opcode *
ia64_find_matching_opcode (name, place)
const char *name;
short place;
{
char op[129];
const char *suffix;
short name_index;
if (strlen (name) > 128)
{
return NULL;
}
suffix = name;
get_opc_prefix (&suffix, op);
name_index = find_string_ent (op);
if (name_index < 0)
{
return NULL;
}
while (main_table[place].name_index == name_index)
{
const char *curr_suffix = suffix;
ia64_insn curr_insn = main_table[place].opcode;
short completer = -1;
do {
if (suffix[0] == '\0')
{
completer = find_completer (place, completer, suffix);
}
else
{
get_opc_prefix (&curr_suffix, op);
completer = find_completer (place, completer, op);
}
if (completer != -1)
{
curr_insn = apply_completer (curr_insn, completer);
}
} while (completer != -1 && curr_suffix[0] != '\0');
if (completer != -1 && curr_suffix[0] == '\0'
&& completer_table[completer].terminal_completer)
{
int depind = completer_table[completer].dependencies;
return make_ia64_opcode (curr_insn, name, place, depind);
}
else
{
place++;
}
}
return NULL;
}
/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL
if one does not exist.
It is the caller's responsibility to invoke ia64_free_opcode () to
release any resources used by the returned entry. */
struct ia64_opcode *
ia64_find_next_opcode (prev_ent)
struct ia64_opcode *prev_ent;
{
return ia64_find_matching_opcode (prev_ent->name,
prev_ent->ent_index + 1);
}
/* Find the first opcode that matches NAME, or return NULL if it does
not exist.
It is the caller's responsibility to invoke ia64_free_opcode () to
release any resources used by the returned entry. */
struct ia64_opcode *
ia64_find_opcode (name)
const char *name;
{
char op[129];
const char *suffix;
short place;
short name_index;
if (strlen (name) > 128)
{
return NULL;
}
suffix = name;
get_opc_prefix (&suffix, op);
name_index = find_string_ent (op);
if (name_index < 0)
{
return NULL;
}
place = find_main_ent (name_index);
if (place < 0)
{
return NULL;
}
return ia64_find_matching_opcode (name, place);
}
/* Free any resources used by ENT. */
void
ia64_free_opcode (ent)
struct ia64_opcode *ent;
{
free ((void *)ent->name);
free (ent);
}
const struct ia64_dependency *
ia64_find_dependency (index)
int index;
{
index = DEP(index);
if (index < 0
|| index >= (int)(sizeof(dependencies) / sizeof(dependencies[0])))
return NULL;
return &dependencies[index];
}
#endif //ud3

130
contrib/disas/ia64-opc.h
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@ -1,130 +0,0 @@
/* ia64-opc.h -- IA-64 opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef IA64_OPC_H
#define IA64_OPC_H
#include "opcode/ia64.h"
/* define a couple of abbreviations: */
#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37)
#define mOp bOp (-1)
#define Op(x) bOp (x), mOp
#define FIRST IA64_OPCODE_FIRST
#define X_IN_MLX IA64_OPCODE_X_IN_MLX
#define LAST IA64_OPCODE_LAST
#define PRIV IA64_OPCODE_PRIV
#define NO_PRED IA64_OPCODE_NO_PRED
#define SLOT2 IA64_OPCODE_SLOT2
#define PSEUDO IA64_OPCODE_PSEUDO
#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
#define MOD_RRBS IA64_OPCODE_MOD_RRBS
#define POSTINC IA64_OPCODE_POSTINC
#define AR_CCV IA64_OPND_AR_CCV
#define AR_PFS IA64_OPND_AR_PFS
#define C1 IA64_OPND_C1
#define C8 IA64_OPND_C8
#define C16 IA64_OPND_C16
#define GR0 IA64_OPND_GR0
#define IP IA64_OPND_IP
#define PR IA64_OPND_PR
#define PR_ROT IA64_OPND_PR_ROT
#define PSR IA64_OPND_PSR
#define PSR_L IA64_OPND_PSR_L
#define PSR_UM IA64_OPND_PSR_UM
#define AR3 IA64_OPND_AR3
#define B1 IA64_OPND_B1
#define B2 IA64_OPND_B2
#define CR3 IA64_OPND_CR3
#define F1 IA64_OPND_F1
#define F2 IA64_OPND_F2
#define F3 IA64_OPND_F3
#define F4 IA64_OPND_F4
#define P1 IA64_OPND_P1
#define P2 IA64_OPND_P2
#define R1 IA64_OPND_R1
#define R2 IA64_OPND_R2
#define R3 IA64_OPND_R3
#define R3_2 IA64_OPND_R3_2
#define CPUID_R3 IA64_OPND_CPUID_R3
#define DBR_R3 IA64_OPND_DBR_R3
#define DTR_R3 IA64_OPND_DTR_R3
#define ITR_R3 IA64_OPND_ITR_R3
#define IBR_R3 IA64_OPND_IBR_R3
#define MR3 IA64_OPND_MR3
#define MSR_R3 IA64_OPND_MSR_R3
#define PKR_R3 IA64_OPND_PKR_R3
#define PMC_R3 IA64_OPND_PMC_R3
#define PMD_R3 IA64_OPND_PMD_R3
#define RR_R3 IA64_OPND_RR_R3
#define CCNT5 IA64_OPND_CCNT5
#define CNT2a IA64_OPND_CNT2a
#define CNT2b IA64_OPND_CNT2b
#define CNT2c IA64_OPND_CNT2c
#define CNT5 IA64_OPND_CNT5
#define CNT6 IA64_OPND_CNT6
#define CPOS6a IA64_OPND_CPOS6a
#define CPOS6b IA64_OPND_CPOS6b
#define CPOS6c IA64_OPND_CPOS6c
#define IMM1 IA64_OPND_IMM1
#define IMM14 IA64_OPND_IMM14
#define IMM17 IA64_OPND_IMM17
#define IMM22 IA64_OPND_IMM22
#define IMM44 IA64_OPND_IMM44
#define SOF IA64_OPND_SOF
#define SOL IA64_OPND_SOL
#define SOR IA64_OPND_SOR
#define IMM8 IA64_OPND_IMM8
#define IMM8U4 IA64_OPND_IMM8U4
#define IMM8M1 IA64_OPND_IMM8M1
#define IMM8M1U4 IA64_OPND_IMM8M1U4
#define IMM8M1U8 IA64_OPND_IMM8M1U8
#define IMM9a IA64_OPND_IMM9a
#define IMM9b IA64_OPND_IMM9b
#define IMMU2 IA64_OPND_IMMU2
#define IMMU21 IA64_OPND_IMMU21
#define IMMU24 IA64_OPND_IMMU24
#define IMMU62 IA64_OPND_IMMU62
#define IMMU64 IA64_OPND_IMMU64
#define IMMU7a IA64_OPND_IMMU7a
#define IMMU7b IA64_OPND_IMMU7b
#define IMMU9 IA64_OPND_IMMU9
#define INC3 IA64_OPND_INC3
#define LEN4 IA64_OPND_LEN4
#define LEN6 IA64_OPND_LEN6
#define MBTYPE4 IA64_OPND_MBTYPE4
#define MHTYPE8 IA64_OPND_MHTYPE8
#define POS6 IA64_OPND_POS6
#define TAG13 IA64_OPND_TAG13
#define TAG13b IA64_OPND_TAG13b
#define TGT25 IA64_OPND_TGT25
#define TGT25b IA64_OPND_TGT25b
#define TGT25c IA64_OPND_TGT25c
#define TGT64 IA64_OPND_TGT64
#endif

891
contrib/disas/mips-dis.cc
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@ -1,891 +0,0 @@
/* Print mips instructions for GDB, the GNU debugger, or for objdump.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
This file is part of GDB, GAS, and the GNU binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "mips.h"
/* FIXME: These are needed to figure out if the code is mips16 or
not. The low bit of the address is often a good indicator. No
symbol table is available when this code runs out in an embedded
system as when it is used for disassembler support in a monitor. */
#ifndef _
#define _(string) string
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
#endif
static void print_address( unsigned long addr );
static int strcmp( const char *s1, const char *s2 )
{
while( 1 ) {
if( !*s1 && !*s2 )
return 0;
if( (!*s1 && *s2) || (*s1 < *s2) )
return -1;
if( (*s1 && !*s2) || (*s1 > *s2) )
return 1;
s1++;
s2++;
}
}
/* Mips instructions are at maximum this many bytes long. */
#define INSNLEN 4
static int _print_insn_mips
PARAMS ((word_t, unsigned long, unsigned long format ));
static int print_insn_mips
PARAMS ((unsigned long, unsigned long int, unsigned long format));
static void print_insn_args
PARAMS ((const char *, unsigned long, unsigned , unsigned long format));
/* FIXME: These should be shared with gdb somehow. */
struct mips_cp0sel_name {
unsigned int cp0reg;
unsigned int sel;
const char * const name;
};
#if 0
static const char * const mips_gpr_names_numeric[32] = {
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
static const char * const mips_gpr_names_oldabi[32] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
static const char * const mips_gpr_names_newabi[32] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
#endif
static const char * const mips_gpr_names_pistachio[32] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"a4", "a5", "a6", "a7", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
static const char * const mips_fpr_names_numeric[32] = {
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
};
#if 0
static const char * const mips_fpr_names_32[32] = {
"fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
"ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
"ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
"fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
};
static const char * const mips_fpr_names_n32[32] = {
"fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
"fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
"fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
};
static const char * const mips_fpr_names_64[32] = {
"fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
"fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
"fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
};
#endif
static const char * const mips_cp0_names_r4x00[32] = {
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "$7",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
"c0_status", "c0_cause", "c0_epc", "c0_prid",
"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
"c0_xcontext", "$21", "$22", "$23",
"$24", "$25", "c0_ecc", "c0_cacheerr",
"c0_taglo", "c0_taghi", "c0_errorepc", "$31",
};
#if 0
static const char * const mips_cp0_names_mips3264[32] = {
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "$7",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
"c0_status", "c0_cause", "c0_epc", "c0_prid",
"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
"c0_xcontext", "$21", "$22", "c0_debug",
"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
{ 16, 1, "c0_config1" },
{ 16, 2, "c0_config2" },
{ 16, 3, "c0_config3" },
{ 18, 1, "c0_watchlo,1" },
{ 18, 2, "c0_watchlo,2" },
{ 18, 3, "c0_watchlo,3" },
{ 18, 4, "c0_watchlo,4" },
{ 18, 5, "c0_watchlo,5" },
{ 18, 6, "c0_watchlo,6" },
{ 18, 7, "c0_watchlo,7" },
{ 19, 1, "c0_watchhi,1" },
{ 19, 2, "c0_watchhi,2" },
{ 19, 3, "c0_watchhi,3" },
{ 19, 4, "c0_watchhi,4" },
{ 19, 5, "c0_watchhi,5" },
{ 19, 6, "c0_watchhi,6" },
{ 19, 7, "c0_watchhi,7" },
{ 25, 1, "c0_perfcnt,1" },
{ 25, 2, "c0_perfcnt,2" },
{ 25, 3, "c0_perfcnt,3" },
{ 25, 4, "c0_perfcnt,4" },
{ 25, 5, "c0_perfcnt,5" },
{ 25, 6, "c0_perfcnt,6" },
{ 25, 7, "c0_perfcnt,7" },
{ 27, 1, "c0_cacheerr,1" },
{ 27, 2, "c0_cacheerr,2" },
{ 27, 3, "c0_cacheerr,3" },
{ 28, 1, "c0_datalo" },
{ 29, 1, "c0_datahi" }
};
static const char * const mips_cp0_names_mips3264r2[32] = {
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
"c0_status", "c0_cause", "c0_epc", "c0_prid",
"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
"c0_xcontext", "$21", "$22", "c0_debug",
"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
{ 4, 1, "c0_contextconfig" },
{ 5, 1, "c0_pagegrain" },
{ 12, 1, "c0_intctl" },
{ 12, 2, "c0_srsctl" },
{ 12, 3, "c0_srsmap" },
{ 15, 1, "c0_ebase" },
{ 16, 1, "c0_config1" },
{ 16, 2, "c0_config2" },
{ 16, 3, "c0_config3" },
{ 18, 1, "c0_watchlo,1" },
{ 18, 2, "c0_watchlo,2" },
{ 18, 3, "c0_watchlo,3" },
{ 18, 4, "c0_watchlo,4" },
{ 18, 5, "c0_watchlo,5" },
{ 18, 6, "c0_watchlo,6" },
{ 18, 7, "c0_watchlo,7" },
{ 19, 1, "c0_watchhi,1" },
{ 19, 2, "c0_watchhi,2" },
{ 19, 3, "c0_watchhi,3" },
{ 19, 4, "c0_watchhi,4" },
{ 19, 5, "c0_watchhi,5" },
{ 19, 6, "c0_watchhi,6" },
{ 19, 7, "c0_watchhi,7" },
{ 23, 1, "c0_tracecontrol" },
{ 23, 2, "c0_tracecontrol2" },
{ 23, 3, "c0_usertracedata" },
{ 23, 4, "c0_tracebpc" },
{ 25, 1, "c0_perfcnt,1" },
{ 25, 2, "c0_perfcnt,2" },
{ 25, 3, "c0_perfcnt,3" },
{ 25, 4, "c0_perfcnt,4" },
{ 25, 5, "c0_perfcnt,5" },
{ 25, 6, "c0_perfcnt,6" },
{ 25, 7, "c0_perfcnt,7" },
{ 27, 1, "c0_cacheerr,1" },
{ 27, 2, "c0_cacheerr,2" },
{ 27, 3, "c0_cacheerr,3" },
{ 28, 1, "c0_datalo" },
{ 28, 2, "c0_taglo1" },
{ 28, 3, "c0_datalo1" },
{ 28, 4, "c0_taglo2" },
{ 28, 5, "c0_datalo2" },
{ 28, 6, "c0_taglo3" },
{ 28, 7, "c0_datalo3" },
{ 29, 1, "c0_datahi" },
{ 29, 2, "c0_taghi1" },
{ 29, 3, "c0_datahi1" },
{ 29, 4, "c0_taghi2" },
{ 29, 5, "c0_datahi2" },
{ 29, 6, "c0_taghi3" },
{ 29, 7, "c0_datahi3" },
};
#endif
#if CONFIG_CPU_MIPS64_SB1
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
static const char * const mips_cp0_names_sb1[32] = {
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
"c0_context", "c0_pagemask", "c0_wired", "$7",
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
"c0_status", "c0_cause", "c0_epc", "c0_prid",
"c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
"c0_xcontext", "$21", "$22", "c0_debug",
"c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
"c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
};
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
{ 16, 1, "c0_config1" },
{ 18, 1, "c0_watchlo,1" },
{ 19, 1, "c0_watchhi,1" },
{ 22, 0, "c0_perftrace" },
{ 23, 3, "c0_edebug" },
{ 25, 1, "c0_perfcnt,1" },
{ 25, 2, "c0_perfcnt,2" },
{ 25, 3, "c0_perfcnt,3" },
{ 25, 4, "c0_perfcnt,4" },
{ 25, 5, "c0_perfcnt,5" },
{ 25, 6, "c0_perfcnt,6" },
{ 25, 7, "c0_perfcnt,7" },
{ 26, 1, "c0_buserr_pa" },
{ 27, 1, "c0_cacheerr_d" },
{ 27, 3, "c0_cacheerr_d_pa" },
{ 28, 1, "c0_datalo_i" },
{ 28, 2, "c0_taglo_d" },
{ 28, 3, "c0_datalo_d" },
{ 29, 1, "c0_datahi_i" },
{ 29, 2, "c0_taghi_d" },
{ 29, 3, "c0_datahi_d" },
};
#endif
static const char * const mips_hwr_names_numeric[32] = {
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
#if 0
static const char * const mips_hwr_names_mips3264r2[32] = {
"hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
"$4", "$5", "$6", "$7",
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
#endif
struct mips_abi_choice {
const char *name;
const char * const *gpr_names;
const char * const *fpr_names;
};
struct mips_arch_choice {
const char *name;
int bfd_mach_valid;
unsigned long bfd_mach;
int processor;
int isa;
const char * const *cp0_names;
const struct mips_cp0sel_name *cp0sel_names;
unsigned int cp0sel_names_len;
const char * const *hwr_names;
};
#if 0
const struct mips_arch_choice mips_arch_choices[] = {
{ "numeric", 0, 0, 0, 0,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
_MIPS32 Architecture For Programmers Volume I: Introduction to the
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
ISA_MIPS32 | INSN_MIPS16,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
ISA_MIPS32R2 | INSN_MIPS16,
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
mips_cp0_names_sb1,
mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
mips_hwr_names_numeric },
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
};
#endif
/* ISA and processor type to disassemble for, and register names to use.
set_default_mips_dis_options and parse_mips_dis_options fill in these
values. */
static int mips_processor;
static int mips_isa;
static const char * const *mips_gpr_names;
static const char * const *mips_fpr_names;
static const char * const *mips_cp0_names;
static const struct mips_cp0sel_name *mips_cp0sel_names;
static int mips_cp0sel_names_len;
static const char * const *mips_hwr_names;
static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
unsigned int));
void
set_default_mips_dis_options ( unsigned int type )
{
/* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
and numeric FPR, CP0 register, and HWR names. */
mips_gpr_names = mips_gpr_names_pistachio;
mips_fpr_names = mips_fpr_names_numeric;
#if CONFIG_CPU_MIPS64_R4X00
mips_isa = ISA_MIPS3;
mips_processor = CPU_R4600;
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
mips_hwr_names = mips_hwr_names_numeric;
mips_cp0_names = mips_cp0_names_r4x00;
#elif CONFIG_CPU_MIPS64_RC64574
mips_isa = ISA_MIPS4;
mips_processor = CPU_R5000;
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
mips_hwr_names = mips_hwr_names_numeric;
mips_cp0_names = mips_cp0_names_r4x00;
#elif CONFIG_CPU_MIPS64_SB1
mips_isa = ISA_MIPS64 | INSN_MIPS3D | INSN_SB1;
mips_processor = CPU_SB1;
mips_cp0sel_names = mips_cp0sel_names_sb1;
mips_cp0sel_names_len = ARRAY_SIZE (mips_cp0sel_names_sb1);
mips_hwr_names = mips_hwr_names_numeric;
mips_cp0_names = mips_cp0_names_sb1;
#elif CONFIG_CPU_MIPS64_VR4121
mips_isa = ISA_MIPS3;
mips_processor = CPU_VR4120;
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
mips_hwr_names = mips_hwr_names_numeric;
mips_cp0_names = mips_cp0_names_r4x00;
#elif CONFIG_CPU_MIPS64_VR4181
mips_isa = ISA_MIPS3;
mips_processor = CPU_R4111;
mips_cp0sel_names = NULL;
mips_cp0sel_names_len = 0;
mips_hwr_names = mips_hwr_names_numeric;
mips_cp0_names = mips_cp0_names_r4x00;
#else
#error unknown CPU
#endif
}
static const struct mips_cp0sel_name *
lookup_mips_cp0sel_name( const struct mips_cp0sel_name *names,
unsigned int len, unsigned int cp0reg,
unsigned int sel )
{
unsigned int i;
for (i = 0; i < len; i++)
if (names[i].cp0reg == cp0reg && names[i].sel == sel)
return &names[i];
return NULL;
}
/* Print insn arguments for 32/64-bit code. */
static void
print_insn_args ( const char *d,
unsigned long int l,
unsigned long pc,
unsigned long format )
{
int op, delta;
unsigned int lsb, msb, msbd;
unsigned long target;
lsb = 0;
for (; *d != '\0'; d++)
{
switch (*d)
{
case ',':
case '(':
case ')':
case '[':
case ']':
printf("%c", *d);
break;
case '+':
/* Extension character; switch for second char. */
d++;
switch (*d)
{
case '\0':
/* xgettext:c-format */
printf( _("# internal error, incomplete extension sequence (+)"));
return;
case 'A':
lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
printf ("0x%x", lsb);
break;
case 'B':
msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
printf ("0x%x", msb - lsb + 1);
break;
case 'C':
msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
printf("0x%x", msbd + 1);
break;
case 'D':
{
const struct mips_cp0sel_name *n;
unsigned int cp0reg, sel;
cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
/* CP0 register including 'sel' code for mtcN (et al.), to be
printed textually if known. If not known, print both
CP0 register name and sel numerically since CP0 register
with sel 0 may have a name unrelated to register being
printed. */
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
mips_cp0sel_names_len, cp0reg, sel);
if (n != NULL)
printf ( "%s", n->name);
else
printf("$%d,%d", cp0reg, sel);
break;
}
default:
/* xgettext:c-format */
printf( _("# internal error, undefined extension sequence (+%c)"),
*d);
return;
}
break;
case 's':
case 'b':
case 'r':
case 'v':
printf("%s", mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
break;
case 't':
case 'w':
printf("%s", mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
break;
case 'i':
case 'u':
printf("0x%x", (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
break;
case 'j': /* Same as i, but sign-extended. */
case 'o':
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
if (delta & 0x8000)
delta |= ~0xffff;
printf("%d", delta);
break;
case 'h':
printf ("0x%x", (unsigned int) ((l >> OP_SH_PREFX)
& OP_MASK_PREFX));
break;
case 'k':
printf("0x%x", (unsigned int) ((l >> OP_SH_CACHE)
& OP_MASK_CACHE));
break;
case 'a':
target = (((pc + 4) & ~(unsigned long) 0x0fffffff)
| (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
print_address (target);
break;
case 'p':
/* Sign extend the displacement. */
delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
if (delta & 0x8000)
delta |= ~0xffff;
target = (delta << 2) + pc + INSNLEN;
print_address(target);
break;
case 'd':
printf ("%s", mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
case 'U':
{
/* First check for both rd and rt being equal. */
unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
printf("%s",
mips_gpr_names[reg]);
else
{
/* If one is zero use the other. */
if (reg == 0)
printf ("%s", mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
printf("%s", mips_gpr_names[reg]);
else /* Bogus, result depends on processor. */
printf("%s or %s", mips_gpr_names[reg],
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
}
}
break;
case 'z':
printf ( "%s", mips_gpr_names[0]);
break;
case '<':
printf( "0x%x", (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
break;
case 'c':
printf ("0x%x", (l >> OP_SH_CODE) & OP_MASK_CODE);
break;
case 'q':
printf ("0x%x", (l >> OP_SH_CODE2) & OP_MASK_CODE2);
break;
case 'C':
printf("0x%x", (l >> OP_SH_COPZ) & OP_MASK_COPZ);
break;
case 'B':
printf ("0x%x", (l >> OP_SH_CODE20) & OP_MASK_CODE20);
break;
case 'J':
printf ("0x%x", (l >> OP_SH_CODE19) & OP_MASK_CODE19);
break;
case 'S':
case 'V':
printf ( "%s", mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
break;
case 'T':
case 'W':
printf( "%s", mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
break;
case 'D':
printf ("%s", mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
break;
case 'R':
printf("%s", mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
break;
case 'E':
/* Coprocessor register for lwcN instructions, et al.
Note that there is no load/store cp0 instructions, and
that FPU (cp1) instructions disassemble this field using
'T' format. Therefore, until we gain understanding of
cp2 register names, we can simply print the register
numbers. */
printf("$%d", (l >> OP_SH_RT) & OP_MASK_RT);
break;
case 'G':
/* Coprocessor register for mtcN instructions, et al. Note
that FPU (cp1) instructions disassemble this field using
'S' format. Therefore, we only need to worry about cp0,
cp2, and cp3. */
op = (l >> OP_SH_OP) & OP_MASK_OP;
if (op == OP_OP_COP0)
printf("%s", mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
else
printf("$%d", (l >> OP_SH_RD) & OP_MASK_RD);
break;
case 'K':
printf ("%s", mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
break;
case 'N':
printf("$fcc%d", (l >> OP_SH_BCC) & OP_MASK_BCC);
break;
case 'M':
printf ("$fcc%d", (l >> OP_SH_CCC) & OP_MASK_CCC);
break;
case 'P':
printf ("%d", (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
break;
case 'e':
printf("%d", (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
break;
case '%':
printf("%d", (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
break;
case 'H':
printf ("%d", (l >> OP_SH_SEL) & OP_MASK_SEL);
break;
case 'O':
printf( "%d", (l >> OP_SH_ALN) & OP_MASK_ALN);
break;
case 'Q':
{
unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
if ((vsel & 0x10) == 0)
{
int fmt;
vsel &= 0x0f;
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
if ((vsel & 1) == 0)
break;
printf( "$v%d[%d]",
(l >> OP_SH_FT) & OP_MASK_FT,
vsel >> 1);
}
else if ((vsel & 0x08) == 0)
{
printf( "$v%d", (l >> OP_SH_FT) & OP_MASK_FT);
}
else
{
printf("0x%x", (l >> OP_SH_FT) & OP_MASK_FT);
}
}
break;
case 'X':
printf("$v%d", (l >> OP_SH_FD) & OP_MASK_FD);
break;
case 'Y':
printf ( "$v%d", (l >> OP_SH_FS) & OP_MASK_FS);
break;
case 'Z':
printf ("$v%d", (l >> OP_SH_FT) & OP_MASK_FT);
break;
default:
/* xgettext:c-format */
printf( _("# internal error, undefined modifier(%c)"),
*d);
return;
}
}
}
/* Print the mips instruction at address MEMADDR in debugged memory,
on using INFO. Returns length of the instruction, in bytes, which is
always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
this is little-endian code. */
static int
print_insn_mips ( unsigned long memaddr,
unsigned long int word,
unsigned long format )
{
register const struct mips_opcode *op;
static bool init = 0;
static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
/* Build a hash table to shorten the search time. */
if (! init)
{
unsigned int i;
for (i = 0; i <= OP_MASK_OP; i++)
{
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo == INSN_MACRO)
continue;
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
{
mips_hash[i] = op;
break;
}
}
}
set_default_mips_dis_options ( 0 );
init = 1;
}
op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
if (op != NULL)
{
for (; op < &mips_opcodes[NUMOPCODES]; op++)
{
if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
{
register const char *d;
/* We always allow to disassemble the jalx instruction. */
if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
&& strcmp (op->name, "jalx"))
continue;
/* Figure out instruction type and branch delay information. */
if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
{
}
else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
| INSN_COND_BRANCH_LIKELY)) != 0)
{
}
else if ((op->pinfo & (INSN_STORE_MEMORY
| INSN_LOAD_MEMORY_DELAY)) != 0)
;
printf( "%s", op->name);
d = op->args;
if (d != NULL && *d != '\0')
{
printf ("\t");
print_insn_args (d, word, memaddr, format);
}
return INSNLEN;
}
}
}
printf("0x%x", word);
return INSNLEN;
}
/* In an environment where we do not know the symbol type of the
instruction we are forced to assume that the low order bit of the
instructions' address may mark it as a mips16 instruction. If we
are single stepping, or the pc is within the disassembled function,
this works. Otherwise, we need a clue. Sometimes. */
static int
_print_insn_mips ( word_t insn, unsigned long memaddr, unsigned long format )
{
return print_insn_mips (memaddr, insn, format);
}

1199
contrib/disas/mips-opc.cc
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contrib/disas/mips.h
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/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
(i >> OP_SH_X) & OP_MASK_X
To set the same field (to j), use
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
Make sure you use fields that are appropriate for the instruction,
of course.
The 'i' format uses OP, RS, RT and IMMEDIATE.
The 'j' format uses OP and TARGET.
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
The 'b' format uses OP, RS, RT and DELTA.
The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits). An optional two-operand form of break/sdbbp
allows the lower ten bits to be set too, and MIPS32 and later
architectures allow 20 bits to be set with a signal operand
(using CODE20).
The syscall instruction uses CODE20.
The general coprocessor instructions use COPZ. */
#define OP_MASK_OP 0x3f
#define OP_SH_OP 26
#define OP_MASK_RS 0x1f
#define OP_SH_RS 21
#define OP_MASK_FR 0x1f
#define OP_SH_FR 21
#define OP_MASK_FMT 0x1f
#define OP_SH_FMT 21
#define OP_MASK_BCC 0x7
#define OP_SH_BCC 18
#define OP_MASK_CODE 0x3ff
#define OP_SH_CODE 16
#define OP_MASK_CODE2 0x3ff
#define OP_SH_CODE2 6
#define OP_MASK_RT 0x1f
#define OP_SH_RT 16
#define OP_MASK_FT 0x1f
#define OP_SH_FT 16
#define OP_MASK_CACHE 0x1f
#define OP_SH_CACHE 16
#define OP_MASK_RD 0x1f
#define OP_SH_RD 11
#define OP_MASK_FS 0x1f
#define OP_SH_FS 11
#define OP_MASK_PREFX 0x1f
#define OP_SH_PREFX 11
#define OP_MASK_CCC 0x7
#define OP_SH_CCC 8
#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
#define OP_SH_TARGET 0
#define OP_MASK_COPZ 0x1ffffff
#define OP_SH_COPZ 0
#define OP_MASK_IMMEDIATE 0xffff
#define OP_SH_IMMEDIATE 0
#define OP_MASK_DELTA 0xffff
#define OP_SH_DELTA 0
#define OP_MASK_FUNCT 0x3f
#define OP_SH_FUNCT 0
#define OP_MASK_SPEC 0x3f
#define OP_SH_SPEC 0
#define OP_SH_LOCC 8 /* FP condition code. */
#define OP_SH_HICC 18 /* FP condition code. */
#define OP_MASK_CC 0x7
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
#define OP_MASK_COP1NORM 0x1 /* a single bit. */
#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
#define OP_MASK_COP1SPEC 0xf
#define OP_MASK_COP1SCLR 0x4
#define OP_MASK_COP1CMP 0x3
#define OP_SH_COP1CMP 4
#define OP_SH_FORMAT 21 /* FP short format field. */
#define OP_MASK_FORMAT 0x7
#define OP_SH_TRUE 16
#define OP_MASK_TRUE 0x1
#define OP_SH_GE 17
#define OP_MASK_GE 0x01
#define OP_SH_UNSIGNED 16
#define OP_MASK_UNSIGNED 0x1
#define OP_SH_HINT 16
#define OP_MASK_HINT 0x1f
#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
#define OP_MASK_MMI 0x3f
#define OP_SH_MMISUB 6
#define OP_MASK_MMISUB 0x1f
#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
#define OP_SH_PERFREG 1
#define OP_SH_SEL 0 /* Coprocessor select field. */
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
#define OP_SH_CODE19 6 /* 19 bit wait code. */
#define OP_MASK_CODE19 0x7ffff
#define OP_SH_ALN 21
#define OP_MASK_ALN 0x7
#define OP_SH_VSEL 21
#define OP_MASK_VSEL 0x1f
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
but 0x8-0xf don't select bytes. */
#define OP_SH_VECBYTE 22
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
#define OP_SH_VECALIGN 21
#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
#define OP_SH_INSMSB 11
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
#define OP_SH_EXTMSBD 11
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
#define OP_OP_COP3 0x13
#define OP_OP_LWC1 0x31
#define OP_OP_LWC2 0x32
#define OP_OP_LWC3 0x33 /* a.k.a. pref */
#define OP_OP_LDC1 0x35
#define OP_OP_LDC2 0x36
#define OP_OP_LDC3 0x37 /* a.k.a. ld */
#define OP_OP_SWC1 0x39
#define OP_OP_SWC2 0x3a
#define OP_OP_SWC3 0x3b
#define OP_OP_SDC1 0x3d
#define OP_OP_SDC2 0x3e
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
/* Values in the 'VSEL' field. */
#define MDMX_FMTSEL_IMM_QH 0x1d
#define MDMX_FMTSEL_IMM_OB 0x1e
#define MDMX_FMTSEL_VEC_QH 0x15
#define MDMX_FMTSEL_VEC_OB 0x16
/* This structure holds information for a particular instruction. */
struct mips_opcode
{
/* The name of the instruction. */
const char *name;
/* A string describing the arguments for this instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
actual opcode anded with the match field equals the opcode field,
then we have found the correct instruction. If pinfo is
INSN_MACRO, then this field is the macro identifier. */
unsigned long mask;
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
};
/* These are the characters which may appear in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
Each of these characters corresponds to a mask field defined above.
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD)
"h" 5 bit prefx hint (OP_*_PREFX)
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
"t" 5 bit target register (OP_*_RT)
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
"v" 5 bit same register used as both source and destination (OP_*_RS)
"w" 5 bit same register used as both target and destination (OP_*_RT)
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
(used by clo and clz)
"C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
"J" 19 bit wait function code (OP_*_CODE19)
"x" accept and ignore register name
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
"S" 5 bit fs source 1 register (OP_*_FS)
"T" 5 bit ft source 2 register (OP_*_FT)
"R" 5 bit fr source 3 register (OP_*_FR)
"V" 5 bit same register used as floating source and destination (OP_*_FS)
"W" 5 bit same register used as floating target and destination (OP_*_FT)
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
see also "k" above
"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only.
Macro instructions:
"A" General 32 bit expression
"I" 32 bit immediate
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
MDMX instruction operands (note that while these use the FP register
fields, they accept both $fN and $vN names for the registers):
"O" MDMX alignment offset (OP_*_ALN)
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
"X" MDMX destination register (OP_*_FD)
"Y" MDMX source register (OP_*_FS)
"Z" MDMX source register (OP_*_FT)
Other:
"()" parens surrounding optional value
"," separates operands
"[]" brackets around index for vector-op scalar operand specifier (vr5400)
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
"%[]<>(),+"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefhijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"ABCD"
*/
/* These are the bits which may be set in the pinfo field of an
instructions, if it is not equal to INSN_MACRO. */
/* Modifies the general purpose register in OP_*_RD. */
#define INSN_WRITE_GPR_D 0x00000001
/* Modifies the general purpose register in OP_*_RT. */
#define INSN_WRITE_GPR_T 0x00000002
/* Modifies general purpose register 31. */
#define INSN_WRITE_GPR_31 0x00000004
/* Modifies the floating point register in OP_*_FD. */
#define INSN_WRITE_FPR_D 0x00000008
/* Modifies the floating point register in OP_*_FS. */
#define INSN_WRITE_FPR_S 0x00000010
/* Modifies the floating point register in OP_*_FT. */
#define INSN_WRITE_FPR_T 0x00000020
/* Reads the general purpose register in OP_*_RS. */
#define INSN_READ_GPR_S 0x00000040
/* Reads the general purpose register in OP_*_RT. */
#define INSN_READ_GPR_T 0x00000080
/* Reads the floating point register in OP_*_FS. */
#define INSN_READ_FPR_S 0x00000100
/* Reads the floating point register in OP_*_FT. */
#define INSN_READ_FPR_T 0x00000200
/* Reads the floating point register in OP_*_FR. */
#define INSN_READ_FPR_R 0x00000400
/* Modifies coprocessor condition code. */
#define INSN_WRITE_COND_CODE 0x00000800
/* Reads coprocessor condition code. */
#define INSN_READ_COND_CODE 0x00001000
/* TLB operation. */
#define INSN_TLB 0x00002000
/* Reads coprocessor register other than floating point register. */
#define INSN_COP 0x00004000
/* Instruction loads value from memory, requiring delay. */
#define INSN_LOAD_MEMORY_DELAY 0x00008000
/* Instruction loads value from coprocessor, requiring delay. */
#define INSN_LOAD_COPROC_DELAY 0x00010000
/* Instruction has unconditional branch delay slot. */
#define INSN_UNCOND_BRANCH_DELAY 0x00020000
/* Instruction has conditional branch delay slot. */
#define INSN_COND_BRANCH_DELAY 0x00040000
/* Conditional branch likely: if branch not taken, insn nullified. */
#define INSN_COND_BRANCH_LIKELY 0x00080000
/* Moves to coprocessor register, requiring delay. */
#define INSN_COPROC_MOVE_DELAY 0x00100000
/* Loads coprocessor register from memory, requiring delay. */
#define INSN_COPROC_MEMORY_DELAY 0x00200000
/* Reads the HI register. */
#define INSN_READ_HI 0x00400000
/* Reads the LO register. */
#define INSN_READ_LO 0x00800000
/* Modifies the HI register. */
#define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */
#define INSN_WRITE_LO 0x02000000
/* Takes a trap (easier to keep out of delay slot). */
#define INSN_TRAP 0x04000000
/* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x08000000
/* Instruction uses single precision floating point. */
#define FP_S 0x10000000
/* Instruction uses double precision floating point. */
#define FP_D 0x20000000
/* Instruction is part of the tx39's integer multiply family. */
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
#define INSN_READ_MDMX_ACC 0
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
#define INSN_WRITE_MDMX_ACC 0
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. ISAs, as defined below, are logical
ORs of these bits, indicating that they support the instructions
defined at the given level. */
#define INSN_ISA_MASK 0x00000fff
#define INSN_ISA1 0x00000001
#define INSN_ISA2 0x00000002
#define INSN_ISA3 0x00000004
#define INSN_ISA4 0x00000008
#define INSN_ISA5 0x00000010
#define INSN_ISA32 0x00000020
#define INSN_ISA64 0x00000040
#define INSN_ISA32R2 0x00000080
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x0000f000
/* MIPS 16 ASE */
#define INSN_MIPS16 0x00002000
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00004000
/* MDMX ASE */
#define INSN_MDMX 0x00008000
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
/* LSI R4010 instruction. */
#define INSN_4010 0x00020000
/* NEC VR4100 instruction. */
#define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00080000
/* MIPS R10000 instruction. */
#define INSN_10000 0x00100000
/* Broadcom SB-1 instruction. */
#define INSN_SB1 0x00200000
/* NEC VR4111/VR4181 instruction. */
#define INSN_4111 0x00400000
/* NEC VR4120 instruction. */
#define INSN_4120 0x00800000
/* NEC VR5400 instruction. */
#define INSN_5400 0x01000000
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_UNKNOWN 0 /* Gas internal use. */
#define ISA_MIPS1 (INSN_ISA1)
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
#define CPU_UNKNOWN 0 /* Gas internal use. */
#define CPU_R3000 3000
#define CPU_R3900 3900
#define CPU_R4000 4000
#define CPU_R4010 4010
#define CPU_VR4100 4100
#define CPU_R4111 4111
#define CPU_VR4120 4120
#define CPU_R4300 4300
#define CPU_R4400 4400
#define CPU_R4600 4600
#define CPU_R4650 4650
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
#define CPU_R6000 6000
#define CPU_R8000 8000
#define CPU_R10000 10000
#define CPU_R12000 12000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_SB1 12310201 /* octal 'SB', 01. */
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
test, or zero if no CPU specific ISA test is desired. */
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
(((insn)->membership & isa) != 0 \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
_I appended means immediate
_A appended means address
_AB appended means address with base register
_D appended means 64 bit floating point constant
_S appended means 32 bit floating point constant. */
enum
{
M_ABS,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_BEQ,
M_BEQ_I,
M_BEQL_I,
M_BGE,
M_BGEL,
M_BGE_I,
M_BGEL_I,
M_BGEU,
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
M_BGT,
M_BGTL,
M_BGT_I,
M_BGTL_I,
M_BGTU,
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
M_BLE,
M_BLEL,
M_BLE_I,
M_BLEL_I,
M_BLEU,
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
M_BLT,
M_BLTL,
M_BLT_I,
M_BLTL_I,
M_BLTU,
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
M_BNE,
M_BNE_I,
M_BNEL_I,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_DDIV_3,
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
M_DIVU_3I,
M_DLA_AB,
M_DLI,
M_DMUL,
M_DMUL_I,
M_DMULO,
M_DMULO_I,
M_DMULOU,
M_DMULOU_I,
M_DREM_3,
M_DREM_3I,
M_DREMU_3,
M_DREMU_3I,
M_DSUB_I,
M_DSUBU_I,
M_DSUBU_I_2,
M_J_A,
M_JAL_1,
M_JAL_2,
M_JAL_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LBU_A,
M_LBU_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDR_AB,
M_LH_A,
M_LH_AB,
M_LHU_A,
M_LHU_AB,
M_LI,
M_LI_D,
M_LI_DD,
M_LI_S,
M_LI_SS,
M_LL_AB,
M_LLD_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
M_MOVE,
M_MUL,
M_MUL_I,
M_MULO,
M_MULO_I,
M_MULOU,
M_MULOU_I,
M_NOR_I,
M_OR_I,
M_REM_3,
M_REM_3I,
M_REMU_3,
M_REMU_3I,
M_DROL,
M_ROL,
M_DROL_I,
M_ROL_I,
M_DROR,
M_ROR,
M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
M_S_DAB,
M_S_S,
M_SC_AB,
M_SCD_AB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDR_AB,
M_SEQ,
M_SEQ_I,
M_SGE,
M_SGE_I,
M_SGEU,
M_SGEU_I,
M_SGT,
M_SGT_I,
M_SGTU,
M_SGTU_I,
M_SLE,
M_SLE_I,
M_SLEU,
M_SLEU_I,
M_SLT_I,
M_SLTU_I,
M_SNE,
M_SNE_I,
M_SB_A,
M_SB_AB,
M_SH_A,
M_SH_AB,
M_SW_A,
M_SW_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
M_SWR_A,
M_SWR_AB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
M_TEQ_I,
M_TGE_I,
M_TGEU_I,
M_TLT_I,
M_TLTU_I,
M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
M_ULD,
M_ULD_A,
M_ULH,
M_ULH_A,
M_ULHU,
M_ULHU_A,
M_ULW,
M_ULW_A,
M_USH,
M_USH_A,
M_USW,
M_USW_A,
M_USD,
M_USD_A,
M_XOR_I,
M_COP0,
M_COP1,
M_COP2,
M_COP3,
M_NUM_MACROS
};
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
assembler to pick the right one. In other words, entries with
immediate operands must apear after the same instruction with
registers.
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
extern const struct mips_opcode mips_builtin_opcodes[];
extern const int bfd_mips_num_builtin_opcodes;
extern struct mips_opcode *mips_opcodes;
extern int bfd_mips_num_opcodes;
#define NUMOPCODES bfd_mips_num_opcodes
/* The rest of this file adds definitions for the mips16 TinyRISC
processor. */
/* These are the bitmasks and shift counts used for the different
fields in the instruction formats. Other than OP, no masks are
provided for the fixed portions of an instruction, since they are
not needed.
The I format uses IMM11.
The RI format uses RX and IMM8.
The RR format uses RX, and RY.
The RRI format uses RX, RY, and IMM5.
The RRR format uses RX, RY, and RZ.
The RRI_A format uses RX, RY, and IMM4.
The SHIFT format uses RX, RY, and SHAMT.
The I8 format uses IMM8.
The I8_MOVR32 format uses RY and REGR32.
The IR_MOV32R format uses REG32R and MOV32Z.
The I64 format uses IMM8.
The RI64 format uses RY and IMM5.
*/
#define MIPS16OP_MASK_OP 0x1f
#define MIPS16OP_SH_OP 11
#define MIPS16OP_MASK_IMM11 0x7ff
#define MIPS16OP_SH_IMM11 0
#define MIPS16OP_MASK_RX 0x7
#define MIPS16OP_SH_RX 8
#define MIPS16OP_MASK_IMM8 0xff
#define MIPS16OP_SH_IMM8 0
#define MIPS16OP_MASK_RY 0x7
#define MIPS16OP_SH_RY 5
#define MIPS16OP_MASK_IMM5 0x1f
#define MIPS16OP_SH_IMM5 0
#define MIPS16OP_MASK_RZ 0x7
#define MIPS16OP_SH_RZ 2
#define MIPS16OP_MASK_IMM4 0xf
#define MIPS16OP_SH_IMM4 0
#define MIPS16OP_MASK_REGR32 0x1f
#define MIPS16OP_SH_REGR32 0
#define MIPS16OP_MASK_REG32R 0x1f
#define MIPS16OP_SH_REG32R 3
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
#define MIPS16OP_MASK_MOVE32Z 0x7
#define MIPS16OP_SH_MOVE32Z 0
#define MIPS16OP_MASK_IMM6 0x3f
#define MIPS16OP_SH_IMM6 5
/* These are the characters which may appears in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
"y" 3 bit register (MIPS16OP_*_RY)
"x" 3 bit register (MIPS16OP_*_RX)
"z" 3 bit register (MIPS16OP_*_RZ)
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
"0" zero register ($0)
"S" stack pointer ($sp or $29)
"P" program counter
"R" return address register ($ra or $31)
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
The remaining codes may be extended. Except as otherwise noted,
the full extended operand is a 16 bit signed value.
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
"q" 11 bit branch address (MIPS16OP_*_IMM11)
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
*/
/* For the mips16, we use the same opcode table format and a few of
the same flags. However, most of the flags are different. */
/* Modifies the register in MIPS16OP_*_RX. */
#define MIPS16_INSN_WRITE_X 0x00000001
/* Modifies the register in MIPS16OP_*_RY. */
#define MIPS16_INSN_WRITE_Y 0x00000002
/* Modifies the register in MIPS16OP_*_RZ. */
#define MIPS16_INSN_WRITE_Z 0x00000004
/* Modifies the T ($24) register. */
#define MIPS16_INSN_WRITE_T 0x00000008
/* Modifies the SP ($29) register. */
#define MIPS16_INSN_WRITE_SP 0x00000010
/* Modifies the RA ($31) register. */
#define MIPS16_INSN_WRITE_31 0x00000020
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
/* Reads the register in MIPS16OP_*_RX. */
#define MIPS16_INSN_READ_X 0x00000080
/* Reads the register in MIPS16OP_*_RY. */
#define MIPS16_INSN_READ_Y 0x00000100
/* Reads the register in MIPS16OP_*_MOVE32Z. */
#define MIPS16_INSN_READ_Z 0x00000200
/* Reads the T ($24) register. */
#define MIPS16_INSN_READ_T 0x00000400
/* Reads the SP ($29) register. */
#define MIPS16_INSN_READ_SP 0x00000800
/* Reads the RA ($31) register. */
#define MIPS16_INSN_READ_31 0x00001000
/* Reads the program counter. */
#define MIPS16_INSN_READ_PC 0x00002000
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
#define MIPS16_INSN_READ_GPR_X 0x00004000
/* Is a branch insn. */
#define MIPS16_INSN_BRANCH 0x00010000
/* The following flags have the same value for the mips16 opcode
table:
INSN_UNCOND_BRANCH_DELAY
INSN_COND_BRANCH_DELAY
INSN_COND_BRANCH_LIKELY (never used)
INSN_READ_HI
INSN_READ_LO
INSN_WRITE_HI
INSN_WRITE_LO
INSN_TRAP
INSN_ISA3
*/
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
#endif /* _MIPS_H_ */

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contrib/disas/opcode/ia64.h
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@ -1,392 +0,0 @@
/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
See the file HP-COPYRIGHT for additional information. */
#ifndef opcode_ia64_h
#define opcode_ia64_h
/* next two comments by ud3 */
//#include <sys/types.h>
//#include <bfd.h>
typedef u64_t ia64_insn;
enum ia64_insn_type
{
IA64_TYPE_NIL = 0, /* illegal type */
IA64_TYPE_A, /* integer alu (I- or M-unit) */
IA64_TYPE_I, /* non-alu integer (I-unit) */
IA64_TYPE_M, /* memory (M-unit) */
IA64_TYPE_B, /* branch (B-unit) */
IA64_TYPE_F, /* floating-point (F-unit) */
IA64_TYPE_X, /* long encoding (X-unit) */
IA64_TYPE_DYN, /* Dynamic opcode */
IA64_NUM_TYPES
};
enum ia64_unit
{
IA64_UNIT_NIL = 0, /* illegal unit */
IA64_UNIT_I, /* integer unit */
IA64_UNIT_M, /* memory unit */
IA64_UNIT_B, /* branching unit */
IA64_UNIT_F, /* floating-point unit */
IA64_UNIT_L, /* long "unit" */
IA64_UNIT_X, /* may be integer or branch unit */
IA64_NUM_UNITS
};
/* Changes to this enumeration must be propagated to the operand table in
bfd/cpu-ia64-opc.c
*/
enum ia64_opnd
{
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
/* constants */
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
IA64_OPND_C1, /* the constant 1 */
IA64_OPND_C8, /* the constant 8 */
IA64_OPND_C16, /* the constant 16 */
IA64_OPND_GR0, /* gr0 */
IA64_OPND_IP, /* instruction pointer (ip) */
IA64_OPND_PR, /* predicate register (pr) */
IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
IA64_OPND_PSR, /* processor status register (psr) */
IA64_OPND_PSR_L, /* processor status register L (psr.l) */
IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
/* register operands: */
IA64_OPND_AR3, /* third application register # (bits 20-26) */
IA64_OPND_B1, /* branch register # (bits 6-8) */
IA64_OPND_B2, /* branch register # (bits 13-15) */
IA64_OPND_CR3, /* third control register # (bits 20-26) */
IA64_OPND_F1, /* first floating-point register # */
IA64_OPND_F2, /* second floating-point register # */
IA64_OPND_F3, /* third floating-point register # */
IA64_OPND_F4, /* fourth floating-point register # */
IA64_OPND_P1, /* first predicate # */
IA64_OPND_P2, /* second predicate # */
IA64_OPND_R1, /* first register # */
IA64_OPND_R2, /* second register # */
IA64_OPND_R3, /* third register # */
IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
/* indirect operands: */
IA64_OPND_CPUID_R3, /* cpuid[reg] */
IA64_OPND_DBR_R3, /* dbr[reg] */
IA64_OPND_DTR_R3, /* dtr[reg] */
IA64_OPND_ITR_R3, /* itr[reg] */
IA64_OPND_IBR_R3, /* ibr[reg] */
IA64_OPND_MR3, /* memory at addr of third register # */
IA64_OPND_MSR_R3, /* msr[reg] */
IA64_OPND_PKR_R3, /* pkr[reg] */
IA64_OPND_PMC_R3, /* pmc[reg] */
IA64_OPND_PMD_R3, /* pmd[reg] */
IA64_OPND_RR_R3, /* rr[reg] */
/* immediate operands: */
IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
IA64_OPND_SOF, /* 8-bit stack frame size */
IA64_OPND_SOL, /* 8-bit size of locals */
IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
};
enum ia64_dependency_mode
{
IA64_DV_RAW,
IA64_DV_WAW,
IA64_DV_WAR,
};
enum ia64_dependency_semantics
{
IA64_DVS_NONE,
IA64_DVS_IMPLIED,
IA64_DVS_IMPLIEDF,
IA64_DVS_DATA,
IA64_DVS_INSTR,
IA64_DVS_SPECIFIC,
IA64_DVS_STOP,
IA64_DVS_OTHER,
};
enum ia64_resource_specifier
{
IA64_RS_ANY,
IA64_RS_AR_K,
IA64_RS_AR_UNAT,
IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
IA64_RS_ARb, /* 48-63, 112-127 */
IA64_RS_BR,
IA64_RS_CFM,
IA64_RS_CPUID,
IA64_RS_CR_IRR,
IA64_RS_CR_LRR,
IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
IA64_RS_DBR,
IA64_RS_FR,
IA64_RS_FRb,
IA64_RS_GR0,
IA64_RS_GR,
IA64_RS_IBR,
IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
IA64_RS_MSR,
IA64_RS_PKR,
IA64_RS_PMC,
IA64_RS_PMD,
IA64_RS_PR, /* non-rotating, 1-15 */
IA64_RS_PRr, /* rotating, 16-62 */
IA64_RS_PR63,
IA64_RS_RR,
IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
IA64_RS_CRX, /* CRs not in RS_CR */
IA64_RS_PSR, /* PSR bits */
IA64_RS_RSE, /* implementation-specific RSE resources */
IA64_RS_AR_FPSR,
};
enum ia64_rse_resource
{
IA64_RSE_N_STACKED_PHYS,
IA64_RSE_BOF,
IA64_RSE_STORE_REG,
IA64_RSE_LOAD_REG,
IA64_RSE_BSPLOAD,
IA64_RSE_RNATBITINDEX,
IA64_RSE_CFLE,
IA64_RSE_NDIRTY,
};
/* Information about a given resource dependency */
struct ia64_dependency
{
/* Name of the resource */
const char *name;
/* Does this dependency need further specification? */
enum ia64_resource_specifier specifier;
/* Mode of dependency */
enum ia64_dependency_mode mode;
/* Dependency semantics */
enum ia64_dependency_semantics semantics;
/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
#define REG_NONE (-1)
int regindex;
/* Special info on semantics */
const char *info;
};
/* Two arrays of indexes into the ia64_dependency table.
chks are dependencies to check for conflicts when an opcode is
encountered; regs are dependencies to register (mark as used) when an
opcode is used. chks correspond to readers (RAW) or writers (WAW or
WAR) of a resource, while regs correspond to writers (RAW or WAW) and
readers (WAR) of a resource. */
struct ia64_opcode_dependency
{
int nchks;
const unsigned short *chks;
int nregs;
const unsigned short *regs;
};
/* encode/extract the note/index for a dependency */
#define RDEP(N,X) (((N)<<11)|(X))
#define NOTE(X) (((X)>>11)&0x1F)
#define DEP(X) ((X)&0x7FF)
/* A template descriptor describes the execution units that are active
for each of the three slots. It also specifies the location of
instruction group boundaries that may be present between two slots. */
struct ia64_templ_desc
{
int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
enum ia64_unit exec_unit[3];
const char *name;
};
/* The opcode table is an array of struct ia64_opcode. */
struct ia64_opcode
{
/* The opcode name. */
const char *name;
/* The type of the instruction: */
enum ia64_insn_type type;
/* Number of output operands: */
int num_outputs;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
ia64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
ia64_insn mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum ia64_opnd operands[5];
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. The defined values are listed below. */
unsigned int flags;
/* Used by ia64_find_next_opcode (). */
short ent_index;
/* Opcode dependencies. */
const struct ia64_opcode_dependency *dependencies;
};
/* Values defined for the flags field of a struct ia64_opcode. */
#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
/* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf)
enum ia64_operand_class
{
IA64_OPND_CLASS_CST, /* constant */
IA64_OPND_CLASS_REG, /* register */
IA64_OPND_CLASS_IND, /* indirect register */
IA64_OPND_CLASS_ABS, /* absolute value */
IA64_OPND_CLASS_REL, /* IP-relative value */
};
/* The operands table is an array of struct ia64_operand. */
struct ia64_operand
{
enum ia64_operand_class class;
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
modified and the returned string describes the cause of the
error. If no error occurs, NULL is returned. */
const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code);
/* Extract the operand bits for an operand of type SELF from
instruction CODE store them in *VALUE. If an error occurs, the
cause of the error is described by the string returned. If no
error occurs, NULL is returned. */
const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
ia64_insn *value);
/* A string whose meaning depends on the operand class. */
const char *str;
struct bit_field
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
}
field[4]; /* no operand has more than this many bit-fields */
unsigned int flags;
const char *desc; /* brief description */
};
/* Values defined for the flags field of a struct ia64_operand. */
/* Disassemble as signed decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
/* Disassemble as unsigned decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
extern const struct ia64_templ_desc ia64_templ_desc[16];
/* The tables are sorted by major opcode number and are otherwise in
the order in which the disassembler should consider instructions. */
extern struct ia64_opcode ia64_opcodes_a[];
extern struct ia64_opcode ia64_opcodes_i[];
extern struct ia64_opcode ia64_opcodes_m[];
extern struct ia64_opcode ia64_opcodes_b[];
extern struct ia64_opcode ia64_opcodes_f[];
extern struct ia64_opcode ia64_opcodes_d[];
extern struct ia64_opcode *ia64_find_opcode (const char *name);
extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
enum ia64_insn_type type);
extern void ia64_free_opcode (struct ia64_opcode *ent);
extern const struct ia64_dependency *ia64_find_dependency (int index);
/* To avoid circular library dependencies, this array is implemented
in bfd/cpu-ia64-opc.c: */
extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
#endif /* opcode_ia64_h */

38
kernel/Mk/Makeconf.alpha
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@ -1,38 +0,0 @@
################ -*- mode: Makefile; -*- #############################
##
## Copyright (C) 2004, Karlsruhe University
##
## File path: Makeconf.alpha
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.alpha,v 1.2 2004/08/25 06:45:47 awiggins Exp $
##
######################################################################
LDFLAGS_alpha +=
CFLAGS_alpha += -O2 -mno-fp-regs -freg-struct-return
CFLAGS_a21264 += -mcpu=ev6
ASMFLAGS_a21264 += -mcpu=ev6 -Wa,-m21264
CFLAGS_a21164 += -mcpu=ev5
CFLAGS_a21164a += -mcpu=ev56
CFLAGS_a21064 += -mcpu=ev4

50
kernel/Mk/Makeconf.arm
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@ -1,50 +0,0 @@
################ -*- mode: Makefile; -*- #############################
##
## Copyright (C) 2004, Karlsruhe University
##
## File path: Makeconf.arm
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.arm,v 1.8 2004/12/02 22:02:16 cvansch Exp $
##
######################################################################
CFLAGS_arm += -O2 -finline-limit=999999999
ASMFLAGS_arm +=
LDFLAGS_arm +=
CFLAGS_sa1100 += -march=armv4 -mtune=strongarm1100
ASMFLAGS_sa1100 += -march=armv4 -mtune=strongarm1100
CFLAGS_xscale += -march=armv5 -mtune=xscale
ASMFLAGS_xscale += -march=armv5 -mtune=xscale
CFLAGS_omap1510 += -march=armv4 -mtune=arm9tdmi -mshort-load-bytes
CFLAGS_cs337 += -march=armv4 -mtune=arm9tdmi -mshort-load-bytes
CFLAGS_ixdp425 += -mbig-endian
ASMFLAGS_ixdp425 += -mbig-endian
ifeq ($(PLATFORM),ixdp425)
LDFLAGS_arm += -EB
VFLAGS += -EB
endif

36
kernel/Mk/Makeconf.ia64
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@ -1,36 +0,0 @@
################ -*- mode: Makefile; -*- #############################
##
## Copyright (C) 2004, Karlsruhe University
##
## File path: Makeconf.ia64
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.ia64,v 1.1 2004/05/25 19:21:51 skoglund Exp $
##
######################################################################
CFLAGS_ia64+= -O2 -freg-struct-return -mconstant-gp -finline-limit=999999
ASMFLAGS_ia64+= -mconstant-gp
# eSk says: CML2 is complete and utter crap. There is no way to
# unconditionally set a simple variable.
DEFINES_ia64+= CONFIG_IA64_PHYSMEM_OFFSET=0x100000000

42
kernel/Mk/Makeconf.mips32
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@ -1,42 +0,0 @@
######################################################################
##
## Copyright (C) 2006, Karlsruhe University
##
## File path: Mk/Makeconf.mips32
## Description: MIPS32 make settings
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.mips32,v 1.1 2006/02/23 21:07:37 ud3 Exp $
##
######################################################################
CFLAGS_mips32 += -mips32 -ggdb -Wall -fno-builtin -fno-pic -mno-abicalls -O2
TOOLPREFIX=mipsel-unknown-linux-gnu-
LDFLAGS_mips32 += -nostdlib -mips32
#LDFLAGS_mips32 += -T/home/thomas/mips32/pistachio/kernel/src/platform/malta/linker.lds # XXX
#VFLAGS += -EL
ASMFLAGS_mips32 += -mips32 -fno-pic

69
kernel/Mk/Makeconf.mips64
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@ -1,69 +0,0 @@
################ -*- mode: Makefile; -*- #############################
##
## Copyright (C) 2004, Karlsruhe University
##
## File path: Makeconf.mips64
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.mips64,v 1.2 2004/12/02 00:16:10 cvansch Exp $
##
######################################################################
CFLAGS_mips64 += -O3 -G 0 -mlong64 -mno-abicalls -non_shared -msplit-addresses
# Mips64 Compile Note: cvansch - UNSW
# GNU GCC/Binutils are broken for anything but ABI=o64
# We support the ABI=64 calling convention
# GCC is not broken for ABI=64 however GAS and LD are.
# Temporary solution is to let GCC generate ABI=64 code
# and pass ABI=o64 to the assembler.
# This works consistantly with diferent GCC/binutils
# versions and has a side effect of producing optimised
# address calculation.
ifeq ($(PLATFORM),erpcn01)
LDFLAGS_mips64 += -EL
VFLAGS += -EL
CFLAGS_rc64574 += -EL -march=r5000 -mabi=64 -Wa,-mabi=o64
ASMFLAGS_mips64 += $(CFLAGS_mips64) $(CFLAGS_rc64574)
endif
ifeq ($(PLATFORM),u4600)
LDFLAGS_mips64 += -EB
VFLAGS += -EB
CFLAGS_r4x00 += -EB -march=r4000 -mabi=64 -Wa,-mabi=o64
ASMFLAGS_mips64 += $(CFLAGS_mips64) $(CFLAGS_r4x00)
endif
ifeq ($(PLATFORM),sb1)
LDFLAGS_mips64 += -EB
VFLAGS += -EB
CFLAGS_sb1 += -EB -march=sb1 -mabi=64 -Wa,-mabi=o64
ASMFLAGS_mips64 += $(CFLAGS_mips64) $(CFLAGS_sb1)
endif
ifeq ($(PLATFORM),vr41xx)
LDFLAGS_mips64 += -EL
VFLAGS += -EL
CFLAGS_vr41xx += -EL -march=vr4100 -mabi=64 -Wa,-mabi=o64
ASMFLAGS_mips64 += $(CFLAGS_mips64) $(CFLAGS_vr41xx)
endif

34
kernel/Mk/Makeconf.sparc64
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@ -1,34 +0,0 @@
################ -*- mode: Makefile; -*- #############################
##
## Copyright (C) 2004, Karlsruhe University
##
## File path: Makeconf.sparc64
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf.sparc64,v 1.3 2004/07/01 04:06:50 philipd Exp $
##
######################################################################
CFLAGS_sparc64 += -O3 -mcmodel=medany
CFLAGS_ultrasparc += -mcpu=ultrasparc
LDFLAGS_sparc64 += -N

4
kernel/config/Makefile
View File

@ -36,12 +36,8 @@ CMLCONFIG= $(CMLPATH)/cmlconfigure.py
CMLCONFIGTRANS= $(CMLPATH)/configtrans.py
CML_INPUT= $(addprefix $(SRCDIR)/config/, rules.cml \
alpha.cml \
amd64.cml \
arm.cml \
ia32.cml \
ia64.cml \
mips64.cml \
powerpc.cml \
powerpc64.cml \
)

111
kernel/config/alpha.cml
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@ -1,111 +0,0 @@
######################################################################
#
# Copyright (C) 1999, 2000, 2001, Karlsruhe University
#
# File path: config/alpha.cml
# Description: rules for Pistachio's Alpha CML2 configuration system
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $Id: alpha.cml,v 1.16 2004/08/25 06:52:31 awiggins Exp $
#
######################################################################
symbols
ARCH_ALPHA 'Alpha'
alpha_type 'System Type'
CPU_ALPHA_A21264 '21264'
# Whate about the different variations (21164A etc.)
CPU_ALPHA_A21164 '21164'
CPU_ALPHA_A21164A '21164A'
CPU_ALPHA_A21064 '21064'
alpha_platform 'Platform'
PLAT_MULTIA 'Multia'
PLAT_MIATA 'Miata'
PLAT_TSUNAMI 'Tsunami'
# PLAT_SRM 'Generic'
NO_CLOCK_IN_INT 'Ignore timer interrupts that occur in interrupts'
ALPHA_PAL_IPC_FASTPATH 'Enable PAL mode IPC fastpath' text
This enables an IPC fast which operates purely in PAL mode. To do
so it needs to copy over memory usually reserved for the SRM console
software. This has been tested on 21264 however if problems exist
disable it and report a bug.
.
ALPHA_ADDRESS_BITS 'Size of the Virtual Address Space'
ALPHA_CONSOLE_RESERVE 'Address at which to load kernel'
USER_LOAD_PHYS 'User load address is a physical address'
choices alpha_type
CPU_ALPHA_A21064
CPU_ALPHA_A21164
CPU_ALPHA_A21164A
CPU_ALPHA_A21264
default CPU_ALPHA_A21164
unless ARCH_ALPHA suppress dependent alpha_type
choices alpha_platform
PLAT_MIATA
PLAT_MULTIA
PLAT_TSUNAMI
default PLAT_MIATA
unless ARCH_ALPHA suppress dependent alpha_platform
unless n suppress PLAT_MULTIA
#derive CPU_ALPHA_A21264 from PLAT_TSUNAMI
#derive CPU_ALPHA_A21164 from PLAT_MIATA
#derive CPU_ALPHA_A21064 from PLAT_MULTIA
derive SWIZZLE_IO_ADDR from PLAT_TSUNAMI and ALPHA_ADDRESS_BITS == 43
menu hardware_misc
ALPHA_ADDRESS_BITS%
ALPHA_CONSOLE_RESERVE@
USER_LOAD_PHYS
default ALPHA_ADDRESS_BITS from 43 range 43 48
default ALPHA_CONSOLE_RESERVE from 0x810000
default USER_LOAD_PHYS from n
unless ARCH_ALPHA suppress ALPHA_ADDRESS_BITS ALPHA_CONSOLE_RESERVE USER_LOAD_PHYS
menu kernel
NO_CLOCK_IN_INT
ALPHA_PAL_IPC_FASTPATH
unless ARCH_ALPHA suppress NO_CLOCK_IN_INT
# awiggins (2004-07-21) Disabled until it is fixed up and tested again.
unless n suppress ALPHA_PAL_IPC_FASTPATH
unless ARCH_ALPHA suppress ALPHA_PAL_IPC_FASTPATH
unless PLAT_TSUNAMI suppress ALPHA_PAL_IPC_FASTPATH
default NO_CLOCK_IN_INT from y
default ALPHA_PAL_IPC_FASTPATH from n
# HACK
derive ALPHA_FASTPATH from IPC_FASTPATH

107
kernel/config/arm.cml
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@ -1,107 +0,0 @@
######################################################################
#
# Copyright (C) 1999, 2000, 2001, Karlsruhe University
#
# File path: config/arm.cml
# Description: rules for Pistachio's ARM CML2 configuration system
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $Id: arm.cml,v 1.6 2004/12/02 21:55:06 cvansch Exp $
#
######################################################################
symbols
ARCH_ARM 'ARM'
arm_type 'Processor Type'
CPU_ARM_SA1100 'StrongARM SA-1100'
CPU_ARM_XSCALE 'Intel XScale'
#CPU_ARM_ARM926 'ARM 926-EJS'
CPU_ARM_ARM920T 'ARM 920T'
CPU_ARM_OMAP1510 'TI OMAP1510 ARM925T'
arm_platform 'Platform'
PLAT_PLEB 'PLEB'
PLAT_PLEB2 'PLEB2 PXA255'
#PLAT_INTEGRATOR 'Integrator'
#PLAT_NOMADIK 'Nomadik'
PLAT_IXDP425 'Intel IXDP425'
PLAT_INNOVATOR 'OMAP1510 Innovator'
PLAT_CSB337 'Cogent CSB337 AT91RM9200(ARM920T)'
#nomadik_subplatform 'Nomadik platform'
#SUBPLAT_NOMADIK_MEK0 'MEVK0'
#SUBPLAT_NOMADIK_MEK1 'MEVK1'
#SUBPLAT_NOMADIK_MEK2 'MEVK2'
#SUBPLAT_NOMADIK_MEK3 'MEVK3'
#SUBPLAT_NOMADIK_MEVKLITE 'MUPOC Lite'
#SUBPLAT_NOMADIK_MEVKFULL 'MUPOC Full'
ENABLE_FASS 'Whether or not to enable Fast Addresss Space Switching'
choices arm_type
CPU_ARM_SA1100
CPU_ARM_XSCALE
# CPU_ARM_ARM926
CPU_ARM_ARM920T
CPU_ARM_OMAP1510
default CPU_ARM_SA1100
unless ARCH_ARM suppress dependent arm_type
choices arm_platform
PLAT_PLEB
PLAT_PLEB2
# PLAT_INTEGRATOR
# PLAT_NOMADIK
PLAT_IXDP425
PLAT_INNOVATOR
PLAT_CSB337
default PLAT_PLEB
unless ARCH_ARM suppress dependent arm_platform
unless CPU_ARM_SA1100 suppress dependent PLAT_PLEB
unless CPU_ARM_XSCALE suppress dependent PLAT_PLEB2 PLAT_IXDP425
unless CPU_ARM_ARM920T suppress dependent PLAT_CSB337
unless CPU_ARM_OMAP1510 suppress dependent PLAT_INNOVATOR
derive ARM_BIG_ENDIAN from PLAT_IXDP425
#choices nomadik_subplatform
# SUBPLAT_NOMADIK_MEK0
# SUBPLAT_NOMADIK_MEK1
# SUBPLAT_NOMADIK_MEK2
# SUBPLAT_NOMADIK_MEK3
# SUBPLAT_NOMADIK_MEVKLITE
# SUBPLAT_NOMADIK_MEVKFULL
# default SUBPLAT_NOMADIK_MEK0
#unless PLAT_NOMADIK suppress dependent nomadik_subplatform
menu hardware_misc
# nomadik_subplatform
ENABLE_FASS
unless ARCH_ARM suppress ENABLE_FASS

93
kernel/config/ia64.cml
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@ -1,93 +0,0 @@
######################################################################
##
## Copyright (C) 2003, Karlsruhe University
##
## File path: config/ia64.cml
## Description: Rules for Pistachio's ia64 configuration system
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: ia64.cml,v 1.8 2004/02/24 01:46:46 cvansch Exp $
##
######################################################################
symbols
ARCH_IA64 'IA-64'
ia64_type 'IA-64 Processor Type'
CPU_IA64_ITANIUM 'Itanium Processor'
CPU_IA64_ITANIUM2 'Itanium2 Processor'
CPU_IA64_SKI 'HP Simulator'
ia64_platform 'IA-64 Platform'
PLAT_EFI 'Extensible Firmware Interface (EFI)'
KDB_CONS_SKI 'SKI (HP IA64 emulator)'
PROFILE_INTERVAL 'Number of intructions between samples'
PROFILE_SIZE 'Number of entries in profile hash-table' text
The size of the profiling hash-table must be large enough such that there
is a very low percentage of instructions in both kernel and the user
application whose virtual address hashes to the same hash bucket.
.
#
# The IA-64 CPU menu
#
choices ia64_type
CPU_IA64_ITANIUM
CPU_IA64_ITANIUM2
CPU_IA64_SKI
default CPU_IA64_ITANIUM
unless ARCH_IA64 suppress ia64_type
#
# The IA-64 platform menu
#
choices ia64_platform
PLAT_EFI
default PLAT_EFI
unless ARCH_IA64 suppress ia64_platform
#
# Setting for the HP SKI emulator.
#
unless CPU_IA64_SKI suppress dependent KDB_CONS_SKI
when CPU_IA64_SKI suppress KDB_CONS_COM KDB_CONS_KBD
require CPU_IA64_SKI implies SMP==n and KDB_CONS_SKI==y
#
# IA-64 requires an I/O SAPIC
#
require ARCH_IA64 implies IOAPIC==y
#
# IA-64 profiling
default PROFILE_INTERVAL from 10000
default PROFILE_SIZE from 393241
unless ARCH_IA64 suppress PROFILE_INTERVAL PROFILE_SIZE

54
kernel/config/mips32.cml
View File

@ -1,54 +0,0 @@
######################################################################
##
## Copyright (C) 2006, Karlsruhe University
##
## File path: config/mips32.cml
## Description: MIPS32 rules for CML2 configuration system
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: mips32.cml,v 1.1 2006/02/23 21:07:38 ud3 Exp $
##
######################################################################
symbols
ARCH_MIPS32 'MIPS-32'
mips32_type 'Processor Type'
CPU_MIPS32_m4kc "MIPS 4kc"
mips32_platform 'Platform'
PLAT_MALTA "MIPS MALTA"
choices mips32_type
CPU_MIPS32_m4kc
default CPU_MIPS32_m4kc
unless ARCH_MIPS32 suppress dependent mips32_type
choices mips32_platform
PLAT_MALTA
default PLAT_MALTA
unless ARCH_MIPS32 suppress dependent mips32_platform

94
kernel/config/mips64.cml
View File

@ -1,94 +0,0 @@
######################################################################
#
# Copyright (C) 1999, 2000, 2001, Karlsruhe University
#
# File path: config/mips64.cml
# Description: rules for Pistachio's mips64 CML2 configuration system
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $Id: mips64.cml,v 1.12 2003/11/17 05:46:00 cvansch Exp $
#
######################################################################
symbols
ARCH_MIPS64 'MIPS-64'
mips64_type 'Processor Type'
CPU_MIPS64_R4X00 "MIPS-64 R4X00"
CPU_MIPS64_RC64574 "IDT MIPS-64 R5000 (RC64T574)"
CPU_MIPS64_SB1 "MIPS-64 Sibyte SB1 core"
CPU_MIPS64_VR4121 "MIPS-64 NEC vr4121"
CPU_MIPS64_VR4181 "MIPS-64 NEC vr4181"
CPU_CLOCK_SPEED "CPU Frequency (kHz)"
mips64_platform 'Platform'
PLAT_ERPCN01 "OpenFuel ERPCN01"
PLAT_U4600 "U4600"
PLAT_SB1 "Sibyte"
PLAT_VR41XX "vr41xx"
MIPS64_LITTLE_ENDIAN 'Enable MIPS64 LITTLE ENDIAN mode'
SB1_PASS1_WORKAROUNDS 'Enable SB1 Sibyte MIPS core pass 1 work arounds?' text
If you enable this option, you may also need to use a version of binutils/gcc
that also builds code with the appropriate work arounds.
Answer yes to this option to enable the pass 1 work arounds.
.
choices mips64_type
CPU_MIPS64_R4X00
CPU_MIPS64_RC64574
CPU_MIPS64_SB1
CPU_MIPS64_VR4121
CPU_MIPS64_VR4181
default CPU_MIPS64_R4X00
unless ARCH_MIPS64 suppress dependent mips64_type
choices mips64_platform
PLAT_ERPCN01
PLAT_U4600
PLAT_SB1
PLAT_VR41XX
default PLAT_U4600
unless ARCH_MIPS64 suppress dependent mips64_platform
menu hardware_misc
MIPS64_LITTLE_ENDIAN
CPU_CLOCK_SPEED%
SB1_PASS1_WORKAROUNDS
default MIPS64_LITTLE_ENDIAN from n
default CPU_CLOCK_SPEED from 100000
default SB1_PASS1_WORKAROUNDS from n
unless ARCH_MIPS64 suppress MIPS64_LITTLE_ENDIAN
unless ARCH_MIPS64 suppress CPU_CLOCK_SPEED
unless CPU_MIPS64_SB1 suppress SB1_PASS1_WORKAROUNDS
require PLAT_ERPCN01 implies MIPS64_LITTLE_ENDIAN==y
require PLAT_VR41XX implies MIPS64_LITTLE_ENDIAN==y

64
kernel/config/rules.cml
View File

@ -62,14 +62,10 @@ SMP 'Multiprocessor Support'
SMP_MAX_PROCS 'Maximum number of CPUs'
SMP_IDLE_POLL 'Poll XCPU queue on idle'
UNCACHED 'Run CPU uncached'
IOAPIC 'Use APIC+IOAPIC'
MAX_IOAPICS 'Maximum number of supported IO APICs'
APIC_TIMER_TICK 'Timer tick length for APIC'
MAX_NUM_ASIDS 'The maximum number of ASIDs'
PREEMPT_ASIDS 'Whether or not to pre-empt ASIDs'
BOOTMEM_PAGES 'The number of pages to reserve for the kernel' text
The kernel reserves an ammount of physical memory to use for kernel
@ -231,39 +227,21 @@ hardware_misc 'Miscellaneous'
menu hardware
arch
ia32_type
ia64_type
alpha_type
mips64_type
mips32_type
arm_type
powerpc_type
amd64_type
x86_platform
ia64_platform
alpha_platform
mips64_platform
mips32_platform
arm_platform
powerpc_platform
powerpc64_platform
powerpc64_type
sparc64_platform
SMP { SMP_MAX_PROCS% SMP_IDLE_POLL}
UNCACHED
hardware_misc
choices arch # Basic architecture
ARCH_IA32
ARCH_IA64
ARCH_POWERPC
ARCH_POWERPC64
ARCH_AMD64
ARCH_ALPHA
ARCH_MIPS64
ARCH_MIPS32
ARCH_ARM
ARCH_SPARC64
default ARCH_IA32
choices powerpc_type
@ -279,8 +257,7 @@ choices amd64_type
unless ARCH_POWERPC suppress dependent powerpc_type
unless ARCH_AMD64 suppress dependent amd64_type
unless ARCH_IA64 or ARCH_IA32 or ARCH_POWERPC or CPU_MIPS64_SB1 or ARCH_AMD64 suppress dependent SMP
unless ARCH_MIPS64 suppress dependent UNCACHED
unless ARCH_IA32 or ARCH_POWERPC or ARCH_AMD64 suppress dependent SMP
unless ARCH_IA32 and SMP suppress dependent SMP_IDLE_POLL
@ -288,36 +265,27 @@ choices powerpc_platform
PLAT_OFPPC
default PLAT_OFPPC
unless ARCH_POWERPC suppress dependent powerpc_platform
choices x86_platform
PLAT_PC99
default PLAT_PC99
unless ARCH_IA32 or ARCH_AMD64 suppress dependent x86_platform
menu hardware_misc
IOAPIC { MAX_IOAPICS% APIC_TIMER_TICK% }
PPC_EXPOSE_OPIC
MAX_NUM_ASIDS%
PREEMPT_ASIDS
BOOTMEM_PAGES%
PROFILE_INTERVAL%
PROFILE_SIZE%
CPU_AMD64_SIMICS_SPEED%
default MAX_IOAPICS from 2
default APIC_TIMER_TICK from 1000
default PPC_EXPOSE_OPIC from n
unless ARCH_POWERPC suppress PPC_EXPOSE_OPIC
when ARCH_POWERPC or ARCH_ALPHA or ARCH_MIPS64 or ARCH_ARM or ARCH_POWERPC64 or ARCH_SPARC64 suppress IOAPIC
default MAX_NUM_ASIDS from 256
default PREEMPT_ASIDS from n
when ARCH_POWERPC or ARCH_POWERPC64 suppress IOAPIC
default BOOTMEM_PAGES from 1024
unless ARCH_MIPS64 or ARCH_ALPHA or ARCH_SPARC64 suppress MAX_NUM_ASIDS PREEMPT_ASIDS
unless ARCH_MIPS64 or ARCH_ALPHA or ARCH_SPARC64 or ARCH_POWERPC64 or ARCH_ARM suppress BOOTMEM_PAGES
unless ARCH_POWERPC64 suppress BOOTMEM_PAGES
default SMP_MAX_PROCS from 4
default CPU_AMD64_SIMICS_SPEED from 100
unless CPU_AMD64_SIMICS suppress CPU_AMD64_SIMICS_SPEED
@ -351,9 +319,9 @@ default NEW_MDB from n
unless EXPERIMENTAL suppress dependent experimental
unless ARCH_POWERPC suppress PPC_BAT_SYSCALLS
unless ARCH_POWERPC64 suppress PPC64_TRASH_OF
unless CPU_IA32_I686 or CPU_IA32_P4 or CPU_IA32_K8 or ARCH_IA64 or ARCH_AMD64 suppress dependent PERFMON
unless ARCH_IA64 or ARCH_POWERPC or ARCH_IA32 or ARCH_ALPHA or ARCH_MIPS64 or ARCH_AMD64 or ARCH_ARM suppress IPC_FASTPATH
unless ARCH_ALPHA or ARCH_AMD64 or ARCH_IA32 or ARCH_IA64 or ARCH_SPARC64 suppress SPIN_WHEELS
unless CPU_IA32_I686 or CPU_IA32_P4 or CPU_IA32_K8 or ARCH_AMD64 suppress dependent PERFMON
unless ARCH_POWERPC or ARCH_IA32 or ARCH_AMD64 suppress IPC_FASTPATH
unless ARCH_AMD64 or ARCH_IA32 suppress SPIN_WHEELS
unless ARCH_IA32 or ARCH_AMD64 suppress NEW_MDB
default K8_FLUSHFILTER from n
unless CPU_AMD64_K8 or CPU_IA32_K8 suppress dependent K8_FLUSHFILTER
@ -387,14 +355,12 @@ when ARCH_POWERPC64 suppress KDB_COMPORT KDB_COMSPEED
unless ARCH_POWERPC suppress ppc_debug_consoles
unless ARCH_POWERPC64 suppress ppc64_debug_consoles
when ARCH_POWERPC64 suppress KDB_CONS_PSIM_COM
when ARCH_MIPS64 or ARCH_ALPHA or ARCH_ARM or ARCH_SPARC64 suppress kdb_console KDB_COMPORT KDB_COMSPEED
when ARCH_ALPHA or ARCH_ARM or ARCH_SPARC64 suppress KDB_DISAS
default KDB_BREAKIN_ESCAPE from y
default KDB_BREAKIN_BREAK from y
unless PLAT_PC99 and KDB_BREAKIN and KDB_CONS_COM suppress dependent KDB_BREAKIN_BREAK KDB_BREAKIN_ESCAPE
choices kdb_console
KDB_CONS_KBD KDB_CONS_COM KDB_CONS_SKI
KDB_CONS_KBD KDB_CONS_COM
default KDB_CONS_COM
menu trace
@ -430,14 +396,12 @@ menu main # Configure the Pistachio kernel
derive IS_32BIT from ARCH_IA32 or ARCH_POWERPC or ARCH_ARM or ARCH_MIPS32
derive IS_64BIT from ARCH_IA64 or ARCH_ALPHA or ARCH_MIPS64 or ARCH_AMD64 or ARCH_POWERPC64 or ARCH_SPARC64
derive BIGENDIAN from ARCH_POWERPC or ARCH_MIPS64 or ARCH_POWERPC64 or ARCH_SPARC64 or ARM_BIG_ENDIAN
when MIPS64_LITTLE_ENDIAN suppress BIGENDIAN
derive IS_32BIT from ARCH_IA32 or ARCH_POWERPC
derive IS_64BIT from ARCH_AMD64 or ARCH_POWERPC64
derive BIGENDIAN from ARCH_POWERPC or ARCH_POWERPC64
derive CPU_K8 from CPU_AMD64_K8 or CPU_IA32_K8
derive CPU_AMD64_EM64T from CPU_AMD64_P4
derive ACPI from ARCH_IA64
derive HAVE_MEMORY_CONTROL from ARCH_POWERPC64 or ARCH_MIPS64 or ARCH_ARM or ARCH_IA64
derive HAVE_MEMORY_CONTROL from ARCH_POWERPC64
require IO_FLEXPAGES implies IA32_SMALL_SPACES==n
require IA32_SMALL_SPACES implies IO_FLEXPAGES==n
derive FLUSHFILTER from CPU_K8 and K8_FLUSHFILTER
@ -446,13 +410,7 @@ derive MULTI_ARCHITECTURE from ARCH_AMD64 and AMD64_COMPATIBILITY_MODE
source "powerpc.cml"
source "powerpc64.cml"
source "ia32.cml"
source "ia64.cml"
source "amd64.cml"
source "alpha.cml"
source "mips64.cml"
source "mips32.cml"
source "arm.cml"
source "sparc64.cml"
#
# here comes the real stuff

70
kernel/config/sparc64.cml
View File

@ -1,70 +0,0 @@
######################################################################
#
# Copyright (C) 2003, University of New South Wales
#
# File path: config/sparc64.cml
# Description: Rules for Pistachio's SPARC v9 CML2 configuration system
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $Id: sparc64.cml,v 1.4 2004/06/28 07:10:42 philipd Exp $
#
######################################################################
symbols
ARCH_SPARC64 'SPARC v9'
# Platform range
sparc64_platform 'Platform'
SPARC64_ULTRA1 'Sun Ultra 1 workstation'
SPARC64_ULTRA10 'Sun Ultra 10 workstation'
SPARC64_SUNFIRE 'Sun Enterprise 3500-6500 server'
choices sparc64_platform
SPARC64_ULTRA1
SPARC64_ULTRA10
SPARC64_SUNFIRE
default SPARC64_ULTRA10
unless ARCH_SPARC64 suppress dependent sparc64_platform
# OpenBoot (Open Firmware std) platforms
derive PLAT_OFSPARC64 from SPARC64_ULTRA1 or SPARC64_ULTRA10 or SPARC64_SUNFIRE
# UltraSPARC CPUs
derive SPARC64_ULTRASPARC2 from SPARC64_ULTRA10 or SPARC64_SUNFIRE
derive SPARC64_ULTRASPARC1 from SPARC64_ULTRA1
derive SPARC64_ULTRASPARC2I from SPARC64_ULTRA10
# CPU types
derive CPU_SPARC64_ULTRASPARC from SPARC64_ULTRASPARC1 or SPARC64_ULTRASPARC2 # or SPARC64_ULTRASPARC3
# Serial port types
derive SPARC64_SAB82532 from SPARC64_ULTRA10
derive SPARC64_Z8530 from SPARC64_SUNFIRE

2
kernel/kdb/arch/alpha/Makeconf
View File

@ -1,2 +0,0 @@
SOURCES += ${addprefix kdb/arch/alpha/, console.cc dispatch.S prepost.cc alpha.cc user.cc}

104
kernel/kdb/arch/alpha/alpha.cc
View File

@ -1,104 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002-2004, University of New South Wales
*
* File path: pistachio/cvs/kernel/kdb/arch/alpha/alpha.cc
* Description: Alpha specific debug functionality
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: alpha.cc,v 1.4 2004/06/02 08:41:41 sgoetz Exp $
*
********************************************************************/
#include <debug.h>
#include <linear_ptab.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(palcalls.h)
#include INC_API(config.h)
#include INC_API(space.h)
#include INC_ARCH(pgent.h)
#include INC_GLUE(intctrl.h)
#include INC_API(tcb.h)
DECLARE_CMD (cmd_halt, root, 'h', "halt", "halt system");
CMD(cmd_halt, cg)
{
PAL::halt();
return CMD_NOQUIT;
}
DECLARE_CMD (cmd_irq, arch, 'i', "irq", "Display IRQ status");
CMD(cmd_irq, cg)
{
get_interrupt_ctrl()->print_status();
return CMD_NOQUIT;
}
DECLARE_CMD (cmd_frame, arch, 'f', "frame", "Display user exception frame");
static void SECTION(SEC_KDEBUG) dump_frame(tcb_t *tcb)
{
alpha_context_t *ctx = get_alpha_context(tcb);
printf("=== ID: %t =======================\n", tcb);
printf(" PS: %p PC: %p GP: %p\n", ctx->ps, ctx->pc, ctx->gp);
printf(" a0: %p a1: %p a2: %p\n", ctx->a0, ctx->a1, ctx->a2);
}
extern tcb_t *kdb_get_tcb();
CMD(cmd_frame, cg)
{
tcb_t * tcb = kdb_get_tcb();
if (tcb)
dump_frame(tcb);
return CMD_NOQUIT;
}
DECLARE_CMD (cmd_pcb, arch, 'p', "pcb", "Display a thread's pcb.");
static void SECTION(SEC_KDEBUG) dump_pcb(tcb_t *tcb)
{
alpha_pcb_t *pcb = &tcb->get_arch()->pcb;
printf("=== ID: %p =======================\n", tcb);
printf(" KSP: %p USP : %p PTBR : %p\n", pcb->ksp, pcb->usp, pcb->ptbr);
printf(" ASN: %d Cycles: %d Unique: %p\n", pcb->asn, pcb->pcc, pcb->unique);
printf(" Flags: FP %s, PM %s\n", (pcb->flags & 0x1) ? "enabled" : "disabled", (pcb->flags & 0x1ull << 62) ? "enabled" : "disabled");
}
CMD(cmd_pcb, cg)
{
tcb_t * tcb = kdb_get_tcb();
if (tcb)
dump_pcb(tcb);
return CMD_NOQUIT;
}

204
kernel/kdb/arch/alpha/console.cc
View File

@ -1,204 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002-2004, University of New South Wales
*
* File path: kdb/arch/alpha/console.cc
* Description: Console routine for Alpha systems
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: console.cc,v 1.12 2004/03/17 19:13:23 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/cmd.h>
#include <kdb/console.h>
#include INC_ARCH(hwrpb.h)
#include INC_ARCH(console.h)
#include INC_ARCH(palcalls.h)
#include INC_GLUE(config.h)
static unsigned long cons_dev;
unsigned long hwrpb_vaddr = HWRPB_VADDR;
/* Takes a varied number of args */
extern "C" unsigned long dispatch(word_t a0, word_t a1, word_t a2, word_t a3, struct hwrpb *hwrpb);
static struct hwrpb *hwrpb_to_use = NULL;
extern void halt(void);
void halt(void)
{
PAL::halt();
}
/* we use this so that we can do without the ctype library */
#define is_digit(c) ((c) >= '0' && (c) <= '9')
#define is_xdigit(c) \
(is_digit(c) || ((c) >= 'A' && (c) <= 'F') || ((c) >= 'a' && (c) <= 'f'))
#define is_lower(c) (((c) >= 'a') && ((c) <= 'z'))
#define to_upper(c) ((c) + 'a' - 'A')
unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base)
{
unsigned long result = 0, value;
if (!base) {
base = 10;
if (*cp == '0') {
base = 8;
cp++;
if ((*cp == 'x') && is_xdigit(cp[1])) {
cp++;
base = 16;
}
}
}
while (is_xdigit(*cp)
&& (value =
(is_digit(*cp)
? *cp - '0' : ((is_lower(*cp)
? to_upper(*cp) : *cp) - 'A' + 10)))
< base)
{
result = result*base + value;
cp++;
}
if (endp)
*endp = (char *)cp;
return result;
}
static long cons_puts(const char *str, long len)
{
long remaining, written;
union ccb_stsdef {
long int l_sts;
struct {
int written;
unsigned discard : 29;
unsigned v_sts0 : 1;
unsigned v_sts1 : 1;
unsigned v_err : 1;
} s;
} ccb_sts;
for (remaining = len; remaining; remaining -= written) {
ccb_sts.l_sts = dispatch((word_t) CCB_PUTS, cons_dev, (word_t) str, remaining, hwrpb_to_use);
if (!ccb_sts.s.v_err) {
written = ccb_sts.s.written;
str += written;
} else {
if (ccb_sts.s.v_sts1)
halt(); /* This is a hard error */
written = 0;
}
}
return len;
}
void putc_srm(char c)
{
char buf[2];
buf[0] = c;
buf[1] = 0;
cons_puts(buf,1);
if (c == '\n')
putc_srm('\r');
}
long getc_srm_nonblock(void)
{
return dispatch((word_t) CCB_GETC, cons_dev, 0, 0, hwrpb_to_use);
}
char getc_srm(bool block)
{
long c;
while ((c = getc_srm_nonblock()) < 0)
;
return c;
}
static long cons_getenv(long index, char *envval, long maxlen)
{
long len = dispatch((word_t) CCB_GET_ENV, index, (word_t) envval, maxlen - 1, hwrpb_to_use);
return len;
}
#if 0
static long cons_open(const char *devname)
{
return dispatch((word_t) CCB_OPEN, devname, strlen(devname), 0, hwrpb_to_use);
}
static long cons_close(long dev)
{
return dispatch((word_t) CCB_CLOSE, dev, 0, 0, hwrpb_to_use);
}
#endif
#if defined(CONFIG_KDB_BREAKIN)
void SECTION(".kdebug") kdebug_check_breakin(void)
{
switch(getc_srm_nonblock()) {
case '\e': /* ESC*/
enter_kdebug("KDB Breakin");
return;
default:
case -1:
return;
}
}
#endif
void init_srm(void)
{
static char envval[256];
if(hwrpb_to_use == NULL) {
hwrpb_to_use = INIT_HWRPB;
if (cons_getenv(ENV_TTY_DEV, (char *) envval, sizeof(envval) * 8) < 0) {
halt(); /* better than random crash */
}
cons_dev = simple_strtoul((char *) envval, 0, 10);
} else {
hwrpb_to_use = (struct hwrpb *) CONSOLE_AREA_START;
}
}
word_t kdb_current_console = 0;
kdb_console_t kdb_consoles[] = {
{ "SRM", &init_srm, &putc_srm, &getc_srm },
KDB_NULL_CONSOLE
};

74
kernel/kdb/arch/alpha/dispatch.S
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@ -1,74 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/platform/dp264/dispatch.S
* Description: Dispatch routine.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: dispatch.S,v 1.4 2003/09/24 19:05:04 skoglund Exp $
*
********************************************************************/
#include INC_ARCH(asm.h)
#include INC_GLUE(config.h)
#include INC_ARCH(pal.h)
BEGIN_PROC(dispatch)
.prologue 0
subq $30,80,$30
stq $26,0($30)
stq $29,8($30)
stq $8,16($30) /* OpenVMS save regs */
stq $9,24($30)
stq $10,32($30)
stq $11,40($30)
stq $12,48($30)
stq $13,56($30)
stq $14,64($30)
stq $15,72($30)
mov $20, $1 /* HWRPB in a4 */
ldq $2,0xc0($1) /* crb offset */
addq $2,$1,$2 /* crb */
ldq $27,0($2) /* dispatch procedure value */
ldq $2,8($27) /* dispatch call address */
jsr $26,($2) /* call it (weird VMS call seq) */
ldq $26,0($30)
ldq $29,8($30)
ldq $8,16($30)
ldq $9,24($30)
ldq $10,32($30)
ldq $11,40($30)
ldq $12,48($30)
ldq $13,56($30)
ldq $14,64($30)
ldq $15,72($30)
addq $30,80,$30
ret $31,($26)
END_PROC(dispatch)

39
kernel/kdb/arch/alpha/prepost.cc
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@ -1,39 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/alpha/prepost.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.4 2003/09/24 19:05:04 skoglund Exp $
*
********************************************************************/
#include <kdb/kdb.h>
#include INC_ARCH(palcalls.h)
/* sjw (30/07/2002): This is stupid --- do something here! */
bool kdb_t::pre() { PAL::swpipl(PAL::IPL_highest); return true; }
void kdb_t::post() { }

64
kernel/kdb/arch/alpha/user.cc
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@ -1,64 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2004, University of New South Wales
*
* File path: kdb/arch/alpha/user.cc
* Description: User debugger support
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: user.cc,v 1.5 2004/03/17 19:12:23 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/console.h>
/* sjw (26/08/2002): Put these somewhere decent */
#define KDB_PUTC 0
#define KDB_GETC 1
#define KDB_ENTER 2
/* this is invoked by the enterIF handler when the user does a gentrap palcall */
word_t handle_user_trap(word_t type, word_t arg)
{
word_t dummy;
switch(type) {
case KDB_PUTC:
putc(arg);
return 0;
case KDB_GETC:
return getc();
case KDB_ENTER:
printf("%s\n", arg);
kdebug_entry(&dummy);
return 0;
default:
break;
}
return -1UL;
}

4
kernel/kdb/arch/arm/Makeconf
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@ -1,4 +0,0 @@
SOURCES += $(addprefix kdb/arch/$(ARCH)/, entry.S prepost.cc frame.cc )
SOURCES += kdb/generic/linear_ptab_dump.cc \
kdb/generic/mapping.cc

91
kernel/kdb/arch/arm/entry.S
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@ -1,91 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/arm/entry.S
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: entry.S,v 1.8 2004/09/07 20:12:40 cvansch Exp $
*
********************************************************************/
#include INC_ARCH(thread.h)
/**********************************************************************
kdebug entry
**********************************************************************/
.section .kdebug
3: .word _Z12kdebug_entryPv
.globl kern_kdebug_entry
kern_kdebug_entry:
stmdb sp, {r0-r14}^
nop
sub sp, sp, #PT_SIZE
str lr, [sp, #PT_PC]
mrs lr, cpsr
str lr, [sp, #PT_KLR]
mrs lr, spsr
str lr, [sp, #PT_CPSR]
adr r0, _kdebug_str
bl printf
mov r0, sp
/* use kdebug's own stack */
ldr sp, _kdebug_stack
stmdb sp!, {r0}
adr lr, 1f
ldr pc, 3b
1:
ldr sp, _kdebug_stack
ldr sp, [sp, #-4]
ldr lr, [sp, #PT_KLR]
msr cpsr, lr
ldr lr, [sp, #PT_CPSR]
msr spsr, lr
add sp, sp, #PT_SIZE
ldmdb sp, {r0-r14}^
nop
ldr lr, [sp, #PT_PC-PT_SIZE]
mov pc, lr
.globl _kdebug_stack
_kdebug_stack:
.word _kdebug_stack_top
_kdebug_str:
.string "--- KD# %s ---\n"
/* alignment so that stack looks like a tcb. NB space_t field should be NULL */
.align 12
.globl _kdebug_stack_bottom
_kdebug_stack_bottom:
.space 1024
_kdebug_stack_top:

143
kernel/kdb/arch/arm/frame.cc
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@ -1,143 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, National ICT Australia (NICTA)
*
* File path: kdb/arch/arm/frame.cc
* Description: Exception frame dumping
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: frame.cc,v 1.3 2004/12/09 01:24:41 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(thread.h)
#include INC_API(tcb.h)
extern tcb_t * kdb_get_tcb();
void SECTION(SEC_KDEBUG) arm_dump_frame(arm_irq_context_t *context)
{
printf ("== Stack frame: %p == \n", context);
printf ("cpsr = %8lx, pc = %8lx, sp = %8lx, lr = %8lx\n", context->cpsr, context->pc, context->sp, context->lr);
printf ("r0 = %8lx, r1 = %8lx, r2 = %8lx, r3 = %8lx, r4 = %8lx\n", context->r0, context->r1, context->r2, context->r3, context->r4);
printf ("r5 = %8lx, r6 = %8lx, r7 = %8lx, r8 = %8lx, r9 = %8lx\n", context->r5, context->r6, context->r7, context->r8, context->r9);
printf ("r10 = %8lx, r11 = %8lx, r12 = %8lx\n", context->r10, context->r11, context->r12);
}
/**
* cmd_dump_current_frame: show exception frame of current thread
*/
DECLARE_CMD (cmd_dump_current_frame, root, ' ', "frame",
"show current user exception frame");
CMD (cmd_dump_current_frame, cg)
{
arm_irq_context_t *frame = (arm_irq_context_t *)(kdb.kdb_param);
arm_dump_frame(frame);
return CMD_NOQUIT;
}
/**
* cmd_dump_frame: show exception frame
*/
DECLARE_CMD (cmd_dump_frame, root, 'F', "dumpframe",
"show exception frame");
arm_irq_context_t SECTION(SEC_KDEBUG) * get_frame()
{
space_t * space = get_current_space();
if (!space) space = get_kernel_space();
word_t val = get_hex("tcb/tid/addr", (word_t)space->get_tcb(kdb.kdb_param), "current");
arm_irq_context_t * frame;
if (val == ABORT_MAGIC)
return NULL;
if (!space->is_tcb_area((addr_t)val) &&
((val & (~0xffful)) != (word_t)get_idle_tcb()))
{
threadid_t tid;
tid.set_raw(val);
frame = (arm_irq_context_t *)((word_t)space->get_tcb(tid) + KTCB_SIZE);
frame --;
} else
{
frame = (arm_irq_context_t *)val;
if (frame == (arm_irq_context_t *) addr_to_tcb ((addr_t) val))
{
frame = (arm_irq_context_t *)((word_t)frame + KTCB_SIZE);
frame --;
}
}
return frame;
}
CMD (cmd_dump_frame, cg)
{
arm_irq_context_t *frame = get_frame();
if (frame)
arm_dump_frame(frame);
return CMD_NOQUIT;
}
/**
* cmd_find_frame: search for an exception frame
*/
DECLARE_CMD (cmd_find_frame, root, 's', "findframe",
"search for an exception frame");
CMD (cmd_find_frame, cg)
{
arm_irq_context_t *frame, *search;
word_t *addr;
tcb_t * tcb = kdb_get_tcb();
if (tcb)
{
tcb = (tcb_t *)((word_t)tcb + KTCB_SIZE);
frame = (arm_irq_context_t *) (tcb) - 1;
for (addr = (word_t *) frame; (word_t) addr >= (word_t) frame - 2048;
addr --)
{
search = (arm_irq_context_t *)addr;
if ((search->cpsr & 0x07ffffdf) == 0x00000010)
arm_dump_frame(search);
}
}
return CMD_NOQUIT;
}

44
kernel/kdb/arch/arm/prepost.cc
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@ -1,44 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/arm/prepost.cc
* Description: Entry and exit hooks for kernel debugger
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.3 2004/02/23 03:39:27 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
bool kdb_t::pre (void)
{
/* enter interactive mode */
return true;
}
void kdb_t::post (void)
{
}

25
kernel/kdb/arch/ia64/Makeconf
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@ -1,25 +0,0 @@
SOURCES+= kdb/arch/ia64/breakpoints.cc \
kdb/arch/ia64/cache.cc \
kdb/arch/ia64/ctrl.cc \
kdb/arch/ia64/cpuid.cc \
kdb/arch/ia64/frame.cc \
kdb/arch/ia64/interrupts.cc \
kdb/arch/ia64/io.cc \
kdb/arch/ia64/pkrs.cc \
kdb/arch/ia64/prepost.cc \
kdb/arch/ia64/rrs.cc \
kdb/arch/ia64/tlb.cc \
kdb/arch/ia64/singlestep.cc \
kdb/arch/ia64/sal.cc
ifeq ("$(CONFIG_PERFMON)","y")
SOURCES+= kdb/arch/ia64/perf.cc
endif
ifeq ("$(CONFIG_KDB_DISAS)","y")
SOURCES+= kdb/arch/ia64/disas.cc kdb/arch/ia64/ia64-dis.c \
kdb/generic/sprintf.cc
endif
SOURCES+= kdb/generic/linear_ptab_dump.cc \
kdb/generic/mapping.cc

287
kernel/kdb/arch/ia64/breakpoints.cc
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@ -1,287 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, 2005, Karlsruhe University
*
* File path: kdb/arch/ia64/breakpoints.cc
* Description: IA-64 data and instruction breakpoints
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: breakpoints.cc,v 1.8 2005/06/06 16:01:07 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(pal.h)
#include INC_ARCH(breakpoint.h)
#include INC_GLUE(context.h)
#include INC_API(tcb.h)
void set_psr_bits (threadid_t thread, bool db);
static void init_numregs (void);
static cmd_ret_t set_breakpoint (word_t type);
static cmd_ret_t clr_breakpoint (word_t type);
static word_t num_iregs = 0;
static word_t num_dregs = 0;
static bool global_bp = false;
DECLARE_CMD_GROUP (breakpoints);
/**
* IA-64 breakpoint management.
*/
DECLARE_CMD (cmd_breakpoints, root, 'b', "breakpoint",
"breakpoint management");
CMD (cmd_breakpoints, cg)
{
return breakpoints.interact (cg, "breakpoint");
}
/**
* Set data breakpoint.
*/
DECLARE_CMD (cmd_dbr_set, breakpoints, 'd', "dset", "set data breakpoint");
CMD (cmd_dbr_set, cg)
{
return set_breakpoint ('d');
}
/**
* Set instruction breakpoint.
*/
DECLARE_CMD (cmd_ibr_set, breakpoints, 'i', "iset",
"set instruction breakpoint");
CMD (cmd_ibr_set, cg)
{
return set_breakpoint ('i');
}
static cmd_ret_t set_breakpoint (word_t type)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
if (num_iregs == 0)
init_numregs ();
word_t regs = type == 'i' ? num_iregs : num_dregs;
word_t reg;
// Get breakpoint register number
do {
printf ("Number pair (%d-%d): ", 0, regs-1);
if ((reg = get_hex (NULL, regs, "")) == ABORT_MAGIC)
return CMD_NOQUIT;
} while (reg >= regs);
// Get breakpoint trigger address
addr_t addr = (addr_t) get_hex ("Address", 0);
if ((word_t) addr == ABORT_MAGIC)
return CMD_NOQUIT;
// Get privilege level
breakpoint_t::priv_e priv = breakpoint_t::both;
switch (get_choice ("Privilege", "User/Kernel/Both", 'b'))
{
case 'u': priv = breakpoint_t::user; break;
case 'k': priv = breakpoint_t::kernel; break;
case 'b': priv = breakpoint_t::both; break;
}
// Enable breakpoints.
tcb_t * tcb = kdb.kdb_current;
if (get_choice ("Context", "All threads/Single thread", 'a') == 'a')
{
tcb->resources.enable_global_breakpoint (tcb);
global_bp = true;
}
else
{
tcb = get_thread ("Thread");
ia64_exception_context_t * user_frame =
(ia64_exception_context_t *) tcb->get_stack_top () - 1;
ia64_switch_context_t * kernel_frame =
(ia64_switch_context_t *) tcb->stack;
if (global_bp)
tcb->resources.disable_global_breakpoint (tcb);
global_bp = false;
user_frame->ipsr.db = kernel_frame->psr.db = 1;
}
if (tcb == kdb.kdb_current)
frame->ipsr.db = 1;
// Set breakpoint registers
if (type == 'i')
{
instr_breakpoint_t ibr (addr, ~0UL, priv, true);
ibr.put (reg);
}
else
{
char acc = get_choice ("Access", "Read/Write/Both", 'b');
data_breakpoint_t dbr (addr, ~0UL, priv,
acc == 'w' || acc == 'b',
acc == 'r' || acc == 'b');
dbr.put (reg);
}
return CMD_NOQUIT;
}
/**
* Disable data breakpoint.
*/
DECLARE_CMD (cmd_dbr_clr, breakpoints, 'D', "dclr",
"disable data breakpoint");
CMD (cmd_dbr_clr, cg)
{
return clr_breakpoint ('d');
}
/**
* Disable instruction breakpoint.
*/
DECLARE_CMD (cmd_ibr_clr, breakpoints, 'I', "iclr",
"disable instruction breakpoint");
CMD (cmd_ibr_clr, cg)
{
return clr_breakpoint ('i');
}
static cmd_ret_t clr_breakpoint (word_t type)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
ia64_exception_context_t * user_frame =
(ia64_exception_context_t *) kdb.kdb_current->get_stack_top () - 1;
if (num_iregs == 0)
init_numregs ();
word_t regs = type == 'i' ? num_iregs : num_dregs;
word_t reg;
// Get breakpoint register number
do {
printf ("Number pair (%d-%d): ", 0, regs-1);
if ((reg = get_hex (NULL, regs, "")) == ABORT_MAGIC)
return CMD_NOQUIT;
} while (reg >= regs);
// Disable breakpoint registers
if (type == 'i')
{
instr_breakpoint_t ibr = get_ibr (reg);
ibr.disable ();
ibr.put (reg);
}
else
{
data_breakpoint_t dbr = get_dbr (reg);
dbr.disable ();
dbr.put (reg);
}
if (global_bp)
kdb.kdb_current->resources.disable_global_breakpoint (kdb.kdb_current);
global_bp = false;
// Disable breakpoints
frame->ipsr.db = user_frame->ipsr.db = 0;
return CMD_NOQUIT;
}
/**
* List all breakpoints
*/
DECLARE_CMD (cmd_bp_list, breakpoints, 'l', "list", "list breakpoints");
CMD (cmd_bp_list, cg)
{
if (num_iregs == 0)
init_numregs ();
printf ("Instruction breakpoints:\n");
for (word_t i = 0; i < num_iregs; i++)
{
instr_breakpoint_t ibr = get_ibr (i);
printf (" ibr[%d]%s = addr: %p, mask: %p, priv: %s %s\n",
i, i >= 10 ? "" : " ",
ibr.get_address (), ibr.get_mask (),
ibr.get_priv () == breakpoint_t::kernel ? "kernel, " :
ibr.get_priv () == breakpoint_t::user ? "user, " :
ibr.get_priv () == breakpoint_t::both ? "both, " :
"unknown,",
ibr.is_active () ? "active" : "inactive");
}
printf ("Data breakpoints:\n");
for (word_t i = 0; i < num_dregs; i++)
{
data_breakpoint_t dbr = get_dbr (i);
printf (" dbr[%d]%s = addr: %p, mask: %p, priv: %s %s\n",
i, i >= 10 ? "" : " ",
dbr.get_address (), dbr.get_mask (),
dbr.get_priv () == breakpoint_t::kernel ? "kernel, " :
dbr.get_priv () == breakpoint_t::user ? "user, " :
dbr.get_priv () == breakpoint_t::both ? "both, " :
"unknown,",
dbr.is_active () ?
dbr.is_read_match () ? dbr.is_write_match () ?
"read/write" : "read" : "write" : "inactive");
}
return CMD_NOQUIT;
}
static void init_numregs (void)
{
pal_status_e status;
if ((status = pal_debug_info (&num_iregs, &num_dregs)) != PAL_OK)
{
printf ("Error: PAL_DEBUG_INFO => %d\n", status);
}
}

147
kernel/kdb/arch/ia64/cache.cc
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@ -1,147 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/cache.cc
* Description: IA-64 cache info/managemnt commands
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: cache.cc,v 1.5 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/cmd.h>
#include INC_ARCH(pal.h)
DECLARE_CMD_GROUP (ia64_cache);
/**
* cmd_ia64_cache: IA-64 cache management
*/
DECLARE_CMD (cmd_ia64_cache, arch, 'c', "cache", "cache management");
CMD(cmd_ia64_cache, cg)
{
return ia64_cache.interact (cg, "cache");
}
/**
* cmd_ia64_cache_info: dump cache information
*/
DECLARE_CMD (cmd_ia64_cache_info, ia64_cache, 'i', "info", "dump cache info");
CMD(cmd_ia64_cache_info, cg)
{
pal_cache_summary_t summary;
pal_cache_info_t info;
pal_status_e status;
if ((status = pal_cache_summary (&summary)) != PAL_OK)
{
printf ("Error: PAL_CACHE_SUMMARY => %d\n", status);
return CMD_NOQUIT;
}
printf ("Cache info:\n");
pal_cache_info_t::type_e type = pal_cache_info_t::code;
const static char *hints[] = {
"Temp L1", "Non-Temp L1", "bit2", "Non-Temp all levels",
"bit4", "bit5", "bit6", "bit7"
};
do {
for (word_t i = 0; i < summary.cache_levels; i++)
{
if ((status = pal_cache_info (i, type, &info)) != PAL_OK)
continue;
printf (" L%d %c-Cache: ",
i+1, info.unified ? 'U' :
type == pal_cache_info_t::code ? 'I' : 'D');
printf ("%3d%cB ",
info.cache_size > GB (1) ? info.cache_size >> 30 :
info.cache_size > MB (1) ? info.cache_size >> 20 :
info.cache_size >> 10,
info.cache_size > GB (1) ? 'G' :
info.cache_size > MB (1) ? 'M' : 'K');
if (info.associativity == 0)
printf ("fully assoc, ");
else if (info.associativity == 1)
printf ("direct, ");
else
printf ("%d-way, ", info.associativity);
if (info.attributes == 0)
printf ("write-through, ");
else if (info.attributes == 1)
printf ("write-back, ");
printf ("line size: %d, ", (1UL << info.line_size));
printf ("stride: %d, ", (1UL << info.stride));
printf ("tag bits: %d-%d, ", info.tag_ls_bit, info.tag_ms_bit);
printf ("alias boundary: %d", info.alias_boundary);
printf ("\n ");
printf ("[ld.latancy: %d, ld.hints:", info.load_latency);
for (word_t k = 0; k < 8; k++)
if (info.load_hints & (1 << k))
printf (" %s,", hints[k]);
if (info.load_hints == 0)
printf (" none ");
printf ("\b] ");
if (info.store_latency != 0xff)
{
printf ("[st.latancy: %d, st.hints:", info.store_latency);
for (word_t k = 0; k < 8; k++)
if (info.store_hints & (1 << k))
printf (" %s,", hints[k]);
if (info.store_hints == 0)
printf (" none ");
printf ("\b]");
}
printf ("\n");
}
if (type == pal_cache_info_t::code)
type = pal_cache_info_t::data;
else
type = pal_cache_info_t::none;
} while (type != pal_cache_info_t::none);
return CMD_NOQUIT;
}

68
kernel/kdb/arch/ia64/cpuid.cc
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@ -1,68 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/cpuid.cc
* Description: IA-64 CPUID
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: cpuid.cc,v 1.3 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(cpuid.h)
/**
* cmd_dpuid: dump CPU ID
*/
DECLARE_CMD (cmd_cpuid, arch, 'C', "cpuid", "dump CPUID");
CMD (cmd_cpuid, cg)
{
printf ("CPUID:\n");
printf (" Vendor: %s\n"
" Serial num: %p\n",
cpuid_vendor_info (), cpuid_serial_number ());
cpuid_version_info_t info = cpuid_version_info ();
printf (" Version: %p "
"[Stepping %c%d, Model %d, Family %d, Archrev %d]\n",
info.raw,
(info.revision >> 1) + 'A' - 1, (info.revision & 0x1),
info.model, info.family, info. archrev);
printf (" cpuid[4]: %p [%s]\n", cpuid_get (4),
cpuid_get (4) & 1 ? "lb" : "");
for (word_t i = 5; i <= info.number; i++)
{
printf (" cpuid[%d]: %p\n", i, cpuid_get (i));
}
return CMD_NOQUIT;
}

198
kernel/kdb/arch/ia64/ctrl.cc
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@ -1,198 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/ctrl.cc
* Description: Control register access
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: ctrl.cc,v 1.8 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include INC_ARCH(psr.h)
#include INC_ARCH(cr.h)
#include INC_ARCH(ar.h)
void ia64_dump_psr (psr_t psr);
/**
* cmd_ctrl_regs: dump control registers
*/
DECLARE_CMD (cmd_ctrl_regs, arch, 'R', "ctrlregs", "dump control registers");
CMD (cmd_ctrl_regs, cg)
{
psr_t psr = get_psr ();
psr_t ipsr = cr_get_ipsr ();
cr_dcr_t dcr = cr_get_dcr ();
cr_pta_t pta = cr_get_pta ();
cr_isr_t isr = cr_get_isr ();
cr_itir_t itir = cr_get_itir ();
cr_ifs_t ifs = cr_get_ifs ();
cr_lid_t lid = cr_get_lid ();
cr_tpr_t tpr = cr_get_tpr ();
cr_ivec_t itv = cr_get_itv ();
cr_ivec_t pmv = cr_get_pmv ();
cr_ivec_t cmcv = cr_get_cmcv ();
cr_ivec_t lrr0 = cr_get_lrr0 ();
cr_ivec_t lrr1 = cr_get_lrr1 ();
static char * delmode[] = {
"INT", "dm=1", "PMI", "dm=3", "NMI", "INIT", "dm=6", "ExtINT"
};
printf ("Processor Status Register:\n");
printf (" psr: %p ", psr); ia64_dump_psr (psr); printf ("\n");
printf ("\nControl Registers:\n");
printf (" cr.ipsr: %p ", ipsr); ia64_dump_psr (ipsr); printf ("\n");
printf (" cr.dcr: %p [%s%s%s%s%s%s%s%s%s%s]\n",
dcr.raw,
dcr.pp ? "pp " : "", dcr.be ? "be " : "",
dcr.lc ? "lc " : "", dcr.dm ? "dm " : "",
dcr.dp ? "dp " : "", dcr.dk ? "dk " : "",
dcr.dr ? "dr " : "", dcr.da ? "da " : "",
dcr.dd ? "dd " : "", dcr.raw ? "\b" : "");
printf (" ar.itc: %p\n", ar_get_itc ());
printf (" cr.itm: %p\n", cr_get_itm ());
printf (" cr.iva: %p\n", cr_get_iva ());
printf (" cr.pta: %p [%s, format: %s, size: %dKB, base: %p]\n",
pta.raw, pta.is_vhpt_enabled () ? "enabled" : "disabled",
pta.format () == cr_pta_t::fmt_short ? "short" : "long",
pta.size () >> 10, pta.base ());
printf (" cr.isr: %p [code: %4x, vec: %2x, slot: %d, acc: %c%c%c "
"%s%s%s%s%s%s%s\b]\n",
isr.raw, isr.code, isr.vector, isr.instruction_slot,
isr.rwx & 4 ? 'r' : '~', isr.rwx & 2 ? 'w' : '~',
isr.rwx & 1 ? 'x' : '~',
isr.non_access ? "na " : "",
isr.speculative_load ? "sp " : "",
isr.register_stack ? "rs " : "",
isr.incomplete_reg_frame ? "ir " : "",
isr.nested_interruption ? "ni " : "",
isr.supervisor_override ? "so " : "",
isr.exception_deferral ? "ed " : "");
printf (" cr.iip: %p\n", cr_get_iip ());
printf (" cr.ifa: %p\n", cr_get_ifa ());
printf (" cr.itir: %p [size: %d%cB, key: %5x]\n",
itir.raw, itir.ps >= 30 ? itir.page_size () >> 30 :
itir.ps >= 20 ? itir.page_size () >> 20 : itir.page_size () >> 10,
itir.ps >= 30 ? 'G' : itir.ps >= 20 ? 'M' : 'K',
itir.protection_key ());
printf (" cr.iipa: %p\n", cr_get_iipa ());
printf (" cr.ifs: %p [%svalid, size: %d (%d+%d), rot: %d, "
"rrb (gr: %d, fr: %d, pr: %d)]\n",
ifs.raw, ifs.valid ? "" : "in",
ifs.framesize (), ifs.locals (), ifs.outputs (), ifs.sor,
ifs.rrb_gr, ifs.rrb_fr, ifs.rrb_pr);
printf (" cr.iim: %p\n", cr_get_iim ());
printf (" cr.iha: %p\n", cr_get_iha ());
printf (" cr.lid: %p [eid: %02x, id: %02x]\n", lid.raw, lid.eid, lid.id);
printf (" cr.tpr: %p [mic: %d, mask %s]\n",
tpr.raw, tpr.mic, tpr.mmi ? "all" : "mic");
printf (" cr.irr: %p %p %p %p\n",
cr_get_irr (3), cr_get_irr (2), cr_get_irr (1), cr_get_irr (0));
printf (" cr.itv: %p [vector: %d, %smasked]\n",
itv.raw, itv.vector, itv.m ? "" : "not ");
printf (" cr.pmv: %p [vector: %d, %smasked]\n",
pmv.raw, pmv.vector, pmv.m ? "" : "not ");
printf (" cr.cmcv: %p [vector: %d, %smasked]\n",
cmcv.raw, cmcv.vector, cmcv.m ? "" : "not ");
printf (" cr.lrr0: %p [vector: %d, %s, active %s, %s triggered, "
"%smasked]\n",
lrr0.raw, lrr0.vector, delmode[lrr0.dm],
lrr0.ipp == 0 ? "high" : "low",
lrr0.dm == 0 ? "edge" : "level",
lrr0.m ? "" : "not ");
printf (" cr.lrr1: %p [vector: %d, %s, active %s, %s triggered, "
"%smasked]\n",
lrr1.raw, lrr1.vector, delmode[lrr1.dm],
lrr1.ipp == 0 ? "high" : "low",
lrr1.dm == 0 ? "edge" : "level",
lrr1.m ? "" : "not ");
printf ("\nApplication Registers:\n");
word_t ar[8];
asm volatile (
" mov %0 = ar.k0 \n"
" mov %1 = ar.k1 \n"
" mov %2 = ar.k2 \n"
" mov %3 = ar.k3 \n"
" mov %4 = ar.k4 \n"
" mov %5 = ar.k5 \n"
" mov %6 = ar.k6 \n"
" mov %7 = ar.k7 \n"
:
"=r"(ar[0]), "=r"(ar[1]), "=r"(ar[2]), "=r"(ar[3]),
"=r"(ar[4]), "=r"(ar[5]), "=r"(ar[6]), "=r"(ar[7]));
for (word_t i = 0; i < 8; i++)
printf (" ar.k%d: %p\n", i, ar[i]);
return CMD_NOQUIT;
}
void ia64_dump_psr (psr_t psr)
{
printf ("[%s%s%s%s%s%s%s%s%s%s",
psr.be ? "be " : "",
psr.up ? "up " : "",
psr.ac ? "ac " : "",
psr.mfl ? "mfl " : "",
psr.mfh ? "mfh " : "",
psr.ic ? "ic " : "",
psr.i ? "i " : "",
psr.pk ? "pk " : "",
psr.dt ? "dt " : "",
psr.dfl ? "dfl " : "");
printf ("%s%s%s%s%s%s%s%s%s%s",
psr.dfh ? "dfh " : "",
psr.sp ? "sp " : "",
psr.pp ? "pp " : "",
psr.di ? "di " : "",
psr.si ? "si " : "",
psr.db ? "db " : "",
psr.lp ? "lp " : "",
psr.tb ? "tb " : "",
psr.rt ? "rt " : "",
psr.is ? "is " : "");
printf ("%s%s%s%s%s%s%s%s%s%s",
psr.mc ? "mc " : "",
psr.it ? "it " : "",
psr.id ? "id " : "",
psr.da ? "da " : "",
psr.dd ? "dd " : "",
psr.ss ? "ss " : "",
psr.ed ? "ed " : "",
psr.bn ? "bn " : "",
psr.ia ? "ia " : "",
psr.raw & ~((3UL << 32) | (3UL << 41)) ? "\b" : "");
printf (" cpl=%d ri=%d]",
psr.cpl, psr.ri);
}

90
kernel/kdb/arch/ia64/disas.cc
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@ -1,90 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/disas.cc
* Description: Disassembler wrapper for IA-32
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: disas.cc,v 1.7 2003/11/06 18:49:19 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(cr.h)
#include INC_API(space.h)
#include INC_API(tcb.h)
extern "C" int disas (addr_t pc);
DECLARE_CMD (cmd_disas, root, 'U', "disas", "disassemble");
CMD (cmd_disas, cg)
{
char c;
word_t pc;
restart:
if ((pc = get_hex("IP", (word_t) cr_get_iip ())) == ABORT_MAGIC)
return CMD_NOQUIT;
do {
printf ("%p: ", pc);
pc += disas ((addr_t) pc);
printf ("\n");
c = get_choice (NULL, "c/u/q", 'c');
} while ((c != 'q') && (c != 'u'));
if (c == 'u')
goto restart;
return CMD_NOQUIT;
}
extern "C" int readmem (addr_t vaddr, addr_t contents, int size)
{
word_t value;
if (vaddr < ia64_phys_to_rr (7, (addr_t) 0))
{
space_t * space = kdb.kdb_current->get_space ();
if (! space->readmem (vaddr, &value))
return 0;
vaddr = (addr_t) &value;
}
switch (size)
{
case 1: *(u8_t *) contents = *(u8_t *) vaddr; break;
case 2: *(u16_t *) contents = *(u16_t *) vaddr; break;
case 4: *(u32_t *) contents = *(u32_t *) vaddr; break;
case 8: *(u64_t *) contents = *(u64_t *) vaddr; break;
default:
return 0;
}
return 1;
}

224
kernel/kdb/arch/ia64/frame.cc
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@ -1,224 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/frame.cc
* Description: Exception frame dumping
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: frame.cc,v 1.19 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_GLUE(context.h)
#include INC_API(tcb.h)
void ia64_dump_psr (psr_t psr);
void ia64_dump_frame (ia64_exception_context_t * frame);
/**
* cmd_dump_current_frame: show exception frame of current thread
*/
DECLARE_CMD (cmd_dump_current_frame, root, ' ', "frame",
"show current exception frame");
CMD (cmd_dump_current_frame, cg)
{
ia64_dump_frame ((ia64_exception_context_t *) kdb.kdb_param);
return CMD_NOQUIT;
}
/**
* cmd_dump_frame: show exception frame
*/
DECLARE_CMD (cmd_dump_frame, root, 'F', "dumpframe",
"show exception frame");
CMD (cmd_dump_frame, cg)
{
tcb_t * tcb = addr_to_tcb (kdb.kdb_param);
ia64_exception_context_t * f =
(ia64_exception_context_t *) tcb->get_stack_top () - 1;
word_t frame = get_hex ("Frame", (word_t) f, "current user frame");
ia64_dump_frame ((ia64_exception_context_t *) frame);
return CMD_NOQUIT;
}
word_t * next_nat_collection (word_t * addr)
{
return (word_t *) (((word_t) (addr + 65) & ~0x1ff) - 8);
}
void ia64_dump_frame (ia64_exception_context_t * frame)
{
word_t *rptr, i;
printf ("Exception %d, frame @ %p:\n", frame->exception_num, frame);
printf (" cr.iip: %p ar.ec: %p ar.lc: %p\n"
" cr.ifa: %p cr.iim: %p cr.iha: %p\n"
" ar.bsp: %p ar.unat: %p ar.rnat: %p\n"
" ar.ccv: %p ar.rsc: %p cr.iipa: %p\n",
frame->iip, frame->ec, frame->lc,
frame->ifa, frame->iim, frame->iha,
frame->bspstore, frame->unat, frame->rnat,
frame->ccv, frame->rsc, frame->iipa);
printf (" ar.fpsr: %p [traps=%c%c%c%c%c%c ",
frame->fpsr.raw,
frame->fpsr.traps_vd ? 'v' : '~',
frame->fpsr.traps_dd ? 'd' : '~',
frame->fpsr.traps_zd ? 'z' : '~',
frame->fpsr.traps_od ? 'o' : '~',
frame->fpsr.traps_ud ? 'u' : '~',
frame->fpsr.traps_id ? 'i' : '~');
printf ("sf=(%03x %03x %03x %03x)]\n",
frame->fpsr.sf0, frame->fpsr.sf1,
frame->fpsr.sf2, frame->fpsr.sf3);
printf (" cr.ipsr: %p ", frame->ipsr);
ia64_dump_psr (frame->ipsr);
printf ("\n");
printf (" cr.isr: %p [code: %4x, vec: %2x, slot: %d, acc: %c%c%c "
"%s%s%s%s%s%s%s\b]\n",
frame->isr.raw, frame->isr.code, frame->isr.vector,
frame->isr.instruction_slot,
frame->isr.rwx & 4 ? 'r' : '~', frame->isr.rwx & 2 ? 'w' : '~',
frame->isr.rwx & 1 ? 'x' : '~',
frame->isr.non_access ? "na " : "",
frame->isr.speculative_load ? "sp " : "",
frame->isr.register_stack ? "rs " : "",
frame->isr.incomplete_reg_frame ? "ir " : "",
frame->isr.nested_interruption ? "ni " : "",
frame->isr.supervisor_override ? "so " : "",
frame->isr.exception_deferral ? "ed " : "");
printf (" ar.pfs: %p [size: %d (%d+%d), rot: %d, "
"rrb (gr: %d, fr: %d, pr: %d)]\n",
frame->pfs.raw, frame->pfs.framesize (),
frame->pfs.locals (), frame->pfs.outputs (), frame->pfs.sor,
frame->pfs.rrb_gr, frame->pfs.rrb_fr, frame->pfs.rrb_pr);
printf (" cr.ifs: %p [size: %d (%d+%d), rot: %d, "
"rrb (gr: %d, fr: %d, pr: %d)]\n",
frame->ifs.raw, frame->ifs.framesize (),
frame->ifs.locals (), frame->ifs.outputs (), frame->ifs.sor,
frame->ifs.rrb_gr, frame->ifs.rrb_fr, frame->ifs.rrb_pr);
printf (" cr.tpr: %p [mic: %d, mask %s]\n",
frame->tpr.raw, frame->tpr.mic, frame->tpr.mmi ? "all" : "mic");
printf ("\nPredicate registers:\n p0-p63: ");
for (int i = 0; i <= 63; i++)
{
printf ("%d", frame->pr & (1UL << i) ? 1 : 0);
if ((i & 7) == 7)
printf (" ");
}
printf ("\n\nBranch registers:\n");
rptr = (word_t *) &frame->b0;
for (i = 0; i <= 7; i++)
{
printf (" br%d: %p ", i, *rptr++);
if ((i & 3) == 3)
printf ("\n");
}
printf ("\nGeneral registers (num dirty = %d):\n", frame->num_dirty/8);
rptr = (word_t *) &frame->r1;
for (i = 0; i <= 31; i++)
{
word_t nat = frame->unat_kern & (1UL << (((word_t) rptr >> 3) & 0x3f));
word_t reg = (i == 0) ? 0 : (i == 12) ? (word_t) frame->r12 : *rptr++;
printf (" r%d%s %p%c ", i, i <= 9 ? ": " : ":", reg, nat ? '*' : ' ');
if ((i & 3) == 3)
printf ("\n");
}
// Determine whether registers were dumped on empty kernel stack
// (i.e., user exception) or the existing kernel stack (kernel
// exceptions)
tcb_t * tcb = addr_to_tcb ((addr_t) frame);
if (frame->ipsr.cpl == 3 ||
get_current_space ()->is_user_area (frame->bspstore))
rptr = (word_t *) tcb->get_reg_stack_bottom ();
else
rptr = (word_t *) frame->bspstore;
// Skip dirty registers which are not part of stack frame
if (frame->num_dirty/8 > frame->ifs.framesize ())
{
word_t * tmp = rptr;
rptr += frame->num_dirty/8 - frame->ifs.framesize ();
// Adjust for NaT collection in dirty partition
if (next_nat_collection (tmp) < rptr + frame->ifs.framesize () &&
next_nat_collection (tmp) >= rptr)
rptr--;
}
// Determine NaT collection for lower registers
word_t rnat;
if (next_nat_collection (rptr) < frame->bspstore_kern)
rnat = *next_nat_collection (rptr);
else
rnat = frame->rnat_kern;
for (i = 0; i < frame->ifs.framesize (); i++, rptr++)
{
if (((word_t) rptr & 0x1f8) == 0x1f8)
{
// Change NaT collection
i--;
rnat = frame->rnat_kern;
continue;
}
word_t reg;
bool mapped = true;
if (get_current_space ()->is_user_area (rptr))
mapped = get_current_space ()->readmem (rptr, &reg);
else
reg = *rptr;
word_t nat = rnat & (1UL << (((word_t) rptr >> 3) & 0x3f));
if (mapped)
printf (" r%d: %p%c ", i+32, reg, nat ? '*' : ' ');
else
printf (" r%d: ################? ", i+32);
if ((i & 3) == 3)
printf ("\n");
}
if ((--i & 3) != 3)
printf ("\n");
}

177
kernel/kdb/arch/ia64/ia64-dis.c
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@ -1,177 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/ia64-dis.c
* Description: Wrapper for IA-64 disassembler
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: ia64-dis.c,v 1.8 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#define SEC_KDEBUG ".kdebug"
/* define stuff needed by the disassembler */
#define PARAMS(x) x SECTION(SEC_KDEBUG)
#define ATTRIBUTE_UNUSED
#define abort() do { } while (0)
#define BFD_HOST_64_BIT u64_t
#define BFD_HOST_U_64_BIT u64_t
typedef u64_t bfd_vma;
typedef u8_t bfd_byte;
int printf(const char * format, ...);
int sprintf(char* obuf, const char* format, ...);
int fprintf(char* f, const char* format, ...);
typedef int (*fprintf_ftype) (char*, const char*, ...);
typedef struct disassemble_info {
void* stream;
int (*read_memory_func)(bfd_vma memaddr,
bfd_byte *myaddr, word_t length,
struct disassemble_info *info);
void (*memory_error_func)(int status,
bfd_vma memaddr,
struct disassemble_info *info);
int bytes_per_line;
int display_endian;
int endian;
fprintf_ftype fprintf_func;
void (*print_address_func)(bfd_vma addr, struct disassemble_info *info);
} disassemble_info;
/*
* functions that the disassembler calls
*/
/* load with enforced little endian */
bfd_vma SECTION(SEC_KDEBUG) bfd_getl64 (bfd_byte* addr)
{
return (((bfd_vma) addr[7] << 56) | ((bfd_vma) addr[6] << 48) |
((bfd_vma) addr[5] << 40) | ((bfd_vma) addr[4] << 32) |
((bfd_vma) addr[3] << 24) | ((bfd_vma) addr[2] << 16) |
((bfd_vma) addr[1] << 8) | ((bfd_vma) addr[0] ));
}
/* read memory */
int SECTION(SEC_KDEBUG) rmf(bfd_vma memaddr,
bfd_byte *myaddr, word_t length,
struct disassemble_info *info)
{
int readmem (addr_t vaddr, addr_t contents, word_t size);
char* d = (char*) myaddr;
char* s = (char*) memaddr;
int len = length;
while (len--)
{
#if 1
if (! readmem ((addr_t) s, (addr_t) d, sizeof (char)))
return 1;
#else
*d = *s;
#endif
d++; s++;
};
return 0;
};
/* respond to memory read error */
void SECTION(SEC_KDEBUG) mef(int status,
bfd_vma memaddr,
struct disassemble_info *info)
{
//printf("%s(%x,%x,%x)\n", __FUNCTION__, status, memaddr, info);
printf("##");
};
/* print address */
void SECTION(SEC_KDEBUG) paf(bfd_vma addr, struct disassemble_info *info)
{
printf("%p", addr);
};
char SECTION(SEC_KDEBUG) *strcpy(char *dest, const char *src)
{
char* d = dest;
const char* s = src;
do { *d++ = *s; } while (*s++);
return dest;
};
char SECTION(SEC_KDEBUG) *strcat(char *dest, const char *src)
{
char* d = dest;
char* s = (char*) src;
/* scan for trailing \0 */
while (*d)
d++;
/* copy until end of s, including the \0 */
while ( (*d++ = *s++) );
return dest;
};
int print_insn_ia64 (bfd_vma pc, disassemble_info *info) SECTION(SEC_KDEBUG);
int SECTION(SEC_KDEBUG) disas(addr_t pc)
{
disassemble_info info =
{
NULL,
rmf,
mef,
6,
0,
0,
fprintf,
paf
};
return print_insn_ia64((u64_t)pc, &info);
}
#include <../../contrib/disas/cpu-ia64-opc.c>
#include <../../contrib/disas/ia64-dis.c>
#undef PARAMS
#define PARAMS(x) x SECTION(SEC_KDEBUG)
#include <../../contrib/disas/ia64-opc.c>

97
kernel/kdb/arch/ia64/interrupts.cc
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@ -1,97 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/interrupts.cc
* Description: Interrupt information
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: interrupts.cc,v 1.4 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/cmd.h>
#include INC_ARCH(cr.h)
#include INC_GLUE(intctrl.h)
#include INC_GLUE(context.h)
/**
* Dump pending/masked interrupts.
*/
DECLARE_CMD (cmd_ia64_pending_ints, arch, 'I', "pendingints",
"dump pending/masked interrupts");
CMD (cmd_ia64_pending_ints, cg)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
cr_tpr_t tpr = cr_get_tpr ();
printf ("Pending/masked interrupts (Global IRQ offset = %d):\n",
INTERRUPT_VECTOR_OFFSET);
printf (" psr.i=%d, tpr.mmi=%d %s\n",
frame->ipsr.i, tpr.mmi,
(frame->ipsr.i == 0 || tpr.mmi) ? "(All interrupts masked)" : "");
word_t max_irqs = get_interrupt_ctrl ()->get_number_irqs ();
for (word_t i = 0; i < 256;)
{
bool deliver_pending = false;
bool ack_pending = false;
bool masked = false;
if (i >= INTERRUPT_VECTOR_OFFSET &&
i < INTERRUPT_VECTOR_OFFSET + max_irqs)
{
// Interrupt delivered through I/O SAPIC.
iosapic_redir_t ent = get_interrupt_ctrl ()->
get_redir (i - INTERRUPT_VECTOR_OFFSET);
deliver_pending = ent.delivery_status != 0;
ack_pending = ent.remote_irr != 0;
masked = ent.mask != 0;
}
if ((i & 15) == 0)
printf (" %3d-%d%s [", i, i+15, (i+15) > 99 ? "" : " ");
printf ("%c%c%c%c", deliver_pending ? 'd' : '~',
is_interrupt_pending (i) ? 'p' : '~',
ack_pending ? 'a' : '~', masked ? 'm' : '~');
i++;
if ((i & 15) == 0)
printf ("] %c\n",
((i-1) < 16 || ((i-1) >> 4) > tpr.mic) ? ' ' : 'M');
else if ((i & 7) == 0)
printf ("] [");
else
printf ("|");
}
return CMD_NOQUIT;
}

487
kernel/kdb/arch/ia64/io.cc
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@ -1,487 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002-2004, Karlsruhe University
*
* File path: kdb/arch/ia64/io.cc
* Description: Console/serial I/O for IA-64 platforms
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: io.cc,v 1.18 2006/10/19 22:57:36 ud3 Exp $
*
********************************************************************/
#include INC_ARCH(ioport.h)
#include INC_ARCH(ski.h)
#include INC_ARCH(tlb.h)
#include INC_ARCH(trmap.h)
#include INC_PLAT(system_table.h)
#include INC_PLAT(hcdp.h)
#include INC_GLUE(hwspace.h)
#include <kdb/kdb.h>
#include <kdb/cmd.h>
#include <kdb/console.h>
#include <debug.h>
#if !defined(CONFIG_KDB_COMSPEED)
#define CONFIG_KDB_COMSPEED 115200
#endif
#if !defined(CONFIG_KDB_COMPORT)
#define CONFIG_KDB_COMPORT 0x3f8
#endif
#if !defined(CONFIG_KDB_CONS_SKI)
static void init_serial (void) SECTION (".init");
static void init_screen (void) SECTION (".init");
static void putc_serial (char) SECTION (".kdebug");
static char getc_serial (bool) SECTION (".kdebug");
static void putc_screen (char) SECTION (".kdebug");
static char getc_screen (bool) SECTION (".kdebug");
kdb_console_t kdb_consoles[] = {
{ "screen", &init_screen, &putc_screen, &getc_screen },
{ "serial", &init_serial, &putc_serial, &getc_serial },
KDB_NULL_CONSOLE
};
#if defined(CONFIG_KDB_CONS_COM)
word_t kdb_current_console = 1;
#else
word_t kdb_current_console = 0;
#endif
/*
**
** Console I/O functions.
**
*/
#define DISPLAY phys_to_virt_uc ((char *) 0xb8000)
#define NUM_LINES (24)
#define NUM_COLS (80)
static void init_screen (void)
{
/*
* Map screen memory uncacheable.
*/
if (! dtrmap.is_mapped (DISPLAY))
{
translation_t tr (1, translation_t::uncacheable, 1, 1, 0,
translation_t::rwx, virt_to_phys (DISPLAY), 0);
dtrmap.add_map (tr, DISPLAY, HUGE_PGSIZE, 0);
}
}
static void putc_screen (char c)
{
static unsigned cursor = 0;
static unsigned color = 7;
static unsigned new_color = 0;
static unsigned esc = 0;
static unsigned esc2 = 0;
static const unsigned col[] = { 0, 4, 2, 14, 1, 5, 3, 15 };
if (esc == 1)
{
if (c == '[')
{
esc++;
return;
}
}
else if (esc == 2)
{
switch (c)
{
case '0': case '1': case '2':
case '3': case '4': case '7':
esc++;
esc2 = c;
return;
}
}
else if (esc == 3)
{
switch (c)
{
case '0': case '1': case '2': case '3':
case '4': case '5': case '6': case '7':
if (esc2 == '3' || esc2 == '4')
{
// New foreground or background color
new_color = col[c - '0'];
esc++;
return;
}
break;
case 'J':
if (esc2 == '2')
{
// Clear screen
for (int i = 0; i < NUM_COLS*NUM_LINES; i++)
((u16_t *) DISPLAY)[i] = (color << 8) + ' ';
cursor = 0;
esc = 0;
return;
}
break;
case 'm':
switch (esc2)
{
case '0':
// Normal text
color = 7;
esc = 0;
return;
case '1':
// Bright text
color = 15;
esc = 0;
return;
case '7':
// Reversed
color = (7 << 4);
esc = 0;
return;
}
}
}
else if (esc == 4)
{
if (c == 'm' && esc2 == '3')
{
// Foreground color
color = (color & 0xf0) | new_color;
esc = 0;
return;
}
else if (c == 'm' && esc2 == '4')
{
// Background color
color = (color & 0x0f) | (new_color << 4);
esc = 0;
return;
}
}
switch(c) {
case '\e':
esc = 1;
return;
case '\r':
cursor -= (cursor % (NUM_COLS*2));
break;
case '\n':
cursor += ((NUM_COLS*2) - (cursor % (NUM_COLS*2)));
break;
case '\t':
cursor += (8 - (cursor % 8));
break;
case '\b':
cursor -= 2;
break;
default:
DISPLAY[cursor++] = c;
DISPLAY[cursor++] = color;
}
esc = 0;
if ((cursor / (NUM_COLS*2)) == NUM_LINES)
{
for (int i = NUM_COLS; i < NUM_COLS*NUM_LINES; i++)
((u16_t *) DISPLAY)[i - NUM_COLS] = ((u16_t *) DISPLAY)[i];
for (int i = 0; i < NUM_COLS; i++)
((u16_t * )DISPLAY)[NUM_COLS * (NUM_LINES-1) + i] = 0;
cursor -= (NUM_COLS*2);
}
}
#define KBD_STATUS_REG 0x64
#define KBD_CNTL_REG 0x64
#define KBD_DATA_REG 0x60
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
#define kbd_read_input() in_u8 (KBD_DATA_REG)
#define kbd_read_status() in_u8 (KBD_STATUS_REG)
static unsigned char keyb_layout[2][128] =
{
"\000\0331234567890-=\010\t" /* 0x00 - 0x0f */
"qwertyuiop[]\r\000as" /* 0x10 - 0x1f */
"dfghjkl;'`\000\\zxcv" /* 0x20 - 0x2f */
"bnm,./\000*\000 \000\201\202\203\204\205" /* 0x30 - 0x3f */
"\206\207\210\211\212\000\000789-456+1" /* 0x40 - 0x4f */
"230\177\000\000\213\214\000\000\000\000\000\000\000\000\000\000"
"\r\000/" /* 0x60 - 0x6f */
,
"\000\033!@#$%^&*()_+\010\t" /* 0x00 - 0x0f */
"QWERTYUIOP{}\r\000AS" /* 0x10 - 0x1f */
"DFGHJKL:\"`\000\\ZXCV" /* 0x20 - 0x2f */
"BNM<>?\000*\000 \000\201\202\203\204\205" /* 0x30 - 0x3f */
"\206\207\210\211\212\000\000789-456+1" /* 0x40 - 0x4f */
"230\177\000\000\213\214\000\000\000\000\000\000\000\000\000\000"
"\r\000/" /* 0x60 - 0x6f */
};
static char getc_screen (bool block)
{
static u8_t last_key = 0;
static u8_t shift = 0;
char c;
for (;;)
{
unsigned char status = kbd_read_status ();
while (status & KBD_STAT_OBF)
{
u8_t scancode;
scancode = kbd_read_input ();
// Check for SHIFT-keys
if (((scancode & 0x7F) == 42) || ((scancode & 0x7F) == 54))
{
shift = !(scancode & 0x80);
continue;
}
// Ignore all other RELEASED-codes
if (scancode & 0x80)
last_key = 0;
else if (last_key != scancode)
{
last_key = scancode;
c = keyb_layout[shift][scancode];
if (c > 0)
return c;
}
}
}
}
/*
**
** Serial port I/O functions.
**
*/
/* Comport register locations */
#define DATA 0
#define IER 1
#define EIR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6
#define DLLO 0
#define DLHI 1
/* LCR related constants */
#define BITS_5 0
#define BITS_6 1
#define BITS_7 2
#define BITS_8 3
#define STOP_ONE (0 << 2)
#define STOP_TWO (1 << 2)
#define PARITY_NONE (0 << 3)
#define PARITY_ODD (1 << 3)
#define PARITY_EVEN (3 << 3)
#define PARITY_MARK (6 << 3)
#define PARITY_SPACE (7 << 3)
#define BREAK_CONTROL (1 << 6)
#define DLR_ON (1 << 7)
/* ISR related constants */
#define RxRDY (1 << 0)
#define TBE (1 << 5)
/* Defaults, usually overridden from EFI HCDP table */
static u64_t com_base = CONFIG_KDB_COMPORT;
static u32_t com_baud = CONFIG_KDB_COMSPEED;
static u8_t com_mmio = 0;
void find_serial (void)
{
hcdp_table_t *hcdp_table;
hcdp_dev_t *hcdp_dev;
hcdp_table = (hcdp_table_t *)efi_config_table.find_table(HCDP_TABLE_GUID);
if (hcdp_table == NULL)
return;
hcdp_table = phys_to_virt(hcdp_table);
hcdp_dev = hcdp_table->find(HCDP_DEV_CONSOLE);
if (hcdp_dev == NULL)
return;
switch (hcdp_dev->base_addr.id)
{
case ACPI_MEM_SPACE:
com_mmio = 1;
break;
case ACPI_IO_SPACE:
com_mmio = 0;
break;
default:
return; /* fall back to defaults */
}
com_base = hcdp_dev->base_addr.address ();
if (hcdp_dev->baud)
com_baud = hcdp_dev->baud;
}
static void com_out_u8 (u8_t port, u8_t data)
{
if (com_mmio)
*(u8_t *)(com_base + port) = data;
else
out_u8(com_base + port, data);
}
static u8_t com_in_u8 (u8_t port)
{
if (com_mmio)
return *(u8_t *)(com_base + port);
else
return in_u8(com_base + port);
}
static void init_serial (void)
{
static bool initialized = false;
u16_t dll;
if (initialized)
return;
initialized = true;
find_serial();
if (com_mmio)
{
com_base = phys_to_virt_uc(com_base);
if (!dtrmap.is_mapped ((void *)com_base))
{
translation_t tr (1, translation_t::uncacheable, 1, 1, 0,
translation_t::rwx,
virt_to_phys ((void *)com_base), 0);
dtrmap.add_map (tr, (void *)com_base, HUGE_PGSIZE, 0);
}
}
/* 64-bit division otherwise we'd need __udivsi3 */
dll = 115200UL / com_baud;
com_out_u8 (LCR, DLR_ON);
com_out_u8 (DLLO, dll & 0xff);
com_out_u8 (DLHI, dll >> 8);
com_out_u8 (LCR, BITS_8 | PARITY_NONE | STOP_ONE); /* 8N1 */
}
void putc_serial (char c)
{
while (! (com_in_u8 (LSR) & TBE))
;
com_out_u8 (DATA, c);
if (c == '\n')
putc_serial ('\r');
}
char getc_serial (bool block)
{
if (block)
{
while (! (com_in_u8 (LSR) & RxRDY))
spin (70);
return com_in_u8 (DATA);
}
else
{
if (com_in_u8 (LSR) & RxRDY)
return com_in_u8 (DATA);
else
return -1;
}
}
#if defined(CONFIG_KDB_BREAKIN)
void SECTION (".kdebug") kdebug_check_breakin (void)
{
while (com_in_u8 (LSR) & RxRDY)
if (com_in_u8 (DATA) == 0x1b)
enter_kdebug ("breakin");
}
#endif
#else /* CONFIG_KDB_SKI */
static void init_ski_console (void) SECTION (".init");
static void putc_ski (char) SECTION (".kdebug");
static char getc_ski (bool) SECTION (".kdebug");
kdb_console_t kdb_consoles[] = {
{ "SKI", &init_ski_console, &putc_ski, &getc_ski },
KDB_NULL_CONSOLE
};
word_t kdb_current_console = 0;
void init_ski_console (void)
{
// ia64_ski_ssc (0, 0, 0, 0, IA64_SKI_SSC_CONSOLE_INIT);
}
char getc_ski (bool block)
{
char c;
do {
c = (char)ia64_ski_ssc (0, 0, 0, 0, IA64_SKI_SSC_GETCHAR);
} while (c == '\0');
return c;
}
void putc_ski (char c)
{
ia64_ski_ssc ((word_t)c, 0, 0, 0, IA64_SKI_SSC_PUTCHAR);
if (c == '\n')
putc_ski ('\r');
}
#if defined(CONFIG_KDB_BREAKIN)
void SECTION (".kdebug") kdebug_check_breakin (void)
{
if ( ia64_ski_ssc (0, 0, 0, 0, IA64_SKI_SSC_GETCHAR) == 0x1b)
enter_kdebug("breakin");
}
#endif
#endif

6
kernel/kdb/arch/ia64/itanium/Makeconf
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@ -1,6 +0,0 @@
ifeq ("$(CONFIG_PERFMON)","y")
SOURCES+= kdb/arch/ia64/itanium/perf.cc \
kdb/arch/ia64/itanium/perf_branchtrace.cc \
kdb/arch/ia64/itanium/perf_events.cc \
kdb/arch/ia64/itanium/perf_profile.cc
endif

191
kernel/kdb/arch/ia64/itanium/perf.cc
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@ -1,191 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/itanium/perf.cc
* Description: Itanium performance monitoring functionality
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perf.cc,v 1.8 2004/04/30 03:42:41 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(itanium_perf.h)
#include INC_GLUE(context.h)
#include INC_API(tcb.h)
#include INC_API(schedule.h)
#include <sync.h>
bool kdb_get_perfctr (pmc_itanium_t * pmc, word_t * pmc_mask);
/**
* Set performance counter register.
*/
DECLARE_CMD (cmd_ia64_perf_setreg, ia64_perfmon, 's', "setreg",
"set performance register");
CMD (cmd_ia64_perf_setreg, cg)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
ia64_exception_context_t * user_frame =
(ia64_exception_context_t *) kdb.kdb_current->get_stack_top () - 1;
pmc_itanium_t pmc = 0;
word_t i, reg, pmc_mask;
if (! kdb_get_perfctr (&pmc, &pmc_mask))
return CMD_NOQUIT;
do {
for (i = 1, reg = 0; (i & pmc_mask) == 0; i <<= 1, reg++)
;
reg = get_dec ("Select register", reg);
if (reg == ABORT_MAGIC)
return CMD_NOQUIT;
} while (((1UL << reg) & pmc_mask) == 0);
pmc.ev = 0; // no external visibility
pmc.oi = 0; // no overflow interrupt
pmc.pm = 1; // allow user access
pmc.threshold = 0; // sum up
pmc.ism = 0; // monitor IA32 and IA64 instructions
printf("perfctr: es=%x, umask=%x, raw = %x\n",
pmc.es, pmc.umask, *(word_t *) &pmc);
switch (get_choice ("Priviledge level", "User/Kernel/All", 'a'))
{
case 'u': pmc.plm = pmc_t::user; break;
case 'k': pmc.plm = pmc_t::kernel; break;
case 'a': pmc.plm = pmc_t::both; break;
default:
return CMD_NOQUIT;
}
set_pmc (reg, pmc);
set_pmd (reg, 0);
frame->ipsr.pp = user_frame->ipsr.pp = 1;
return CMD_NOQUIT;
}
extern tcb_t * global_present_list UNIT("kdebug");
extern spinlock_t present_list_lock;
/**
* Enable performance counters for all threads.
*/
DECLARE_CMD (cmd_ia64_perf_enable_all, ia64_perfmon, 'E', "enableall",
"set performance monitoring for all threads");
CMD (cmd_ia64_perf_enable_all, cg)
{
int abort = 1000000;
present_list_lock.lock();
scheduler_t * scheduler = get_current_scheduler();
printf("\n");
/* check whether we have something for this prio */
tcb_t* walk = global_present_list;
do {
ia64_exception_context_t * frame =
(ia64_exception_context_t *) walk->get_stack_top () - 1;
frame->ipsr.pp = 1;
printf(walk->queue_state.is_set(queue_state_t::ready) ? " %p" : "(%p)", walk);
printf("\n");
walk = walk->present_list.next;
if (abort-- == 0)
{
// huha -- something fucked up?
printf("present-list fucked???\n");
return CMD_NOQUIT;
}
} while (walk != global_present_list);
present_list_lock.unlock();
cr_dcr_t dcr = cr_get_dcr ();
dcr.pp = 1;
__asm__ ("mov cr.dcr = %0 " :: "r" (dcr.raw));
return CMD_NOQUIT;
}
/**
* Disable performance counters for all threads.
*/
DECLARE_CMD (cmd_ia64_perf_disable_all, ia64_perfmon, 'D', "disableall",
"disable performance monitoring for all threads");
CMD (cmd_ia64_perf_disable_all, cg)
{
int abort = 1000000;
present_list_lock.lock();
scheduler_t * scheduler = get_current_scheduler();
printf("\n");
/* check whether we have something for this prio */
tcb_t* walk = global_present_list;
do {
ia64_exception_context_t * frame =
(ia64_exception_context_t *) walk->get_stack_top () - 1;
frame->ipsr.pp = 0;
printf(walk->queue_state.is_set(queue_state_t::ready) ? " %p" : "(%p)", walk);
printf("\n");
walk = walk->present_list.next;
if (abort-- == 0)
{
// huha -- something fucked up?
printf("present-list fucked???\n");
return CMD_NOQUIT;
}
} while (walk != global_present_list);
present_list_lock.unlock();
cr_dcr_t dcr = cr_get_dcr ();
dcr.pp = 0;
__asm__ ("mov cr.dcr = %0 " :: "r" (dcr.raw));
return CMD_NOQUIT;
}

158
kernel/kdb/arch/ia64/itanium/perf_branchtrace.cc
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@ -1,158 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/itanium/perf_branchtrace.cc
* Description: Itanium Branch Trace Buffer
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perf_branchtrace.cc,v 1.4 2003/09/24 19:05:07 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(itanium_perf_branchtrace.h)
#include INC_GLUE(context.h)
#include INC_API(tcb.h)
#if defined(CONFIG_KDB_DISAS)
extern "C" int disas (addr_t ip);
#define DISAS(ip) disas (ip)
#else
#define DISAS(ip)
#endif
/**
* Enable/disable the Itanium branch trace buffer.
*/
DECLARE_CMD (cmd_ia64_perf_branchtrace, ia64_perfmon, 'B', "branchtrace",
"configure branch tracing");
CMD (cmd_ia64_perf_branchtrace, cg)
{
pmc_branch_trace_config_t btc;
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
ia64_exception_context_t * user_frame =
(ia64_exception_context_t *) kdb.kdb_current->get_stack_top () - 1;
if (get_choice ("Branch trace", "Enable/Disable", 'e') == 'd')
{
btc.disable ();
frame->ipsr.pp = user_frame->ipsr.pp = 0;
return CMD_NOQUIT;
}
btc.pm = 1;
btc.plm = pmc_t::both;
switch (get_choice ("Branch outcome", "Taken/Not taken/All", 't'))
{
case 't': btc.tm = pmc_branch_trace_config_t::taken; break;
case 'n': btc.tm = pmc_branch_trace_config_t::not_taken; break;
case 'a': btc.tm = pmc_branch_trace_config_t::all; break;
}
switch (get_choice ("Target predication",
"Predicted/Mispredicted/All", 'a'))
{
case 'p': btc.ptm = pmc_branch_trace_config_t::predicted_targets; break;
case 'm': btc.ptm = pmc_branch_trace_config_t::mispredicted_targets; break;
case 'a': btc.ptm = pmc_branch_trace_config_t::all_targets; break;
}
switch (get_choice ("Predicate predication",
"Predicted/Mispredicted/All", 'a'))
{
case 'p': btc.ppm = pmc_branch_trace_config_t::predicted_preds; break;
case 'm': btc.ppm = pmc_branch_trace_config_t::mispredicted_preds; break;
case 'a': btc.ppm = pmc_branch_trace_config_t::all_targets; break;
}
btc.tar = get_choice ("Capture TAR predictions", "y/n", 'y') == 'y';
btc.bpt = get_choice ("Capture TAC predictions", "y/n", 'y') == 'y';
btc.bac = get_choice ("Capture BAC predictions", "y/n", 'y') == 'y';
// Clear trace buffer
pmd_branch_trace_index_t bti;
bti.clear ();
// Enable tracing
btc.activate ();
frame->ipsr.pp = user_frame->ipsr.pp = 1;
return CMD_NOQUIT;
}
/**
* Dump the branch trace buffer.
*/
DECLARE_CMD (cmd_branches_show, ia64_perfmon, 'b', "dumpbranches",
"dump last branches");
CMD (cmd_branches_show, cg)
{
pmd_branch_trace_index_t bti;
word_t n, k;
if (bti.num_entries () == 0)
{
printf ("No branch trace.\n");
return CMD_NOQUIT;
}
printf ("Branch trace (oldest first):\n");
for (n = bti.oldest_idx (), k = bti.num_entries ();
k > 0;
k--, n = bti.next_idx (n))
{
pmd_branch_trace_t bt (n);
if (bt.is_invalid ())
continue;
else if (bt.is_target ())
{
printf (" ===> %p ", bt.address ());
DISAS (bt.canonical_address ());
printf ("\n");
}
else
{
printf ("%s %p ",
bt.is_predicted () ? "(predicted) " : "(mispredicted)",
bt.canonical_address ());
DISAS (bt.canonical_address ());
printf ("\n");
}
}
return CMD_NOQUIT;
}

315
kernel/kdb/arch/ia64/itanium/perf_events.cc
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@ -1,315 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/itanium/perf_events.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perf_events.cc,v 1.4 2003/09/24 19:05:07 skoglund Exp $
*
********************************************************************/
#include <kdb/kdb.h>
#include <kdb/input.h>
#include <debug.h>
#include INC_ARCH(itanium_perf.h)
#define PMC_45 ((1 << 4) | (1 << 5))
#define PMC_67 ((1 << 6) | (1 << 7))
#define PMC_4567 (PMC_45 | PMC_67)
class ia64_perf_event_t
{
public:
class ia64_umask_t {
public:
char * name;
u8_t umask;
};
char * name;
u8_t event_selector;
word_t pmc_mask;
ia64_umask_t umask[5];
};
ia64_perf_event_t perf_events[] =
{
{ "ALAT_REPLACEMENT", 0x38, PMC_4567,
{ { "ALL", 3 }, { "FP", 2 }, { "INT", 1 } }
},
{ "ALAT_INST_CHKA_LDC", 0x36, PMC_4567,
{ { "ALL", 3 }, { "FP", 2 }, { "INT", 1 } }
},
{ "ALAT_INST_FAILED_LDC", 0x37, PMC_4567,
{ { "ALL", 3 }, { "FP", 2 }, { "INT", 1 } }
},
{ "ALL_STOPS_DISPERSED", 0x2f, PMC_4567, { }
},
{ "BRANCH_EVENT", 0x11, PMC_4567, { } },
{ "BRANCH_MULTIWAY.ALL_PATHS", 0x0e, PMC_4567,
{ { "ALL_PREDICTIONS", 0 },
{ "CORRECT_PREDICTIONS", 1 },
{ "WRONG_PATH", 2 },
{ "WRONG_TARGET", 3 } }
},
{ "BRANCH_MULTIWAY.NOT_TAKEN", 0x0e, PMC_4567,
{ { "ALL_PREDICTIONS", 0x8 },
{ "CORRECT_PREDICTIONS", 0x9 },
{ "WRONG_PATH", 0xa },
{ "WRONG_TARGET", 0xb } }
},
{ "BRANCH_MULTIWAY.TAKEN", 0x0e, PMC_4567,
{ { "ALL_PREDICTIONS", 0xc },
{ "CORRECT_PREDICTIONS", 0xd },
{ "WRONG_PATH", 0xe },
{ "WRONG_TARGET", 0xf } }
},
{ "BRANCH_PATH.ALL", 0x0f, PMC_4567,
{ { "NT_OUTCOMES_CORRECTLY_PREDICTED", 0x2 },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0x3 },
{ "NT_OUTCOMES_INCORRECTLY_PREDICTED", 0x0 },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0x1 } }
},
{ "BRANCH_PATH.1ST_STAGE", 0x0f, PMC_4567,
{ { "NT_OUTCOMES_CORRECTLY_PREDICTED", 0x6 },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0x7 },
{ "NT_OUTCOMES_INCORRECTLY_PREDICTED", 0x4 },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0x5 } }
},
{ "BRANCH_PATH.2ND_STAGE", 0x0f, PMC_4567,
{ { "NT_OUTCOMES_CORRECTLY_PREDICTED", 0xa },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0xb },
{ "NT_OUTCOMES_INCORRECTLY_PREDICTED", 0x8 },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0x9 } }
},
{ "BRANCH_PATH.3RD_STAGE", 0x0f, PMC_4567,
{ { "NT_OUTCOMES_CORRECTLY_PREDICTED", 0xe },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0xf },
{ "NT_OUTCOMES_INCORRECTLY_PREDICTED", 0xc },
{ "TK_OUTCOMES_CORRECTLY_PREDICTED", 0xd } }
},
{ "BUS_MEMORY", 0x4a, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_PARTIAL", 0x48, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_ALL", 0x4b, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_DATA", 0x4c, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_HIT", 0x40, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_HITM", 0x41, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_INVAL", 0x4e, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_INVAL_BST", 0x4f, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_INVAL_HITM", 0x4e, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_INVAL_BST_HITM", 0x43, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_IO", 0x51, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_RD_PRTL", 0x4d, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_SNOOPS", 0x46, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_SNOOPS_HITM", 0x45, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_SNOOP_STALL_CYCLES", 0x55, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "BUS_SNOOPQ_REQ", 0x56, PMC_45, { } },
{ "BUS_WR_WB", 0x52, PMC_4567,
{ { "ANY", 1 }, { "SELF", 2 }, { "IO", 4 } }
},
{ "CPU_CPL_CHANGES", 0x34, PMC_4567, { } },
{ "CPU_CYCLES", 0x12, PMC_4567, { } },
{ "DATA_ACCESS_CYCLE", 0x03, PMC_4567, { } },
{ "DATA_EAR_EVENTS", 0x67, PMC_4567, { } },
{ "DATA_PREFERENCES_RETIRED", 0x63, PMC_4567, { } },
{ "DEPENDENCY_ALL_CYCLE", 0x06, PMC_4567, { } },
{ "DEPENDENCY_SCOREBOARD_CYCLE", 0x02, PMC_4567, { } },
{ "DTC_MISSES", 0x60, PMC_4567, { } },
{ "DTLB_INSERTS_HPW", 0x62, PMC_4567, { } },
{ "DTLB_MISSES", 0x61, PMC_4567, { } },
{ "EXPL_STOP_DISPERSED", 0x2e, PMC_4567, { } },
{ "FP_OPS_RETIRED_HI", 0x0a, PMC_4567, { } },
{ "FP_OPS_RETIRED_LO", 0x09, PMC_4567, { } },
{ "FP_FLUSH_TO_ZERO", 0x0b, PMC_4567, { } },
{ "FP_SIR_FLUSH", 0x0c, PMC_4567, { } },
{ "IA32_INST_RETIRED", 0x15, PMC_4567, { } },
{ "IA64_INST_RETIRED", 0x08, PMC_45,
{ { "ALL", 0 }, { "PMC8", 0x3}, { "PMC9", 0x2 } }
},
{ "INST_ACCESS_CYCLE", 0x01, PMC_4567, { } },
{ "INST_DISPERSED", 0x2d, PMC_45, { } },
{ "INST_FAILED_CHKS_RETIRED", 0x35, PMC_4567,
{ { "ALL", 0x3}, { "FP", 0x2 }, { "INTEGER", 0x1 } }
},
{ "INSTRUCTION_EAR_EVENTS", 0x23, PMC_4567, { } },
{ "ISA_TRANSITIONS", 0x14, PMC_4567, { } },
{ "ISB_LINES_IN", 0x26, PMC_4567, { } },
{ "ITLB_INSERT_HPW", 0x28, PMC_4567, { } },
{ "ITLB_MISSES_FETCH", 0x27, PMC_4567, { } },
{ "L1_READ_FORCED_MISSES_RETIRED", 0x6b, PMC_4567, { } },
{ "L1_READ_MISSES_RETIRED", 0x66, PMC_4567, { } },
{ "L1_READS_RETIRED", 0x64, PMC_4567, { } },
{ "L1_DEMAND_READS", 0x20, PMC_4567, { } },
{ "L1I_FILLS", 0x21, PMC_4567, { } },
{ "L1I_PREFETCH_READS", 0x24, PMC_4567, { } },
{ "L2_DATA_REFERENCES", 0x69, PMC_4567,
{ { "ALL", 0x3 }, { "READS", 0x1 }, { "WRITES", 0x2 } }
},
{ "L2_FLUSH_DETAILS", 0x77, PMC_4567,
{ { "ALL", 0x7 },
{ "L2_ST_BUFFER_FLUSH", 0x1 },
{ "L2_ADDR_CONFLICT", 0x2 },
{ "L2_BUS_REJECT", 0x4 },
{ "L2_FULL_FLUSH", 0x8 } }
},
{ "L2_INST_DEMAND_READS", 0x22, PMC_4567, { } },
{ "L2_INST_PREFETCH_READS", 0x25, PMC_4567, { } },
{ "L2_MISSES", 0x6a, PMC_4567, { } },
{ "L2_REFERENCES", 0x68, PMC_4567, { } },
{ "L3_LINES_REPLACED", 0x7f, PMC_4567, { } },
{ "L3_MISSES", 0x7c, PMC_4567, { } },
{ "L3_READS.ALL_READS", 0x7d, PMC_4567,
{ { "ALL", 0xf }, { "HIT", 0xd }, { "MISS", 0xe } }
},
{ "L3_READS.DATA_READS", 0x7d, PMC_4567,
{ { "ALL", 0xb }, { "HIT", 0x9 }, { "MISS", 0xa } }
},
{ "L3_READS.INST_READS", 0x7d, PMC_4567,
{ { "ALL", 0x7 }, { "HIT", 0x5 }, { "MISS", 0x6 } }
},
{ "L3_REFERENCES", 0x7b, PMC_4567, { } },
{ "L3_WRITES.ALL_WRITES", 0x7e, PMC_4567,
{ { "ALL", 0xf }, { "HIT", 0xd }, { "MISS", 0xe } }
},
{ "L3_WRITES.L2_WRITEBACK", 0x7e, PMC_4567,
{ { "ALL", 0xb }, { "HIT", 0x9 }, { "MISS", 0xa } }
},
{ "L3_WRITES.DATA_WRITES", 0x7e, PMC_4567,
{ { "ALL", 0x7 }, { "HIT", 0x5 }, { "MISS", 0x6 } }
},
{ "LOADS_RETIRED", 0x6c, PMC_4567, { } },
{ "MEMORY_CYCLE", 0x07, PMC_4567, { } },
{ "MISALIGNED_LOADS_RETIRED", 0x70, PMC_4567, { } },
{ "MISALIGNED_STORES_RETIRED", 0x71, PMC_4567, { } },
{ "NOPS_RETIRED", 0x30, PMC_45, { } },
{ "PIPELINE_ALL_FLUSH_CYCLE", 0x4, PMC_4567, { } },
{ "PIPELINE_BACKEND_FLUSH_CYCLE", 0x0, PMC_4567, { } },
{ "PIPELINE_FLUSH", 0x33, PMC_4567,
{ { "ALL", 0xf },
{ "IEU_FLUSH", 0x8 },
{ "DTC_FLUSH", 0x4 },
{ "L1D_WAYMP_FLUSH", 0x2 },
{ "OTHER_FLUSH", 0x1 } }
},
{ "PREDICATE_SQUASHED_RETIRED", 0x31, PMC_45, { } },
{ "RSE_LOADS_RETIRED", 0x72, PMC_4567, { } },
{ "RSE_REFERENCES_RETIRED", 0x65, PMC_4567, { } },
{ "STORES_RETIRED", 0x6d, PMC_4567, { } },
{ "UC_LOADS_RETIRED", 0x6e, PMC_4567, { } },
{ "UC_STORES_RETIRED", 0x6f, PMC_4567, { } },
{ "UNSTALLED_BACKEND_CYCLES", 0x05, PMC_4567, { } },
};
bool kdb_get_perfctr (pmc_itanium_t * pmc, word_t * pmc_mask)
{
for (;;)
{
word_t ctr = get_dec ("Performance counter", ~0UL, "list");
if (ctr == ABORT_MAGIC)
return false;
if (ctr == ~0UL)
{
// List performance counters.
word_t size = sizeof (perf_events) / sizeof (ia64_perf_event_t);
for (word_t i = 1; i <= (size + 1) / 2; i++)
{
printf ("%3d - %32s", i, perf_events[i-1].name);
if (i + ((size + 1) / 2) <= size)
printf ("%3d - %32s", i + ((size + 1) / 2),
perf_events[i + ((size + 1) / 2) - 1].name);
printf ("\n");
}
}
else
{
ctr--;
ia64_perf_event_t * p = &perf_events[ctr];
pmc->es = p->event_selector;
pmc->umask = 0;
*pmc_mask = p->pmc_mask;
// Select umask.
if (p->umask[0].name)
{
word_t umask;
do {
for (word_t i = 0; p->umask[i].name && i < 5; i++)
printf("%d=%s, ", i, perf_events[ctr].umask[i].name);
umask = get_dec ("Select umask", 0, NULL);
if (umask == ABORT_MAGIC)
return false;
} while (umask >= 4 || (! p->umask[umask].name));
pmc->umask = p->umask[umask].umask;
printf ("Perf counter: %s.%s\n",
p->name, p->umask[umask].name);
}
else
printf ("Perf counter: %s\n", p->name);
return true;
}
}
}

221
kernel/kdb/arch/ia64/itanium/perf_profile.cc
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@ -1,221 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/itanium/perf_profile.cc
* Description: Continous profiling for Itanium
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perf_profile.cc,v 1.6 2004/02/24 23:54:52 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(itanium_perf.h)
#include INC_GLUE(context.h)
#include INC_GLUE(intctrl.h)
#include INC_API(tcb.h)
#define KNUTH_MAGIC 2654435761
#define PROFILE_SIZE ( CONFIG_PROFILE_SIZE)
#define PROFILE_INTERVAL (-CONFIG_PROFILE_INTERVAL)
bool kdb_get_perfctr (pmc_itanium_t * pmc, word_t * pmc_mask);
static bool profiling_enabled = false;
static word_t profiling_counter = 0;
static word_t profile_table[PROFILE_SIZE];
static void profile_handler (word_t irq, ia64_exception_context_t * frame);
/**
* Enable continous profiling.
*/
DECLARE_CMD (cmd_ia64_perf_profile, ia64_perfmon, 'p', "profile",
"enable continous profiling");
CMD (cmd_ia64_perf_profile, cg)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
ia64_exception_context_t * user_frame =
(ia64_exception_context_t *) kdb.kdb_current->get_stack_top () - 1;
pmc_itanium_t pmc = 0;
word_t i, reg, pmc_mask;
if (! kdb_get_perfctr (&pmc, &pmc_mask))
return CMD_NOQUIT;
do {
for (i = 1, reg = 0; (i & pmc_mask) == 0; i <<= 1, reg++)
;
reg = get_dec ("Select register", reg);
if (reg == ABORT_MAGIC)
return CMD_NOQUIT;
} while (((1UL << reg) & pmc_mask) == 0);
pmc.ev = 0; // no external visibility
pmc.oi = 1; // enable overflow interrupt
pmc.pm = 1; // allow user access
pmc.threshold = 0; // sum up
#ifdef CONFIG_CPU_IA64_ITANIUM2
pmc.enabled = 1;
#endif
pmc.ism = 0; // monitor IA32 and IA64 instructions
switch (get_choice ("Priviledge level", "User/Kernel/All", 'a'))
{
case 'u': pmc.plm = pmc_t::user; break;
case 'k': pmc.plm = pmc_t::kernel; break;
case 'a': pmc.plm = pmc_t::both; break;
default:
return CMD_NOQUIT;
}
if (profiling_enabled)
{
// Disable previous profiling counter.
pmc_t old_pmc = get_pmc (profiling_counter);
old_pmc.plm = pmc_t::none;
set_pmc (profiling_counter, old_pmc);
}
profiling_counter = reg;
profiling_enabled = true;
// Initalise profile table
for (i=0; i < PROFILE_SIZE; i++) {
profile_table[i] = 0;
}
// Enable interrupt vector
cr_ivec_t ivec;
ivec.raw = 0;
ivec.vector = IVEC_PERFMON;
cr_set_pmv (ivec);
get_interrupt_ctrl ()->register_handler (IVEC_PERFMON, profile_handler);
// Initialize performance monitoring registers.
set_pmc (reg, pmc);
set_pmd (reg, ((word_t)PROFILE_INTERVAL & PMD_MASK));
#ifdef CONFIG_CPU_IA64_ITANIUM2
set_pmc (0, 0);
#endif
frame->ipsr.pp = user_frame->ipsr.pp = 1;
return CMD_NOQUIT;
}
/**
* Disable continous profiling.
*/
DECLARE_CMD (cmd_ia64_perf_profile_disable, ia64_perfmon, 'P', "noprofile",
"disable continous profiling");
CMD (cmd_ia64_perf_profile_disable, cg)
{
if (profiling_enabled)
{
// Disable previous profiling counter.
pmc_t old_pmc = get_pmc (profiling_counter);
old_pmc.plm = pmc_t::none;
set_pmc (profiling_counter, old_pmc);
// Disable profiling interrupt.
cr_ivec_t ivec;
ivec.raw = 0;
ivec.m = 1;
cr_set_pmv (ivec);
}
profiling_enabled = false;
return CMD_NOQUIT;
}
static void profile_handler (word_t irq, ia64_exception_context_t * frame)
{
pmc_overflow_t overflow;
word_t hash;
// printf ("profile @ %p\n", frame->iip);
hash = ((word_t)frame->iip * KNUTH_MAGIC) % PROFILE_SIZE;
profile_table[hash] ++;
set_pmd (profiling_counter, ((word_t)PROFILE_INTERVAL & PMD_MASK));
#ifdef CONFIG_CPU_IA64_ITANIUM2
set_pmc (0, 0); // clear freeze bit and overflow bit
#endif
overflow.clr_freeze ();
}
/**
* Dump profile
*/
DECLARE_CMD (cmd_ia64_perf_profile_dump, ia64_perfmon, 'd', "dump",
"dump profile");
CMD (cmd_ia64_perf_profile_dump, cg)
{
word_t i;
set_pmc(0, 1); // set freeze bit
printf("Profile IP hash-table dump:\n");
printf("Bucket\tCount\n");
for (i=0; i < PROFILE_SIZE; i++) {
if (profile_table[i] > 0) {
printf("%d\t%d\n", i, profile_table[i]);
}
}
set_pmc(0, 0); // clear freeze bit
return CMD_NOQUIT;
}

37
kernel/kdb/arch/ia64/itanium2/Makeconf
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@ -1,37 +0,0 @@
######################################################################
##
## Copyright (C) 2003, Karlsruhe University
##
## File path: kdb/arch/ia64/itanium2/Makeconf
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf,v 1.2 2003/09/24 19:05:07 skoglund Exp $
##
######################################################################
ifeq ("$(CONFIG_PERFMON)","y")
SOURCES+= kdb/arch/ia64/itanium/perf.cc \
kdb/arch/ia64/itanium/perf_branchtrace.cc \
kdb/arch/ia64/itanium/perf_events.cc \
kdb/arch/ia64/itanium/perf_profile.cc
endif

110
kernel/kdb/arch/ia64/perf.cc
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@ -1,110 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/perf.cc
* Description: IA64 performance monitoring functionailty
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: perf.cc,v 1.5 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include INC_ARCH(pal.h)
#include INC_ARCH(perf.h)
/*
* We read the perfmon info and mask on first time entering the
* perfmon submenu to avoid doing it on each function
*/
pal_perf_mon_info_t perf_info;
pal_perf_mon_masks_t perf_masks;
/**
* Command group for IA64 performance monitoring functionality.
*/
DECLARE_CMD_GROUP (ia64_perfmon);
/**
* Enter IA64 performance monitoring menu.
*/
DECLARE_CMD (cmd_ia64_perfmon, arch, 'p', "perfmon", "performance monitoring");
CMD (cmd_ia64_perfmon, cg)
{
static bool initialized = false;
if (! initialized)
{
pal_status_e status;
if ((status = pal_perf_mon_info (&perf_masks, &perf_info)) != PAL_OK)
{
printf ("Error: PAL_PERF_MON_INFO => %d\n", (long) status);
return CMD_NOQUIT;
}
initialized = true;
}
return ia64_perfmon.interact (cg, "perfmon");
}
/**
* Dump all performance monitoring configuration and data registers.
*/
DECLARE_CMD (cmd_dump_all_regs, ia64_perfmon, 'a', "dumpregs",
"dump all registers");
CMD (cmd_dump_all_regs, cg)
{
printf ("Performance configuration registers:\n");
for (word_t i = 0; i < 256; i++)
if (perf_masks.is_pmc_implemented (i))
printf (" pmc[%d]%s = %p %s%s\n",
i, i >= 100 ? "" : i >= 10 ? " " : " ",
(word_t) get_pmc (i),
perf_masks.can_count_cycles (i) ? "(cycles) " : "",
perf_masks.can_count_retired_bundles (i) ?
"(retired bundles) " : "");
printf ("\nPerformance data registers:\n");
for (word_t i = 0; i < 256; i++)
if (perf_masks.is_pmd_implemented (i))
printf (" pmd[%d]%s = %p %s%s\n",
i, i >= 100 ? "" : i >= 10 ? " " : " ",
(word_t) get_pmd (i),
perf_masks.can_count_cycles (i) ? "(cycles) " : "",
perf_masks.can_count_retired_bundles (i) ?
"(retired bundles) " : "");
return CMD_NOQUIT;
}

77
kernel/kdb/arch/ia64/pkrs.cc
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@ -1,77 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/pkrs.cc
* Description: Protection key register access
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: pkrs.cc,v 1.6 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include INC_ARCH(pkr.h)
#include INC_ARCH(pal.h)
#include <kdb/cmd.h>
#include <kdb/kdb.h>
/**
* cmd_pkrs: dump protection key registers
*/
DECLARE_CMD (cmd_pkrs, arch, 'P', "pkrs", "dump protection key registers");
CMD(cmd_pkrs, cg)
{
pal_vm_summary_t info;
pal_status_e status;
/*
* Get number of implemented registers.
*/
if ((status = pal_vm_summary (&info)) != PAL_OK)
{
printf ("Error: PAL_VM_SUMMARY => %d\n", status);
return CMD_NOQUIT;
}
int num_pkrs = info.max_pkr + 1;
static const char * rights[] = {
"no rights", "write-only", "read-only", "exec-only",
"read/write", "read/exec", "write/exec", "read/write/exec"
};
printf ("Protection key registers:\n");
for (int i = 0; i < num_pkrs; i++)
{
pkr_t pkr = get_pkr (i);
printf (" pkr[%d]%s = %s key: 0x%5x, %s\n",
i, i < 10 ? " " : "",
pkr.is_valid () ? "valid, " : "invalid,", pkr.key (),
rights[pkr.access_rights ()]);
}
return CMD_NOQUIT;
}

214
kernel/kdb/arch/ia64/prepost.cc
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@ -1,214 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002-2004, Karlsruhe University
*
* File path: kdb/arch/ia64/prepost.cc
* Description: Entry and exit stubs for kernel debugger
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.25 2004/06/02 08:41:42 sgoetz Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/console.h>
#include <linear_ptab.h>
#include INC_ARCH(instr.h)
#include INC_GLUE(context.h)
#include INC_GLUE(registers.h)
#include INC_API(tcb.h)
#if defined(CONFIG_KDB_DISAS)
extern "C" int disas (addr_t ip);
#define DISAS(ip) do { \
printf ("%p: ", ip); \
disas (ip); \
printf ("\n"); \
} while (0)
#define BSRC(ip) printf ("src - ")
#define BDST(ip) printf ("dst - ")
#else /* !CONFIG_KDB_DISAS */
#define DISAS(ip)
#define BSRC(ip) printf ("Branch %p ===> ", ip)
#define BDST(ip) printf ("%p\n", ip)
#endif
bool kdb_t::pre (void)
{
ia64_exception_context_t * frame = (ia64_exception_context_t *) kdb_param;
tcb_t * current = addr_to_tcb (frame);
space_t * space = current->get_space ();
ia64_instr_t i0, i1, i2;
ia64_bundle_t bundle;
if (frame->exception_num == 11)
{
if (space->is_user_area (frame->iip))
{
// Instruction may not be mapped in the DTLB
space->readmem (frame->iip, &bundle.raw64[0]);
space->readmem (addr_offset (frame->iip, sizeof (word_t)),
&bundle.raw64[1]);
}
else
{
// Instruction should be mapped by kernel TR
bundle.raw64[0] = ((word_t *) frame->iip)[0];
bundle.raw64[1] = ((word_t *) frame->iip)[1];
}
i0 = bundle.slot (0);
i1 = bundle.slot (1);
i2 = bundle.slot (2);
}
/*
* Check for single step traps.
*/
if (frame->exception_num == 35 || frame->exception_num == 36)
{
addr_t ip = addr_offset (frame->iipa,
frame->isr.instruction_slot * 6);
if (frame->exception_num == 35)
BSRC (ip);
DISAS (ip);
if (frame->exception_num == 35)
{
ip = addr_offset (frame->iip, frame->ipsr.ri * 6);
BDST (ip);
DISAS (ip);
}
frame->ipsr.ss = 0;
frame->ipsr.tb = 0;
return true;
}
else if (frame->exception_num == 29)
{
addr_t ip = addr_offset (frame->iip, frame->ipsr.ri * 6);
if (frame->isr.rwx == 1)
printf ("Debug exec fault @ %p [current=%t]\n", ip, current);
else
printf ("Debug %s fault @ %p (data @ %p) [current=%t]\n",
frame->isr.rwx == 2 ? "write" :
frame->isr.rwx == 4 ? "read" : "read/write",
ip, frame->ifa, current);
DISAS (ip);
return true;
}
/*
* Check if break instruction is a kdebug operation. Kdebug
* operations have the following format:
*
* { .mlx
* (qp) break.m <type>
* (qp) movl r0 = <arg> ;;
* }
*/
else if (frame->exception_num == 11 &&
bundle.get_template () == ia64_bundle_t::mlx_s3 &&
i0.m_nop.is_break () &&
i2.x_movl.is_movl () && i2.x_movl.reg () == 0)
{
switch (i0.m_nop.immediate ())
{
case 3:
{
//
// enter_kdebug (string)
//
addr_t addr = (addr_t) i2.x_movl.immediate (i1);
if (! space->is_user_area (addr) && frame->ipsr.cpl != 0)
{
printf (TXT_BRIGHT "--- KD# [Invalid string @ %p] ---"
TXT_NORMAL "\n", addr);
}
else
{
char c;
printf (TXT_BRIGHT "--- KD# ");
while (readmem (space, addr, &c) && (c != 0))
{
putc (c);
addr = addr_offset (addr, 1);
}
printf (" ---" TXT_NORMAL "\n");
}
return true;
}
case 1:
//
// PrintChar (r14)
//
printf ("%c", frame->r14);
return false;
case 2:
//
// r14 = GetChar_Blocked ()
//
frame->r14 = getc (true);
return false;
case 4:
//
// r14 = GetChar ()
//
frame->r14 = getc (false);
return false;
default:
printf (TXT_BRIGHT "--- Unknown KDB operation (%d) ---"
TXT_NORMAL "\n", i0.m_nop.immediate ());
return true;
}
}
return true;
}
void kdb_t::post (void)
{
ia64_exception_context_t * frame = (ia64_exception_context_t *) kdb_param;
if (frame->exception_num == 29)
{
if (frame->isr.rwx == 1)
frame->ipsr.id = 1;
else
frame->ipsr.dd = 1;
}
}

66
kernel/kdb/arch/ia64/rrs.cc
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@ -1,66 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/rrs.cc
* Description: Region register access
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: rrs.cc,v 1.5 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include INC_ARCH(rr.h)
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <debug.h>
/**
* cmd_rrs: dump region registers
*/
DECLARE_CMD (cmd_rrs, arch, 'r', "rrs", "dump region registers");
CMD(cmd_rrs, cg)
{
printf ("Region registers:\n");
for (int i = 0; i < 8; i++)
{
rr_t rr = get_rr (i);
word_t size = rr.page_size ();
char ss;
if (size >= GB (1))
ss = 'G', size >>= 30;
else if (size >= MB (1))
ss = 'M', size >>= 20;
else
ss = 'K', size >>= 10;
printf (" rr[%d] = rid: 0x%5x, page size: %3d%cB, VHPT %s\n",
i, rr.region_id (), size, ss,
rr.is_vhpt_enabled () ? "enabled" : "disabled");
}
return CMD_NOQUIT;
}

160
kernel/kdb/arch/ia64/sal.cc
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@ -1,160 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/sal.cc
* Description: SAL table dumping
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: sal.cc,v 1.3 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include INC_ARCH(sal.h)
DECLARE_CMD (cmd_ia64_dumpsal, arch, 'S', "sal", "dump SAL table");
CMD(cmd_ia64_dumpsal, cg)
{
// declared in arch/ia64/sal.cc
extern sal_system_table_t * ia64_sal_table;
if (ia64_sal_table == NULL || !ia64_sal_table->is_valid())
{
printf("SAL table invalid (%p)\n", ia64_sal_table);
return CMD_NOQUIT;
}
printf("OEM id: \"");
for (unsigned i = 0; i < 32; i++)
{
if (ia64_sal_table->oem_id[i] == 0) break;
printf("%c", ia64_sal_table->oem_id[i]);
}
printf("\"\nProduct id: \"");
for (unsigned i = 0; i < 32; i++)
{
if (ia64_sal_table->product_id[i] == 0) break;
printf("%c", ia64_sal_table->oem_id[i]);
}
printf("\"\n");
u8_t * entry = (u8_t *) ia64_sal_table + sizeof (*ia64_sal_table);
for (int i = 0; i < ia64_sal_table->entry_count; i++)
{
switch (*entry)
{
case 0:
{
printf ("\nEntrypoint Descriptor:\n");
sal_entrypoint_desc_t * ed = (sal_entrypoint_desc_t *) entry;
printf (" PAL proc at %p\n"
" SAL proc at %p, gp at %p\n",
ed->pal_proc, ed->sal_proc, ed->sal_global_data);
entry += 48;
break;
}
case 1:
{
//printf ("Memory Descriptor:\n");
entry += 32;
break;
}
case 2:
{
printf ("\nPlatform Features Descriptor:\n");
sal_feature_desc_t * fd = (sal_feature_desc_t *) entry;
static const char * sal_features[] = {"bus lock",
"IRQ redirection hint",
"IPI redirection hint",
"?", "?", "?", "?", "?" };
printf(" Platform features: 0x%x [", fd->raw);
for (word_t i = 0; i < 8; i++)
if (fd->raw & (1UL << i))
printf ("%s%s", sal_features[i],
fd->raw >> (i + 1) ? ", " : "");
printf ("]\n");
entry += 16;
break;
}
case 3:
{
printf ("\nTranslation Register Descriptor:\n");
sal_trans_reg_desc_t* reg = (sal_trans_reg_desc_t *) entry;
printf (" %s translation register # %d\n"
" Covered area: %p\n"
" Page size: %d\n",
reg->reg_type == 0 ? "Instruction" :
reg->reg_type == 1 ? "Data" : "Unknown",
reg->reg_num,
reg->covered_area,
reg->page_size);
entry += 32;
break;
}
case 4:
{
printf ("\nPurge Translation Cache Coherence Descriptor:\n");
sal_purge_tc_domain_desc_t * ptc =
(sal_purge_tc_domain_desc_t *) entry;
printf (" Translation cache coherency domains: %d\n"
" Domain info at %p\n",
ptc->num_domains, ptc->domain_info);
entry += 16;
break;
}
case 5:
{
printf ("\nAP Wakeup Descriptor:\n");
sal_ap_wakeup_desc_t * wd = (sal_ap_wakeup_desc_t *) entry;
printf (" AP wakeup mechanism: %s (%x), IRQ vector: 0x%2x\n",
wd->wakeup_mechanism == 0 ? "external interrupt" :
"unknown", wd->wakeup_mechanism,
wd->irq_vector);
entry += 16;
break;
}
default:
/*
* Unknown SAL entries will always be located at end.
*/
printf ("Unknown SAL entry: %d\n", *entry);
break;
}
}
return CMD_NOQUIT;
}

66
kernel/kdb/arch/ia64/singlestep.cc
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@ -1,66 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, Karlsruhe University
*
* File path: kdb/arch/ia64/singlestep.cc
* Description: Single stepping for IA-64
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: singlestep.cc,v 1.4 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <kdb/kdb.h>
#include INC_GLUE(context.h)
/**
* cmd_singlestep: execute next instrucion in instruction stream
*/
DECLARE_CMD (cmd_singlestep, root, 's', "singlestep",
"single step instrucion");
CMD (cmd_singlestep, cg)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
frame->ipsr.ss = 1;
return CMD_QUIT;
}
/**
* cmd_branchstep: execute instructions until next branch is taken
*/
DECLARE_CMD (cmd_branchstep, root, 'S', "branchstep",
"execute until next taken branch");
CMD (cmd_branchstep, cg)
{
ia64_exception_context_t * frame =
(ia64_exception_context_t *) kdb.kdb_param;
frame->ipsr.tb = 1;
return CMD_QUIT;
}

274
kernel/kdb/arch/ia64/tlb.cc
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@ -1,274 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2003, Karlsruhe University
*
* File path: kdb/arch/ia64/tlb.cc
* Description: TLB and TR management commands
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: tlb.cc,v 1.11 2003/09/24 19:05:06 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include INC_ARCH(pal.h)
#include INC_ARCH(tlb.h)
#include INC_ARCH(trmap.h)
#include INC_ARCH(rr.h)
static void dump_trs (word_t type);
DECLARE_CMD_GROUP (ia64_tlb);
/**
* IA-64 TLB management.
*/
DECLARE_CMD (cmd_ia64_tlb, arch, 't', "tlb", "TLB and TR management");
CMD(cmd_ia64_tlb, cg)
{
return ia64_tlb.interact (cg, "tlb");
}
/**
* Dump IA-64 instruction TRs.
*/
DECLARE_CMD (cmd_ia64_itrs, ia64_tlb, 'i', "itrs", "dump instruction TRs");
CMD(cmd_ia64_itrs, cg)
{
printf ("Instruction translation registers:\n");
dump_trs (0);
return CMD_NOQUIT;
}
/**
* Dump in-memory ITR map.
*/
DECLARE_CMD (cmd_ia64_itrmap, ia64_tlb, 'I', "itrmap",
"dump in-memory ITR map");
CMD(cmd_ia64_itrmap, cg)
{
printf ("In-memory instruction translation mappings:\n");
itrmap.dump ();
return CMD_NOQUIT;
}
/**
* Dump IA-64 data TRs.
*/
DECLARE_CMD (cmd_ia64_dtrs, ia64_tlb, 'd', "dtrs", "dump data TRs");
CMD(cmd_ia64_dtrs, cg)
{
printf ("Data translation registers:\n");
dump_trs (1);
return CMD_NOQUIT;
}
/**
* Dump in-memory DTR map.
*/
DECLARE_CMD (cmd_ia64_dtrmap, ia64_tlb, 'D', "dtrmap",
"dump in-memory DTR map");
CMD(cmd_ia64_dtrmap, cg)
{
printf ("In-memory data translation mappings:\n");
dtrmap.dump ();
return CMD_NOQUIT;
}
void SECTION(SEC_KDEBUG) dump_trs (word_t type)
{
pal_vm_summary_t info;
pal_status_e status;
/*
* Get number of implemented registers.
*/
if ((status = pal_vm_summary (&info)) != PAL_OK)
{
printf ("Error: PAL_VM_SUMMARY => %d\n", status);
return;
}
word_t max_entry = (type == 0) ? info.max_itr_entry : info.max_dtr_entry;
struct {
translation_t tr;
word_t itir;
word_t ifa;
rr_t rr;
} translation;
pal_vm_tr_read_t valbits;
static const char * rights[] = {
"ro", "rx", "rw", "rwx",
"ro/rw", "rx/rwx", "rwx/rw", "xp/rx"
};
static const char * memattrib[] = {
"WB ", "~~~", "~~~", "~~~",
"UC ", "UCe", "WC ", "NaT"
};
/*
* Dump translations.
*/
printf (" %9s%16s %16s PAD Priv PSize Key RID Mem Access\n",
"", "Virt", "Phys");
for (word_t i = 0; i <= max_entry; i++)
{
status = pal_vm_tr_read (i, type, &translation, &valbits);
if (status != PAL_OK)
{
printf ("Error: PAL_VM_TR_READ => %d\n", status);
continue;
}
word_t pgsz = (translation.itir & 0xff) >> 2;
printf (" %ctr[%d]%s %p => %p %c%c%c %4d ",
(type == 0 ? 'i' : 'd'), i, (i < 10 ? " " : ""),
translation.ifa & ~((1 << 12) - 1),
translation.tr.phys_addr (),
translation.tr.is_present () ? 'p' : '~',
translation.tr.is_accessed () ? 'a' : '~',
translation.tr.is_dirty () ? 'd' : '~',
translation.tr.privilege_level ());
printf ("%3d%cB %5x %5x %s %s\n",
1 << (pgsz - ((pgsz >= 30) ? 30 : (pgsz >= 20) ? 20 : 10)),
((pgsz >= 30) ? 'G' : (pgsz >= 20) ? 'M' : 'K'),
(translation.itir >> 8) & 0xfffff,
translation.rr.region_id (),
(valbits.memory_attributes_valid ?
memattrib[translation.tr.memattrib ()] : "~~~"),
(valbits.access_right_valid ?
rights[translation.tr.access_rights ()] : "~"));
}
}
void print_size (word_t k) __attribute__ ((noinline));
void print_size (word_t k)
{
if (k >= 60)
printf ("%dbits ", k);
else
printf (" %d%c",
1UL << (k - ((k>=50) ? 50 : (k>=40) ? 40 : (k>=30) ? 30 :
(k>=20) ? 20 : 10)),
(k>=50) ? 'P' : (k>=40) ? 'T' : (k>=30) ? 'G' :
(k>=20) ? 'M' : 'K');
}
/**
* cmd_tlb_info: dump TLB information
*/
DECLARE_CMD (cmd_tlb_info, ia64_tlb, 't', "info", "dump TLB information");
CMD(cmd_tlb_info, cg)
{
pal_vm_summary_t summary;
pal_vm_info_t info;
pal_status_e status;
if ((status = pal_vm_summary (&summary)) != PAL_OK)
{
printf ("Error: PAL_VM_SUMMARY => %d\n", status);
return CMD_NOQUIT;
}
printf ("TLB info:\n");
pal_vm_info_t::type_e type = pal_vm_info_t::code;
do {
for (word_t i = 0; i < summary.num_tc_levels; i++)
{
if ((status = pal_vm_info (i, type, &info)) != PAL_OK)
continue;
printf (" %cTLB L%d: %4d entries ",
type == pal_vm_info_t::code ? 'I' : 'D',
i+1, info.num_entries);
if (info.num_ways == 1)
printf ("(direct)");
else
printf ("(%d-way)", info.num_ways);
if (info.unified)
printf (" UNIFIED");
if (info.unified)
printf (" OPTIMIZED");
printf (" (sizes:");
for (word_t k = 12; k < 64; k++)
if (info.page_size_mask & (1UL << k))
print_size (k);
printf (")\n");
}
if (type == pal_vm_info_t::code)
type = pal_vm_info_t::data;
else
type = pal_vm_info_t::none;
} while (type != pal_vm_info_t::none);
printf ("\nTR info:\n");
printf (" Num ITRs: %3d\n Num DTRs: %3d\n",
summary.max_itr_entry+1, summary.max_dtr_entry+1);
word_t insertable, purgeable;
if ((status = pal_vm_page_size (&insertable, &purgeable)) != PAL_OK)
{
printf ("Error: PAL_VM_PAGE_SIZE => %d\n", (long) status);
return CMD_NOQUIT;
}
printf ("\nPage size info:\n Insertable:");
for (word_t k = 12; k < 64; k++)
if (insertable & (1UL << k))
print_size (k);
printf ("\n Purgeable: ");
for (word_t k = 12; k < 64; k++)
if (purgeable & (1UL << k))
print_size (k);
printf ("\n");
return CMD_NOQUIT;
}

41
kernel/kdb/arch/mips32/Makeconf
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@ -1,41 +0,0 @@
######################################################################
##
## Copyright (C) 2006, Karlsruhe University
##
## File path: kdb/arch/mips32/Makeconf
## Description:
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf,v 1.1 2006/02/23 21:07:42 ud3 Exp $
##
######################################################################
SOURCES += ${addprefix kdb/arch/mips32/, prepost.cc breakin.cc }
SOURCES += kdb/generic/linear_ptab_dump.cc
ifeq ("$(CONFIG_NEW_MDB)","y")
SOURCES+= kdb/generic/mdb.cc
else
SOURCES+= kdb/generic/mapping.cc
endif

48
kernel/kdb/arch/mips32/breakin.cc
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@ -1,48 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2006, Karlsruhe University
*
* File path: kdb/arch/mips32/breakin.cc
* Description: Asynchronous KDB entry check for MIPS32
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: breakin.cc,v 1.1 2006/02/23 21:07:42 ud3 Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/console.h>
#if defined(CONFIG_KDB_BREAKIN)
void SECTION(".kdebug") kdebug_check_breakin(void) {
switch( getc(false) ) {
case '\e':
enter_kdebug("KDB Breakin");
return;
default:
return;
}
}
#endif

47
kernel/kdb/arch/mips32/prepost.cc
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@ -1,47 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2006, Karlsruhe University
*
* File path: kdb/arch/mips32/prepost.cc
* Description: KDB entry/exit hooks for MIPS32
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.1 2006/02/23 21:07:42 ud3 Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(cp0regs.h)
#include INC_API(tcb.h)
bool kdb_t::pre() {
word_t entryhi = read_32bit_cp0_register(CP0_ENTRYHI);
word_t epc = read_32bit_cp0_register(CP0_EPC);
word_t badvaddr = read_32bit_cp0_register(CP0_BADVADDR);
printf ("\t-- asid = %d, epc = 0x%x, badvaddr = 0x%x --\n", entryhi&0xFF, epc, badvaddr);
return true;
}
void kdb_t::post() { }

9
kernel/kdb/arch/mips64/Makeconf
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@ -1,9 +0,0 @@
SOURCES += ${addprefix kdb/arch/mips64/, prepost.cc tlb.cc cpuid.cc reboot.cc cp0.cc watch.cc frame.cc}
ifeq ("$(CONFIG_KDB_DISAS)","y")
SOURCES+= kdb/arch/mips64/disas.cc
endif
SOURCES += kdb/generic/linear_ptab_dump.cc \
kdb/generic/mapping.cc

165
kernel/kdb/arch/mips64/cp0.cc
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@ -1,165 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/cp0.cc
* Description: MIPS-64 CPUID
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: cp0.cc,v 1.2 2003/09/24 19:05:08 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(mips_cpu.h)
#include INC_ARCH(cpu.h)
/**
* cmd_dpuid: dump CPU ID
*/
DECLARE_CMD (cmd_cp0, arch, '0', "dumpcp0", "dump cp0 registers");
typedef struct
{
char *name;
int num;
int word64;
} cp0_reg;
/* Coprocessor 0 register names */
#define INDEX 0
#define RANDOM 1
#define ENTRYLO0 2
#define ENTRYLO1 3
#define CONTEXT 4
#define PAGEMASK 5
#define WIRED 6
#define BADVADDR 8
#define COUNT 9
#define ENTRYHI 10
#define COMPARE 11
#define STATUS 12
#define CAUSE 13
#define EPC 14
#define PRID 15
#define CONFIG 16
#define LLADDR 17
#define WATCHLO 18
#define WATCHHI 19
#define XCONTEXT 20
#define FRAMEMASK 21
#define DIAGNOSTIC 22
#define PERFORMANCE 25
#define ECC 26
#define CACHEERR 27
#define TAGLO 28
#define TAGHI 29
#define ERROREPC 30
static cp0_reg regs[] =
{
{ "BadVaddr", BADVADDR, 1 },
{ "CacheErr", CACHEERR, 0 },
{ "Cause", CAUSE, 0 },
{ "Compare", COMPARE, 0 },
{ "Config", CONFIG, 0 },
{ "Context", CONTEXT, 1 },
{ "Count", COUNT, 0 },
{ "ECC", ECC, 0 },
{ "EntryHi", ENTRYHI, 1 },
{ "EntryLo0", ENTRYLO0, 1 },
{ "EntryLo1", ENTRYLO1, 1 },
{ "EPC", EPC, 1 },
{ "ErrorEPC", ERROREPC, 1 },
{ "Index", INDEX, 0 },
{ "LLaddr", LLADDR, 0 },
{ "PageMask", PAGEMASK, 0 },
{ "PerfCount", PERFORMANCE, 0 },
{ "PRID", PRID, 0 },
{ "Random", RANDOM, 0 },
{ "Status", STATUS, 0 },
{ "TagHi0", TAGHI, 0 },
{ "TagLo0", TAGLO, 0 },
{ "WatchHi", WATCHHI, 0 },
{ "WatchLo", WATCHLO, 0 },
{ "Wired", WIRED, 0 },
{ "XContext", XCONTEXT, 1 },
{ 0, 0, 0 }
};
word_t read_cp0_reg(word_t i)
{
word_t ret;
switch (i) {
case INDEX: ret = read_32bit_cp0_register($0 ); break;
case RANDOM: ret = read_32bit_cp0_register($1 ); break;
case ENTRYLO0: ret = read_64bit_cp0_register($2 ); break;
case ENTRYLO1: ret = read_64bit_cp0_register($3 ); break;
case CONTEXT: ret = read_64bit_cp0_register($4 ); break;
case PAGEMASK: ret = read_32bit_cp0_register($5 ); break;
case WIRED: ret = read_32bit_cp0_register($6 ); break;
case BADVADDR: ret = read_64bit_cp0_register($8 ); break;
case COUNT: ret = read_32bit_cp0_register($9 ); break;
case ENTRYHI: ret = read_64bit_cp0_register($10); break;
case COMPARE: ret = read_32bit_cp0_register($11); break;
case STATUS: ret = read_32bit_cp0_register($12); break;
case CAUSE: ret = read_32bit_cp0_register($13); break;
case EPC: ret = read_64bit_cp0_register($14); break;
case PRID: ret = read_32bit_cp0_register($15); break;
case CONFIG: ret = read_32bit_cp0_register($16); break;
case LLADDR: ret = read_32bit_cp0_register($17); break;
case WATCHLO: ret = read_32bit_cp0_register($18); break;
case WATCHHI: ret = read_32bit_cp0_register($19); break;
case XCONTEXT: ret = read_64bit_cp0_register($20); break;
case FRAMEMASK: ret = read_64bit_cp0_register($21); break;
case DIAGNOSTIC: ret = read_64bit_cp0_register($22); break;
case PERFORMANCE: ret = read_32bit_cp0_register($25); break;
case ECC: ret = read_32bit_cp0_register($26); break;
case CACHEERR: ret = read_32bit_cp0_register($27); break;
case TAGLO: ret = read_32bit_cp0_register($28); break;
case TAGHI: ret = read_32bit_cp0_register($29); break;
case ERROREPC: ret = read_64bit_cp0_register($30); break;
default: ret = 0x0000deadbeef0000UL;
}
return ret;
}
CMD (cmd_cp0, cg)
{
word_t x;
printf("Dumping Contents of CP0 Registers\n");
x = 0;
while (regs[x].name) {
if (regs[x].word64)
printf(" %12s [%2d] 0x%016lx\n", regs[x].name,
regs[x].num, read_cp0_reg(regs[x].num));
else
printf(" %12s [%2d] 0x%08lx\n", regs[x].name,
regs[x].num, read_cp0_reg(regs[x].num));
x++;
}
return CMD_NOQUIT;
}

130
kernel/kdb/arch/mips64/cpuid.cc
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@ -1,130 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/cpuid.cc
* Description: MIPS-64 CPUID
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: cpuid.cc,v 1.6 2003/11/18 02:03:27 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(mips_cpu.h)
#include INC_ARCH(cpu.h)
/**
* cmd_dpuid: dump CPU ID
*/
DECLARE_CMD (cmd_cpuid, arch, 'C', "cpuid", "dump CPUID");
CMD (cmd_cpuid, cg)
{
word_t prid = read_32bit_cp0_register(CP0_PRID);
word_t config = read_32bit_cp0_register(CP0_CONFIG);
int icache_size, dcache_size, icache_width, dcache_width;
int icache_ways, dcache_ways;
static const char * pattern[] = {
"D Doubleword every cycle",
"DDxDDx 2 Doublewords every 3 cycles",
"DDxxDDxx 2 Doublewords every 4 cycles",
"DxDxDxDx 2 Doublewords every 4 cycles",
"DDxxxDDxxx 2 Doublewords every 5 cycles",
"DDxxxxDDxxxx 2 Doublewords every 6 cycles",
"DxxDxxDxxDxx 2 Doublewords every 6 cycles",
"DDxxxxxxDDxxxxxx 2 Doublewords every 8 cycles",
"DxxxDxxxDxxxDxxx 2 Doublewords every 8 cycles",
};
printf ("CPUID: ");
switch (prid & MIPS_IMP_MASK)
{
case MIPS_IMP_SB1:
printf("Sibyte SB1, Rev %d\n", prid&0x00FF); break;
case MIPS_IMP_RC64574:
printf("IDT RC64574/2, Rev %d\n", prid&0x00FF); break;
case MIPS_IMP_R4700:
printf("R4700, Rev %d.%d\n", (prid&0x00F0)>>4, prid&0x000F); break;
case MIPS_IMP_VR41XX:
printf("NEC ");
switch (prid & MIPS_REV_MASK_VR)
{
case MIPS_REV_VR4121:
printf("vr4121 rev %d\n", prid&0xf); break;
case MIPS_REV_VR4181:
printf("vr4181 rev %d\n", prid&0xf); break;
default:
printf("unknown\n");
}
break;
default:
printf("unknown CP0_PRID=%8x\n", prid);
}
switch (prid & MIPS_IMP_MASK)
{
case MIPS_IMP_VR41XX:
icache_width = 16 << ((config>>5)&1);
dcache_width = 16 << ((config>>4)&1);
icache_size = (1<<10) << ((config>>9)&7);
dcache_size = (1<<10) << ((config>>6)&7);
icache_ways = dcache_ways = 1;
break;
case MIPS_IMP_RC64574:
case MIPS_IMP_R4700:
default:
icache_width = 16 << ((config>>5)&1);
dcache_width = 16 << ((config>>4)&1);
icache_size = (1<<12) << ((config>>9)&7);
dcache_size = (1<<12) << ((config>>6)&7);
icache_ways = dcache_ways = 2;
}
switch (prid & MIPS_IMP_MASK)
{
case MIPS_IMP_VR41XX:
printf("MIPS16 is %s\n", (config>>20) ? "available" : "disabled");
break;
case MIPS_IMP_RC64574:
printf("Data transmit pattern: %s\n", pattern[(config>>24)&0xf]);
printf("System clock is CPU clock divided by %d\n", 2 + (config>>28) & 7);
printf("Fast Multiply is %s\n", (config>>31) ? "enabled" : "disabled");
break;
case MIPS_IMP_R4700:
printf("Data transmit pattern: %s\n", pattern[(config>>24)&0xf]);
printf("System clock is CPU clock divided by %d\n", 2 + (config>>28) & 7);
printf("Master-Checker Mode is %s\n", (config>>31) ? "enabled" : "disabled");
break;
default:;
}
/*XXX secondary cache probes */
printf("Detected cache: icache = %dk, %d bytes per line, %d way associative\n",
icache_size/1024, icache_width, icache_ways);
printf(" dcache = %dk, %d bytes per line, %d way associative\n",
dcache_size/1024, dcache_width, dcache_ways);
return CMD_NOQUIT;
}

95
kernel/kdb/arch/mips64/disas.cc
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@ -1,95 +0,0 @@
/****************************************************************************
*
* Copyright (C) 2003, National ICT Australia (NICTA)
*
* File path: kdb/arch/mips64/disas.cc
* Description: Mips disassembler support.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*
***************************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
/* This is an ugly hack to incorporate the disassembler. It lives outside
* the kernel tree in the contrib branch, so we have to 'include' it
* in our source.
*/
#ifndef PARAMS
# define PARAMS(a) a
#endif
/* Undefine conflicting macros. */
#undef MB
#include "../../contrib/disas/mips.h"
#include "../../contrib/disas/mips-opc.cc"
#include "../../contrib/disas/mips-dis.cc"
/* Undefine conflicting macros. */
#undef MB
#include INC_GLUE(context.h)
DECLARE_CMD (cmd_disasm, arch, 'D', "disasm", "Disassemble");
int print_insn( unsigned long memaddr, unsigned long insn )
{
return print_insn_mips ( memaddr, insn, 0);
}
static void print_address( unsigned long addr )
{
printf( "0x%016x", addr );
}
static void dbg_addr_disasm( word_t addr )
{
u32_t insn = *(u32_t *)addr;
printf( "%016x: %08x\t", addr, insn );
print_insn( addr, insn );
printf( "\n" );
}
CMD(cmd_disasm, cg)
{
int i;
mips64_irq_context_t *frame = (mips64_irq_context_t *)(kdb.kdb_param);
// Ask for the start address.
word_t addr = get_hex( "Disassemble address", frame->epc );
// Until requested to quit, dump a page of disassembled code.
do {
for( i = 0; i < 24; i++ ) {
dbg_addr_disasm( addr );
addr += sizeof(u32_t);
}
} while( get_choice("continue?", "Continue/Quit", 'c') != 'q' );
return CMD_NOQUIT;
}

188
kernel/kdb/arch/mips64/frame.cc
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@ -1,188 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/frame.cc
* Description: Exception frame dumping
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: frame.cc,v 1.9 2004/01/06 01:12:36 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_GLUE(context.h)
#include INC_API(tcb.h)
extern tcb_t * kdb_get_tcb();
void SECTION(SEC_KDEBUG) mips64_dump_frame(mips64_irq_context_t *context)
{
printf ("== Stack frame: %p == \n", context);
printf ("== STATUS: %8x == CAUSE: %16lx == EPC: %16lx\n", context->status, context->cause, context->epc);
printf ("at = %16lx, v0 = %16lx, v1 = %16lx, sp = %16lx\n", context->at, context->v0, context->v1, context->sp);
printf ("a0 = %16lx, a1 = %16lx, a2 = %16lx, a3 = %16lx\n", context->a0, context->a1, context->a2, context->a3);
printf ("t0 = %16lx, t1 = %16lx, t2 = %16lx, t3 = %16lx\n", context->t0, context->t1, context->t2, context->t3);
printf ("t4 = %16lx, t5 = %16lx, t6 = %16lx, t7 = %16lx\n", context->t4, context->t5, context->t6, context->t7);
printf ("s0 = %16lx, s1 = %16lx, s2 = %16lx, s3 = %16lx\n", context->s0, context->s1, context->s2, context->s3);
printf ("s4 = %16lx, s5 = %16lx, s6 = %16lx, s7 = %16lx\n", context->s4, context->s5, context->s6, context->s7);
printf ("t8 = %16lx, t9 = %16lx, s8 = %16lx, gp = %16lx\n", context->t8, context->t9, context->s8, context->gp);
printf ("ra = %16lx, hi = %16lx, lo = %16lx\n", context->ra, context->hi, context->lo);
}
void SECTION(SEC_KDEBUG) dump_fprs( tcb_t *tcb )
{
u64_t * fprs = (u64_t *)&tcb->resources;
for (int i = 0; i < 32; i++)
printf ("f%d\t= %16lx\n", i, fprs[i]);
printf("FPCSR\t= %16lx\n", fprs[32]);
}
/**
* cmd_dump_current_frame: show exception frame of current thread
*/
DECLARE_CMD (cmd_dump_current_frame, root, ' ', "frame",
"show current user exception frame");
CMD (cmd_dump_current_frame, cg)
{
mips64_irq_context_t *frame = (mips64_irq_context_t *)(kdb.kdb_param);
mips64_dump_frame(frame);
// printf("tcb = %p\n", addr_to_tcb((addr_t)kdb.kdb_param));
// printf("stack = %p\n",addr_to_tcb((addr_t)kdb.kdb_param)->stack);
return CMD_NOQUIT;
}
/**
* cmd_dump_frame: show exception frame
*/
DECLARE_CMD (cmd_dump_frame, root, 'F', "dumpframe",
"show exception frame");
mips64_irq_context_t SECTION(SEC_KDEBUG) * get_frame()
{
space_t * space = get_current_space();
if (!space) space = get_kernel_space();
word_t val = get_hex("tcb/tid/addr", (word_t)space->get_tcb(kdb.kdb_param), "current");
mips64_irq_context_t * frame;
if (val == ABORT_MAGIC)
return NULL;
if (!space->is_tcb_area((addr_t)val) &&
((val & (~0xffful)) != (word_t)get_idle_tcb()))
{
threadid_t tid;
tid.set_raw(val);
frame = (mips64_irq_context_t *)((word_t)space->get_tcb(tid) + MIPS64_PAGE_SIZE);
frame --;
} else
{
frame = (mips64_irq_context_t *)val;
if (frame == (mips64_irq_context_t *) addr_to_tcb ((addr_t) val))
{
frame = (mips64_irq_context_t *)((word_t)frame + MIPS64_PAGE_SIZE);
frame --;
}
}
return frame;
}
CMD (cmd_dump_frame, cg)
{
mips64_irq_context_t *frame = get_frame();
if (frame)
mips64_dump_frame(frame);
return CMD_NOQUIT;
}
/**
* cmd_find_frame: search for an exception frame
*/
DECLARE_CMD (cmd_find_frame, root, 's', "findframe",
"search for an exception frame");
CMD (cmd_find_frame, cg)
{
mips64_irq_context_t *frame, *search;
space_t * space = get_current_space();
word_t val = get_hex("tcb/tid/addr", (word_t)space->get_tcb(kdb.kdb_param), "current");
word_t *addr;
if (val == ABORT_MAGIC)
return CMD_NOQUIT;
if (!space->is_tcb_area((addr_t)val) &&
((val & (~(MIPS64_PAGE_SIZE-1))) != (word_t)get_idle_tcb()))
{
threadid_t tid;
tid.set_raw(val);
frame = (mips64_irq_context_t *)((word_t)space->get_tcb(tid) + MIPS64_PAGE_SIZE);
frame --;
} else
{
frame = (mips64_irq_context_t *) ((val & (~(MIPS64_PAGE_SIZE-1))) + MIPS64_PAGE_SIZE);
frame --;
}
for (addr = (word_t *) frame; (word_t) addr >= (word_t) frame - 2048; addr --) {
search = (mips64_irq_context_t *)addr;
if ((search->status & ~0x3ff1f) == 0x40000e0)
mips64_dump_frame(search);
}
return CMD_NOQUIT;
}
/**
* cmd_dump_fprs: dump floating point registers
*/
DECLARE_CMD (cmd_dump_fprs, root, 'f', "fpr",
"show floating point registers");
CMD (cmd_dump_fprs, cg)
{
tcb_t * tcb = kdb_get_tcb();
if (tcb) {
tcb->resources.mips64_fpu_spill( tcb );
dump_fprs( tcb );
}
return CMD_NOQUIT;
}

45
kernel/kdb/arch/mips64/prepost.cc
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@ -1,45 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/prepost.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.5 2003/09/24 19:05:08 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(mipsregs.h)
#include INC_API(tcb.h)
bool kdb_t::pre()
{
u32_t entryhi = read_32bit_cp0_register(CP0_ENTRYHI);
printf ("-- current ASID is %d, CPU %d --\n", entryhi&0xFF, get_current_cpu());
return true;
}
void kdb_t::post() { }

57
kernel/kdb/arch/mips64/reboot.cc
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@ -1,57 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002-2003, University of New South Wales
*
* File path: kdb/arch/mips64/reboot.cc
* Description: MIPS-64 system reset
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: reboot.cc,v 1.4 2003/09/24 19:05:08 skoglund Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_ARCH(mips_cpu.h)
#include INC_ARCH(cpu.h)
#include INC_API(smp.h)
/*
* Reboot the box
*/
DECLARE_CMD (cmd_reboot, root, '6', "reset", "Reset system");
CMD (cmd_reboot, cg)
{
void (*mips64_reboot_cpu)(void) = (void (*)(void))0xffffffffbfc00000UL;
#ifdef CONFIG_SMP
if (get_current_cpu() != 0)
xcpu_request (0,(xcpu_handler_t)0xffffffffbfc00000UL);
else
#endif
mips64_reboot_cpu();
return CMD_NOQUIT;
}

190
kernel/kdb/arch/mips64/tlb.cc
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@ -1,190 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/tlb.cc
* Description: TLB management commands
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: tlb.cc,v 1.5 2003/11/17 05:42:14 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include INC_ARCH(tlb.h)
#include INC_PLAT(config.h)
#include INC_ARCH(mipsregs.h)
#include INC_GLUE(context.h)
DECLARE_CMD_GROUP (mips64_tlb);
/**
* cmd_mips64_tlb: Mips64 TLB management.
*/
DECLARE_CMD (cmd_mips64_tlb, arch, 't', "tlb", "TLB management");
CMD(cmd_mips64_tlb, cg)
{
return mips64_tlb.interact (cg, "tlb");
}
/**
* cmd_mips64_dum: dump Mips64 TLB
*/
DECLARE_CMD (cmd_mips64_dum, mips64_tlb, 'd', "dump", "dump hardware TLB");
CMD(cmd_mips64_dum, cg)
{
word_t i, save;
static const char * pagemask[] = {
" 4k", " 8k", " 16k", " 32k",
" 64k", "128k", "256k", " 1M",
" 2M", " 4M", " 8M", " 16M",
" 32M", " 64M", "128M", "256M",
};
static const char * cache[] = {
"Wthr ", "WthrA", "Off ", "Wb ",
"CoEx ", "CoCOW", "CoCUW", "Accel"
};
__asm__ __volatile__ (
"dmfc0 %0, "STR(CP0_ENTRYHI)"\n\t"
: "=r" (save)
);
printf ("Index EntryHi EntryLo0 (cache v d) EntryLo1 (cache v d) | Size ASID Global\n");
for (i=0; i<CONFIG_MIPS64_TLB_SIZE; i++)
{
word_t hi, lo0, lo1, mask, size;
__asm__ __volatile__ (
"mtc0 %4,"STR(CP0_INDEX)"\n\t"
"nop;nop;nop;tlbr;nop;nop;nop;nop\n\t"
"dmfc0 %0,"STR(CP0_ENTRYHI)"\n\t"
"dmfc0 %1,"STR(CP0_ENTRYLO0)"\n\t"
"dmfc0 %2,"STR(CP0_ENTRYLO1)"\n\t"
"mfc0 %3,"STR(CP0_PAGEMASK)"\n\t"
: "=r" (hi), "=r" (lo0), "=r" (lo1), "=r" (mask)
: "r" (i)
);
size = 0;
mask >>= 13;
while (mask&1)
{
mask >>= 1;
size ++;
}
printf("%2d: %p %8lx (%s %d %d) %8lx (%s %d %d) | %s %3d %s\n",
i, hi,
lo0, cache[(lo0&0x38)>>3], (lo0>>1)&1, (lo0>>2)&1,
lo1, cache[(lo1&0x38)>>3], (lo1>>1)&1, (lo1>>2)&1,
pagemask[size], hi&0xFF, lo0&1 ? "Yes" : " No");
}
__asm__ __volatile__ (
"dmtc0 %0, "STR(CP0_ENTRYHI)"\n\t"
: : "r" (save)
);
return CMD_NOQUIT;
}
/**
* cmd_mips64_tran: translate Mips64 TLB
*/
DECLARE_CMD (cmd_mips64_trans, mips64_tlb, 't', "translate", "translate TLB");
CMD(cmd_mips64_trans, cg)
{
word_t i, save;
__asm__ __volatile__ (
"dmfc0 %0, "STR(CP0_ENTRYHI)"\n\t"
: "=r" (save)
);
printf ("Index (virt) Even Page (phys) | (virt) Odd Page (phys) ASID\n");
for (i=0; i<CONFIG_MIPS64_TLB_SIZE; i++)
{
word_t hi, lo0, lo1, mask, size;
__asm__ __volatile__ (
"mtc0 %4,"STR(CP0_INDEX)"\n\t"
"nop;nop;nop;tlbr;nop;nop;nop;nop\n\t"
"dmfc0 %0,"STR(CP0_ENTRYHI)"\n\t"
"dmfc0 %1,"STR(CP0_ENTRYLO0)"\n\t"
"dmfc0 %2,"STR(CP0_ENTRYLO1)"\n\t"
"dmfc0 %3,"STR(CP0_PAGEMASK)"\n\t"
: "=r" (hi), "=r" (lo0), "=r" (lo1), "=r" (mask)
: "r" (i)
);
size = 0;
mask >>= 13;
while (mask&1)
{
mask >>= 1;
size ++;
}
printf("%2d: ", i);
if (lo0&2)
printf("%p -> %p", (hi&(~((1<<13)-1))), (lo0>>6)<<CONFIG_MIPS64_VPN_SHIFT);
else
printf("------------------------------------");
printf(" | ");
if (lo1&2)
printf("%p -> %p", (hi&(~((1<<13)-1)))+(1<<(size+12)), (lo1>>6)<<CONFIG_MIPS64_VPN_SHIFT);
else
printf("------------------------------------");
if (lo0&1)
printf(" all\n");
else
printf(" %3d\n", hi&0xFF);
}
__asm__ __volatile__ (
"dmtc0 %0, "STR(CP0_ENTRYHI)"\n\t"
: : "r" (save)
);
return CMD_NOQUIT;
}
/**
* cmd_tlb_info: dump TLB information
*/
DECLARE_CMD (cmd_tlb_info, mips64_tlb, 'i', "info", "dump TLB information");
CMD(cmd_tlb_info, cg)
{
printf("tlb info\n");
return CMD_NOQUIT;
}

103
kernel/kdb/arch/mips64/watch.cc
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@ -1,103 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: kdb/arch/mips64/watch.cc
* Description: MIPS WATCH point
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: watch.cc,v 1.3 2004/04/05 06:22:15 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/cmd.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(mipsregs.h)
DECLARE_CMD_GROUP (watchpoint);
/**
* cmd_mips64_watch: Mips64 WATCH management.
*/
DECLARE_CMD (cmd_mips64_watch, arch, 'w', "watch", "MIPS Watchpoint");
CMD(cmd_mips64_watch, cg)
{
return watchpoint.interact (cg, "watch");
}
/**
* cmd_mips64_wshow: show current
*/
DECLARE_CMD (cmd_mips64_wset, watchpoint, 's', "set", "set watch point");
CMD(cmd_mips64_wset, cg)
{
word_t addr = get_hex ("Phys Address", 0x0, NULL);
char r = get_choice ("Watch read access", "y/n", 'y');
char w = get_choice ("Watch write access", "y/n", 'y');
u32_t watchlo = (u32_t)addr & (~3);
u32_t watchhi = (addr>>32)&0xF;
if (r == 'y')
watchlo |= 2;
if (w == 'y')
watchlo |= 1;
write_32bit_cp0_register(CP0_WATCHLO, watchlo);
write_32bit_cp0_register(CP0_WATCHHI, watchhi);
return CMD_NOQUIT;
}
/**
* cmd_mips64_wshow: show current
*/
DECLARE_CMD (cmd_mips64_wshow, watchpoint, 'w', "show", "show watch status");
CMD(cmd_mips64_wshow, cg)
{
u32_t watchlo = read_32bit_cp0_register(CP0_WATCHLO);
u32_t watchhi = read_32bit_cp0_register(CP0_WATCHHI);
printf("watch status\n");
printf(" Watch is %s\n", watchlo & 3 ? "enabled" : "disabled");
if (watchlo & 3)
{
printf("Watching physical address: %p for", watchlo&(~3) | (((word_t)watchhi)<<32));
switch (watchlo & 3) {
case 1: printf("write access\n"); break;
case 2: printf("read access\n"); break;
case 3: printf("any access\n"); break;
default: ;
}
}
return CMD_NOQUIT;
}

1
kernel/kdb/arch/sparc64/Makeconf
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@ -1 +0,0 @@
SOURCES += $(addprefix kdb/arch/sparc64/, prepost.cc reboot.cc registers.cc)

45
kernel/kdb/arch/sparc64/prepost.cc
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@ -1,45 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, University of New South Wales
*
* File path: kdb/arch/sparc64/prepost.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: prepost.cc,v 1.3 2004/05/21 02:34:53 philipd Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
bool
kdb_t::pre()
{
return true;
}
void
kdb_t::post()
{
}

49
kernel/kdb/arch/sparc64/reboot.cc
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@ -1,49 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, University of New South Wales
*
* File path: kdb/arch/sparc64/reboot.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: reboot.cc,v 1.4 2004/05/21 02:34:54 philipd Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
/**
* Reboot the machine.
* Notes: Need to revisit this to make it work without any Open Firmware
* mappings in the TLB.
*/
DECLARE_CMD(cmd_reboot, root, '6', "reset", "Reset system");
CMD(cmd_reboot, cg)
{
printf("Sorry you have to reset it yourself :)\n");
#warning awiggins (17-09-03): Since we killed Open Firmware mappings sir does not work!
//asm("sir\t0\t! Software initiated reset\n");
}

152
kernel/kdb/arch/sparc64/registers.cc
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@ -1,152 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, University of New South Wales
*
* File path: kdb/arch/sparc64/registers.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: registers.cc,v 1.3 2004/05/21 02:34:54 philipd Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_ARCH(registers.h)
extern void putc(char);
DECLARE_CMD(cmd_dump_version, arch, 'v',
"version register", "Dump the version register");
DECLARE_CMD(cmd_dump_pstate, arch, 's',
"processor state registers", "Dump the processors state registers");
DECLARE_CMD(cmd_dump_tstate, arch, 't',
"trap state registers", "Dump the trap state registers, current");
DECLARE_CMD(cmd_dump_tstate_all, arch, 'T',
"trap state registers, all TLs",
"Dump the trap state registers, all TLs");
DECLARE_CMD(cmd_dump_wstate, arch, 'w',
"register-window state registers",
"Dump the register-window state registers");
//DECLARE_CMD(?, arch, 'f',
// "floating-point registers", "Dump the floating-point registers");
//DECLARE_CMD(?, arch, 'g',
// "global registers", "Dump the global registers");
//DECLARE_CMD(?, arch, 'i',
// "windowed registers", "Dump the windowed integer registers");
CMD(cmd_dump_version, cg)
{
ver_t ver;
ver.get();
ver.print();
return CMD_NOQUIT;
} // CMD(cmd_dump_version, cg)
CMD(cmd_dump_pstate, cg)
{
y_reg_t y;
ccr_t ccr;
asi_t asi;
//fprs_t fprs;
//tick_t tick;
pstate_t pstate;
pil_t pil;
tl_t tl;
y.get();
ccr.get();
asi.get();
pstate.get();
pil.get();
tl.get();
pstate.print(), putc(' '), pil.print(), putc(' '), tl.print(), putc(' '),
ccr.print(), putc(' '), asi.print(), putc(' '), y.print(), putc('\n');
return CMD_NOQUIT;
} // CMD(cmd_dump_state, cg)
CMD(cmd_dump_tstate, cg)
{
tpc_t tpc;
tnpc_t tnpc;
tt_t tt;
tstate_t tstate;
tpc.get();
tnpc.get();
tt.get();
tstate.get();
tpc.print(), putc(' '), tnpc.print(), putc(' '), tt.print(),
putc(' '), tstate.print();
return CMD_NOQUIT;
} // CMD(cmd_dump_tstate, cg)
CMD(cmd_dump_tstate_all, cg)
{
tl_t tl_old;
tl_t tl_new;
tpc_t tpc;
tnpc_t tnpc;
tt_t tt;
tstate_t tstate;
ver_t ver;
tl_old.get(); /* Save the current TL. */
ver.get(); /* We need rev.maxtl. */
for(u8_t i = 1; i <= ver.ver.maxtl; i++) { /* For every TL. */
tl_new.tl = i; /* Set TL we want. */
tl_new.set();
tpc.get();
tnpc.get();
tt.get();
tstate.get(); /* Get the trap state. */
tl_new.print(), putc(' '), tpc.print(), /* Print the results. */
putc('\t'), tnpc.print(), putc('\t'),
tt.print(), putc(' '), tstate.print();
}
tl_old.set(); /* Restore original TL. */
return CMD_NOQUIT;
} // CMD(cmd_dump_tstate_all, cg)
CMD(cmd_dump_wstate, cg)
{
reg_win_t reg_win;
reg_win.get();
reg_win.print();
return CMD_NOQUIT;
} // CMD(cmd_dump_wstate, cg)

1
kernel/kdb/arch/sparc64/ultrasparc/Makeconf
View File

@ -1 +0,0 @@
SOURCES += $(addprefix kdb/arch/sparc64/ultrasparc/, mmu.cc)

189
kernel/kdb/arch/sparc64/ultrasparc/mmu.cc
View File

@ -1,189 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2003, University of New South Wales
*
* File path: kdb/arch/sparc64/registers.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: mmu.cc,v 1.4 2004/05/21 02:34:54 philipd Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include <kdb/input.h>
#include INC_CPU(mmu.h)
#include INC_CPU(tsb.h)
DECLARE_CMD_GROUP(mmu);
DECLARE_CMD(cmd_mmu, arch, 'm', "mmu", "mmu specifics");
DECLARE_CMD(cmd_dump_state, mmu, 's', "MMU state", "Dump MMU state");
DECLARE_CMD(cmd_dump_tlb, mmu, 't', "TLB entry", "Dump a TLB entry");
DECLARE_CMD(cmd_dump_tlb_all, mmu, 'T', "TLB(s)", "Dump whole TLB");
DECLARE_CMD(cmd_dump_tsb, mmu, 'h', "TSB (software TLB) entry",
"Dump a TSB entry");
DECLARE_CMD(cmd_dump_tsb_all, mmu, 'H', "TSB (software TLB)",
"Dump whole TSB");
CMD(cmd_mmu, cg)
{
return mmu.interact (cg, "mmu");
}
CMD(cmd_dump_state, cg)
{
mmu_t mmu;
tsb_t tsb;
mmu.print(sfsr_t::both, context_t::reserved);
tsb.print();
return CMD_NOQUIT;
} // CMD(cmd_dump_state, cg)
CMD(cmd_dump_tlb, cg)
{
u16_t entry;
char selection;
tlb_t::tlb_e tlb;
selection = get_choice("TLB to dump", "D-TLB/I-TLB", 'd');
switch (selection) {
case 'd':
tlb = tlb_t::d_tlb;
break;
case 'i':
tlb = tlb_t::i_tlb;
break;
default:
printf("Invalid selection '%c'\n", selection);
return CMD_NOQUIT;
}
entry = get_dec("Entry to dump [0..63]", 0, "0");
mmu_t::print(entry, tlb);
return CMD_NOQUIT;
} // CMD(cmd_dump_tlb, cg)
CMD(cmd_dump_tlb_all, cg)
{
char selection;
tlb_t::tlb_e tlb;
selection = get_choice("TLB to dump", "D-TLB/I-TLB/Both", 'd');
switch (selection) {
case 'd':
tlb = tlb_t::d_tlb;
break;
case 'i':
tlb = tlb_t::i_tlb;
break;
case 'b':
tlb = tlb_t::all_tlb;
break;
default:
printf("Invalid selection '%c'\n", selection);
return CMD_NOQUIT;
}
mmu_t::print(tlb);
return CMD_NOQUIT;
} // CMD(cmd_dump_tlb_all, cg)
CMD(cmd_dump_tsb, cg)
{
u16_t entry;
char selection;
tsb_t::tsb_e tsb;
selection = get_choice("TSB to dump",
"D-TSB 8K 'd'/D-TSB 64K 'e'/"
"I-TSB 8K 'i'/D-TSB64K 'j'", 'd');
switch (selection) {
case 'd':
tsb = tsb_t::d8k_tsb;
break;
case 'e':
tsb = tsb_t::d64k_tsb;
break;
case 'i':
tsb = tsb_t::i8k_tsb;
break;
case 'j':
tsb = tsb_t::i64k_tsb;
break;
default:
printf("Invalid selection '%c'\n", selection);
return CMD_NOQUIT;
}
entry = get_dec("Entry to dump [0..512]", 0, "0");
tsb_t::print(entry, tsb);
return CMD_NOQUIT;
} // CMD(cmd_dump_tsb, cg)
CMD(cmd_dump_tsb_all, cg)
{
char selection;
tsb_t::tsb_e tsb;
selection =
get_choice("TSB to dump",
"D-TSB 8K 'd'/D-TSB 64K 'e'/I-TSB 8K 'i'/I-TSB 64K 'j'",
'd');
switch (selection) {
case 'd':
tsb = tsb_t::d8k_tsb;
break;
case 'e':
tsb = tsb_t::d64k_tsb;
break;
case 'i':
tsb = tsb_t::i8k_tsb;
break;
case 'j':
tsb = tsb_t::i64k_tsb;
break;
default:
printf("Invalid selection '%c'\n", selection);
return CMD_NOQUIT;
}
tsb_t::print(tsb);
return CMD_NOQUIT;
} // CMD(cmd_dump_tsb_all, cg)

1
kernel/kdb/platform/brutus/Makeconf
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@ -1 +0,0 @@
SOURCES += kdb/platform/brutus/io.cc

88
kernel/kdb/platform/brutus/io.cc
View File

@ -1,88 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2004, Karlsruhe University
*
* File path: kdb/platform/brutus/io.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: io.cc,v 1.9 2004/03/17 19:13:24 skoglund Exp $
*
********************************************************************/
#include "../sa1100/uart.h"
#define BRD CONFIG_KDB_COMSPEED
#define UART_VBASE 0xFF
void init_console (void)
{
u32_t enbl = 0;
enbl |= L4_UART_RXE;
enbl |= L4_UART_TXE;
L4_UART_UTCR3 = 0; /* Diable UART */
L4_UART_UTSR0 = 0xf; /* Clear pending interrupts */
L4_UART_UTCR0 = L4_UART_DSS; /* No parity, 1 stop bit, 8 bit */
L4_UART_UTCR1 = BRD >> 8; /* Set baudrate */
L4_UART_UTCR2 = BRD & 0xff;
L4_UART_UTCR3 = enbl; /* Enable UART */
}
void putc(char chr)
{
volatile u32_t tmp;
/*
* Wait till the transmit FIFO has a free slot.
*/
do {
tmp = L4_UART_UTSR1;
} while ( !(tmp & L4_UART_TNF) );
/*
* Add the character to the transmit FIFO.
*/
L4_UART_UTDR = (u32_t) chr;
}
char getc(bool block)
{
volatile u32_t tmp;
/*
* Wait till the receive FIFO has something in it.
*/
do {
tmp = L4_UART_UTSR1;
} while ( !(tmp & L4_UART_RNE) );
/*
* Read a character from the receive FIFO.
*/
return (char) L4_UART_UTDR;
}

2
kernel/kdb/platform/csb337/Makeconf
View File

@ -1,2 +0,0 @@
SOURCES += $(addprefix kdb/platform/$(PLATFORM)/, console.cc reboot.cc )

130
kernel/kdb/platform/csb337/console.cc
View File

@ -1,130 +0,0 @@
/****************************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: platform/csb337/console.cc
* Description: Cogent CSB337 Console
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: console.cc,v 1.1 2004/08/12 12:00:34 cvansch Exp $
*
***************************************************************************/
#include <debug.h>
#include INC_GLUE(config.h)
#include INC_PLAT(console.h)
#include <kdb/console.h>
#define SERIAL_NAME "serial"
/****************************************************************************
*
* Serial console support
* Atmel AT91RM9200
*
****************************************************************************/
struct serial_at91rm9200 {
word_t us_cr; /* 0x00 Control Register */
word_t us_mr; /* 0x04 Mode Register */
word_t us_ier; /* 0x08 Interrupt Enable Register */
word_t us_idr; /* 0x0c Interrupt Disable Register */
word_t us_imr; /* 0x10 Interrupt Mask Register */
word_t us_csr; /* 0x14 Channel Status Register */
word_t us_rhr; /* 0x18 Receiver Holding Register */
word_t us_thr; /* 0x1c Transmitter Holding Register */
word_t us_brgr; /* 0x20 Baud Rate Generator Register */
word_t us_rtor; /* 0x24 Receiver Time-out Register */
word_t us_rrgr; /* 0x28 Transmitter Timeguard Register */
word_t res1[5];
word_t us_fidi; /* 0x40 FI DI Ratio Register */
word_t us_ner; /* 0x44 Number of Errors Register */
word_t res2;
word_t us_if; /* 0x4c IrDA Filter Register */
};
#define CSR_TXRDY (1 << 1)
#define CSR_RXRDY (1 << 0)
static volatile struct serial_at91rm9200 *serial_regs = 0;
static void putc_serial( char c )
{
if ( serial_regs )
{
while ((serial_regs->us_csr & CSR_TXRDY) == 0 );
serial_regs->us_thr = c;
if ( c == '\n' )
putc_serial( '\r' );
}
}
static char getc_serial( bool block )
{
if ( serial_regs )
{
if ((serial_regs->us_csr & CSR_RXRDY) == 0 )
{
if (!block)
return (signed char)-1;
while ((serial_regs->us_csr & CSR_RXRDY) == 0 );
}
return (serial_regs->us_rhr & 0xff);
}
return 0;
}
#if defined(CONFIG_KDB_BREAKIN)
void kdebug_check_breakin (void)
{
if (( serial_regs->us_csr & CSR_RXRDY) != 0 )
{
if ((serial_regs->us_rhr & 0xff) == 27)
enter_kdebug("breakin");
}
}
#endif
static void init(void)
{
serial_regs = (struct serial_at91rm9200*)(CONSOLE_VADDR);
}
/****************************************************************************
*
* Console registration
*
****************************************************************************/
kdb_console_t kdb_consoles[] = {
{ SERIAL_NAME, init, putc_serial, getc_serial},
KDB_NULL_CONSOLE
};
word_t kdb_current_console = 0;

57
kernel/kdb/platform/csb337/reboot.cc
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@ -1,57 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: kdb/platform/csb337/reboot.cc
* Description: Cogent CSB337 system reset
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: reboot.cc,v 1.2 2004/08/21 13:37:52 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_API(space.h)
#include INC_PLAT(timer.h)
#define ST_OFFSET 0xd00
#define ST_VADDR (SYS_VADDR | ST_OFFSET)
#define ST_WATCHDOG_CONTROL *((volatile word_t *)(ST_VADDR + 0x00))
#define ST_WATCHDOG_MODE *((volatile word_t *)(ST_VADDR + 0x08))
/*
* Reboot the box
*/
DECLARE_CMD (cmd_reboot, root, '6', "reset", "Reset system");
CMD (cmd_reboot, cg)
{
printf("\nReset...\n");
ST_WATCHDOG_MODE = 0x10 | (0x1ul<<16); /* Short timeout + reset */
ST_WATCHDOG_CONTROL = 0x01; /* Go! */
return CMD_NOQUIT;
}

1
kernel/kdb/platform/erpcn01/Makeconf
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@ -1 +0,0 @@
SOURCES += kdb/platform/erpcn01/propane.cc kdb/platform/erpcn01/uart.cc

73
kernel/kdb/platform/erpcn01/propane.cc
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@ -1,73 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, University of New South Wales
*
* File path: platform/erpcn01/propane.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: propane.cc,v 1.3 2003/09/24 19:05:18 skoglund Exp $
*
********************************************************************/
#include INC_PLAT(gt64115.h)
volatile unsigned int *propane;
volatile unsigned int *propane_uart;
/* Setup / Check for propane interface */
int propane_init()
{
int i;
volatile unsigned int *reg;
/* Auto detect FPGA Address for Propane */
propane = (unsigned int *)0x9000000000000000UL; // Uncached
reg = (unsigned int *)(0x9000000000000000UL | 0x14000000 | GT_CS_2_0_LOW_DECODE_ADDRESS);
propane = (unsigned int *)((unsigned long)propane | (((unsigned int)(*reg)&0x7FF)<<21));
reg = (unsigned int *)(0x9000000000000000UL | 0x14000000 | GT_CS_1_LOW_DECODE_ADDRESS);
propane = (unsigned int *)((unsigned long)propane | (((unsigned int)(*reg)&0xFF)<<20));
if ((propane[0] & 0xF0000000) != 0xE0000000)
return -1;
if (((propane[0] & 0x0F000000) >> 24) == 0x1)
{
propane[2] = 0x0; /* Disable interrupts */
}
else
return -1;
for (i=0; i<8; i++) {
if ((propane[0]&0xF) & (1<<i)) {
if ((propane[i<<18] & 0xF0000000) == 0xA0000000) {
propane_uart = &propane[i<<18];
break;
}
}
}
return 0;
}

157
kernel/kdb/platform/erpcn01/uart.cc
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@ -1,157 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2002, 2004, University of New South Wales
*
* File path: kdb/platform/erpcn01/uart.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: uart.cc,v 1.10 2004/03/17 22:36:05 cvansch Exp $
*
********************************************************************/
/* Talk to propane uart interface */
#include <debug.h>
#include INC_PLAT(serial.h)
#include INC_PLAT(gt64115.h)
#include INC_GLUE(schedule.h)
#include <kdb/console.h>
#include <debug.h>
#define ECHO 1
extern volatile unsigned int *propane_uart;
extern volatile unsigned int *propane;
/* Must be called first */
static int puart_change_settings(unsigned int settings)
{
unsigned int config, baud;
switch (settings & 0x00FF) {
case BAUDRATE_1200_BPS: baud = 3472; break;
case BAUDRATE_1800_BPS: baud = 2315; break;
case BAUDRATE_2400_BPS: baud = 1736; break;
case BAUDRATE_4800_BPS: baud = 868; break;
case BAUDRATE_7200_BPS: baud = 579; break;
case BAUDRATE_9600_BPS: baud = 434; break;
case BAUDRATE_14400_BPS: baud = 289; break;
case BAUDRATE_19200_BPS: baud = 217; break;
case BAUDRATE_38400_BPS: baud = 109; break;
case BAUDRATE_57600_BPS: baud = 72; break;
case BAUDRATE_115200_BPS: baud = 36; break;
case BAUDRATE_230400_BPS: baud = 18; break;
case BAUDRATE_460800_BPS: baud = 9; break;
case BAUDRATE_921600_BPS: baud = 5; break; /* won't work */
default:
return -1;
}
config = baud << 8;
switch ((settings>>8) & 0x0F) {
case SERIAL_DATABITS_7: config |= 0x08; break;
case SERIAL_DATABITS_8: config |= 0x00; break;
default:
return -1;
}
switch ((settings>>12) & 0x0F) {
case SERIAL_PARITY_NONE: config |= 0x00; break;
case SERIAL_PARITY_EVEN: config |= 0x03; break;
case SERIAL_PARITY_ODD: config |= 0x01; break;
default:
return -1;
}
switch ((settings>>16) & 0x0F) {
case SERIAL_STOPBITS_10: config |= 0x00; break;
case SERIAL_STOPBITS_15: config |= 0x04; break;
case SERIAL_STOPBITS_20: config |= 0x04; break;
default:
return -1;
}
config |= 1 << 21; /* Enable */
propane_uart[0] = config;
return 0;
}
extern "C" void puart_write_char(char c)
{
while ((propane_uart[2] & 0x0F) >= 0xD); /* fifo count */
propane_uart[1] = (unsigned char)c;
}
extern "C" int puart_read_char(int blocking)
{
if (blocking) {
while ((propane_uart[2] & 0x200));
}
if (!(propane_uart[2] & 0x200))
return propane_uart[1];
return -1;
}
void putc_serial(char chr)
{
puart_write_char(chr);
if (chr == '\n') puart_write_char('\r');
}
static char getc_serial(bool block)
{
return puart_read_char(block);
}
extern int propane_init(void);
static void init_serial (void)
{
if (propane_init())
while(1);
puart_change_settings(BAUDRATE_57600_BPS | SERIAL_DATABITS_8 |
SERIAL_PARITY_NONE | SERIAL_STOPBITS_10);
printf("\e[2J\e[H---- ERPCN01 ---- L4 Pistachio ----- \n");
printf("(C) 2002, Carl van Schaik, University of New South Wales, OpenFuel\n\n");
printf("Detected PROPANE system interface at 0x%016lx\n", propane);
printf(" PROPANE UART at 0x%16lx\n", propane_uart);
}
word_t kdb_current_console = 0;
kdb_console_t kdb_consoles[] = {
{ "serial", &init_serial, &putc_serial, &getc_serial },
KDB_NULL_CONSOLE
};
#ifdef CONFIG_KDB_BREAKIN
void SECTION(".kdebug") kdebug_check_breakin(void)
{
if (puart_read_char(0) == 27)
enter_kdebug("breakin");
}
#endif

2
kernel/kdb/platform/innovator/Makeconf
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@ -1,2 +0,0 @@
SOURCES += $(addprefix kdb/platform/$(PLATFORM)/, console.cc reboot.cc )

132
kernel/kdb/platform/innovator/console.cc
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@ -1,132 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: kdb/arch/platform/innovator/console.cc
* Description:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: console.cc,v 1.2 2004/06/04 06:43:13 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include INC_GLUE(config.h)
#include <kdb/console.h>
#include INC_PLAT(reg.h)
#include INC_PLAT(console.h)
#include INC_CPU(io.h)
/****************************************************************************
*
* Serial console support
*
****************************************************************************/
static word_t UART_IOBASE = NULL;
static char
inreg_ser (word_t reg)
{
char val;
val = *((volatile char *) (UART_IOBASE + (reg * SER_UART_REGDELTA)));
return val;
}
static void
outreg_ser (word_t reg, char val)
{
*((volatile char *) (UART_IOBASE + (reg * SER_UART_REGDELTA))) = val;
}
static bool
is_ser_char ()
{
if (inreg_ser (SER_LSR) & SER_LSR_DR)
return true;
else
return false;
}
static void
putc_serial (char c)
{
if (UART_IOBASE)
{
if ('\n' == c)
putc_serial ('\r');
while (0 == (inreg_ser (SER_LSR) & SER_LSR_THRE))
{
}
outreg_ser (SER_THR, c);
}
}
static char
getc_serial (bool block)
{
if (UART_IOBASE)
{
if (is_ser_char ())
return inreg_ser (SER_RBR);
else
{
if (!block)
return 0xff;
while (!is_ser_char ());
}
return inreg_ser (SER_RBR);
}
return 0xff;
}
#if defined(CONFIG_KDB_BREAKIN)
void
kdebug_check_breakin (void)
{
if (is_ser_char ())
{
if (inreg_ser (SER_RBR) == 27)
enter_kdebug ("breakin");
}
}
#endif
static void
init (void)
{
UART_IOBASE = io_to_virt (CONSOLE_PADDR);
// printf("DPLL is %p, CKCTL is %p\n", \
// *((volatile word_t*) io_to_virt(0xfffecf00)), \
// *((volatile word_t*) io_to_virt(0xfffece00)));
}
word_t kdb_current_console = 0;
kdb_console_t kdb_consoles[] = {
{"serial", &init, &putc_serial, &getc_serial},
KDB_NULL_CONSOLE
};

55
kernel/kdb/platform/innovator/reboot.cc
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@ -1,55 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: kdb/platform/pleb/reboot.cc
* Description: SA1100 system reset
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: reboot.cc,v 1.2 2004/06/04 06:43:13 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_API(space.h)
#include INC_API(tcb.h)
#include INC_PLAT(reg.h)
#include INC_CPU(io.h)
/*
* Reboot the box
*/
DECLARE_CMD (cmd_reboot, root, '6', "reset", "Reset system");
CMD (cmd_reboot, cg)
{
tcb_t *tcb;
space_t *s = NULL;
tcb = s->get_tcb (kdb.kdb_param);
s = tcb->get_space ();
*((word_t *) io_to_virt (OMAP_ARM_RSTCT1)) = VAL_ARM_SW_RST;
return CMD_NOQUIT;
}

2
kernel/kdb/platform/ixdp425/Makeconf
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@ -1,2 +0,0 @@
SOURCES += $(addprefix kdb/platform/$(PLATFORM)/, console.cc reboot.cc )

134
kernel/kdb/platform/ixdp425/console.cc
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@ -1,134 +0,0 @@
/****************************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: platform/ixdp425/console.cc
* Description: Intel XScale Console
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: console.cc,v 1.2 2004/06/04 06:43:13 cvansch Exp $
*
***************************************************************************/
#include <debug.h>
#include INC_GLUE(config.h)
#include INC_PLAT(console.h)
#include <kdb/console.h>
#define SERIAL_NAME "serial"
/****************************************************************************
*
* Serial console support
*
****************************************************************************/
struct serial_xscalecon {
word_t rbr; /* 0 */
word_t ier; /* 4 */
word_t fcr; /* 8 */
word_t lcr; /* 12 */
word_t mcr; /* 16 */
word_t lsr; /* 20 */
word_t msr; /* 24 */
word_t scr; /* 28 */
};
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier
#define dlab lcr
#define LSR_DR 0x01 /* Data ready */
#define LSR_OE 0x02 /* Overrun */
#define LSR_PE 0x04 /* Parity error */
#define LSR_FE 0x08 /* Framing error */
#define LSR_BI 0x10 /* Break */
#define LSR_THRE 0x20 /* Xmit holding register empty */
#define LSR_TEMT 0x40 /* Xmitter empty */
#define LSR_ERR 0x80 /* Error */
static volatile struct serial_xscalecon *serial_regs = 0;
static void putc_serial( char c )
{
if ( serial_regs )
{
while (( serial_regs->lsr & LSR_THRE ) == 0 );
serial_regs->thr = c;
if ( c == '\n' )
putc_serial( '\r' );
}
}
static char getc_serial( bool block )
{
if ( serial_regs )
{
if (( serial_regs->lsr & LSR_DR ) == 0 )
{
if (!block)
return (signed char)-1;
while (( serial_regs->lsr & LSR_DR ) == 0 );
}
return serial_regs->rbr;
}
return 0;
}
#if defined(CONFIG_KDB_BREAKIN)
void kdebug_check_breakin (void)
{
if (( serial_regs->lsr & LSR_DR ) != 0 )
{
if (serial_regs->rbr == 27)
enter_kdebug("breakin");
}
}
#endif
static void init(void)
{
serial_regs = (struct serial_xscalecon*)(IODEVICE_VADDR + CONSOLE_OFFSET);
}
/****************************************************************************
*
* Console registration
*
****************************************************************************/
kdb_console_t kdb_consoles[] = {
{ SERIAL_NAME, init, putc_serial, getc_serial},
KDB_NULL_CONSOLE
};
word_t kdb_current_console = 0;

52
kernel/kdb/platform/ixdp425/reboot.cc
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@ -1,52 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2004, National ICT Australia (NICTA)
*
* File path: kdb/platform/ixdp425/reboot.cc
* Description: Intel IXDP425 system reset
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: reboot.cc,v 1.3 2004/08/12 12:01:43 cvansch Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/kdb.h>
#include INC_API(space.h)
#include INC_PLAT(timer.h)
/*
* Reboot the box
*/
DECLARE_CMD (cmd_reboot, root, '6', "reset", "Reset system");
CMD (cmd_reboot, cg)
{
printf("\nReset...\n");
XSCALE_WATCHDOG_KEY = 0x482E; /* Write the Key */
XSCALE_WATCHDOG_TIMER = 0xA0000; /* Set the timeout (1ms) */
XSCALE_WATCHDOG_EN = 0x05; /* Enable reset watchdog */
return CMD_NOQUIT;
}

33
kernel/kdb/platform/malta/Makeconf
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@ -1,33 +0,0 @@
######################################################################
##
## Copyright (C) 2006, Karlsruhe University
##
## File path: kdb/platform/malta/Makeconf
## Description:
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## $Id: Makeconf,v 1.1 2006/02/23 21:07:44 ud3 Exp $
##
######################################################################
SOURCES += kdb/platform/malta/console.cc

129
kernel/kdb/platform/malta/console.cc
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@ -1,129 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2006, Karlsruhe University
*
* File path: kdb/platform/malta/console.cc
* Description: Serial console for the Malta platform
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: console.cc,v 1.1 2006/02/23 21:07:44 ud3 Exp $
*
********************************************************************/
#include <debug.h>
#include <kdb/console.h>
#include "uart16550.h"
#include "pio.h"
//static
void putc_serial (char);
static char getc_serial (bool);
static void init_serial (void);
kdb_console_t kdb_consoles[] = {
{ "serial", &init_serial, &putc_serial, &getc_serial },
KDB_NULL_CONSOLE
};
word_t kdb_current_console = 0;
// SEND
static int _serial_tx_ready( unsigned int port ) {
return inb(port + USART_LSR) & LSR_THR_Empty;
}
static void _serial_tx_byte( unsigned int port, char c ) {
outb(port + USART_THR, c);
}
void putc_serial(char c) { // XXX
while( !_serial_tx_ready( USART_0_BASE ) );
_serial_tx_byte( USART_0_BASE, c );
if( c == '\n' ) {
putc_serial('\r');
}
}
// RECEIVE
static int _serial_rx_ready( unsigned int port ) {
return inb(port + USART_LSR) & LSR_Data_Ready;
}
static char _serial_rx_byte( unsigned int port ) {
return inb(port + USART_RBR);
}
static char getc_serial(bool block) { // XXX
if( block ) {
while( !_serial_rx_ready( USART_0_BASE ) );
}
else if( !_serial_rx_ready( USART_0_BASE ) ) {
return 0; // XXX
}
return( _serial_rx_byte( USART_0_BASE ) );
}
// INIT
static void init_serial() {
#define COMPORT USART_0_BASE
#define out_u8 outb
#define in_u8 inb
#define RATE 115200
#define IER (COMPORT+1)
#define EIR (COMPORT+2)
#define LCR (COMPORT+3)
#define MCR (COMPORT+4)
#define LSR (COMPORT+5)
#define MSR (COMPORT+6)
#define DLLO (COMPORT+0)
#define DLHI (COMPORT+1)
__asm__ __volatile__ (" .word 0x24000000 ");
out_u8(LCR, 0x80); /* select bank 1 */
for (volatile int i = 10000000; i--; );
out_u8(DLLO, (((115200/RATE) >> 0) & 0x00FF));
out_u8(DLHI, (((115200/RATE) >> 8) & 0x00FF));
out_u8(LCR, 0x03); /* set 8,N,1 */
out_u8(IER, 0x00); /* disable interrupts */
out_u8(EIR, 0x07); /* enable FIFOs */
out_u8(IER, 0x01); /* enable RX interrupts */
in_u8(IER);
in_u8(EIR);
in_u8(LCR);
in_u8(MCR);
in_u8(LSR);
in_u8(MSR);
}

38
kernel/kdb/platform/malta/pio.h
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/*********************************************************************
*
* Copyright (C) 2006, Karlsruhe University
*
* File path: kdb/platform/malta/pio.h
* Description: Malta platform I/O port access macros
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: pio.h,v 1.1 2006/02/23 21:07:44 ud3 Exp $
*
********************************************************************/
#ifndef __KDB__PLATFORM__MALTA__PIO_H__
#define __KDB__PLATFORM__MALTA__PIO_H__
#define inb( port ) (*((volatile unsigned char*)(port)))
#define outb( port, data ) ((*((volatile unsigned char*)(port))) = data)
#endif /* !__KDB__PLATFORM__MALTA__PIO_H__ */

151
kernel/kdb/platform/malta/uart16550.h
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@ -1,151 +0,0 @@
/*********************************************************************
*
* Copyright (C) 2006, Karlsruhe University
*
* File path: kdb/platform/malta/uart16550.h
* Description: Malta platform UART definitions
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: uart16550.h,v 1.1 2006/02/23 21:07:44 ud3 Exp $
*
********************************************************************/
#ifndef __KDB__PLATFORM__MALTA__UART16550_H__
#define __KDB__PLATFORM__MALTA__UART16550_H__
/* USART ADDRESSES */
#define USART_0_BASE (0xb80003f8) /* reflects PC hardware */
/* Handy shortforms, based on old system. Touch misleading: more status */
#define USART_0_STATUS (USART_0_BASE + USART_LSR)
#define USART_0_DATA (USART_0_BASE + USART_RBR)
/*
* 16550 IO register offsets - should be added to USART_n_BASE
*/
#define USART_RBR 0 /* receive data register */
#define USART_THR 0 /* transmit holding register */
#define USART_IER 1 /* interrupt enable offset */
#define USART_IIR 2 /* interupt identification register */
#define USART_FCR 2 /* FIFO control register */
#define USART_LCR 3 /* line control register */
#define USART_MCR 4 /* modem control register */
#define USART_LSR 5 /* line status register */
#define USART_MSR 6 /* modem status register */
/*
* The following constants are primarily for documentation purposes
* to show what the values sent to the 8250 Control Registers do to
* the chip.
*
* INTERRUPT ENABLE REGISTER
*/
#define IER_Received_Data 1
#define IER_Xmt_Hld_Reg_Empty (1<<1)
#define IER_Recv_Line_Status (1<<2)
#define IER_Modem_Status (1<<3)
#define IER_Not_Used 0xF0
/*
* LINE CONTROL REGISTER
*/
#define LCR_Word_Length_Mask 3
#define LCR_Stop_Bits (1<<2)
#define LCR_Parity_Enable (1<<3)
#define LCR_Even_Parity (1<<4)
#define LCR_Stick_Parity (1<<5)
#define LCR_Set_Break (1<<6)
#define LCR_Divisor_Latch_Access (1<<7)
/* Divisor Latch - must be set to 1
* to get to the divisor latches of
* the baud rate generator - must
* be set to 0 to access the
* Receiver Buffer Register and
* the Transmit Holding Register
*/
#define LCR_DLAB LCR_Divisor_Latch_Access
/*
* MODEM CONTROL REGISTER
*/
#define MCR_dtr 1
#define MCR_rts (1<<1)
#define MCR_Out_1 (1<<2)
#define MCR_Out_2 (1<<3) /* MUST BE ASSERTED TO ENABLE INTERRRUPTS */
#define MCR_Loop_Back (1<<4)
#define MCR_Not_Used (7<<1)
/*
* LINE STATUS REGISTER
*/
#define LSR_Data_Ready 1
#define LSR_Overrun_Error (1<<1)
#define LSR_Parity_Error (1<<2)
#define LSR_Framing_Error (1<<3)
#define LSR_Break_Interrupt (1<<4)
#define LSR_THR_Empty (1<<5) /* Transmitter Holding Register */
#define LSR_TSR_Empty (1<<6) /* Transmitter Shift Register */
#define LSR_Not_Used (1<<7)
/*
* MODEM STATUS REGISTER
*/
#define MSR_Delta_CTS 1
#define MSR_Delta_DSR (1<<1)
#define MSR_TERD (1<<2) /* Trailing Edge Ring Detect */
#define MSR_Delta_RLSD (1<<3) /* Received Line Signal Detect */
#define MSR_CTS (1<<4) /* Clear to Send */
#define MSR_DSR (1<<5) /* Data Set Ready */
#define MSR_RD (1<<6) /* Ring Detect */
#define MSR_RLSD (1<<7) /* Received Line Signal Detect */
/*
* Fifo CONTROL REGISTER (Write only)
*/
#define FCR_Fifo_Enable 1 /* set to one to enable Fifos */
#define FCR_Rcvr_Reset (1<<1) /* set to clear receiver FIFO */
#define FCR_Xmit_Reset (1<<2) /* set to clear transmitter FIFO */
#define FCR_DMA_Mode (1<<3) /* no effect */
#define FCR_Trigger_1 (0<<6) /* trigger IRQ on one byte */
#define FCR_Trigger_4 (1<<6) /* 4 bytes in fifo */
#define FCR_Trigger_8 (2<<6) /* 8 bytes */
#define FCR_Trigger_14 (3<<6) /* 14 bytes before IRQ occurs */
#endif /* !__KDB__PLATFORM__MALTA__UART16550_H__ */

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