mirror of https://github.com/l4ka/pistachio.git
More UIC stuff:
* Read daisychain interrupts from fdt * Interrupts are now masked/unmasked correctly during handling * Some more smaller fixes
This commit is contained in:
Jens Kehne
parent
7456802898
commit
75811bec07
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@ -76,14 +76,8 @@ void SECTION (".init") intctrl_t::init_arch()
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if (prop->get_word(1) != 9)
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panic("Invalid number of control registers found (%d)",prop->get_word(1));
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#if defined(PPC440EPx)
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num_irqs=30;
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#else
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num_irqs=31;
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#endif
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TRACE_INIT("UIC0: DCR base 0x%x, %d interrupts\n",
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UIC0_DCR_BASE, num_irqs);
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UIC0_DCR_BASE, UIC0_NUM_IRQS);
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//Controller 1
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printf("Looking for interrupt controller 1... ");
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@ -115,10 +109,15 @@ void SECTION (".init") intctrl_t::init_arch()
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if (prop->get_word(1) != 9)
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panic("UIC1: Invalid number of control registers found (%d)",prop->get_word(1));
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num_irqs=32;
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prop = fdt->find_property_node(hdr, "interrupts");
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if (!prop)
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panic("UIC1: Couldn't determine daisychain interrupts");
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uic1_dchain_mask = 1 << (31 - prop->get_word(0));
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uic1_dchain_mask |= 1 << (31 - prop->get_word(2));
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TRACE_INIT("UIC1: DCR base 0x%x, %d interrupts\n",
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UIC1_DCR_BASE, num_irqs);
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UIC1_DCR_BASE, UIC1_NUM_IRQS);
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//Controller 2
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#if defined(PPC440EPx)
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@ -151,10 +150,15 @@ void SECTION (".init") intctrl_t::init_arch()
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if (prop->get_word(1) != 9)
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panic("UIC2: Invalid number of control registers found (%d)",prop->get_word(1));
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num_irqs=32;
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prop = fdt->find_property_node(hdr, "interrupts");
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if (!prop)
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panic("UIC2: Couldn't determine daisychain interrupts");
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uic2_dchain_mask = 1 << (31 - prop->get_word(0));
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uic2_dchain_mask |= 1 << (31 - prop->get_word(2));
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TRACE_INIT("UIC2: DCR base 0x%x, %d interrupts\n",
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UIC2_DCR_BASE, num_irqs);
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UIC2_DCR_BASE, UIC2_NUM_IRQS);
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#endif //PPC440EPx
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@ -305,10 +309,10 @@ void intctrl_t::mask(word_t irq)
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/* really disable interrupt */
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mtdcr(UIC2_ER, (~intMask) & mfdcr(UIC2_ER));
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lock.unlock(); /* re-enable interrupts */
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mtdcr(UIC2_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, 0x0000000c); /* clear dchained UIC1 ints */
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mtdcr(UIC0_SR, uic2_dchain_mask); /* clear dchained UIC1 ints */
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lock.unlock(); /* re-enable interrupts */
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}
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else if (irq > INT_LEVEL_UIC0_MAX) /* For UIC1 */
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#else
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@ -329,10 +333,11 @@ void intctrl_t::mask(word_t irq)
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/* really disable interrupt */
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mtdcr(UIC1_ER, (~intMask) & mfdcr(UIC1_ER));
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mtdcr(UIC1_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, uic1_dchain_mask); /* clear dchained UIC1 ints */
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lock.unlock(); /* re-enable interrupts */
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mtdcr(UIC1_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, 0x00000003); /* clear dchained UIC1 ints */
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}
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else
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{
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@ -349,9 +354,9 @@ void intctrl_t::mask(word_t irq)
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/* really disable interrupt */
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mtdcr(UIC0_ER, (~intMask) & mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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mtdcr(UIC0_SR, intMask); /* clear pending interrupts */
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lock.unlock(); /* re-enable interrupts */
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}
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return;
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@ -372,7 +377,7 @@ bool intctrl_t::unmask(word_t irq)
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intMask = 1 << (31 - irq) ;
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mtdcr(UIC2_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, 0x0000000c); /* clear pending dchain */
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mtdcr(UIC0_SR, uic2_dchain_mask); /* clear pending dchain */
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/*
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* enable the interrupt level
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@ -385,7 +390,7 @@ bool intctrl_t::unmask(word_t irq)
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mtdcr(UIC2_ER, intMask | mfdcr(UIC2_ER));
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/* Enable dchain*/
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mtdcr(UIC0_ER, 0x0000000c | mfdcr(UIC0_ER));
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mtdcr(UIC0_ER, uic2_dchain_mask | mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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@ -398,7 +403,7 @@ bool intctrl_t::unmask(word_t irq)
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irq -= INT_LEVEL_UIC1_MIN ;
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intMask = 1 << (31 - irq) ;
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mtdcr(UIC1_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, 0x00000003); /* clear pending dchain */
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mtdcr(UIC0_SR, uic1_dchain_mask); /* clear pending dchain */
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/*
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* enable the interrupt level
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@ -411,7 +416,7 @@ bool intctrl_t::unmask(word_t irq)
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mtdcr(UIC1_ER, intMask | mfdcr(UIC1_ER));
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/* Enable dchain*/
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mtdcr(UIC0_ER, 0x00000003 | mfdcr(UIC0_ER));
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mtdcr(UIC0_ER, uic1_dchain_mask | mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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@ -562,7 +567,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic2Er = mfdcr(UIC2_ER);
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newUicXEr = uic2Er \
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& ~(vecToUicBit(vector - INT_LEVEL_UIC2_MIN));
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& ~(vecToUicMask(vector - INT_LEVEL_UIC2_MIN));
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}
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else
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{
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@ -575,7 +580,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic2Cr = mfdcr(UIC2_CR);
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uic2Er = mfdcr(UIC2_ER);
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newUicXEr = ((uic2Er &
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(~(vecToUicBit(vector - INT_LEVEL_UIC2_MIN)))) |
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(~(vecToUicMask(vector - INT_LEVEL_UIC2_MIN)))) |
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uic2Cr );
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}
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@ -586,7 +591,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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/* Clear the Status registers */
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mtdcr(UIC2_SR, (1 << (31 - (vector - INT_LEVEL_UIC2_MIN)))) ;
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mtdcr(UIC0_SR, 0x0000000c); /* clear daisychain */
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mtdcr(UIC0_SR, uic2_dchain_Mask); /* clear daisychain */
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}
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else if (vector > INT_LEVEL_UIC0_MAX)
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@ -611,7 +616,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic1Er = mfdcr(UIC1_ER);
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newUicXEr = uic1Er \
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& ~(vecToUicBit(vector - INT_LEVEL_UIC1_MIN));
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& ~(vecToUicMask(vector - INT_LEVEL_UIC1_MIN));
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}
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else
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{
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@ -624,7 +629,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic1Cr = mfdcr(UIC1_CR);
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uic1Er = mfdcr(UIC1_ER);
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newUicXEr = ((uic1Er &
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(~(vecToUicBit(vector - INT_LEVEL_UIC1_MIN)))) |
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(~(vecToUicMask(vector - INT_LEVEL_UIC1_MIN)))) |
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uic1Cr );
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}
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@ -635,7 +640,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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/* Clear the Status registers */
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mtdcr(UIC1_SR, (1 << (31 - (vector - INT_LEVEL_UIC1_MIN)))) ;
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mtdcr(UIC0_SR, 0x00000003); /* clear daisychain */
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mtdcr(UIC0_SR, uic1_dchain_mask); /* clear daisychain */
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}
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else
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{
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@ -656,7 +661,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic0Er = mfdcr(UIC0_ER);
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newUicXEr = uic0Er \
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& ~(vecToUicBit(vector - INT_LEVEL_UIC0_MIN));
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& ~(vecToUicMask(vector - INT_LEVEL_UIC0_MIN));
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}
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else
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{
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@ -668,7 +673,7 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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uic0Cr = mfdcr(UIC0_CR);
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uic0Er = mfdcr(UIC0_ER);
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newUicXEr = ((uic0Er &
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(~(vecToUicBit(vector - INT_LEVEL_UIC0_MIN)))) |
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(~(vecToUicMask(vector - INT_LEVEL_UIC0_MIN)))) |
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uic0Cr);
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}
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@ -706,37 +711,28 @@ void intctrl_t::sysUicIntHandlerCommon (bool intIsCritical) {
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*/
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::handle_interrupt(vector);
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#if 0
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/*
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* Clear this interrupt level to ensure that this interrupt level is
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* disabled before re-enabling interrupts.
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*/
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if (intIsCritical)
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vxMsrSet(vxMsrGet() & ~(_PPC_MSR_CE));
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else
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vxMsrSet(vxMsrGet() & ~(_PPC_MSR_EE));
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//this is not done in bic.cc, so I'm assuming it's done somewhere else.
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/*
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* Reenable the interrupts as they were went we got called.
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*/
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lock.lock();
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#if defined(PPC440EPx)
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if (vector > INT_LEVEL_UIC1_MAX)
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{
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mtdcr(UIC2_ER, uic2Er );
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mtdcr(UIC2_ER, uic2Er );
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}
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else if (vector > INT_LEVEL_UIC0_MAX)
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#else
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if (vector > INT_LEVEL_UIC0_MAX)
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#endif
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{
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mtdcr(UIC1_ER, uic1Er );
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mtdcr(UIC1_ER, uic1Er );
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}
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else
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{
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mtdcr(UIC0_ER, uic0Er );
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mtdcr(UIC0_ER, uic0Er );
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}
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#endif
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lock.unlock();
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}
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bool intctrl_t::is_masked(word_t irq) {
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@ -804,9 +800,9 @@ void intctrl_t::dump() {
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mfdcr(UIC1_SR),mfdcr(UIC1_ER),mfdcr(UIC1_CR),mfdcr(UIC1_PR),
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mfdcr(UIC1_TR),mfdcr(UIC1_MSR),mfdcr(UIC1_VCR),mfdcr(UIC1_VR));
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#if defined(PPC440EPx)
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printf("UIC2:\nSR: %08x\nER: %08x\nCR: %08x\nPR: %08x\nTR: %08x\nMSR: %08x\nVCR: %08x\nVR: %08x\n",
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printf("UIC2:\nSR: %08x\nER: %08x\nCR: %08x\nPR: %08x\nTR: %08x\nMSR: %08x\nVCR: %08x\nVR: %08x\n",
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mfdcr(UIC2_SR),mfdcr(UIC2_ER),mfdcr(UIC2_CR),mfdcr(UIC2_PR),
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mfdcr(UIC2_TR),mfdcr(UIC2_MSR),mfdcr(UIC2_VCR),mfdcr(UIC2_VR));
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#endif
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lock.unlock();
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lock.unlock();
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}
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@ -94,11 +94,15 @@
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#define INT_LEVEL_UIC0_MIN 0 /* First interrupt level on UIC-0 */
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#define INT_LEVEL_UIC0_MAX 31 /* Last interrupt level on UIC-0 */
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#define UIC0_NUM_IRQS (INT_LEVEL_UIC0_MAX - INT_LEVEL_UIC0_MIN + 1)
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#define INT_LEVEL_UIC1_MIN 32 /* First interrupt level on UIC-1 */
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#define INT_LEVEL_UIC1_MAX 63 /* Last interrupt level on UIC-1 */
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#define UIC1_NUM_IRQS (INT_LEVEL_UIC1_MAX - INT_LEVEL_UIC1_MIN + 1)
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#if defined(PPC440EPx)
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#define INT_LEVEL_UIC2_MIN 64 /* First interrupt level on UIC-2 */
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#define INT_LEVEL_UIC2_MAX 74 /* Last interrupt level on UIC-2 */
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#define UIC2_NUM_IRQS (INT_LEVEL_UIC2_MAX - INT_LEVEL_UIC2_MIN + 1)
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#endif
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#define INT_IS_CRT (true) /* Int. is critical (for handler) */
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@ -141,7 +145,7 @@ public:
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void init_cpu(int cpu);
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word_t get_number_irqs()
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{ return INT_LEVEL_MAX; }
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{ return INT_LEVEL_MAX + 1; }
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bool is_irq_available(word_t irq)
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{ return (irq >= INT_LEVEL_MIN && irq <= INT_LEVEL_MAX); }
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@ -164,7 +168,11 @@ public:
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{ return is_masked(irq); }
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void set_cpu(word_t irq, word_t cpu)
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{ UNIMPLEMENTED(); }
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{
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set_irq_routing(irq, cpu);
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if (!is_masked(irq))
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unmask(irq);
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}
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/* handler invoked on interrupt (left for compatibility)
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@ -195,7 +203,10 @@ private:
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spinlock_t lock;
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word_t num_irqs;
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word_t mem_size;
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word_t uic1_dchain_mask;
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#if defined(PPC440EPx)
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word_t uic2_dchain_mask;
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#endif
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word_t init_controllers();
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word_t get_irq_routing(word_t irq)
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{
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