mirror of https://github.com/l4ka/pistachio.git
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4a249a0bd3
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@ -169,11 +169,13 @@ void SECTION (".init") intctrl_t::init_arch()
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void SECTION(".init") intctrl_t::init_cpu(int cpu)
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void SECTION(".init") intctrl_t::init_cpu(int cpu)
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{
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{
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#ifdef CONFIG_SMP
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ASSERT(cpu < 4);
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ASSERT(cpu < 4);
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/* map IPIs */
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/* map IPIs */
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set_irq_routing(get_ipi_irq(cpu, 0), cpu);
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set_irq_routing(get_ipi_irq(cpu, 0), cpu);
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enable(get_ipi_irq(cpu, 0));
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enable(get_ipi_irq(cpu, 0));
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#endif
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}
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}
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word_t intctrl_t::init_controllers() {
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word_t intctrl_t::init_controllers() {
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@ -496,8 +498,12 @@ bool intctrl_t::unmask(word_t irq)
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irq -= INT_LEVEL_UIC2_MIN ;
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irq -= INT_LEVEL_UIC2_MIN ;
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intMask = 1 << (31 - irq) ;
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intMask = 1 << (31 - irq) ;
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//Check if interrupt was already pending
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if ((mfdcr(UIC2_SR) & intMask) > 0) {
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mtdcr(UIC2_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC2_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, uic2_dchain_mask); /* clear pending dchain */
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mtdcr(UIC0_SR, uic2_dchain_mask); /* clear pending dchain */
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return true;
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} else {
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/*
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/*
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* enable the interrupt level
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* enable the interrupt level
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@ -513,7 +519,8 @@ bool intctrl_t::unmask(word_t irq)
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mtdcr(UIC0_ER, uic2_dchain_mask | mfdcr(UIC0_ER));
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mtdcr(UIC0_ER, uic2_dchain_mask | mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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lock.unlock(); /* re-enable interrupts */
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return false;
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}
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}
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}
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else if (irq > INT_LEVEL_UIC0_MAX) /* For UIC1 */
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else if (irq > INT_LEVEL_UIC0_MAX) /* For UIC1 */
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#else
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#else
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@ -522,8 +529,13 @@ bool intctrl_t::unmask(word_t irq)
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{
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{
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irq -= INT_LEVEL_UIC1_MIN ;
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irq -= INT_LEVEL_UIC1_MIN ;
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intMask = 1 << (31 - irq) ;
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intMask = 1 << (31 - irq) ;
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//Check if interrupt was already pending
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if ((mfdcr(UIC1_SR) & intMask) > 0) {
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mtdcr(UIC1_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC1_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, uic1_dchain_mask); /* clear pending dchain */
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mtdcr(UIC0_SR, uic1_dchain_mask); /* clear pending dchain */
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return true;
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} else {
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/*
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/*
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* enable the interrupt level
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* enable the interrupt level
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@ -539,12 +551,18 @@ bool intctrl_t::unmask(word_t irq)
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mtdcr(UIC0_ER, uic1_dchain_mask | mfdcr(UIC0_ER));
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mtdcr(UIC0_ER, uic1_dchain_mask | mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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lock.unlock(); /* re-enable interrupts */
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return false;
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}
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}
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}
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else
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else
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{
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{
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intMask = 1 << (31 - irq) ;
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intMask = 1 << (31 - irq) ;
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//Check if interrupt was already pending
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if ((mfdcr(UIC0_SR) & intMask) > 0) {
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mtdcr(UIC0_SR, intMask); /* clear pending interrupts */
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mtdcr(UIC0_SR, intMask); /* clear pending interrupts */
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return true;
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} else {
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/*
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/*
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* enable the interrupt level
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* enable the interrupt level
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@ -557,10 +575,10 @@ bool intctrl_t::unmask(word_t irq)
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mtdcr(UIC0_ER, intMask | mfdcr(UIC0_ER));
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mtdcr(UIC0_ER, intMask | mfdcr(UIC0_ER));
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lock.unlock(); /* re-enable interrupts */
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lock.unlock(); /* re-enable interrupts */
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return false;
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}
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}
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}
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return true;
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}
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}
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bool intctrl_t::is_masked(word_t irq) {
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bool intctrl_t::is_masked(word_t irq) {
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@ -158,8 +158,10 @@ public:
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bool is_pending(word_t irq);
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bool is_pending(word_t irq);
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void enable(word_t irq)
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void enable(word_t irq) {
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{ unmask(irq); }
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if (unmask(irq))
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::handle_interrupt(irq);
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}
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void disable(word_t irq)
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void disable(word_t irq)
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{ mask(irq); }
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{ mask(irq); }
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@ -180,12 +182,6 @@ public:
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*/
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*/
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void handle_irq(word_t cpu);
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void handle_irq(word_t cpu);
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//noncritical interrupt handler
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void sysUicIntHandler(void);
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//critical interrupt handler;
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void sysUicCrtIntHandler(void);
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/* map routine provided by glue */
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/* map routine provided by glue */
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void map();
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void map();
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@ -225,7 +221,6 @@ private:
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return cpu * 8 + ipi;
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return cpu * 8 + ipi;
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}
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}
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//common interrupt handler, should not be called directly.
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//common interrupt handler, should not be called directly.
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void sysUicIntHandlerCommon(bool intIsCritical);
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void raise_irq(word_t irq);
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void raise_irq(word_t irq);
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};
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};
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