forked from OSSInnovation/mindspore
!6627 [MSLITE][Develop] support conv_depthwise arm32 int8 weight perchannel
Merge pull request !6627 from yangruoqi713/lite
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@ -0,0 +1,113 @@
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#ifdef __arm__
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#ifndef __aarch64__
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.text
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.align 5
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.global ConvDwInt8PostAlign4PerChannel
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#ifndef __APPLE__
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.type ConvDwInt8PostAlign4PerChannel, %function
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#endif
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// void ConvDwInt8PostAlign4PerChannel(int8_t *dst, int32_t *buffer, int channel4, int32_t output_zp, int32_t *out_multiplier,
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// int32_t *left_shift, int32_t *right_shift, int32_t acc_min, int32_t acc_max);
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// r0: dst, r1: buffer, r2: num_pixels, r3: output_zp, r4: out_multiplier,
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// r5: left_shift, r6: right_shift, r7: acc_min, r8: acc_max
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ConvDwInt8PostAlign4PerChannel:
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// at return, clang generates "push {lr}, pop {pc}"" while gcc will generate "bx lr"
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// according to https://stackoverflow.com/questions/53625807
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// even if we jump to link register instead of saving it, we still have to save it in subroutine calls anyway
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// clang's rule seems more simple, though there are no subroutine calls here
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// r4-r8 and q4-q7 must be saved according to https://static.docs.arm.com/ihi0042/i/aapcs32.pdf
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push {r4-r8, r10}
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vpush {q4-q7}
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add sp, sp, #88
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vdup.32 q15, r3 // output_zp
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ldr r4, [sp] // out_multiplier
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ldr r5, [sp, #4] // left_shift
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ldr r6, [sp, #8] // right_shift
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ldr r7, [sp, #12] // acc_min
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vdup.32 q11, r7
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ldr r8, [sp, #16] // acc_max
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vdup.32 q10, r8
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mov r10, r0
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LoopDepth8:
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cmp r2, #8
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blt End
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vld1.32 {q0}, [r1]!
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vld1.32 {q13}, [r5]!
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vshl.s32 q0, q0, q13
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vld1.32 {q14}, [r4]!
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vqrdmulh.s32 q0, q0, q14
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vld1.32 {q12}, [r6]!
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vand q4, q0, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q0, q0, q4
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vrshl.s32 q0, q0, q12
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vadd.i32 q0, q0, q15
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vmax.s32 q0, q0, q11
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vmin.s32 q0, q0, q10
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vqmovn.s32 d4, q0
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vld1.32 {q1}, [r1]!
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vld1.32 {q13}, [r5]!
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vshl.s32 q1, q1, q13
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vld1.32 {q14}, [r4]!
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vqrdmulh.s32 q1, q1, q14
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vld1.32 {q12}, [r6]!
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vand q4, q1, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q1, q1, q4
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vrshl.s32 q1, q1, q12
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vadd.i32 q1, q1, q15
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vmax.s32 q1, q1, q11
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vmin.s32 q1, q1, q10
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vqmovn.s32 d5, q1
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vqmovn.s16 d4, q2
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vst1.8 {d4}, [r10]!
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sub r2, r2, #8
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b LoopDepth8
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LoopDepth4:
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cmp r2, #4
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blt End
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vld1.32 {q0}, [r1]!
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vld1.32 {q13}, [r5]!
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vshl.s32 q0, q0, q13
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vld1.32 {q14}, [r4]!
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vqrdmulh.s32 q0, q0, q14
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vld1.32 {q12}, [r6]!
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vand q4, q0, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q0, q0, q4
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vrshl.s32 q0, q0, q12
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vadd.i32 q0, q0, q15
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vmax.s32 q0, q0, q11
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vmin.s32 q0, q0, q10
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vqmovn.s32 d0, q0
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vqmovn.s16 d0, q0
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vst1.8 {d0[0]}, [r10]!
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vst1.8 {d0[1]}, [r10]!
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vst1.8 {d0[2]}, [r10]!
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vst1.8 {d0[3]}, [r10]!
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sub r2, r2, #4
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b LoopDepth4
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End:
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sub sp, sp, #88
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vpop {q4-q7}
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pop {r4-r8, r10}
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bx lr
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#endif
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#endif
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@ -35,6 +35,9 @@ void PostFuncInt8C4(const int32_t *in, const int32_t *bias, int8_t *out, size_t
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#ifdef ENABLE_ARM
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void ConvDwInt8Row(int32_t *output_ptr, const int8_t *input_ptr, const int16_t *weight_ptr, int num_pixels,
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int output_channel, int input_step, int8_t input_zp);
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void ConvDwInt8PostAlign4PerChannel(int8_t *dst, int32_t *buffer, int channel4, int32_t output_zp,
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int32_t *out_multiplier, int32_t *left_shift, int32_t *right_shift, int32_t acc_min,
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int32_t acc_max);
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void ConvDwInt8PostAlign4(int8_t *dst, int32_t *buffer, int num_pixels, int32_t output_zp, int32_t out_multiplier,
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int32_t left_shift, int32_t right_shift, int32_t acc_min, int32_t acc_max);
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void IndirectGemmInt16to32_8x4(int32_t *dst, const int16_t *src, const int16_t *weight, size_t ksize, size_t ic8,
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@ -64,9 +67,6 @@ void IndirectGemmInt8_4x4(int8_t *output, const int8_t *input, const int8_t *wei
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void DeconvDwInt8Center(int32_t *dst, const int16_t *src, const int16_t *weight, size_t height, size_t width,
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size_t kernel_h, size_t kernel_w, size_t out_h_step, size_t block_channel, size_t in_sh_step,
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size_t in_sw_step, size_t in_kh_step, size_t in_kw_step);
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void ConvDwInt8PostAlign4PerChannel(int8_t *dst, int32_t *buffer, int channel4, int32_t output_zp,
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int32_t *out_multiplier, int32_t *left_shift, int32_t *right_shift, int32_t acc_min,
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int32_t acc_max);
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#endif
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#ifdef __cplusplus
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@ -39,7 +39,7 @@ void ConvDwInt8Post(int8_t *dst, int32_t *buffer, int output_w, int channel, int
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// support perchannel
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for (int w = 0; w < output_w; w++) {
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int channel4 = 0;
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#ifdef ENABLE_ARM64
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#ifdef ENABLE_ARM
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channel4 = channel / 4 * 4;
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ConvDwInt8PostAlign4PerChannel(dst, buffer, channel4, output_zp, out_multiplier, left_shift, right_shift, acc_min,
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acc_max);
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