forked from OSSInnovation/mindspore
!3831 CUDA - GPU MirrorPad New Op
Merge pull request !3831 from danishnxt/GPU_One
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8f17535045
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <assert.h>
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#include <stdio.h>
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#include <stdint.h>
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#include "backend/kernel_compiler/gpu/cuda_impl/mirror_pad_impl.cuh"
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__inline__ __device__ bool range_check(int x, int y, int padded_width, int padded_height) {
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// check for existence in current padded array
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if (((x >= 0) && (x <= padded_width - 1)) && ((y >= 0) && (y <= padded_height - 1))) {
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return true;
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}
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return false;
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}
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template <typename T>
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__global__ void MirrorPad(const size_t size, const T *input, const int num, const int channels, const int old_height,
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const int old_width, const int padded_height, const int padded_width, const int padd_dim,
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const int *paddings, int mode, T *output) {
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int padd_offset = 4 * (padd_dim - 2);
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int pad_left_ = paddings[padd_offset + 4];
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int pad_top_ = paddings[padd_offset + 0];
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// Create anchor points for old tensor positions inside new tensor
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int ap1_x = pad_left_;
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int ap1_y = pad_top_;
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int ap2_x = pad_left_ + old_width - 1;
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int ap2_y = pad_top_ + old_height - 1;
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for (size_t pos = blockIdx.x * blockDim.x + threadIdx.x; pos < size; pos += blockDim.x * gridDim.x) {
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int block_num = (pos / padded_width) / padded_height;
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const int padded_x = pos % padded_width;
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const int padded_y = (pos / padded_width) % padded_height;
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// distance to move from anchor point
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int x_dist = 0;
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int y_dist = 0;
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// x,y value to mirror in new tenspr
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int matchval_x_index = padded_x;
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int matchval_y_index = padded_y;
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if (padded_y - pad_top_ < 0 || padded_x - pad_left_ < 0 || padded_y - pad_top_ >= old_height ||
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padded_x - pad_left_ >= old_width) {
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if ((padded_x < ap1_x) || (padded_x > ap2_x)) {
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x_dist = (padded_x < ap1_x) ? (ap1_x - padded_x) : (padded_x - ap2_x); // GEN DIST
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matchval_x_index = (padded_x < ap1_x) ? (ap1_x + x_dist - mode) : (ap2_x - x_dist + mode);
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}
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if ((padded_y < ap1_y) || (padded_y > ap2_y)) {
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y_dist = (padded_y < ap1_y) ? (ap1_y - padded_y) : (padded_y - ap2_y);
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matchval_y_index = (padded_y < ap1_y) ? (ap1_y + y_dist - mode) : (ap2_y - y_dist + mode);
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}
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output[pos] =
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input[(block_num * old_height + matchval_y_index - pad_top_) * old_width + matchval_x_index - pad_left_];
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} else {
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// existing values remain the same
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output[pos] = input[(block_num * old_height + padded_y - pad_top_) * old_width + padded_x - pad_left_];
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}
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}
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return;
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}
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template <typename T>
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__global__ void MirrorPadGrad(const size_t size, const T *dy, const int num, const int channels,
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const int padded_height, const int padded_width, const int old_height,
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const int old_width, const int padd_dim, const int *paddings, int mode, T *dx) {
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int padd_offset = 4 * (padd_dim - 2);
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int pad_left_ = paddings[padd_offset + 4];
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int pad_top_ = paddings[padd_offset + 0];
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// Create anchor points for positions in the dy array
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int ap1_x = pad_left_;
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int ap1_y = pad_top_;
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int ap2_x = pad_left_ + old_width - 1;
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int ap2_y = pad_top_ + old_height - 1;
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int adjust = 0; // adjust dist from reflection axis for symmetric padding
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if (mode == 1) {
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adjust = 1;
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}
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for (size_t pos = blockIdx.x * blockDim.x + threadIdx.x; pos < size; pos += blockDim.x * gridDim.x) {
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int block_num = (pos / old_width) / old_height;
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// refer to indices of original values inside padded array
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const int padded_x = (pos % old_width) + pad_left_;
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const int padded_y = ((pos / old_width) % old_height) + pad_top_;
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// copy positions own value into output
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dx[pos] = dx[pos] + dy[(block_num * padded_height + padded_y) * padded_width + padded_x];
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int x_dist_1 = (ap1_x - padded_x - adjust);
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int y_dist_1 = (ap1_y - padded_y - adjust);
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int x_dist_2 = (ap2_x - padded_x + adjust);
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int y_dist_2 = (ap2_y - padded_y + adjust);
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int axis_dist[] = {x_dist_1, x_dist_2, y_dist_1, y_dist_2};
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int anch_point[] = {ap1_x, ap2_x, ap1_y, ap2_y};
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bool x_axis_check[] = {true, true, false, false}; // true - update X , false - update Y
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int temp_x = 0;
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int temp_y = 0;
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// mirroring in axis lines
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for (int x = 0; x < 4; x++) {
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if (axis_dist[x] != 0) {
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if (x_axis_check[x]) {
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temp_y = padded_y;
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temp_x = anch_point[x] + axis_dist[x];
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} else {
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temp_x = padded_x;
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temp_y = anch_point[x] + axis_dist[x];
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}
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if (range_check(temp_x, temp_y, padded_width, padded_height)) {
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dx[pos] = dx[pos] + dy[(block_num * padded_height + temp_y) * padded_width + temp_x];
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}
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}
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}
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// mirroring at corners
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for (int x = 0; x < 2; x++) {
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for (int y = 2; y < 4; y++) {
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if ((axis_dist[x] != 0) && (axis_dist[y] != 0)) {
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temp_x = anch_point[x] + axis_dist[x];
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temp_y = anch_point[y] + axis_dist[y];
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if (range_check(temp_x, temp_y, padded_width, padded_height)) {
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dx[pos] = dx[pos] + dy[(block_num * padded_height + temp_y) * padded_width + temp_x];
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}
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}
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}
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}
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}
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return;
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}
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template <typename T>
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void CalMirrorPad(const size_t size, const T *input, const int num, const int channels, const int old_height,
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const int old_width, const int padded_height, const int padded_width, int padd_num,
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const int *paddings, const int mode, T *output, cudaStream_t cuda_stream) {
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MirrorPad<<<GET_BLOCKS(size), GET_THREADS, 0, cuda_stream>>>(
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size, input, num, channels, old_height, old_width, padded_height, padded_width, padd_num, paddings, mode, output);
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return;
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}
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template <typename T>
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void CalMirrorPadGrad(const size_t size, const T *dy, const int num, const int channels, const int padded_height,
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const int padded_width, const int old_height, const int old_width, const int padd_dim,
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const int *paddings, int mode, T *dx, cudaStream_t cuda_stream) {
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MirrorPadGrad<<<GET_BLOCKS(size), GET_THREADS, 0, cuda_stream>>>(size, dy, num, channels, padded_height, padded_width,
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old_height, old_width, padd_dim, paddings, mode, dx);
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return;
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}
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template void CalMirrorPad<float>(const size_t size, const float *input, const int num, const int channels,
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const int old_height, const int old_width, const int padded_height,
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const int padded_width, int padd_num, const int *paddings, int mode, float *output,
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cudaStream_t cuda_stream);
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template void CalMirrorPadGrad<float>(const size_t size, const float *dy, const int num, const int channels,
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const int old_height, const int old_width, const int padded_height,
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const int padded_width, const int padd_dim, const int *paddings, int mode,
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float *dx, cudaStream_t cuda_stream);
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template void CalMirrorPad<half>(const size_t size, const half *input, const int num, const int channels,
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const int old_height, const int old_width, const int padded_height,
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const int padded_width, int padd_num, const int *paddings, int mode, half *output,
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cudaStream_t cuda_stream);
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template void CalMirrorPadGrad<half>(const size_t size, const half *dy, const int num, const int channels,
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const int old_height, const int old_width, const int padded_height,
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const int padded_width, const int padd_dim, const int *paddings, int mode,
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half *dx, cudaStream_t cuda_stream);
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@ -0,0 +1,31 @@
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_MIRROR_PAD_IMPL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_MIRROR_PAD_IMPL_H_
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#include <cuda_runtime.h>
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#include "runtime/device/gpu/cuda_common.h"
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template <typename T>
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void CalMirrorPad(const size_t size, const T *input, const int num, const int channels, const int old_height,
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const int old_width, const int padded_height, const int padded_width, int padd_num,
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const int *paddings, int mode, T *output, cudaStream_t cuda_stream);
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template <typename T>
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void CalMirrorPadGrad(const size_t size, const T *dy, const int num, const int channels, const int padded_height,
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const int padded_width, const int old_height, const int old_width, const int padd_dim,
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const int *paddings, int mode, T *dx, cudaStream_t cuda_stream);
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#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_MIRROR_PAD_IMPL_H_
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
|
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "backend/kernel_compiler/gpu/nn/mirror_pad_gpu_kernel.h"
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namespace mindspore {
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namespace kernel {
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MS_REG_GPU_KERNEL_ONE(
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MirrorPad,
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KernelAttr().AddInputAttr(kNumberTypeFloat32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat32),
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MirrorPadGpuFwdKernel, float)
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MS_REG_GPU_KERNEL_ONE(
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MirrorPad,
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KernelAttr().AddInputAttr(kNumberTypeFloat16).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat16),
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MirrorPadGpuFwdKernel, half)
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} // namespace kernel
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} // namespace mindspore
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@ -0,0 +1,150 @@
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
|
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* http://www.apache.org/licenses/LICENSE-2.0
|
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*
|
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
|
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* limitations under the License.
|
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GPU_KERNEL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GPU_KERNEL_H_
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#include <iostream>
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#include <vector>
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#include <string>
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#include "backend/kernel_compiler/gpu/gpu_kernel.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
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#include "backend/kernel_compiler/gpu/cuda_impl/mirror_pad_impl.cuh"
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namespace mindspore {
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namespace kernel {
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template <typename T>
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class MirrorPadGpuFwdKernel : public GpuKernel {
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public:
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MirrorPadGpuFwdKernel()
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: num_input_(0), num_paddings_(0), mode_(0), input_size_(1), output_size_(1), workspace_size_(0) {}
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~MirrorPadGpuFwdKernel() override = default;
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const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
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const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
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const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
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bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
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const std::vector<AddressPtr> &outputs, void *stream_ptr) override {
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T *input = GetDeviceAddress<T>(inputs, 0);
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int *paddings = GetDeviceAddress<int>(inputs, 1);
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T *output = GetDeviceAddress<T>(outputs, 0);
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size_t size = output_size_ / sizeof(T);
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int dim_offset = output_shape_.size() - 2;
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CalMirrorPad(size, input, input_shape_[0], input_shape_[1], input_shape_[2], input_shape_[3],
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output_shape_[dim_offset + 0], output_shape_[dim_offset + 1], num_paddings_, paddings, mode_, output,
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reinterpret_cast<cudaStream_t>(stream_ptr));
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return true;
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}
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bool Init(const CNodePtr &kernel_node) override {
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size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
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if (input_num != 2) {
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MS_LOG(ERROR) << "Input number is " << input_num << ", but MirrorPad needs 2 input.";
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return false;
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}
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// check number of output -> should be 1
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size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
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if (output_num != 1) {
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MS_LOG(ERROR) << "Output number is " << output_num << ", but Pad needs 1 output.";
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return false;
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}
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string mode = GetValue<string>(AnfAlgo::GetCNodePrimitive(kernel_node)->GetAttr("mode"));
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if (mode == "REFLECT") {
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mode_ = 0; // reflected mirroring
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} else {
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mode_ = 1; // symmetric mirroring
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}
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auto input_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
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// shape adjustement -> from 2d/3d to 4d to standardize
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if (input_shape.size() == 4) {
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} else if (input_shape.size() == 3) {
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auto it = input_shape.begin();
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input_shape.insert(it, 1); // batch padding
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} else if (input_shape.size() == 2) {
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auto it = input_shape.begin();
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input_shape.insert(it, 2, 1); // channel padding
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}
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for (auto in_shape : input_shape) {
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input_size_ *= in_shape;
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input_shape_.push_back(in_shape);
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}
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num_input_ = input_size_;
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input_size_ *= sizeof(T);
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auto padding_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 1);
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num_paddings_ = padding_shape[0];
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input_size_ += 2 * num_paddings_ * sizeof(int);
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output_size_ = sizeof(T);
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auto output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
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for (auto x : output_shape) {
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output_size_ *= x;
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output_shape_.push_back(x);
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}
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int max_width = input_shape_[3];
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int max_height = input_shape_[2];
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// basic error check for padding value
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if (mode_ == 1) { // symmetric
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max_width = max_width + (2 * max_width);
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max_height = max_height + (2 * max_height);
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} else { // reflect
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max_width = max_width + (2 * (max_width - 1));
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max_height = max_height + (2 * (max_height - 1));
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}
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if (output_shape_[(output_shape_.size() - 2) + 0] > max_width ||
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output_shape_[(output_shape_.size() - 2) + 1] > max_width) {
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MS_LOG(ERROR) << "ERROR: Padding value too high for input Tensor on 1 or more dims";
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return false;
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}
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InitSizeLists();
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return true;
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}
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protected:
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void InitSizeLists() override {
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input_size_list_.push_back(num_input_ * sizeof(T));
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input_size_list_.push_back(2 * num_paddings_ * sizeof(int));
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output_size_list_.push_back(output_size_);
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}
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private:
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||||
size_t num_input_;
|
||||
int num_paddings_;
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||||
int mode_;
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||||
std::vector<int> input_shape_; // dims of the input data
|
||||
std::vector<int> output_shape_; // dims of the output data
|
||||
// default
|
||||
size_t input_size_;
|
||||
size_t output_size_;
|
||||
size_t workspace_size_;
|
||||
std::vector<size_t> input_size_list_;
|
||||
std::vector<size_t> output_size_list_;
|
||||
std::vector<size_t> workspace_size_list_;
|
||||
};
|
||||
} // namespace kernel
|
||||
} // namespace mindspore
|
||||
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GPU_KERNEL_H_
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/**
|
||||
* Copyright 2020 Huawei Technologies Co., Ltd
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "backend/kernel_compiler/gpu/nn/mirror_pad_grad_gpu_kernel.h"
|
||||
|
||||
namespace mindspore {
|
||||
namespace kernel {
|
||||
MS_REG_GPU_KERNEL_ONE(
|
||||
MirrorPadGrad,
|
||||
KernelAttr().AddInputAttr(kNumberTypeFloat32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat32),
|
||||
MirrorPadGpuBackKernel, float)
|
||||
MS_REG_GPU_KERNEL_ONE(
|
||||
MirrorPadGrad,
|
||||
KernelAttr().AddInputAttr(kNumberTypeFloat16).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat16),
|
||||
MirrorPadGpuBackKernel, half)
|
||||
} // namespace kernel
|
||||
} // namespace mindspore
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/**
|
||||
* Copyright 2020 Huawei Technologies Co., Ltd
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GRAD_GPU_KERNEL_H_
|
||||
#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GRAD_GPU_KERNEL_H_
|
||||
|
||||
#include <iostream>
|
||||
#include <vector>
|
||||
#include <string>
|
||||
#include "backend/kernel_compiler/gpu/gpu_kernel.h"
|
||||
#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
|
||||
#include "backend/kernel_compiler/gpu/cuda_impl/mirror_pad_impl.cuh"
|
||||
|
||||
namespace mindspore {
|
||||
namespace kernel {
|
||||
template <typename T>
|
||||
class MirrorPadGpuBackKernel : public GpuKernel {
|
||||
public:
|
||||
MirrorPadGpuBackKernel()
|
||||
: num_input_(0), num_paddings_(0), mode_(0), input_size_(1), output_size_(1), workspace_size_(0) {}
|
||||
~MirrorPadGpuBackKernel() override = default;
|
||||
|
||||
const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
|
||||
const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
|
||||
const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
|
||||
|
||||
bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
|
||||
const std::vector<AddressPtr> &outputs, void *stream_ptr) override {
|
||||
T *input = GetDeviceAddress<T>(inputs, 0);
|
||||
int *paddings = GetDeviceAddress<int>(inputs, 1);
|
||||
T *output = GetDeviceAddress<T>(outputs, 0);
|
||||
|
||||
size_t size = output_size_ / sizeof(T);
|
||||
int dim_offset = output_shape_.size() - 2;
|
||||
|
||||
CalMirrorPadGrad(size, input, input_shape_[0], input_shape_[1], input_shape_[2], input_shape_[3],
|
||||
output_shape_[dim_offset + 0], output_shape_[dim_offset + 1], num_paddings_, paddings, mode_,
|
||||
output, reinterpret_cast<cudaStream_t>(stream_ptr));
|
||||
return true;
|
||||
}
|
||||
|
||||
bool Init(const CNodePtr &kernel_node) override {
|
||||
size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
|
||||
if (input_num != 2) {
|
||||
MS_LOG(ERROR) << "Input number is " << input_num << ", but MirrorPadGrad needs 2 input.";
|
||||
return false;
|
||||
}
|
||||
// check number of output -> should be 1
|
||||
size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
|
||||
if (output_num != 1) {
|
||||
MS_LOG(ERROR) << "Output number is " << output_num << ", but MirrorPadGrad needs 1 output.";
|
||||
return false;
|
||||
}
|
||||
|
||||
string mode = GetValue<string>(AnfAlgo::GetCNodePrimitive(kernel_node)->GetAttr("mode"));
|
||||
|
||||
if (mode == "REFLECT") {
|
||||
mode_ = 0; // reflected mirroring
|
||||
} else {
|
||||
mode_ = 1; // symmetric mirroring
|
||||
}
|
||||
|
||||
auto input_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
|
||||
// shape adjustement -> from 2d/3d to 4d to standardize
|
||||
if (input_shape.size() == 4) {
|
||||
} else if (input_shape.size() == 3) {
|
||||
auto it = input_shape.begin();
|
||||
input_shape.insert(it, 1); // batch padding
|
||||
} else if (input_shape.size() == 2) {
|
||||
auto it = input_shape.begin();
|
||||
input_shape.insert(it, 2, 1); // channel padding
|
||||
}
|
||||
|
||||
for (auto in_shape : input_shape) {
|
||||
input_size_ *= in_shape;
|
||||
input_shape_.push_back(in_shape);
|
||||
}
|
||||
num_input_ = input_size_;
|
||||
input_size_ *= sizeof(T);
|
||||
|
||||
auto padding_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 1);
|
||||
num_paddings_ = padding_shape[0];
|
||||
input_size_ += +(2 * num_paddings_ * sizeof(int));
|
||||
|
||||
output_size_ = sizeof(T);
|
||||
auto output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
|
||||
for (auto x : output_shape) {
|
||||
output_size_ *= x;
|
||||
output_shape_.push_back(x);
|
||||
}
|
||||
|
||||
int max_width = input_shape_[3];
|
||||
int max_height = input_shape_[2];
|
||||
|
||||
// basic error check for padding value
|
||||
if (mode_ == 1) { // symmetric
|
||||
max_width = max_width + (2 * max_width);
|
||||
max_height = max_height + (2 * max_height);
|
||||
} else { // reflect
|
||||
max_width = max_width + (2 * (max_width - 1));
|
||||
max_height = max_height + (2 * (max_height - 1));
|
||||
}
|
||||
|
||||
if (output_shape_[(output_shape_.size() - 2) + 0] > max_width ||
|
||||
output_shape_[(output_shape_.size() - 2) + 1] > max_width) {
|
||||
MS_LOG(ERROR) << "ERROR: Padding value too high for input Tensor on 1 or more DIMS";
|
||||
return false;
|
||||
}
|
||||
|
||||
InitSizeLists();
|
||||
return true;
|
||||
}
|
||||
|
||||
protected:
|
||||
void InitSizeLists() override {
|
||||
input_size_list_.push_back(num_input_ * sizeof(T));
|
||||
input_size_list_.push_back(2 * num_paddings_ * sizeof(int));
|
||||
output_size_list_.push_back(output_size_);
|
||||
}
|
||||
|
||||
private:
|
||||
size_t num_input_;
|
||||
int num_paddings_;
|
||||
int mode_;
|
||||
std::vector<int> input_shape_; // dims of the input data
|
||||
std::vector<int> output_shape_; // dims of the output data
|
||||
// default
|
||||
size_t input_size_;
|
||||
size_t output_size_;
|
||||
size_t workspace_size_;
|
||||
std::vector<size_t> input_size_list_;
|
||||
std::vector<size_t> output_size_list_;
|
||||
std::vector<size_t> workspace_size_list_;
|
||||
};
|
||||
} // namespace kernel
|
||||
} // namespace mindspore
|
||||
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_MIRROR_PAD_GRAD_GPU_KERNEL_H_
|
||||
|
|
@ -2761,12 +2761,17 @@ class MirrorPad(PrimitiveWithInfer):
|
|||
paddings_value = paddings['value'].asnumpy()
|
||||
paddings_size = paddings_value.size
|
||||
validator.check_integer('paddings.shape', paddings_size, len(x_shape) * 2, Rel.EQ, self.name)
|
||||
if not np.all(paddings_size >= 0):
|
||||
if not np.all(paddings_value >= 0):
|
||||
raise ValueError('All elements of paddings must be >= 0.')
|
||||
adjust = 0
|
||||
if self.mode == 'SYMMETRIC':
|
||||
adjust = 1
|
||||
for i in range(0, int(paddings_size / 2)):
|
||||
if (paddings_value[i, 0] >= x_shape[i] + adjust) or (paddings_value[i, 1] >= x_shape[i] + adjust):
|
||||
raise ValueError('At least one dim has too high a padding value for this input and mode')
|
||||
y_shape = ()
|
||||
for i in range(0, int(paddings_size / 2)):
|
||||
y_shape += ((x_shape[i] + paddings_value[i, 0] + paddings_value[i, 1]),)
|
||||
|
||||
return {'shape': y_shape,
|
||||
'dtype': input_x['dtype'],
|
||||
'value': None}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,88 @@
|
|||
# Copyright 2020 Huawei Technologies Co., Ltd
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# ============================================================================
|
||||
|
||||
import pytest
|
||||
import numpy as np
|
||||
|
||||
import mindspore
|
||||
import mindspore.nn as nn
|
||||
import mindspore.context as context
|
||||
|
||||
from mindspore import Tensor
|
||||
from mindspore.ops.composite import GradOperation
|
||||
|
||||
@pytest.mark.level0
|
||||
@pytest.mark.platform_x86_gpu_training
|
||||
@pytest.mark.env_onecard
|
||||
def test_mirror_pad():
|
||||
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||
|
||||
test1_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]]
|
||||
test_1_paddings = ((0, 0), (0, 0), (1, 1), (2, 2))
|
||||
test1_arr_exp = [[[[6, 5, 4, 5, 6, 5, 4], [3, 2, 1, 2, 3, 2, 1], [6, 5, 4, 5, 6, 5, 4],
|
||||
[9, 8, 7, 8, 9, 8, 7], [6, 5, 4, 5, 6, 5, 4]]]]
|
||||
|
||||
test2_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]]
|
||||
test_2_paddings = ((0, 0), (0, 0), (1, 1), (2, 2))
|
||||
test2_arr_exp = [[[[2, 1, 1, 2, 3, 3, 2], [2, 1, 1, 2, 3, 3, 2], [5, 4, 4, 5, 6, 6, 5],
|
||||
[8, 7, 7, 8, 9, 9, 8], [8, 7, 7, 8, 9, 9, 8]]]]
|
||||
|
||||
reflectOp = nn.Pad(mode='REFLECT', paddings=test_1_paddings)
|
||||
symmOp = nn.Pad(mode='SYMMETRIC', paddings=test_2_paddings)
|
||||
|
||||
x_test_1 = Tensor(np.array(test1_arr_in), dtype=mindspore.float32)
|
||||
x_test_2 = Tensor(np.array(test2_arr_in), dtype=mindspore.float32)
|
||||
|
||||
y_test_1 = reflectOp(x_test_1).asnumpy()
|
||||
y_test_2 = symmOp(x_test_2).asnumpy()
|
||||
|
||||
print(np.array(test1_arr_in))
|
||||
print(y_test_1)
|
||||
|
||||
np.testing.assert_equal(np.array(test1_arr_exp), y_test_1)
|
||||
np.testing.assert_equal(np.array(test2_arr_exp), y_test_2)
|
||||
|
||||
|
||||
class Grad(nn.Cell):
|
||||
def __init__(self, network):
|
||||
super(Grad, self).__init__()
|
||||
self.grad = GradOperation(name="get_all", get_all=True, sens_param=True)
|
||||
self.network = network
|
||||
def construct(self, input_, output_grad):
|
||||
return self.grad(self.network)(input_, output_grad)
|
||||
|
||||
class Net(nn.Cell):
|
||||
def __init__(self):
|
||||
super(Net, self).__init__()
|
||||
self.pad = nn.Pad(mode="REFLECT", paddings=((0, 0), (0, 0), (1, 0), (0, 2)))
|
||||
def construct(self, x):
|
||||
return self.pad(x)
|
||||
|
||||
|
||||
@pytest.mark.level0
|
||||
@pytest.mark.platform_x86_gpu_training
|
||||
@pytest.mark.env_onecard
|
||||
def test_mirror_pad_backprop():
|
||||
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||
test_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]] # size -> 3*3
|
||||
test_arr_in = Tensor(test_arr_in, dtype=mindspore.float32)
|
||||
dy = (np.ones((1, 1, 4, 5)) * 0.1).astype(np.float32)
|
||||
expected_dx = np.array([[[[0.2, 0.2, 0.1],
|
||||
[0.4, 0.4, 0.2],
|
||||
[0.2, 0.2, 0.1]]]])
|
||||
net = Grad(Net())
|
||||
dx = net(test_arr_in, Tensor(dy))
|
||||
dx = dx[0].asnumpy()
|
||||
np.testing.assert_array_almost_equal(dx, expected_dx)
|
||||
Loading…
Reference in New Issue