add ExampleTopWithBlockDevice and tests

src/main/scala/blkdev/Configs.scala

@@ -0,0 +1,9 @@
+package blkdev
+
+import config.{Parameters, Config}
+import example.DefaultExampleConfig
+import testchipip.{WithBlockDevice, WithNBlockDeviceTrackers}
+
+class BlockDeviceConfig extends Config(
+  new WithBlockDevice ++
+  new DefaultExampleConfig)

src/main/scala/blkdev/TestHarness.scala

@@ -0,0 +1,22 @@
+package blkdev
+
+import diplomacy.LazyModule
+import chisel3._
+import config.Parameters
+import testchipip.GeneratorApp
+import example._
+
+class TestHarness(implicit p: Parameters) extends Module {
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
+
+  val dut = Module(LazyModule(new ExampleTopWithBlockDevice).module)
+  dut.connectSimAXIMem()
+  dut.connectSimBlockDevice()
+  io.success := dut.connectSimSerial()
+}
+
+object Generator extends GeneratorApp {
+  generateFirrtl
+}

src/main/scala/blkdev/Top.scala

@@ -0,0 +1,15 @@
+package blkdev
+
+import chisel3._
+import config.Parameters
+import testchipip._
+import example._
+
+class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
+    with HasPeripheryBlockDevice {
+  override lazy val module = new ExampleTopWithBlockDeviceModule(this)
+}
+
+class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
+  extends ExampleTopModule(l)
+  with HasPeripheryBlockDeviceModuleImp

testchipip

@@ -1 +1 @@
-Subproject commit 2e9301c19012d7895abca7165296dd788893bccc
+Subproject commit 27f0aed7b6b57d0621081b2638569775f9a530fc

tests/.gitignore

@@ -1,2 +1,3 @@
 *.o
 *.riscv
+*.dump

tests/Makefile

@@ -3,7 +3,7 @@ OBJDUMP=riscv64-unknown-elf-objdump
 CFLAGS=-mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf
 LDFLAGS=-static -nostdlib -nostartfiles -lgcc
 
-PROGRAMS = pwm
+PROGRAMS = pwm blkdev
 
 default: $(addsuffix .riscv,$(PROGRAMS))
 
@@ -15,8 +15,8 @@ dumps: $(addsuffix .dump,$(PROGRAMS))
 %.o: %.c mmio.h
 	$(GCC) $(CFLAGS) -c $< -o $@
 
-%.riscv: %.o crt.o syscalls.o
-	$(GCC) -T link.ld $(LDFLAGS) $^ -o $@
+%.riscv: %.o crt.o syscalls.o link.ld
+	$(GCC) -T link.ld $(LDFLAGS) $< crt.o syscalls.o -o $@
 
 %.dump: %.riscv
 	$(OBJDUMP) -D $< > $@

tests/blkdev.c

@@ -0,0 +1,96 @@
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "mmio.h"
+
+#define BLKDEV_BASE 0x10015000
+#define BLKDEV_ADDR BLKDEV_BASE
+#define BLKDEV_OFFSET (BLKDEV_BASE + 4)
+#define BLKDEV_LEN (BLKDEV_BASE + 8)
+#define BLKDEV_WRITE (BLKDEV_BASE + 12)
+#define BLKDEV_REQUEST (BLKDEV_BASE + 16)
+#define BLKDEV_NREQUEST (BLKDEV_BASE + 20)
+#define BLKDEV_COMPLETE (BLKDEV_BASE + 24)
+#define BLKDEV_NCOMPLETE (BLKDEV_BASE + 28)
+#define BLKDEV_NSECTORS (BLKDEV_BASE + 32)
+#define BLKDEV_SECTOR_SIZE 512
+#define BLKDEV_SECTOR_SHIFT 9
+
+size_t blkdev_nsectors(void)
+{
+	return read_reg(BLKDEV_NSECTORS);
+}
+
+int blkdev_read(void *addr, unsigned long offset, size_t nsectors)
+{
+	int req_tag, resp_tag;
+
+	write_reg(BLKDEV_ADDR, (unsigned long) addr);
+	write_reg(BLKDEV_OFFSET, offset);
+	write_reg(BLKDEV_LEN, nsectors);
+	write_reg(BLKDEV_WRITE, 0);
+
+	while (read_reg(BLKDEV_NREQUEST) == 0);
+	req_tag = read_reg(BLKDEV_REQUEST);
+
+	while (read_reg(BLKDEV_NCOMPLETE) == 0);
+
+	resp_tag = read_reg(BLKDEV_COMPLETE);
+	return (resp_tag == req_tag) ? 0 : -1;
+}
+
+int blkdev_write(unsigned long offset, void *addr, size_t nsectors)
+{
+	int req_tag, resp_tag;
+
+	write_reg(BLKDEV_ADDR, (unsigned long) addr);
+	write_reg(BLKDEV_OFFSET, offset);
+	write_reg(BLKDEV_LEN, nsectors);
+	write_reg(BLKDEV_WRITE, 1);
+
+	req_tag = read_reg(BLKDEV_REQUEST);
+
+	while (read_reg(BLKDEV_NCOMPLETE) == 0);
+
+	resp_tag = read_reg(BLKDEV_COMPLETE);
+	return (resp_tag == req_tag) ? 0 : -1;
+}
+
+#define NSECTORS 2
+#define TEST_SIZE (NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int))
+
+unsigned int test_data[TEST_SIZE];
+unsigned int res_data[TEST_SIZE];
+
+int main(void)
+{
+	for (int i = 0; i < TEST_SIZE; i++) {
+		test_data[i] = i << 8;
+	}
+
+	asm volatile ("fence");
+
+	printf("Block device with %ld sectors\n", blkdev_nsectors());
+
+	if (blkdev_write(0, (void *) test_data, NSECTORS)) {
+		printf("write error\n");
+		return 1;
+	}
+
+	if (blkdev_read((void *) res_data, 0, NSECTORS)) {
+		printf("read error\n");
+		return 1;
+	}
+
+	for (int i = 0; i < TEST_SIZE; i++) {
+		if (test_data[i] != res_data[i]) {
+			printf("data mismatch at %d: %x != %x\n",
+					i, test_data[i], res_data[i]);
+			return 1;
+		}
+	}
+
+	printf("All correct\n");
+
+	return 0;
+}

tests/link.ld

@@ -30,7 +30,7 @@ SECTIONS
   .text : { *(.text) }
 
   /* data segment */
-  .data : { *(.data) }
+  .data ALIGN(0x40) : { *(.data) }
 
   .sdata : {
     __global_pointer$ = . + 0x800;
@@ -43,7 +43,7 @@ SECTIONS
     *(.sbss .sbss.* .gnu.linkonce.sb.*)
     *(.scommon)
   }
-  .bss : { *(.bss) }
+  .bss ALIGN(0x40) : { *(.bss) }
 
   /* thread-local data segment */
   .tdata :

vsim/Makefile

@@ -22,16 +22,19 @@ sim_vsrcs = \
 	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
 	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
 	$(base_dir)/testchipip/vsrc/SimSerial.v \
+	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
 
 sim_csrcs = \
-	$(base_dir)/testchipip/csrc/SimSerial.cc
+	$(base_dir)/testchipip/csrc/SimSerial.cc \
+	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
+	$(base_dir)/testchipip/csrc/blkdev.cc \
 
 VCS = vcs -full64
 
 VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
 	+rad +v2k +vcs+lic+wait \
 	+vc+list -CC "-I$(VCS_HOME)/include" \
-	-CC "-I$(RISCV)/include" \
+	-CC "-I$(RISCV)/include -I$(base_dir)/testchipip/csrc" \
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
 	$(RISCV)/lib/libfesvr.so \