upgrade to latest rocket-chip

Makefrag

@@ -30,9 +30,11 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala
 
 build_dir=$(sim_dir)/generated-src
 
+bootrom_img = $(base_dir)/bootrom/bootrom.img
+
 CHISEL_ARGS ?=
 
-$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
+$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 

bootrom/Makefile

@@ -7,10 +7,13 @@ OBJDUMP=riscv64-unknown-elf-objdump
 all: $(bootrom_img)
 
 %.img: %.elf
-	$(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@
+	$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
 
 %.elf: %.S linker.ld
 	$(GCC) -Tlinker.ld $< -nostdlib -static -o $@
 
 %.dump: %.elf
 	$(OBJDUMP) -d $< > $@
+
+clean:
+	rm -f *.elf *.dump *.img

bootrom/bootrom.S

@@ -1,20 +1,23 @@
-.text
-.global _start
+#define DRAM_BASE 0x80000000
+
+.section .text.start, "ax", @progbits
+.globl _start
 _start:
+  csrr a0, mhartid
+  sll a0, a0, 2 // offset for hart msip
+  li a1, 0x2000000 // base address of clint
+  add a0, a0, a1
+  sw zero, 0(a0) // clear the interrupt
+  li a0, DRAM_BASE // program reset vector
+  csrw mepc, a0 // return from interrupt to start of user program
+  mret
+
+.section .text.hang, "ax", @progbits
+.globl _hang
+_hang:
   // This boot ROM doesn't know about any boot devices, so it just spins,
   // waiting for the serial interface to load the program and interrupt it
-  j setup_wfi_loop // reset vector
-  .word 0 // reserved
-  .word 0 // reserved
-  .word 0 // pointer to config string
-default_trap_vec:
-  j boot_trap // default trap vector
-  .word 0
-  .word 0
-  .word 0
-
-setup_wfi_loop:
-  la a0, default_trap_vec
+  la a0, _start
   csrw mtvec, a0
   li a0, 8 // MIE or MSIP bit
   csrw mie, a0 // set only MSIP in mie CSR
@@ -23,13 +26,3 @@ setup_wfi_loop:
 wfi_loop:
   wfi
   j wfi_loop
-
-boot_trap:
-  csrr a0, mhartid
-  sll a0, a0, 2 // offset for hart msip
-  li a1, 0x2000000 // base address of clint
-  add a0, a0, a1
-  sw zero, 0(a0) // clear the interrupt
-  li a0, 0x80000000 // program reset vector
-  csrw mepc, a0 // return from interrupt to start of user program
-  mret

bootrom/linker.ld

@@ -1,5 +1,9 @@
 SECTIONS
 {
-    . = 0x1000;
-    .text : { *(.text) }
+    ROM_BASE = 0x10000; /* ... but actually position independent */
+
+    . = ROM_BASE;
+    .text.start : { *(.text.start) }
+    . = ROM_BASE + 0x40;
+    .text.hang : { *(.text.hang) }
 }

rocket-chip

@@ -1 +1 @@
-Subproject commit 282b1ca766931463deefe0e404627171357c924a
+Subproject commit 7f1d3c445fbed98e4e16c508a23b92a90e349c3b

src/main/scala/example/TestHarness.scala

@@ -1,11 +1,12 @@
 package example
 
-import util.GeneratorApp
 import diplomacy.LazyModule
 import rocketchip._
 import testchipip._
 import chisel3._
 import config.Parameters
+import _root_.util.{HasGeneratorUtilities, ParsedInputNames}
+import java.io.File
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle {
@@ -17,11 +18,6 @@ class TestHarness(implicit val p: Parameters) extends Module {
   val dut = Module(buildTop(p).module)
   val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
 
-  dut.io.debug.map { dbg =>
-    dbg.req.valid := false.B
-    dbg.resp.ready := false.B
-  }
-
   val nMemChannels = p(coreplex.BankedL2Config).nMemoryChannels
   val mem = Module(LazyModule(new SimAXIMem(nMemChannels)).module)
   mem.io.axi4 <> dut.io.mem_axi4
@@ -29,9 +25,32 @@ class TestHarness(implicit val p: Parameters) extends Module {
   io.success := ser.io.exit
 }
 
-object Generator extends GeneratorApp {
-  val longName = names.topModuleProject + "." +
+trait ExampleGeneratorApp extends App with HasGeneratorUtilities {
+  lazy val names = ParsedInputNames(
+    targetDir = args(0),
+    topModuleProject = args(1),
+    topModuleClass = args(2),
+    configProject = args(3),
+    configs = args(4))
+
+  lazy val config = getConfig(names)
+  lazy val world = config.toInstance
+  lazy val params = Parameters.root(world)
+  lazy val circuit = Driver.elaborate(() =>
+      Class.forName(names.fullTopModuleClass)
+        .getConstructor(classOf[Parameters])
+        .newInstance(params)
+        .asInstanceOf[Module])
+
+  lazy val longName = names.topModuleProject + "." +
                  names.topModuleClass + "." +
                  names.configs
+
+  def generateFirrtl =
+    Driver.dumpFirrtl(circuit,
+      Some(new File(names.targetDir, s"$longName.fir")))
+}
+
+object Generator extends ExampleGeneratorApp {
   generateFirrtl
 }

src/main/scala/example/Top.scala

@@ -10,9 +10,9 @@ class ExampleTop(implicit p: Parameters) extends BaseTop()(p)
     with PeripheryBootROM
     with PeripheryZero
     with PeripheryCounter
-    with PeripheryDebug
     with HardwiredResetVector
     with RocketPlexMaster
+    with NoDebug
     with PeripherySerial {
   override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
 }
@@ -22,7 +22,6 @@ class ExampleTopBundle[+L <: ExampleTop](l: L) extends BaseTopBundle(l)
     with PeripheryBootROMBundle
     with PeripheryZeroBundle
     with PeripheryCounterBundle
-    with PeripheryDebugBundle
     with HardwiredResetVectorBundle
     with RocketPlexMasterBundle
     with PeripherySerialBundle
@@ -33,7 +32,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](l: L, b: ()
     with PeripheryBootROMModule
     with PeripheryZeroModule
     with PeripheryCounterModule
-    with PeripheryDebugModule
     with HardwiredResetVectorModule
     with RocketPlexMasterModule
+    with NoDebugModule
     with PeripherySerialModule

src/main/scala/pwm/TestHarness.scala

@@ -1,6 +1,5 @@
 package pwm
 
-import util.GeneratorApp
 import config.Parameters
 import diplomacy.LazyModule
 
@@ -9,9 +8,6 @@ class TestHarness(q: Parameters) extends example.TestHarness()(q) {
     LazyModule(new ExampleTopWithPWM()(p))
 }
 
-object Generator extends GeneratorApp {
-  val longName = names.topModuleProject + "." +
-                 names.topModuleClass + "." +
-                 names.configs
+object Generator extends example.ExampleGeneratorApp {
   generateFirrtl
 }

testchipip

@@ -1 +1 @@
-Subproject commit bc3e2d13579b05c453a98e5b3478c7db657d635b
+Subproject commit edecf84bfe8b4a2678de9e1e33d506f654e5c16f

tests/Makefile

@@ -1,8 +1,13 @@
 GCC=riscv64-unknown-elf-gcc
+OBJDUMP=riscv64-unknown-elf-objdump
 CFLAGS=-mcmodel=medany -std=gnu99 -O2 -fno-common -fno-builtin-printf
 LDFLAGS=-static -nostdlib -nostartfiles -lgcc
 
-default: pwm.riscv
+PROGRAMS = pwm
+
+default: $(addsuffix .riscv,$(PROGRAMS))
+
+dumps: $(addsuffix .dump,$(PROGRAMS))
 
 %.o: %.S
 	$(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@
@@ -13,5 +18,8 @@ default: pwm.riscv
 %.riscv: %.o crt.o syscalls.o
 	$(GCC) -T link.ld $(LDFLAGS) $^ -o $@
 
+%.dump: %.riscv
+	$(OBJDUMP) -D $< > $@
+
 clean:
-	rm -f *.riscv *.o
+	rm -f *.riscv *.o *.dump

tests/crt.S

@@ -2,7 +2,7 @@
 
 #include "encoding.h"
 
-#ifdef __riscv64
+#if __riscv_xlen == 64
 # define LREG ld
 # define SREG sd
 # define REGBYTES 8
@@ -12,12 +12,9 @@
 # define REGBYTES 4
 #endif
 
-  .text
+  .section ".text.init"
   .globl _start
 _start:
-  la t0, trap_entry
-  csrw mtvec, t0
-
   li  x1, 0
   li  x2, 0
   li  x3, 0
@@ -55,20 +52,23 @@ _start:
   csrs mstatus, t0
 
   # make sure XLEN agrees with compilation choice
-  csrr t0, misa
-#ifdef __riscv64
-  bltz t0, 1f
-#else
+  li t0, 1
+  slli t0, t0, 31
+#if __riscv_xlen == 64
   bgez t0, 1f
+#else
+  bltz t0, 1f
 #endif
-  li a0, 1234
-  j tohost_exit
+2:
+  li a0, 1
+  sw a0, tohost, t0
+  j 2b
 1:
 
-#ifdef __riscv_hard_float
+#ifdef __riscv_flen
   # initialize FPU if we have one
-  andi t0, t0, 1 << ('f' - 'a')
-  beqz t0, 1f
+  la t0, 1f
+  csrw mtvec, t0
 
   fssr    x0
   fmv.s.x f0, x0
@@ -103,12 +103,18 @@ _start:
   fmv.s.x f29,x0
   fmv.s.x f30,x0
   fmv.s.x f31,x0
+1:
 #endif
 
-1:
+  # initialize trap vector
+  la t0, trap_entry
+  csrw mtvec, t0
 
   # initialize global pointer
-  la gp, _gp
+.option push
+.option norelax
+  la gp, __global_pointer$
+.option pop
 
   la  tp, _end + 63
   and tp, tp, -64

tests/link.ld

@@ -12,6 +12,7 @@
    specifically one of the entires in bfd/cpu-mips.c */
 
 OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
 
 /*----------------------------------------------------------------------*/
 /* Sections                                                             */
@@ -22,7 +23,7 @@ SECTIONS
 
   /* text: test code section */
   . = 0x80000000;
-  .text.init : { crt.o(.text) }
+  .text.init : { *(.text.init) }
 
   .tohost ALIGN(0x1000) : { *(.tohost) }
 
@@ -32,7 +33,7 @@ SECTIONS
   .data : { *(.data) }
 
   .sdata : {
-    _gp = . + 0x800;
+    __global_pointer$ = . + 0x800;
     *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
     *(.sdata .sdata.* .gnu.linkonce.s.*)
   }
@@ -48,14 +49,14 @@ SECTIONS
   .tdata :
   {
     _tls_data = .;
-    crt.o(.tdata.begin)
+    *(.tdata.begin)
     *(.tdata)
-    crt.o(.tdata.end)
+    *(.tdata.end)
   }
   .tbss :
   {
     *(.tbss)
-    crt.o(.tbss.end)
+    *(.tbss.end)
   }
 
   /* End of uninitalized data segement */

tests/syscalls.c

@@ -5,16 +5,17 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <limits.h>
+#include <sys/signal.h>
 #include "util.h"
 
 #define SYS_write 64
-#define SYS_exit 93
-#define SYS_stats 1234
+
+#undef strcmp
 
 extern volatile uint64_t tohost;
 extern volatile uint64_t fromhost;
 
-static uintptr_t handle_frontend_syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2)
 {
   volatile uint64_t magic_mem[8] __attribute__((aligned(64)));
   magic_mem[0] = which;
@@ -36,7 +37,7 @@ static uintptr_t handle_frontend_syscall(uintptr_t which, uint64_t arg0, uint64_
 static uintptr_t counters[NUM_COUNTERS];
 static char* counter_names[NUM_COUNTERS];
 
-static int handle_stats(int enable)
+void setStats(int enable)
 {
   int i = 0;
 #define READ_CTR(name) do { \
@@ -50,7 +51,6 @@ static int handle_stats(int enable)
   READ_CTR(minstret);
 
 #undef READ_CTR
-  return 0;
 }
 
 void __attribute__((noreturn)) tohost_exit(uintptr_t code)
@@ -59,39 +59,19 @@ void __attribute__((noreturn)) tohost_exit(uintptr_t code)
   while (1);
 }
 
-uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
 {
-  if (cause != CAUSE_MACHINE_ECALL)
-    tohost_exit(1337);
-  else if (regs[17] == SYS_exit)
-    tohost_exit(regs[10]);
-  else if (regs[17] == SYS_stats)
-    regs[10] = handle_stats(regs[10]);
-  else
-    regs[10] = handle_frontend_syscall(regs[17], regs[10], regs[11], regs[12]);
-
-  return epc + ((*(unsigned short*)epc & 3) == 3 ? 4 : 2);
-}
-
-static uintptr_t syscall(uintptr_t num, uintptr_t arg0, uintptr_t arg1, uintptr_t arg2)
-{
-  register uintptr_t a7 asm("a7") = num;
-  register uintptr_t a0 asm("a0") = arg0;
-  register uintptr_t a1 asm("a1") = arg1;
-  register uintptr_t a2 asm("a2") = arg2;
-  asm volatile ("scall" : "+r"(a0) : "r"(a1), "r"(a2), "r"(a7));
-  return a0;
+  tohost_exit(1337);
 }
 
 void exit(int code)
 {
-  syscall(SYS_exit, code, 0, 0);
-  while (1);
+  tohost_exit(code);
 }
 
-void setStats(int enable)
+void abort()
 {
-  syscall(SYS_stats, enable, 0, 0);
+  exit(128 + SIGABRT);
 }
 
 void printstr(const char* s)

vsim/Makefile

@@ -20,7 +20,8 @@ sim_vsrcs = \
 	$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
 	$(base_dir)/rocket-chip/vsrc/TestDriver.v \
 	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
-	$(base_dir)/testchipip/vsrc/SimSerial.v
+	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
+	$(base_dir)/testchipip/vsrc/SimSerial.v \
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc