From d34b6a774f11c28d6c66ba1403ffc4e95491a558 Mon Sep 17 00:00:00 2001 From: liangchenghui Date: Mon, 29 Nov 2021 11:24:49 +0800 Subject: [PATCH] Add cast transdata operators register format. --- mindspore/ops/_op_impl/aicpu/cast.py | 1 + mindspore/ops/_op_impl/aicpu/trans_data.py | 2 ++ 2 files changed, 3 insertions(+) diff --git a/mindspore/ops/_op_impl/aicpu/cast.py b/mindspore/ops/_op_impl/aicpu/cast.py index 32dbea3147a..cd55e9ad0dc 100644 --- a/mindspore/ops/_op_impl/aicpu/cast.py +++ b/mindspore/ops/_op_impl/aicpu/cast.py @@ -104,6 +104,7 @@ cast_op_info = AiCPURegOp("Cast") \ .dtype_format(DataType.I32_Default, DataType.F32_Default) \ .dtype_format(DataType.I32_Default, DataType.F64_Default) \ .dtype_format(DataType.I32_Default, DataType.BOOL_Default) \ + .dtype_format(DataType.I32_5HD, DataType.I64_5HD) \ .dtype_format(DataType.I64_Default, DataType.U8_Default) \ .dtype_format(DataType.I64_Default, DataType.U16_Default) \ .dtype_format(DataType.I64_Default, DataType.U32_Default) \ diff --git a/mindspore/ops/_op_impl/aicpu/trans_data.py b/mindspore/ops/_op_impl/aicpu/trans_data.py index 6ceb905caff..17b9779e45e 100644 --- a/mindspore/ops/_op_impl/aicpu/trans_data.py +++ b/mindspore/ops/_op_impl/aicpu/trans_data.py @@ -24,6 +24,8 @@ trans_data_op_info = AiCPURegOp("TransData") \ .attr("dst_format", "str") \ .dtype_format(DataType.U16_Default, DataType.U16_5HD) \ .dtype_format(DataType.U16_5HD, DataType.U16_Default) \ + .dtype_format(DataType.I64_5HD, DataType.I64_Default) \ + .dtype_format(DataType.I32_5HD, DataType.I32_Default) \ .get_op_info() @op_info_register(trans_data_op_info)