forked from mindspore-Ecosystem/mindspore
sparse apply ftrl gpu kernel
This commit is contained in:
tom__chen
parent
8aaa20f918
commit
71b235c302
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "sparse_ftrl_impl.cuh"
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#include "runtime/device/gpu/cuda_common.h"
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#include "include/cuda_fp16.h"
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template <typename T>
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__device__ __forceinline__ T PowFunc(T x, T y) {
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return pow(x, y);
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}
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template <>
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__device__ __forceinline__ half PowFunc(half x, half y) {
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return __float2half(pow(__half2float(x), __half2float(y)));
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}
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template <typename T>
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__device__ __forceinline__ bool CompareFunc(T x, T y) {
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return abs(x) > y;
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}
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template <>
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__device__ __forceinline__ bool CompareFunc(half x, half y) {
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return abs(__half2float(x)) > __half2float(y);
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}
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template <typename T>
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__device__ __forceinline__ T Sgn(T x) {
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return static_cast<T>(x != 0 ? (x > 0 ? 1 : -1) : 0);
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}
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template <>
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__device__ __forceinline__ half Sgn(half x) {
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return __float2half(__half2float(x) != 0 ? (__half2float(x) > 0 ? 1 : -1) : 0);
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}
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template <typename T, typename S>
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__global__ void SparseApplyFtrlKernel(const T *gradient, const S *indices, const int num_index, const size_t n_stride,
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const float learning_rate, const float l1_regularization,
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const float l2_regularization, const float learning_rate_power,
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T *variable, T *accumulation, T *linear) {
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const T two = static_cast<T>(2.0);
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const T learning_rate_val = static_cast<T>(learning_rate);
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const T l1_regularization_val = static_cast<T>(l1_regularization);
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const T l2_regularization_val = static_cast<T>(l2_regularization);
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const T learning_rate_power_val = static_cast<T>(-learning_rate_power);
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for (size_t pos = blockIdx.x * blockDim.x + threadIdx.x;
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pos < (num_index*n_stride);
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pos += gridDim.x * blockDim.x) {
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const int posn = pos / n_stride;
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const int posi = pos % n_stride;
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const int indexed_n = indices[posn];
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const int i = indexed_n*n_stride + posi;
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const T cur_accumulation = accumulation[i] + gradient[pos] * gradient[pos];
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const T accumulation_power = PowFunc(accumulation[i], learning_rate_power_val);
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const T cur_accumulation_power = PowFunc(cur_accumulation, learning_rate_power_val);
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const T sigma = (cur_accumulation_power - accumulation_power) / learning_rate_val;
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linear[i] += gradient[pos] - sigma * variable[i];
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variable[i] = CompareFunc(linear[i], l1_regularization_val)
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? ((l1_regularization_val * Sgn(linear[i]) - linear[i]) /
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(cur_accumulation_power / learning_rate_val + two * l2_regularization_val))
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: static_cast<T>(0);
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accumulation[i] = cur_accumulation;
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}
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return;
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}
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template <typename T, typename S>
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void CalSparseApplyFtrl(const T *gradient, const S *indices, const int num_index, const size_t n_stride,
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const float learning_rate, const float l1_regularization, const float l2_regularization,
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const float learning_rate_power, const bool use_locking, T *variable, T *accumulation,
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T *linear, cudaStream_t cuda_stream) {
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SparseApplyFtrlKernel<<<GET_BLOCKS(num_index*n_stride), GET_THREADS, 0, cuda_stream>>>(gradient, indices, num_index,
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n_stride, learning_rate, l1_regularization, l2_regularization, learning_rate_power, variable, accumulation, linear);
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return;
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}
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template void CalSparseApplyFtrl<float, int>(const float *gradient, const int *indices, const int num_index,
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const size_t n_stride, const float learning_rate,
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const float l1_regularization, const float l2_regularization,
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const float learning_rate_power, const bool use_locking, float *variable,
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float *accumulation, float *linear, cudaStream_t cuda_stream);
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template void CalSparseApplyFtrl<half, int>(const half *gradient, const int *indices, const int num_index,
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const size_t n_stride, const float learning_rate,
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const float l1_regularization, const float l2_regularization,
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const float learning_rate_power, const bool use_locking, half *variable,
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half *accumulation, half *linear, cudaStream_t cuda_stream);
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_SPARSE_FTRL_IMPL_H_
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#define MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_SPARSE_FTRL_IMPL_H_
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template <typename T, typename S>
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void CalSparseApplyFtrl(const T *gradient, const S *indices, const int num_index, const size_t n_stride,
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const float learning_rate, const float l1_regularization, const float l2_regularization,
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const float learning_rate_power, const bool use_locking, T *variable, T *accumulation,
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T *linear, cudaStream_t cuda_stream);
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#endif // MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_SPARSE_FTRL_IMPL_H_
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "backend/kernel_compiler/gpu/nn/sparse_ftrl_gpu_kernel.h"
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namespace mindspore {
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namespace kernel {
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MS_REG_GPU_KERNEL_TWO(SparseApplyFtrl,
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KernelAttr()
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeInt32)
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.AddOutputAttr(kNumberTypeFloat32)
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.AddOutputAttr(kNumberTypeFloat32)
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.AddOutputAttr(kNumberTypeFloat32),
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SparseFtrlGpuKernel, float, int)
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MS_REG_GPU_KERNEL_TWO(SparseApplyFtrl,
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KernelAttr()
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeInt32)
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.AddOutputAttr(kNumberTypeFloat16)
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.AddOutputAttr(kNumberTypeFloat16)
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.AddOutputAttr(kNumberTypeFloat16),
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SparseFtrlGpuKernel, half, int)
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} // namespace kernel
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} // namespace mindspore
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_SPARSE_FTRL_GPU_KERNEL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_SPARSE_FTRL_GPU_KERNEL_H_
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#include <vector>
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#include "backend/kernel_compiler/gpu/gpu_kernel.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
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#include "backend/kernel_compiler/gpu/cuda_impl/sparse_ftrl_impl.cuh"
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namespace mindspore {
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namespace kernel {
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template <typename T, typename S>
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class SparseFtrlGpuKernel : public GpuKernel {
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public:
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SparseFtrlGpuKernel()
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: variable_size_(0),
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accumulation_size_(0),
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linear_size_(0),
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gradient_size_(0),
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indices_size_(0),
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lr_(0.0f),
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l1_(0.0f),
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l2_(0.0f),
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lr_power_(0.0f),
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use_locking_(false),
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num_index_(0),
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n_stride_(1) {}
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~SparseFtrlGpuKernel() override = default;
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const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
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const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
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const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
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bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &, const std::vector<AddressPtr> &,
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void *stream_ptr) override {
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T *variable = GetDeviceAddress<T>(inputs, 0);
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T *accumulation = GetDeviceAddress<T>(inputs, 1);
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T *linear = GetDeviceAddress<T>(inputs, 2);
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T *gradient = GetDeviceAddress<T>(inputs, 3);
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S *indices = GetDeviceAddress<S>(inputs, 4);
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CalSparseApplyFtrl(gradient, indices, num_index_, n_stride_, lr_, l1_, l2_, lr_power_, use_locking_, variable,
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accumulation, linear, reinterpret_cast<cudaStream_t>(stream_ptr));
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return true;
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}
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bool Init(const CNodePtr &kernel_node) override {
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size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
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if (input_num != 5) {
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MS_LOG(ERROR) << "Input number is " << input_num << ", but sparse ftrl needs 5 inputs.";
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return false;
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}
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variable_size_ = sizeof(T);
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accumulation_size_ = sizeof(T);
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linear_size_ = sizeof(T);
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gradient_size_ = sizeof(T);
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indices_size_ = sizeof(S);
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auto variable_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
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for (size_t i = 0; i < variable_shape.size(); i++) {
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variable_size_ *= variable_shape[i];
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if (i > 0) {
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n_stride_ *= variable_shape[i];
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}
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}
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auto accumulation_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 1);
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for (size_t i = 0; i < accumulation_shape.size(); i++) {
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accumulation_size_ *= accumulation_shape[i];
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}
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auto linear_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 2);
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for (size_t i = 0; i < linear_shape.size(); i++) {
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linear_size_ *= linear_shape[i];
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}
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auto gradient_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 3);
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for (size_t i = 0; i < gradient_shape.size(); i++) {
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gradient_size_ *= gradient_shape[i];
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}
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auto indices_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 4);
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for (size_t i = 0; i < indices_shape.size(); i++) {
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indices_size_ *= indices_shape[i];
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}
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lr_ = GetAttr<float>(kernel_node, "lr");
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l1_ = GetAttr<float>(kernel_node, "l1");
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l2_ = GetAttr<float>(kernel_node, "l2");
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lr_power_ = GetAttr<float>(kernel_node, "lr_power");
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use_locking_ = GetAttr<bool>(kernel_node, "use_locking");
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num_index_ = indices_shape[0];
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InitSizeLists();
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return true;
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}
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protected:
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void InitSizeLists() override {
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input_size_list_.push_back(variable_size_);
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input_size_list_.push_back(accumulation_size_);
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input_size_list_.push_back(linear_size_);
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input_size_list_.push_back(gradient_size_);
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input_size_list_.push_back(indices_size_);
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output_size_list_.push_back(0);
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output_size_list_.push_back(0);
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output_size_list_.push_back(0);
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}
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private:
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size_t variable_size_;
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size_t accumulation_size_;
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size_t linear_size_;
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size_t gradient_size_;
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size_t indices_size_;
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float lr_;
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float l1_;
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float l2_;
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float lr_power_;
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bool use_locking_;
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int num_index_;
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size_t n_stride_;
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std::vector<size_t> input_size_list_;
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std::vector<size_t> output_size_list_;
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std::vector<size_t> workspace_size_list_;
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};
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} // namespace kernel
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} // namespace mindspore
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#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_SPARSE_FTRL_GPU_KERNEL_H_
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@ -0,0 +1,149 @@
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# Copyright 2020 Huawei Technologies Co., Ltd
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ============================================================================
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import numpy as np
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import pytest
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import mindspore.context as context
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import mindspore.nn as nn
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from mindspore import Tensor
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from mindspore.common.parameter import Parameter
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from mindspore.ops import operations as P
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import mindspore.common.dtype as mstype
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class Net(nn.Cell):
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def __init__(self):
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super(Net, self).__init__()
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self.sparse_apply_ftrl = P.SparseApplyFtrl(lr=0.001, l1=0.0, l2=0.0, lr_power=-0.5, use_locking=False)
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self.var = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float32)), name="var")
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self.accum = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float32)), name="accum")
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self.linear = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float32)), name="linear")
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def construct(self, grad, indices):
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out = self.sparse_apply_ftrl(self.var, self.accum, self.linear, grad, indices)
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return out
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class Net_half(nn.Cell):
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def __init__(self):
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super(Net_half, self).__init__()
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self.sparse_apply_ftrl = P.SparseApplyFtrl(lr=0.001, l1=0.0, l2=0.0, lr_power=-0.5, use_locking=False)
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self.var = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float16)), name="var")
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self.accum = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float16)), name="accum")
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self.linear = Parameter(Tensor(np.ones([3, 3, 3]).astype(np.float16)), name="linear")
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def construct(self, grad, indices):
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out = self.sparse_apply_ftrl(self.var, self.accum, self.linear, grad, indices)
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return out
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@pytest.mark.level0
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@pytest.mark.platform_x86_gpu_training
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@pytest.mark.env_onecard
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def test_ftrl():
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gradient = Tensor(np.ones([3, 3, 3]).astype(np.float32))
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indices = Tensor([0, 1, 2], mstype.int32)
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expect_var = np.array([[[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479]],
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[[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479]],
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[[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479],
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[0.291479, 0.291479, 0.291479]]]).astype(np.float32)
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context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
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sparse_apply_ftrl = Net()
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sparse_apply_ftrl(gradient, indices)
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assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
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context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
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sparse_apply_ftrl = Net()
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sparse_apply_ftrl(gradient, indices)
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assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
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@pytest.mark.level0
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@pytest.mark.platform_x86_gpu_training
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@pytest.mark.env_onecard
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def test_ftrl_sparse():
|
||||
gradient = Tensor(np.ones([2, 3, 3]).astype(np.float32))
|
||||
indices = Tensor([0, 2], mstype.int32)
|
||||
expect_var = np.array([[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]],
|
||||
[[1, 1, 1],
|
||||
[1, 1, 1],
|
||||
[1, 1, 1]],
|
||||
[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]]]).astype(np.float32)
|
||||
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
|
||||
|
||||
@pytest.mark.level0
|
||||
@pytest.mark.platform_x86_gpu_training
|
||||
@pytest.mark.env_onecard
|
||||
def test_ftrl_half():
|
||||
gradient = Tensor(np.ones([3, 3, 3]).astype(np.float16))
|
||||
indices = Tensor([0, 1, 2], mstype.int32)
|
||||
expect_var = np.array([[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]],
|
||||
[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]],
|
||||
[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]]]).astype(np.float16)
|
||||
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net_half()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net_half()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
|
||||
|
||||
@pytest.mark.level0
|
||||
@pytest.mark.platform_x86_gpu_training
|
||||
@pytest.mark.env_onecard
|
||||
def test_ftrl_sparse_half():
|
||||
gradient = Tensor(np.ones([2, 3, 3]).astype(np.float16))
|
||||
indices = Tensor([0, 2], mstype.int32)
|
||||
expect_var = np.array([[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]],
|
||||
[[1, 1, 1],
|
||||
[1, 1, 1],
|
||||
[1, 1, 1]],
|
||||
[[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479],
|
||||
[0.291479, 0.291479, 0.291479]]]).astype(np.float16)
|
||||
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net_half()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||
sparse_apply_ftrl = Net_half()
|
||||
sparse_apply_ftrl(gradient, indices)
|
||||
assert np.all(sparse_apply_ftrl.var.data.asnumpy() == expect_var)
|
||||
Loading…
Reference in New Issue