- Updated files to the new syntax.
git-svn-id: http://lampsvn.epfl.ch/svn-repos/scala/scala/trunk@2558 5e8d7ff9-d8ef-0310-90f0-a4852d11357a
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@ -26,7 +26,8 @@ class MailBox {
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private var lastReceiver = receivers;
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def send(msg: Any): unit = synchronized {
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var r = receivers, r1 = r.next;
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var r = receivers;
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var r1 = r.next;
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while (r1 != null && !r1.elem.isDefined(msg)) {
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r = r1; r1 = r1.next;
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}
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@ -39,7 +40,8 @@ class MailBox {
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def receive[a](f: PartialFunction[Any, a]): a = {
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val msg: Any = synchronized {
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var s = sent, s1 = s.next;
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var s = sent;
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var s1 = s.next;
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while (s1 != null && !f.isDefinedAt(s1.elem)) {
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s = s1; s1 = s1.next
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}
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@ -59,7 +61,8 @@ class MailBox {
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def receiveWithin[a](msec: long)(f: PartialFunction[Any, a]): a = {
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val msg: Any = synchronized {
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var s = sent, s1 = s.next;
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var s = sent;
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var s1 = s.next;
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while (s1 != null && !f.isDefinedAt(s1.elem)) {
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s = s1; s1 = s1.next ;
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}
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@ -3,14 +3,18 @@ import scala._;
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package scalac.util {
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trait A {
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type X1, X2;
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val x1: X1, x2: X2;
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type X1;
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type X2;
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val x1: X1;
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val x2: X2;
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}
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trait B extends A {
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type Y;
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val y1: Y, y2: Y;
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type X1 = Y, X2 = Y;
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val x1 = y1, x2 = y2;
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val y1, y2: Y;
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type X1 = Y;
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type X2 = Y;
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val x1 = y1;
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val x2 = y2;
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def f(x: Y, xs: B): Unit = {}
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def g() = f(y1, this);
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}
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@ -18,16 +22,19 @@ trait B extends A {
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object test {
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val b: B { type Y = Int } = new B {
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type Y = Int;
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val y1 = 1, y2 = 1;
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val y1, y2 = 1;
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}
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val a: A { type X1 = Int, X2 = Int } = b;
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val a: A { type X1 = Int; type X2 = Int } = b;
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val a1 = new A {
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type X1 = Int, X2 = String;
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val x1 = 1, x2 = "hello"
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type X1 = Int;
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type X2 = String;
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val x1 = 1;
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val x2 = "hello"
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}
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val b1 = new B {
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type Y = Any;
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val y1 = 1, y2 = "hello";
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val y1 = 1;
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val y2 = "hello";
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}
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}
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}
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@ -59,7 +59,8 @@ object M1 {
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def sort1(l: Int, r: Int): Unit = {
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val pivot = xs((l + r) / 2);
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var i = l, j = r;
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var i = l;
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var j = r;
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While (i <= j) {
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While (less(xs(i), pivot)) { i = i + 1 }
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While (less(pivot, xs(j))) { j = j - 1 }
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@ -506,7 +506,7 @@ abstract class BasicCircuitSimulator() extends Simulator() {
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}
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def orGate2(a1: Wire, a2: Wire, output: Wire) = {
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val w1 = new Wire(), w2 = new Wire(), w3 = new Wire();
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val w1, w2, w3 = new Wire();
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inverter(a1, w1);
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inverter(a2, w2);
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andGate(w1, w2, w3);
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@ -517,7 +517,7 @@ abstract class BasicCircuitSimulator() extends Simulator() {
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abstract class CircuitSimulator() extends BasicCircuitSimulator() {
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def demux2(in: Wire, ctrl: List[Wire], out: List[Wire]) : Unit = {
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val ctrlN = ctrl.map(w => { val iw = new Wire(); inverter(w,iw); iw});
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val w0 = new Wire(), w1 = new Wire(), w2 = new Wire(), w3 = new Wire();
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val w0, w1, w2, w3 = new Wire();
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andGate(in, ctrl(1), w3);
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andGate(in, ctrl(1), w2);
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@ -537,7 +537,7 @@ abstract class CircuitSimulator() extends BasicCircuitSimulator() {
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def demux(in: Wire, ctrl: List[Wire], out: List[Wire]): Unit = ctrl match {
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case List() => connect(in, out.head);
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case c :: rest =>
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val c_ = new Wire(), w1 = new Wire(), w2 = new Wire();
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val c_, w1, w2 = new Wire();
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inverter(c, c_);
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andGate(in, c_, w1);
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andGate(in, c, w2);
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