diff --git a/test/files/neg/bug122.check b/test/files/neg/bug122.check index 9c4927188..0ab336bd4 100644 --- a/test/files/neg/bug122.check +++ b/test/files/neg/bug122.check @@ -1,7 +1,7 @@ bug122.scala:2: recursive value v$ needs type val List(v:int,2) = List(2,v:int); - ^ + ^ bug122.scala:3: recursive value ds$0$ needs type val Pair(a:int,b:int) = Pair(1,a); - ^ + ^ two errors found diff --git a/test/files/pos/MailBox.scala b/test/files/pos/MailBox.scala index 3d5ce9fa6..69fe3e1cb 100644 --- a/test/files/pos/MailBox.scala +++ b/test/files/pos/MailBox.scala @@ -26,7 +26,8 @@ class MailBox { private var lastReceiver = receivers; def send(msg: Any): unit = synchronized { - var r = receivers, r1 = r.next; + var r = receivers; + var r1 = r.next; while (r1 != null && !r1.elem.isDefined(msg)) { r = r1; r1 = r1.next; } @@ -39,7 +40,8 @@ class MailBox { def receive[a](f: PartialFunction[Any, a]): a = { val msg: Any = synchronized { - var s = sent, s1 = s.next; + var s = sent; + var s1 = s.next; while (s1 != null && !f.isDefinedAt(s1.elem)) { s = s1; s1 = s1.next } @@ -59,7 +61,8 @@ class MailBox { def receiveWithin[a](msec: long)(f: PartialFunction[Any, a]): a = { val msg: Any = synchronized { - var s = sent, s1 = s.next; + var s = sent; + var s1 = s.next; while (s1 != null && !f.isDefinedAt(s1.elem)) { s = s1; s1 = s1.next ; } diff --git a/test/files/pos/clsrefine.scala b/test/files/pos/clsrefine.scala index 35ccafc66..d54a0c340 100644 --- a/test/files/pos/clsrefine.scala +++ b/test/files/pos/clsrefine.scala @@ -3,14 +3,18 @@ import scala._; package scalac.util { trait A { - type X1, X2; - val x1: X1, x2: X2; + type X1; + type X2; + val x1: X1; + val x2: X2; } trait B extends A { type Y; - val y1: Y, y2: Y; - type X1 = Y, X2 = Y; - val x1 = y1, x2 = y2; + val y1, y2: Y; + type X1 = Y; + type X2 = Y; + val x1 = y1; + val x2 = y2; def f(x: Y, xs: B): Unit = {} def g() = f(y1, this); } @@ -18,16 +22,19 @@ trait B extends A { object test { val b: B { type Y = Int } = new B { type Y = Int; - val y1 = 1, y2 = 1; + val y1, y2 = 1; } - val a: A { type X1 = Int, X2 = Int } = b; + val a: A { type X1 = Int; type X2 = Int } = b; val a1 = new A { - type X1 = Int, X2 = String; - val x1 = 1, x2 = "hello" + type X1 = Int; + type X2 = String; + val x1 = 1; + val x2 = "hello" } val b1 = new B { type Y = Any; - val y1 = 1, y2 = "hello"; + val y1 = 1; + val y2 = "hello"; } } } \ No newline at end of file diff --git a/test/files/run/Course-2002-04.scala b/test/files/run/Course-2002-04.scala index 733a290db..e74711d45 100644 --- a/test/files/run/Course-2002-04.scala +++ b/test/files/run/Course-2002-04.scala @@ -59,7 +59,8 @@ object M1 { def sort1(l: Int, r: Int): Unit = { val pivot = xs((l + r) / 2); - var i = l, j = r; + var i = l; + var j = r; While (i <= j) { While (less(xs(i), pivot)) { i = i + 1 } While (less(pivot, xs(j))) { j = j - 1 } diff --git a/test/files/run/Course-2002-08.scala b/test/files/run/Course-2002-08.scala index f15568938..d50d98ffc 100644 --- a/test/files/run/Course-2002-08.scala +++ b/test/files/run/Course-2002-08.scala @@ -506,7 +506,7 @@ abstract class BasicCircuitSimulator() extends Simulator() { } def orGate2(a1: Wire, a2: Wire, output: Wire) = { - val w1 = new Wire(), w2 = new Wire(), w3 = new Wire(); + val w1, w2, w3 = new Wire(); inverter(a1, w1); inverter(a2, w2); andGate(w1, w2, w3); @@ -517,7 +517,7 @@ abstract class BasicCircuitSimulator() extends Simulator() { abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux2(in: Wire, ctrl: List[Wire], out: List[Wire]) : Unit = { val ctrlN = ctrl.map(w => { val iw = new Wire(); inverter(w,iw); iw}); - val w0 = new Wire(), w1 = new Wire(), w2 = new Wire(), w3 = new Wire(); + val w0, w1, w2, w3 = new Wire(); andGate(in, ctrl(1), w3); andGate(in, ctrl(1), w2); @@ -537,7 +537,7 @@ abstract class CircuitSimulator() extends BasicCircuitSimulator() { def demux(in: Wire, ctrl: List[Wire], out: List[Wire]): Unit = ctrl match { case List() => connect(in, out.head); case c :: rest => - val c_ = new Wire(), w1 = new Wire(), w2 = new Wire(); + val c_, w1, w2 = new Wire(); inverter(c, c_); andGate(in, c_, w1); andGate(in, c, w2);