From bee9f4c7c4b1ccf56170cc3d2755b815baa104da Mon Sep 17 00:00:00 2001 From: ACM32_MCU <90822414+ACM32-MCU@users.noreply.github.com> Date: Sat, 26 Mar 2022 15:40:33 +0800 Subject: [PATCH] Add some drivers (#5208) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * 1. 新增了i2c/spi/rtc/crypto等驱动；2. 删除了部分文件中的未使用到的头文件包含; 3. 修改keil编译时pm文件atoi的头文件stdlib未包含的警告 * 修改文件格式 * BSP 1. 修改f4系列bsp的readme文件与工程文件 2. 修改f0系列源文件的版权信息、删除目前没有的库文件。 3. 其他 * 还原.gitignore文件 Co-authored-by: aisino2200 <90822414+aisino2200@users.noreply.github.com> --- bsp/acm32f0x0-nucleo/.config | 84 +- bsp/acm32f0x0-nucleo/Kconfig | 2 + bsp/acm32f0x0-nucleo/applications/main.c | 12 +- bsp/acm32f0x0-nucleo/drivers/board.c | 5 +- bsp/acm32f0x0-nucleo/drivers/board.h | 135 ++- bsp/acm32f0x0-nucleo/drivers/drv_adc.c | 17 +- bsp/acm32f0x0-nucleo/drivers/drv_gpio.c | 53 +- bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c | 6 +- bsp/acm32f0x0-nucleo/drivers/drv_i2c.c | 203 +++++ bsp/acm32f0x0-nucleo/drivers/drv_pm.c | 170 ++++ bsp/acm32f0x0-nucleo/drivers/drv_rtc.c | 123 +++ bsp/acm32f0x0-nucleo/drivers/drv_soft_i2c.c | 159 ++++ bsp/acm32f0x0-nucleo/drivers/drv_spi.c | 640 +++++++++++++ bsp/acm32f0x0-nucleo/drivers/drv_uart.c | 2 +- bsp/acm32f0x0-nucleo/drivers/drv_wdt.c | 2 +- bsp/acm32f0x0-nucleo/drivers/i2c_config.h | 123 +++ bsp/acm32f0x0-nucleo/drivers/spi_config.h | 138 +++ bsp/acm32f0x0-nucleo/drivers/tim_config.h | 2 +- bsp/acm32f0x0-nucleo/drivers/uart_config.h | 2 +- bsp/acm32f0x0-nucleo/libraries/SConscript | 9 +- bsp/acm32f0x0-nucleo/project.ewp | 162 +++- bsp/acm32f0x0-nucleo/project.uvoptx | 964 ++++++++++++++++++++ bsp/acm32f0x0-nucleo/project.uvprojx | 461 +++++----- bsp/acm32f0x0-nucleo/rtconfig.h | 27 +- bsp/acm32f4xx-nucleo/README.md | 2 +- bsp/acm32f4xx-nucleo/project.uvoptx | 652 +++++++++++++ bsp/acm32f4xx-nucleo/project.uvprojx | 198 ++-- 27 files changed, 3866 insertions(+), 487 deletions(-) create mode 100644 bsp/acm32f0x0-nucleo/drivers/drv_i2c.c create mode 100644 bsp/acm32f0x0-nucleo/drivers/drv_pm.c create mode 100644 bsp/acm32f0x0-nucleo/drivers/drv_rtc.c create mode 100644 bsp/acm32f0x0-nucleo/drivers/drv_soft_i2c.c create mode 100644 bsp/acm32f0x0-nucleo/drivers/drv_spi.c create mode 100644 bsp/acm32f0x0-nucleo/drivers/i2c_config.h create mode 100644 bsp/acm32f0x0-nucleo/drivers/spi_config.h diff --git a/bsp/acm32f0x0-nucleo/.config b/bsp/acm32f0x0-nucleo/.config index 5a20703666..2ae98d25c3 100644 --- a/bsp/acm32f0x0-nucleo/.config +++ b/bsp/acm32f0x0-nucleo/.config @@ -95,17 +95,8 @@ CONFIG_RT_USING_USER_MAIN=y CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 CONFIG_RT_MAIN_THREAD_PRIORITY=10 # CONFIG_RT_USING_LEGACY is not set - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_THREAD_PRIORITY=20 @@ -119,11 +110,9 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# # CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set # # Device Drivers @@ -167,7 +156,7 @@ CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_USB_DEVICE is not set # -# POSIX layer and C standard library +# C/C++ and POSIX layer # CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 @@ -191,36 +180,16 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Socket is in the 'Network' category # +# CONFIG_RT_USING_CPLUSPLUS is not set # # Network # - -# -# Socket abstraction layer -# # CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# # CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# # CONFIG_RT_USING_LWIP is not set - -# -# AT commands -# # CONFIG_RT_USING_AT is not set -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - # # Utilities # @@ -229,7 +198,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_LWP is not set +# CONFIG_RT_USING_VBUS is not set # # RT-Thread Utestcases @@ -243,6 +212,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # IoT - internet of things # +# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -253,12 +223,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set # @@ -298,6 +264,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_EZ_IOT_OS is not set # CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set @@ -311,16 +278,13 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set # CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_RAPIDJSON is not set # CONFIG_PKG_USING_BSAL is not set # CONFIG_PKG_USING_AGILE_MODBUS is not set # CONFIG_PKG_USING_AGILE_FTP is not set @@ -345,6 +309,22 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # language packages # + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set @@ -432,6 +412,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SOLAR_TERMS is not set # CONFIG_PKG_USING_GAN_ZHI is not set # CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set # # system packages @@ -474,12 +456,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_RT_USING_ARDUINO is not set +# CONFIG_PKG_USING_RTDUINO is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set # CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set # CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set @@ -505,7 +486,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_ARM_2D is not set # CONFIG_PKG_USING_MCUBOOT is not set # CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_USB_STACK is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set # # peripheral libraries and drivers @@ -529,6 +511,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set @@ -585,6 +568,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set # # AI packages @@ -603,6 +587,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # miscellaneous packages # +# +# project laboratory +# + # # samples: kernel and components samples # @@ -635,6 +623,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set @@ -652,6 +641,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DESIGN_PATTERN is not set # CONFIG_PKG_USING_CONTROLLER is not set # CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set CONFIG_SOC_SERIES_ACM32F0=y # diff --git a/bsp/acm32f0x0-nucleo/Kconfig b/bsp/acm32f0x0-nucleo/Kconfig index 851a0c7409..cf56d6850b 100644 --- a/bsp/acm32f0x0-nucleo/Kconfig +++ b/bsp/acm32f0x0-nucleo/Kconfig @@ -21,6 +21,8 @@ source "$PKGS_DIR/Kconfig" config SOC_SERIES_ACM32F0 bool select ARCH_ARM_CORTEX_M0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN default y source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/acm32f0x0-nucleo/applications/main.c b/bsp/acm32f0x0-nucleo/applications/main.c index 2e827e89f2..18d7a17b4d 100644 --- a/bsp/acm32f0x0-nucleo/applications/main.c +++ b/bsp/acm32f0x0-nucleo/applications/main.c @@ -1,15 +1,13 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2021-08-23 AisinoChip the first version + * 2021-10-17 AisinoChip remove unused header file */ - -#include -#include #include "board.h" #include @@ -19,12 +17,12 @@ int main(void) { rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); - while(1) + while (1) { rt_pin_write(LED_PIN_NUM, PIN_LOW); - rt_thread_delay(RT_TICK_PER_SECOND/2); + rt_thread_delay(RT_TICK_PER_SECOND / 2); rt_pin_write(LED_PIN_NUM, PIN_HIGH); - rt_thread_delay(RT_TICK_PER_SECOND/2); + rt_thread_delay(RT_TICK_PER_SECOND / 2); } } diff --git a/bsp/acm32f0x0-nucleo/drivers/board.c b/bsp/acm32f0x0-nucleo/drivers/board.c index 841560184e..67eb1ec815 100644 --- a/bsp/acm32f0x0-nucleo/drivers/board.c +++ b/bsp/acm32f0x0-nucleo/drivers/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,9 +8,6 @@ * 2021-08-25 AisinoChip first implementation */ -#include -#include -#include "rtconfig.h" #include "board.h" #include diff --git a/bsp/acm32f0x0-nucleo/drivers/board.h b/bsp/acm32f0x0-nucleo/drivers/board.h index 39032064cb..d07dbfe512 100644 --- a/bsp/acm32f0x0-nucleo/drivers/board.h +++ b/bsp/acm32f0x0-nucleo/drivers/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #ifndef __BOARD_H__ #define __BOARD_H__ -#include +#include #include "ACM32Fxx_HAL.h" /*-------------------------- UART CONFIG BEGIN --------------------------*/ @@ -106,9 +106,138 @@ #endif /* BSP_USING_UART3 */ /*-------------------------- UART CONFIG END --------------------------*/ -/* board configuration */ +/*-------------------------- SPI CONFIG BEGIN --------------------------*/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT GPIOA + #define SPI1_CS_PIN GPIO_PIN_2 + #define SPI1_CS_ALTERNATE GPIO_FUNCTION_3 + #define SPI1_SCK_PORT GPIOA + #define SPI1_SCK_PIN GPIO_PIN_1 + #define SPI1_SCK_ALTERNATE GPIO_FUNCTION_1 + #define SPI1_MISO_PORT GPIOB + #define SPI1_MISO_PIN GPIO_PIN_0 + #define SPI1_MISO_ALTERNATE GPIO_FUNCTION_5 + #define SPI1_MOSI_PORT GPIOB + #define SPI1_MOSI_PIN GPIO_PIN_1 + #define SPI1_MOSI_ALTERNATE GPIO_FUNCTION_5 + #define SPI1_WP_PORT GPIOA + #define SPI1_WP_PIN GPIO_PIN_7 + #define SPI1_WP_ALTERNATE GPIO_FUNCTION_4 + #define SPI1_HOLD_PORT GPIOA + #define SPI1_HOLD_PIN GPIO_PIN_6 + #define SPI1_HOLD_ALTERNATE GPIO_FUNCTION_4 + + #if defined(BSP_SPI1_RX_USING_DMA) + #define SPI1_RX_DMA_INSTANCE DMA_Channel0 + #define SPI1_RX_DMA_RCC BIT12 + #define SPI1_RX_DMA_IRQ DMA_IRQn + #define SPI1_RX_DMA_CHANNEL 0 + #define SPI1_RX_DMA_REQUEST REQ2_SPI1_RECV + #endif /* BSP_SPI1_RX_USING_DMA */ + + #if defined(BSP_SPI1_TX_USING_DMA) + #define SPI1_TX_DMA_INSTANCE DMA_Channel1 + #define SPI1_TX_DMA_RCC BIT12 + #define SPI1_TX_DMA_IRQ DMA_IRQn + #define SPI1_TX_DMA_CHANNEL 1 + #define SPI1_TX_DMA_REQUEST REQ1_SPI1_SEND + #endif /* BSP_SPI1_TX_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#if defined(BSP_USING_SPI2) + #define SPI2_CS_PORT GPIOB + #define SPI2_CS_PIN GPIO_PIN_12 + #define SPI2_CS_ALTERNATE GPIO_FUNCTION_4 + #define SPI2_SCK_PORT GPIOB + #define SPI2_SCK_PIN GPIO_PIN_13 + #define SPI2_SCK_ALTERNATE GPIO_FUNCTION_4 + #define SPI2_MISO_PORT GPIOB + #define SPI2_MISO_PIN GPIO_PIN_14 + #define SPI2_MISO_ALTERNATE GPIO_FUNCTION_4 + #define SPI2_MOSI_PORT GPIOB + #define SPI2_MOSI_PIN GPIO_PIN_15 + #define SPI2_MOSI_ALTERNATE GPIO_FUNCTION_4 + #define SPI2_WP_PORT GPIOC + #define SPI2_WP_PIN GPIO_PIN_7 + #define SPI2_WP_ALTERNATE GPIO_FUNCTION_2 + #define SPI2_HOLD_PORT GPIOC + #define SPI2_HOLD_PIN GPIO_PIN_6 + #define SPI2_HOLD_ALTERNATE GPIO_FUNCTION_2 + + #if defined(BSP_SPI2_RX_USING_DMA) + #define SPI2_RX_DMA_INSTANCE DMA_Channel2 + #define SPI2_RX_DMA_RCC BIT12 + #define SPI2_RX_DMA_IRQ DMA_IRQn + #define SPI2_RX_DMA_CHANNEL 2 + #define SPI2_RX_DMA_REQUEST REQ4_SPI2_RECV + #endif /* BSP_SPI2_RX_USING_DMA */ + + #if defined(BSP_SPI2_TX_USING_DMA) + #define SPI2_TX_DMA_INSTANCE DMA_Channel3 + #define SPI2_TX_DMA_RCC BIT12 + #define SPI2_TX_DMA_IRQ DMA_IRQn + #define SPI2_TX_DMA_CHANNEL 3 + #define SPI2_TX_DMA_REQUEST REQ3_SPI2_SEND + #endif /* BSP_SPI2_TX_USING_DMA */ +#endif /* BSP_USING_SPI2 */ +/*-------------------------- SPI CONFIG END --------------------------*/ + +/*-------------------------- I2C CONFIG BEGIN --------------------------*/ +#if defined(BSP_USING_I2C1) + #define I2C1_SCL_PORT GPIOB + #define I2C1_SCL_PIN GPIO_PIN_6 + #define I2C1_SCL_ALTERNATE GPIO_FUNCTION_6 + #define I2C1_SDA_PORT GPIOB + #define I2C1_SDA_PIN GPIO_PIN_7 + #define I2C1_SDA_ALTERNATE GPIO_FUNCTION_6 + + #if defined(BSP_I2C1_RX_USING_DMA) + #define I2C1_RX_DMA_INSTANCE DMA_Channel0 + #define I2C1_RX_DMA_RCC BIT12 + #define I2C1_RX_DMA_IRQ DMA_IRQn + #define I2C1_RX_DMA_CHANNEL 0 + #define I2C1_RX_DMA_REQUEST REQ10_I2C1_RECV + #endif /* BSP_I2C1_RX_USING_DMA */ + + #if defined(BSP_I2C1_TX_USING_DMA) + #define I2C1_TX_DMA_INSTANCE DMA_Channel1 + #define I2C1_TX_DMA_RCC BIT12 + #define I2C1_TX_DMA_IRQ DMA_IRQn + #define I2C1_TX_DMA_CHANNEL 1 + #define I2C1_TX_DMA_REQUEST REQ9_I2C1_SEND + #endif /* BSP_I2C1_TX_USING_DMA */ +#endif /* BSP_USING_I2C1 */ + +#if defined(BSP_USING_I2C2) + #define I2C2_SCL_PORT GPIOB + #define I2C2_SCL_PIN GPIO_PIN_10 + #define I2C2_SCL_ALTERNATE GPIO_FUNCTION_6 + #define I2C2_SDA_PORT GPIOB + #define I2C2_SDA_PIN GPIO_PIN_11 + #define I2C2_SDA_ALTERNATE GPIO_FUNCTION_6 + + #if defined(BSP_I2C2_RX_USING_DMA) + #define I2C2_RX_DMA_INSTANCE DMA_Channel0 + #define I2C2_RX_DMA_RCC BIT12 + #define I2C2_RX_DMA_IRQ DMA_IRQn + #define I2C2_RX_DMA_CHANNEL 0 + #define I2C2_RX_DMA_REQUEST REQ10_I2C1_RECV + #endif /* BSP_I2C2_RX_USING_DMA */ + + #if defined(BSP_I2C2_TX_USING_DMA) + #define I2C2_TX_DMA_INSTANCE DMA_Channel1 + #define I2C2_TX_DMA_RCC BIT12 + #define I2C2_TX_DMA_IRQ DMA_IRQn + #define I2C2_TX_DMA_CHANNEL 1 + #define I2C2_TX_DMA_REQUEST REQ9_I2C1_SEND + #endif /* BSP_I2C2_TX_USING_DMA */ +#endif /* BSP_USING_I2C2 */ +/*-------------------------- I2C CONFIG END --------------------------*/ void rt_hw_board_init(void); +#if defined(RT_USING_SPI) + rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, enum_GPIOx_t cs_gpiox, uint16_t cs_gpio_pin); +#endif #endif /* __BOARD_H__ */ diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_adc.c b/bsp/acm32f0x0-nucleo/drivers/drv_adc.c index 7f7675beaa..c8245a5c3f 100644 --- a/bsp/acm32f0x0-nucleo/drivers/drv_adc.c +++ b/bsp/acm32f0x0-nucleo/drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,11 +9,11 @@ */ #include -#include #include #define ADC_NAME "adc" +#if defined(RT_USING_ADC) #if defined(BSP_USING_ADC) struct acm32_adc @@ -24,7 +24,7 @@ struct acm32_adc static struct acm32_adc acm32_adc_obj = {0}; -static rt_err_t acm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) { struct acm32_adc *adcObj = RT_NULL; @@ -70,7 +70,7 @@ static rt_err_t acm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan return RT_EOK; } -static rt_err_t acm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t _get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { struct acm32_adc *adcObj = RT_NULL; ADC_ChannelConfTypeDef channelConf = {0}; @@ -107,18 +107,19 @@ static rt_err_t acm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch static const struct rt_adc_ops acm_adc_ops = { - .enabled = acm32_adc_enabled, - .convert = acm32_get_adc_value, + .enabled = _adc_enabled, + .convert = _get_adc_value, }; -static int acm32_adc_init(void) +static int rt_hw_adc_init(void) { return rt_hw_adc_register(&acm32_adc_obj.acm32_adc_device, ADC_NAME, &acm_adc_ops, RT_NULL); } -INIT_BOARD_EXPORT(acm32_adc_init); +INIT_BOARD_EXPORT(rt_hw_adc_init); #endif /* BSP_USING_ADC */ +#endif /* RT_USING_ADC */ diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c b/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c index b26b837d79..de7bdda26a 100644 --- a/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c +++ b/bsp/acm32f0x0-nucleo/drivers/drv_gpio.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2021-08-26 AisinoChip first version + * 2021-10-15 AisinoChip add special pin setting */ #include @@ -254,7 +255,53 @@ static void acm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) } /* special PIN process */ - __HAL_RTC_PC13_DIGIT(); + if(index->gpio == GPIOC && index->pin == GPIO_PIN_13) + { + __HAL_RTC_PC13_DIGIT(); + __HAL_RTC_PC13_SEL(0); /* GPIO function */ + __HAL_RTC_PC13_PULL_DOWN_DISABLE(); + __HAL_RTC_PC13_PULL_UP_DISABLE(); + if(GPIO_InitStruct.Pull == GPIO_PULLUP) + { + __HAL_RTC_PC13_PULL_UP_ENABLE(); + } + else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN) + { + __HAL_RTC_PC13_PULL_DOWN_ENABLE(); + } + } + + if(index->gpio == GPIOC && index->pin == GPIO_PIN_14) + { + __HAL_RTC_PC14_DIGIT(); + __HAL_RTC_PC14_SEL(0); /* GPIO function */ + __HAL_RTC_PC14_PULL_DOWN_DISABLE(); + __HAL_RTC_PC14_PULL_UP_DISABLE(); + if(GPIO_InitStruct.Pull == GPIO_PULLUP) + { + __HAL_RTC_PC14_PULL_UP_ENABLE(); + } + else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN) + { + __HAL_RTC_PC14_PULL_DOWN_ENABLE(); + } + } + + if(index->gpio == GPIOC && index->pin == GPIO_PIN_15) + { + __HAL_RTC_PC15_DIGIT(); + __HAL_RTC_PC15_SEL(0); /* GPIO function */ + __HAL_RTC_PC15_PULL_DOWN_DISABLE(); + __HAL_RTC_PC15_PULL_UP_DISABLE(); + if(GPIO_InitStruct.Pull == GPIO_PULLUP) + { + __HAL_RTC_PC15_PULL_UP_ENABLE(); + } + else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN) + { + __HAL_RTC_PC15_PULL_DOWN_ENABLE(); + } + } HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); } @@ -358,6 +405,8 @@ static rt_err_t acm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_ENOSYS; } + System_Module_Enable(EN_EXTI); + /* Configure GPIO_InitStructure */ GPIO_InitStruct.Pin = index->pin; GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c b/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c index 1d168c10de..9b34ef869b 100644 --- a/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c +++ b/bsp/acm32f0x0-nucleo/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,10 +12,9 @@ #include #include -#ifdef BSP_USING_TIM +#ifdef RT_USING_HWTIMER #include "tim_config.h" -#ifdef RT_USING_HWTIMER enum { #ifdef BSP_USING_TIM1 @@ -361,5 +360,4 @@ static int acm32_hwtimer_init(void) INIT_BOARD_EXPORT(acm32_hwtimer_init); #endif /* RT_USING_HWTIMER */ -#endif /* BSP_USING_TIM */ diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_i2c.c b/bsp/acm32f0x0-nucleo/drivers/drv_i2c.c new file mode 100644 index 0000000000..dedf02710b --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_i2c.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-03 AisinoChip first implementation. + */ + +#include "board.h" + +#if defined(RT_USING_I2C) +#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) +#include +#include "i2c_config.h" + +enum +{ +#ifdef BSP_USING_I2C1 + I2C1_INDEX, +#endif +#ifdef BSP_USING_I2C2 + I2C2_INDEX, +#endif + I2C_MAX_INDEX +}; + +struct acm32_i2c_config +{ + I2C_TypeDef *Instance; + char *name; + IRQn_Type irq_type; + enum_Enable_ID_t enable_id; + + uint32_t clock_speed; + + enum_GPIOx_t scl_port; + rt_uint32_t scl_pin; + rt_uint32_t scl_alternate; + + enum_GPIOx_t sda_port; + rt_uint32_t sda_pin; + rt_uint32_t sda_alternate; +}; + +struct acm32_i2c +{ + I2C_HandleTypeDef handle; + struct acm32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; +}; + +static struct acm32_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_CONFIG, +#endif + +#ifdef BSP_USING_I2C2 + I2C2_CONFIG, +#endif +}; + +static struct acm32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + +static int acm32_i2c_read(struct acm32_i2c *hi2c, rt_uint16_t slave_address, rt_uint8_t *p_buffer, rt_uint16_t data_byte) +{ + if (HAL_I2C_Master_Receive(&hi2c->handle, slave_address, p_buffer, data_byte, 1000) != HAL_OK) + { + return -1; + } + + return 0; +} + +static int acm32_i2c_write(struct acm32_i2c *hi2c, uint16_t slave_address, uint8_t *p_buffer, uint16_t data_byte) +{ + if (HAL_I2C_Master_Transmit(&hi2c->handle, slave_address, p_buffer, data_byte, 1000) != HAL_OK) + { + return -1; + } + + return 0; +} + +static rt_size_t _i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + struct acm32_i2c *i2c_obj; + + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(msgs != RT_NULL); + + i2c_obj = rt_container_of(bus, struct acm32_i2c, i2c_bus); + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_RD) + { + if (acm32_i2c_read(i2c_obj, msg->addr, msg->buf, msg->len) != 0) + { + goto out; + } + } + else + { + if (acm32_i2c_write(i2c_obj, msg->addr, msg->buf, msg->len) != 0) + { + goto out; + } + } + } + +out: + + return i; +} + +static const struct rt_i2c_bus_device_ops i2c_ops = +{ + _i2c_xfer, + RT_NULL, + RT_NULL +}; + +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(i2c_config) / sizeof(i2c_config[0]); i++) + { + i2c_objs[i].config = &i2c_config[i]; + i2c_objs[i].i2c_bus.parent.user_data = &i2c_config[i]; + i2c_objs[i].handle.Instance = i2c_config[i].Instance; + + i2c_objs[i].i2c_bus.ops = &i2c_ops; + + /* hardware initial */ + i2c_objs[i].handle.Init.Clock_Speed = i2c_config[i].clock_speed ; + i2c_objs[i].handle.Init.Tx_Auto_En = TX_AUTO_EN_ENABLE; + i2c_objs[i].handle.Init.I2C_Mode = I2C_MODE_MASTER; + + HAL_I2C_Init(&i2c_objs[i].handle); + + result = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_config[i].name); + RT_ASSERT(result == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +/************************************************************************ + * function : HAL_I2C_MspInit + * Description: + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + GPIO_InitTypeDef GPIO_Handle; + struct acm32_i2c *i2c_obj; + struct acm32_i2c_config *i2c_config; + + RT_ASSERT(hi2c != RT_NULL); + + i2c_obj = rt_container_of(hi2c, struct acm32_i2c, handle); + + RT_ASSERT(i2c_obj->i2c_bus.parent.user_data != RT_NULL); + + i2c_config = (struct acm32_i2c_config *)i2c_obj->i2c_bus.parent.user_data; + + /* Enable Clock */ + System_Module_Enable(i2c_config->enable_id); + + /* I2C SDA */ + GPIO_Handle.Pin = i2c_config->sda_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = i2c_config->sda_alternate; + HAL_GPIO_Init(i2c_config->sda_port, &GPIO_Handle); + + /* I2C SCL */ + GPIO_Handle.Pin = i2c_config->scl_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = i2c_config->scl_alternate; + HAL_GPIO_Init(i2c_config->scl_port, &GPIO_Handle); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(i2c_config->irq_type); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(i2c_config->irq_type); +} + +#endif /* defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) */ +#endif /* RT_USING_I2C */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_pm.c b/bsp/acm32f0x0-nucleo/drivers/drv_pm.c new file mode 100644 index 0000000000..c39190df0b --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_pm.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-13 AisinoChip first add to bsp + */ + +#include "board.h" +#include + +#if defined(RT_USING_PM) + +#define IWDT_SRC_CLK 32000 +#define IWDT_CLK_PRESCALER IWDT_CLOCK_PRESCALER_32 +#define IWDT_CLK (IWDT_SRC_CLK / (4<parent.user_data); + + if(timeout != RT_TICK_MAX) + { + tick = get_pm_tick_from_os_tick(timeout); + phiwdt->Instance = IWDT; + phiwdt->Init.Prescaler = IWDT_CLK_PRESCALER; + phiwdt->Init.Reload = tick; + phiwdt->Init.Window = tick; /* window function disabled when window >= reload */ + phiwdt->Init.Wakeup = tick - 1; /* wakeup function disabled when wakeup >= reload */ + HAL_IWDT_Init(phiwdt); + } +} + +static void _pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); + + IWDT_HandleTypeDef *phiwdt = (IWDT_HandleTypeDef *)(pm->parent.user_data); + + phiwdt->Instance->CMDR = 0xFFFF; +} + +static rt_tick_t _pm_timer_get_tick(struct rt_pm *pm) +{ + rt_tick_t tick; + RT_ASSERT(pm != RT_NULL); + + return get_os_tick_from_pm_tick(tick); +} + +static const struct rt_pm_ops _pm_ops = +{ + _pm_sleep, + _pm_run, + _pm_timer_start, + _pm_timer_stop, + _pm_timer_get_tick +}; + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + + rt_uint8_t timer_mask = 0; + + /* initialize timer mask */ + timer_mask = (1UL << PM_SLEEP_MODE_DEEP) | (1UL << PM_SLEEP_MODE_STANDBY); + + /* initialize system pm module */ + rt_system_pm_init(&_pm_ops, timer_mask, &hiwdt); + + return 0; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +#endif /* RT_USING_PM */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_rtc.c b/bsp/acm32f0x0-nucleo/drivers/drv_rtc.c new file mode 100644 index 0000000000..84ffc72fe5 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_rtc.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-31 AisinoChip first add to bsp + */ + +#include "board.h" +#include +#include + +#ifdef BSP_USING_RTC + +static RTC_ConfigTypeDef RTC_Handle; + +rt_inline rt_uint8_t dec2hex(rt_uint8_t dec) +{ + return ((dec / 10) << 4) + (dec % 10); +} + +rt_inline rt_uint8_t hex2dec(rt_uint8_t hex) +{ + return ((hex / 16) * 10) + (hex % 16); +} + +static time_t get_rtc_timestamp(void) +{ + RTC_TimeTypeDef RTC_TimeStruct = {0}; + RTC_DateTypeDef RTC_DateStruct = {0}; + struct tm tm_new = {0}; + + HAL_RTC_GetTime(&RTC_TimeStruct); + HAL_RTC_GetDate(&RTC_DateStruct); + + tm_new.tm_sec = hex2dec(RTC_TimeStruct.u8_Seconds); + tm_new.tm_min = hex2dec(RTC_TimeStruct.u8_Minutes); + tm_new.tm_hour = hex2dec(RTC_TimeStruct.u8_Hours); + tm_new.tm_mday = hex2dec(RTC_DateStruct.u8_Date); + tm_new.tm_mon = hex2dec(RTC_DateStruct.u8_Month) - 1; + tm_new.tm_year = hex2dec(RTC_DateStruct.u8_Year) + 100; + + return timegm(&tm_new); +} + +static rt_err_t set_rtc_time_stamp(time_t time_stamp) +{ + RTC_TimeTypeDef RTC_TimeStruct = {0}; + RTC_DateTypeDef RTC_DateStruct = {0}; + struct tm *p_tm; + + p_tm = gmtime(&time_stamp); + if (p_tm->tm_year < 100) + { + return -RT_ERROR; + } + + RTC_TimeStruct.u8_Seconds = dec2hex(p_tm->tm_sec); + RTC_TimeStruct.u8_Minutes = dec2hex(p_tm->tm_min); + RTC_TimeStruct.u8_Hours = dec2hex(p_tm->tm_hour); + RTC_DateStruct.u8_Date = dec2hex(p_tm->tm_mday); + RTC_DateStruct.u8_Month = dec2hex(p_tm->tm_mon + 1); + RTC_DateStruct.u8_Year = dec2hex(p_tm->tm_year - 100); + RTC_DateStruct.u8_WeekDay = dec2hex(p_tm->tm_wday) + 1; + + HAL_RTC_SetTime(&RTC_TimeStruct); + HAL_RTC_SetDate(&RTC_DateStruct); + + return RT_EOK; +} + +static rt_err_t _rtc_init(void) +{ + RTC_Handle.u32_ClockSource = RTC_CLOCK_XTL; + RTC_Handle.u32_Compensation = COMPENSATION_INCREASE; + RTC_Handle.u32_CompensationValue = 0x05; + + HAL_RTC_Config(&RTC_Handle); + + return RT_EOK; +} + +static rt_err_t _rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = get_rtc_timestamp(); + return RT_EOK; +} + +static rt_err_t _rtc_set_secs(void *args) +{ + rt_err_t result = RT_EOK; + if (set_rtc_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + + return result; +} + +static const struct rt_rtc_ops acm32_rtc_ops = +{ + _rtc_init, + _rtc_get_secs, + _rtc_set_secs, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, +}; + +static rt_rtc_dev_t acm32_rtc_dev; + +static int rt_hw_rtc_init(void) +{ + acm32_rtc_dev.ops = &acm32_rtc_ops; + + return rt_hw_rtc_register(&acm32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL); +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); +#endif /* BSP_USING_RTC */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_soft_i2c.c b/bsp/acm32f0x0-nucleo/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..764a6891bc --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_soft_i2c.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-13 AisinoChip first implementation. + */ + +#include + +#ifdef RT_USING_I2C_BITOPS + +#include +#include + +#define I2C_BUS_NAME "i2cs" + +/* user should change this to adapt specific board */ +#define I2C_SCL_PIN GPIO_PIN_6 +#define I2C_SCL_PORT GPIOD +#define I2C_SDA_PIN GPIO_PIN_7 +#define I2C_SDA_PORT GPIOD + +struct acm32_i2c_bit_data +{ + struct + { + enum_GPIOx_t port; + rt_uint32_t pin; + } scl, sda; +}; + +static void _set_sda(void *data, rt_int32_t state) +{ + struct acm32_i2c_bit_data* bd = data; + + if (state) + { + HAL_GPIO_WritePin(bd->sda.port, bd->sda.pin, GPIO_PIN_SET); + } + else + { + HAL_GPIO_WritePin(bd->sda.port, bd->sda.pin, GPIO_PIN_CLEAR); + } +} + +static void _set_scl(void *data, rt_int32_t state) +{ + struct acm32_i2c_bit_data* bd = data; + if (state) + { + HAL_GPIO_WritePin(bd->scl.port, bd->scl.pin, GPIO_PIN_SET); + } + else + { + HAL_GPIO_WritePin(bd->scl.port, bd->scl.pin, GPIO_PIN_CLEAR); + } +} + +static rt_int32_t _get_sda(void *data) +{ + struct acm32_i2c_bit_data* bd = data; + + return HAL_GPIO_ReadPin(bd->sda.port, bd->sda.pin); +} + +static rt_int32_t _get_scl(void *data) +{ + struct acm32_i2c_bit_data* bd = data; + + return HAL_GPIO_ReadPin(bd->scl.port, bd->scl.pin); +} + +static void acm32_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static void drv_i2c_gpio_init(const struct acm32_i2c_bit_data* bd) +{ + GPIO_InitTypeDef GPIO_Handle; + + GPIO_Handle.Pin = bd->sda.pin; + GPIO_Handle.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_0; + HAL_GPIO_Init(bd->sda.port, &GPIO_Handle); + + GPIO_Handle.Pin = bd->scl.pin; + GPIO_Handle.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_0; + HAL_GPIO_Init(bd->scl.port, &GPIO_Handle); + + _set_sda((void*)bd, 1); + _set_scl((void*)bd, 1); +} + +int rt_soft_i2c_init(void) +{ + static struct rt_i2c_bus_device i2c_device; + static const struct acm32_i2c_bit_data _i2c_bdata = + { + /* SCL */ + { I2C_SCL_PORT, I2C_SCL_PIN}, + /* SDA */ + { I2C_SDA_PORT, I2C_SDA_PIN}, + }; + + static const struct rt_i2c_bit_ops _i2c_bit_ops = + { + (void*)&_i2c_bdata, + _set_sda, + _set_scl, + _get_sda, + _get_scl, + acm32_udelay, + 1, + 100 + }; + + drv_i2c_gpio_init(&_i2c_bdata); + + i2c_device.priv = (void *)&_i2c_bit_ops; + rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); + + return 0; +} +INIT_DEVICE_EXPORT(rt_soft_i2c_init); + +#endif /* RT_USING_I2C_BITOPS */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_spi.c b/bsp/acm32f0x0-nucleo/drivers/drv_spi.c new file mode 100644 index 0000000000..dea1ed9775 --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/drv_spi.c @@ -0,0 +1,640 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-31 AisinoChip first version + */ + +#include "board.h" +#include + +#ifdef RT_USING_SPI + +#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) + +#include "spi_config.h" + +enum +{ +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +#ifdef BSP_USING_SPI2 + SPI2_INDEX, +#endif + SPI_MAX_INDEX +}; + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) +struct dma_config +{ + DMA_Channel_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + rt_uint32_t channel; + rt_uint32_t request; +}; +#endif + +struct acm32_hw_spi_cs +{ + enum_GPIOx_t GPIOx; + uint16_t GPIO_Pin; +}; + +struct acm32_spi_config +{ + SPI_TypeDef *Instance; + char *bus_name; + IRQn_Type irq_type; + enum_Enable_ID_t enable_id; +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + struct dma_config *dma_rx; +#endif +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) + struct dma_config *dma_tx; +#endif + + enum_GPIOx_t cs_port; + rt_uint32_t cs_pin; + rt_uint32_t cs_alternate; + + enum_GPIOx_t sck_port; + rt_uint32_t sck_pin; + rt_uint32_t sck_alternate; + + enum_GPIOx_t mosi_port; + rt_uint32_t mosi_pin; + rt_uint32_t mosi_alternate; + + enum_GPIOx_t miso_port; + rt_uint32_t miso_pin; + rt_uint32_t miso_alternate; + + enum_GPIOx_t wp_port; + rt_uint32_t wp_pin; + rt_uint32_t wp_alternate; + + enum_GPIOx_t hold_port; + rt_uint32_t hold_pin; + rt_uint32_t hold_alternate; +}; + +struct acm32_spi_device +{ + rt_uint32_t pin; + char *bus_name; + char *device_name; +}; + +#define SPI_USING_RX_DMA_FLAG (1<<0) +#define SPI_USING_TX_DMA_FLAG (1<<1) + +struct acm32_spi +{ + SPI_HandleTypeDef handle; + struct acm32_spi_config *config; + struct rt_spi_configuration *cfg; + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + struct + { +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + DMA_HandleTypeDef handle_rx; +#endif +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) + DMA_HandleTypeDef handle_tx; +#endif + } dma; + + rt_uint8_t spi_dma_flag; +#endif + + struct rt_spi_bus spi_bus; +}; + +static struct acm32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif +}; + +static struct acm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +static rt_err_t acm32_spi_init(struct acm32_spi *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + SPI_HandleTypeDef *spi_handle = &spi_drv->handle; + + if (cfg->mode & RT_SPI_SLAVE) + { + spi_handle->Init.SPI_Mode = SPI_MODE_SLAVE; + } + else + { + spi_handle->Init.SPI_Mode = SPI_MODE_MASTER; + } + + spi_handle->Init.X_Mode = SPI_1X_MODE; + if (cfg->mode & RT_SPI_3WIRE) + { + return -RT_EINVAL; + } + + if (cfg->data_width != 8) + { + return -RT_EINVAL; + } + + switch (cfg->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_0; + break; + case RT_SPI_MODE_1: + spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_1; + break; + case RT_SPI_MODE_2: + spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_2; + break; + case RT_SPI_MODE_3: + spi_handle->Init.SPI_Work_Mode = SPI_WORK_MODE_3; + break; + } + + if (cfg->mode & RT_SPI_MSB) + { + spi_handle->Init.First_Bit = SPI_FIRSTBIT_MSB; + } + else + { + spi_handle->Init.First_Bit = SPI_FIRSTBIT_LSB; + } + + uint32_t SPI_APB_CLOCK; + SPI_APB_CLOCK = System_Get_SystemClock(); + + if (cfg->max_hz >= SPI_APB_CLOCK / 4) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_4; + } + else if (cfg->max_hz >= SPI_APB_CLOCK / 8) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_8; + } + else if (cfg->max_hz >= SPI_APB_CLOCK / 16) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_16; + } + else if (cfg->max_hz >= SPI_APB_CLOCK / 32) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_32; + } + else if (cfg->max_hz >= SPI_APB_CLOCK / 64) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_64; + } + else if (cfg->max_hz >= SPI_APB_CLOCK / 128) + { + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_128; + } + else + { + /* min prescaler 254 */ + spi_handle->Init.BaudRate_Prescaler = SPI_BAUDRATE_PRESCALER_254; + } + + if (HAL_SPI_Init(spi_handle) != HAL_OK) + { + return -RT_EIO; + } + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + /* DMA configuration */ + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + HAL_DMA_Init(&spi_drv->dma.handle_rx); + + __HAL_LINK_DMA(spi_drv->handle, HDMA_Rx, spi_drv->dma.handle_rx); + } +#endif + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + HAL_DMA_Init(&spi_drv->dma.handle_tx); + + __HAL_LINK_DMA(spi_drv->handle, HDMA_Tx, spi_drv->dma.handle_tx); + } +#endif +#endif + + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + HAL_StatusTypeDef state; + rt_uint8_t *recv_buf; + const rt_uint8_t *send_buf; + rt_uint32_t timeout = 1000; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct acm32_spi *spi_drv = rt_container_of(device->bus, struct acm32_spi, spi_bus); + SPI_HandleTypeDef *spi_handle = &spi_drv->handle; + struct acm32_hw_spi_cs *cs = device->parent.user_data; + + if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS)) + { + HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_CLEAR); + } + + recv_buf = message->recv_buf; + send_buf = message->send_buf; + + /* start once data exchange in DMA mode */ + if (message->send_buf && message->recv_buf) + { +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)) + { + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, message->length); + while (HAL_SPI_GetTxState(spi_handle) != SPI_TX_STATE_IDLE); + } + else + { + state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, message->length, timeout); + } + + if (state == HAL_OK) + { + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, message->length); + while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE); + } + else + { + state = HAL_SPI_Receive_IT(spi_handle, (uint8_t *)recv_buf, message->length); + while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE); + } + } + } + else +#endif + { + state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, message->length, timeout); + } + + if (state != HAL_OK) + { + message->length = 0; + } + } + else if (message->send_buf) + { +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) + if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, message->length); + while (HAL_SPI_GetTxState(spi_handle) != SPI_TX_STATE_IDLE); + } + else +#endif + { + state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, message->length, 0); + } + if (state != HAL_OK) + { + message->length = 0; + } + } + else + { + memset((uint8_t *)recv_buf, 0xff, message->length); +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, message->length); + while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE); + } + else +#endif + { + rt_kprintf("expect %d bytes\n", message->length); + state = HAL_SPI_Receive_IT(spi_handle, (uint8_t *)recv_buf, message->length); + while (HAL_SPI_GetRxState(spi_handle) != SPI_RX_STATE_IDLE); + rt_kprintf("recv %d bytes\n", spi_handle->Rx_Count); + } + if (state != HAL_OK) + { + message->length = 0; + } + } + + if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS)) + { + HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET); + } + + return message->length; +} + +static rt_err_t _configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct acm32_spi *spi_drv = rt_container_of(device->bus, struct acm32_spi, spi_bus); + spi_drv->cfg = configuration; + + return acm32_spi_init(spi_drv, configuration); +} + +static const struct rt_spi_ops acm_spi_ops = +{ + .configure = _configure, + .xfer = spixfer, +}; + +static int rt_hw_spi_bus_init(void) +{ + rt_err_t result = RT_EOK; + + for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; + spi_bus_obj[i].handle.Instance = spi_config[i].Instance; + +#if defined(BSP_SPI1_RX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA) + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG) + { + /* Configure the DMA handler for Transmission process */ + spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance; + spi_bus_obj[i].dma.handle_rx.Init.Data_Flow = DMA_DATA_FLOW_P2M; + spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_rx.Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE; + spi_bus_obj[i].dma.handle_rx.Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE; + spi_bus_obj[i].dma.handle_rx.Init.Request_ID = spi_config[i].dma_rx->request; + spi_bus_obj[i].dma.handle_rx.Init.Source_Width = DMA_SRC_WIDTH_BYTE; + spi_bus_obj[i].dma.handle_rx.Init.Desination_Width = DMA_DST_WIDTH_BYTE; + spi_bus_obj[i].dma.handle_rx.DMA_ITC_Callback = NULL; + spi_bus_obj[i].dma.handle_rx.DMA_IE_Callback = NULL; + } +#endif + +#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI2_TX_USING_DMA) + if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG) + { + spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance; + spi_bus_obj[i].dma.handle_tx.Init.Data_Flow = DMA_DATA_FLOW_M2P; + spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL; + spi_bus_obj[i].dma.handle_tx.Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE; + spi_bus_obj[i].dma.handle_tx.Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE; + spi_bus_obj[i].dma.handle_tx.Init.Request_ID = spi_config[i].dma_tx->request; + spi_bus_obj[i].dma.handle_tx.Init.Source_Width = DMA_SRC_WIDTH_BYTE; + spi_bus_obj[i].dma.handle_tx.Init.Desination_Width = DMA_DST_WIDTH_BYTE; + spi_bus_obj[i].dma.handle_tx.DMA_ITC_Callback = NULL; + spi_bus_obj[i].dma.handle_tx.DMA_IE_Callback = NULL; + } +#endif + + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &acm_spi_ops); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +#if defined(BSP_USING_SPI1) +void SPI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(BSP_USING_SPI2) +void SPI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static void acm32_get_dma_info(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif +} + +int rt_hw_spi_init(void) +{ + acm32_get_dma_info(); + return rt_hw_spi_bus_init(); +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +static uint32_t get_gpio_alternate(enum_GPIOx_t gpio_port, uint16_t gpio_pin) +{ + /* SPI1_CS : PA2->AF3 PA4->AF1 PA15->AF1 PB0->AF1 PB11->AF5 */ + /* SPI2_CS : PA8->AF4 PB9->AF4 PB12->AF4 */ + if (gpio_port == GPIOA || gpio_port == GPIOB) + { + if (gpio_port == GPIOA) + { + switch (gpio_pin) + { + case GPIO_PIN_2: + return GPIO_FUNCTION_3; + case GPIO_PIN_4: + return GPIO_FUNCTION_1; + case GPIO_PIN_8: + return GPIO_FUNCTION_4; + case GPIO_PIN_15: + return GPIO_FUNCTION_1; + default: + return RT_UINT32_MAX; + } + } + else + { + switch (gpio_pin) + { + case GPIO_PIN_0: + return GPIO_FUNCTION_1; + case GPIO_PIN_9: + return GPIO_FUNCTION_4; + case GPIO_PIN_11: + return GPIO_FUNCTION_5; + case GPIO_PIN_12: + return GPIO_FUNCTION_4; + default: + return RT_UINT32_MAX; + } + } + } + + return RT_UINT32_MAX; +} + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, enum_GPIOx_t cs_gpiox, uint16_t cs_gpio_pin) +{ + rt_uint32_t alternate; + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct acm32_hw_spi_cs *cs_pin; + + alternate = get_gpio_alternate(cs_gpiox, cs_gpio_pin); + if (alternate == RT_UINT32_MAX) + { + return -RT_EINVAL; + } + + /* initialize the cs pin && select the slave*/ + GPIO_InitTypeDef GPIO_Initure; + GPIO_Initure.Pin = cs_gpio_pin; + GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_Initure.Pull = GPIO_PULLUP; + GPIO_Initure.Alternate = alternate; + HAL_GPIO_Init(cs_gpiox, &GPIO_Initure); + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct acm32_hw_spi_cs *)rt_malloc(sizeof(struct acm32_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->GPIOx = cs_gpiox; + cs_pin->GPIO_Pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + RT_ASSERT(result == RT_EOK); + + return result; +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + GPIO_InitTypeDef GPIO_Handle; + struct acm32_spi *spi_drv; + struct acm32_spi_config *spi_config; + + RT_ASSERT(hspi != RT_NULL); + + spi_drv = rt_container_of(hspi, struct acm32_spi, handle); + + RT_ASSERT(spi_drv->spi_bus.parent.user_data != RT_NULL); + + spi_config = (struct acm32_spi_config *)spi_drv->spi_bus.parent.user_data; + + /* Enable Clock */ + System_Module_Enable(spi_config->enable_id); + + /* SPI CS */ + GPIO_Handle.Pin = spi_config->cs_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->cs_alternate ; + HAL_GPIO_Init(spi_config->cs_port, &GPIO_Handle); + + /* SPI SCK */ + GPIO_Handle.Pin = spi_config->sck_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->sck_alternate ; + HAL_GPIO_Init(spi_config->sck_port, &GPIO_Handle); + + /* SPI MOSI */ + GPIO_Handle.Pin = spi_config->mosi_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->mosi_alternate ; + HAL_GPIO_Init(spi_config->mosi_port, &GPIO_Handle); + + /* SPI MISO */ + GPIO_Handle.Pin = spi_config->miso_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->miso_alternate ; + HAL_GPIO_Init(spi_config->miso_port, &GPIO_Handle); + + if (hspi->Init.X_Mode == SPI_4X_MODE) + { + /* SPI WP */ + GPIO_Handle.Pin = spi_config->wp_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->wp_alternate ; + HAL_GPIO_Init(spi_config->wp_port, &GPIO_Handle); + + /* SPI HOLD */ + GPIO_Handle.Pin = spi_config->hold_pin; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = spi_config->hold_alternate ; + HAL_GPIO_Init(spi_config->hold_port, &GPIO_Handle); + } + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(spi_config->irq_type); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(spi_config->irq_type); +} +#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 */ +#endif /* RT_USING_SPI */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_uart.c b/bsp/acm32f0x0-nucleo/drivers/drv_uart.c index f84d0c9874..64951270ff 100644 --- a/bsp/acm32f0x0-nucleo/drivers/drv_uart.c +++ b/bsp/acm32f0x0-nucleo/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c b/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c index 6ea8767692..6cb02c014b 100644 --- a/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c +++ b/bsp/acm32f0x0-nucleo/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/acm32f0x0-nucleo/drivers/i2c_config.h b/bsp/acm32f0x0-nucleo/drivers/i2c_config.h new file mode 100644 index 0000000000..285fec3a3a --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/i2c_config.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-03 AisinoChip the first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "board.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_I2C) + +#if defined(BSP_USING_I2C1) + +#if defined(BSP_I2C1_RX_USING_DMA) +#ifndef I2C1_DMA_RX_CONFIG +#define I2C1_DMA_RX_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .request = I2C1_RX_DMA_REQUEST, \ + } +#endif /* I2C1_DMA_RX_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#if defined(BSP_I2C1_TX_USING_DMA) +#ifndef I2C1_DMA_TX_CONFIG +#define I2C1_DMA_TX_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .request = I2C1_TX_DMA_REQUEST, \ + } +#endif /* I2C1_DMA_TX_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = I2C1, \ + .clock_speed = CLOCK_SPEED_STANDARD, \ + .irq_type = I2C1_IRQn, \ + .enable_id = EN_I2C1, \ + .scl_port = I2C1_SCL_PORT, \ + .scl_pin = I2C1_SCL_PIN, \ + .scl_alternate = I2C1_SCL_ALTERNATE, \ + .sda_port = I2C1_SDA_PORT, \ + .sda_pin = I2C1_SDA_PIN, \ + .sda_alternate = I2C1_SDA_ALTERNATE, \ + } +#endif /* I2C1_CONFIG */ +#endif /* BSP_USING_I2C1 */ + +#if defined(BSP_USING_I2C2) + +#if defined(BSP_I2C2_RX_USING_DMA) +#ifndef I2C2_DMA_RX_CONFIG +#define I2C2_DMA_RX_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .request = I2C2_RX_DMA_REQUEST, \ + } +#endif /* I2C2_DMA_RX_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#if defined(BSP_I2C2_TX_USING_DMA) +#ifndef I2C2_DMA_TX_CONFIG +#define I2C2_DMA_TX_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .request = I2C2_TX_DMA_REQUEST, \ + } +#endif /* I2C2_DMA_TX_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = I2C2, \ + .clock_speed = CLOCK_SPEED_STANDARD, \ + .irq_type = I2C2_IRQn, \ + .enable_id = EN_I2C2, \ + .scl_port = I2C2_SCL_PORT, \ + .scl_pin = I2C2_SCL_PIN, \ + .scl_alternate = I2C2_SCL_ALTERNATE, \ + .sda_port = I2C2_SDA_PORT, \ + .sda_pin = I2C2_SDA_PIN, \ + .sda_alternate = I2C2_SDA_ALTERNATE, \ + } +#endif /* I2C2_CONFIG */ +#endif /* BSP_USING_I2C2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_I2C */ + +#endif /* __I2C_CONFIG_H__ */ + diff --git a/bsp/acm32f0x0-nucleo/drivers/spi_config.h b/bsp/acm32f0x0-nucleo/drivers/spi_config.h new file mode 100644 index 0000000000..386b7a966b --- /dev/null +++ b/bsp/acm32f0x0-nucleo/drivers/spi_config.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-31 AisinoChip first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = SPI1, \ + .bus_name = "spi1", \ + .irq_type = SPI1_IRQn, \ + .enable_id=EN_SPI1, \ + .cs_port = SPI1_CS_PORT, \ + .cs_pin = SPI1_CS_PIN, \ + .cs_alternate = SPI1_CS_ALTERNATE, \ + .sck_port = SPI1_SCK_PORT, \ + .sck_pin = SPI1_SCK_PIN, \ + .sck_alternate = SPI1_SCK_ALTERNATE, \ + .mosi_port = SPI1_MOSI_PORT, \ + .mosi_pin = SPI1_MOSI_PIN, \ + .mosi_alternate = SPI1_MOSI_ALTERNATE, \ + .miso_port = SPI1_MISO_PORT, \ + .miso_pin = SPI1_MISO_PIN, \ + .miso_alternate = SPI1_MISO_ALTERNATE, \ + .wp_port = SPI1_WP_PORT, \ + .wp_pin = SPI1_WP_PIN, \ + .wp_alternate = SPI1_WP_ALTERNATE, \ + .hold_port = SPI1_HOLD_PORT, \ + .hold_pin = SPI1_HOLD_PIN, \ + .hold_alternate = SPI1_HOLD_ALTERNATE, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_TX_DMA_RCC, \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .dma_irq = SPI1_TX_DMA_IRQ, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .request = SPI1_TX_DMA_REQUEST, \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI1_RX_DMA_RCC, \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .dma_irq = SPI1_RX_DMA_IRQ, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .request = SPI1_RX_DMA_REQUEST, \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = SPI2, \ + .bus_name = "spi2", \ + .irq_type = SPI2_IRQn, \ + .enable_id=EN_SPI2, \ + .cs_port = SPI2_CS_PORT, \ + .cs_pin = SPI2_CS_PIN, \ + .cs_alternate = SPI2_CS_ALTERNATE, \ + .sck_port = SPI2_SCK_PORT, \ + .sck_pin = SPI2_SCK_PIN, \ + .sck_alternate = SPI2_SCK_ALTERNATE, \ + .mosi_port = SPI2_MOSI_PORT, \ + .mosi_pin = SPI2_MOSI_PIN, \ + .mosi_alternate = SPI2_MOSI_ALTERNATE, \ + .miso_port = SPI2_MISO_PORT, \ + .miso_pin = SPI2_MISO_PIN, \ + .miso_alternate = SPI2_MISO_ALTERNATE, \ + .wp_port = SPI2_WP_PORT, \ + .wp_pin = SPI2_WP_PIN, \ + .wp_alternate = SPI2_WP_ALTERNATE, \ + .hold_port = SPI2_HOLD_PORT, \ + .hold_pin = SPI2_HOLD_PIN, \ + .hold_alternate = SPI2_HOLD_ALTERNATE, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_TX_DMA_RCC, \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .dma_irq = SPI2_TX_DMA_IRQ, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .request = SPI2_TX_DMA_REQUEST, \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .dma_rcc = SPI2_RX_DMA_RCC, \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .dma_irq = SPI2_RX_DMA_IRQ, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .request = SPI2_RX_DMA_REQUEST, \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ + + diff --git a/bsp/acm32f0x0-nucleo/drivers/tim_config.h b/bsp/acm32f0x0-nucleo/drivers/tim_config.h index 5ae9cf3c6b..c22487df59 100644 --- a/bsp/acm32f0x0-nucleo/drivers/tim_config.h +++ b/bsp/acm32f0x0-nucleo/drivers/tim_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/acm32f0x0-nucleo/drivers/uart_config.h b/bsp/acm32f0x0-nucleo/drivers/uart_config.h index 90e5a10d67..0a7a8a5202 100644 --- a/bsp/acm32f0x0-nucleo/drivers/uart_config.h +++ b/bsp/acm32f0x0-nucleo/drivers/uart_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/acm32f0x0-nucleo/libraries/SConscript b/bsp/acm32f0x0-nucleo/libraries/SConscript index 8f7a97ad30..c410bca43f 100644 --- a/bsp/acm32f0x0-nucleo/libraries/SConscript +++ b/bsp/acm32f0x0-nucleo/libraries/SConscript @@ -15,9 +15,16 @@ HAL_Driver/Src/HAL_IWDT.c HAL_Driver/Src/HAL_UART.c HAL_Driver/Src/HAL_TIMER.c HAL_Driver/Src/HAL_EXTI.c +HAL_Driver/Src/HAL_RTC.c +HAL_Driver/Src/HAL_SPI.c +HAL_Driver/Src/HAL_I2C.c +HAL_Driver/Src/HAL_CRC.c """) +libpath = ['.', cwd + '/Device', cwd + '/HAL_Driver/Src'] +libs = [] + if rtconfig.CROSS_TOOL == 'gcc': src = src + ['Device/Startup_ACM32F0x0_gcc.s'] elif rtconfig.CROSS_TOOL == 'keil': @@ -29,6 +36,6 @@ path = [cwd + '/HAL_Driver/Inc', cwd + '/Device', cwd + '/CMSIS'] -group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path) +group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath) Return('group') diff --git a/bsp/acm32f0x0-nucleo/project.ewp b/bsp/acm32f0x0-nucleo/project.ewp index 437ad9e558..2a1be66c76 100644 --- a/bsp/acm32f0x0-nucleo/project.ewp +++ b/bsp/acm32f0x0-nucleo/project.ewp @@ -357,7 +357,6 @@ $PROJ_DIR$\..\..\components\libc\compilers\common $PROJ_DIR$\..\..\components\libc\posix\ipc $PROJ_DIR$\drivers - $PROJ_DIR$\..\..\examples\utest\testcases\kernel $PROJ_DIR$\. $PROJ_DIR$\libraries\Device $PROJ_DIR$\applications @@ -367,7 +366,9 @@ $PROJ_DIR$\..\..\libcpu\arm\cortex-m0 $PROJ_DIR$\..\..\components\drivers\include $PROJ_DIR$\..\..\libcpu\arm\common + $PROJ_DIR$\..\..\components\drivers\spi $PROJ_DIR$\..\..\components\finsh + $PROJ_DIR$\..\..\components\drivers\hwcrypto