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[lpcxxx] auto formatted

This commit is contained in:
Meco Man 2021-03-17 02:26:35 +08:00
parent c3ffe18688
commit 958d940575
171 changed files with 5365 additions and 5302 deletions
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4
bsp/lpc1114/driver/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -33,7 +33,7 @@
#define NVIC_ISPR HWREG32(SCB_BASE + 0x200)
#define NVIC_ICPR HWREG32(SCB_BASE + 0x280)
#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
extern unsigned char __bss_end__[];
extern unsigned char _ram_end[];

2
bsp/lpc1114/driver/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

36
bsp/lpc176x/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -38,44 +38,44 @@ extern int lwip_system_init(void);
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/* initialize platform */
platform_init();
/* initialize platform */
platform_init();
#ifdef RT_USING_LWIP
/* register Ethernet interface device */
lpc17xx_emac_hw_init();
/* initialize lwip stack */
/* register ethernetif device */
eth_system_device_init();
/* register ethernetif device */
eth_system_device_init();
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
/* initialize lwip system */
lwip_system_init();
rt_kprintf("TCP/IP initialized!\n");
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
rt_hw_sdcard_init();
/* initialize the device file system */
dfs_init();
/* initialize the device file system */
dfs_init();
#ifdef RT_USING_DFS_ELMFAT
/* initialize the elm chan FatFS file system*/
elm_init();
/* initialize the elm chan FatFS file system*/
elm_init();
#endif
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
rt_kprintf("File System initialized!\n");
rt_kprintf("File System initialized!\n");
else
rt_kprintf("File System init failed!\n");
rt_kprintf("File System init failed!\n");
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
/* initialize finsh */
finsh_system_init();
#endif
}
@ -84,8 +84,8 @@ int rt_application_init()
rt_thread_t tid;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;

8
bsp/lpc176x/applications/platform.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
void platform_init(void)
{
#ifdef RT_USING_MEMHEAP
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
#ifdef RT_USING_LWIP
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
#else
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
#endif
#endif
}

2
bsp/lpc176x/applications/platform.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

56
bsp/lpc176x/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -33,28 +33,28 @@ extern int __bss_end;
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
#else
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize application */
rt_application_init();
/* initialize application */
rt_application_init();
/* initialize timer */
rt_system_timer_init();
@ -62,25 +62,25 @@ void rtthread_startup(void)
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}
/*@}*/

34
bsp/lpc176x/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -29,13 +29,13 @@
*/
void rt_hw_timer_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
}
void SysTick_Handler(void)
@ -48,24 +48,24 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
/* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
/* initialize systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_UART0
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

2
bsp/lpc176x/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

714
bsp/lpc176x/drivers/emac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -11,20 +11,20 @@
#include "lwipopts.h"
#include <netif/ethernetif.h>
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6
struct lpc17xx_emac
{
/* inherit from ethernet device */
struct eth_device parent;
/* inherit from ethernet device */
struct eth_device parent;
rt_uint8_t phy_mode;
rt_uint8_t phy_mode;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct lpc17xx_emac lpc17xx_emac_device;
static struct rt_semaphore sem_lock;
@ -36,40 +36,40 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
void ENET_IRQHandler(void)
{
rt_uint32_t status;
rt_uint32_t status;
/* enter interrupt */
rt_interrupt_enter();
status = LPC_EMAC->IntStatus;
status = LPC_EMAC->IntStatus;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* leave interrupt */
rt_interrupt_leave();
}
@ -77,440 +77,440 @@ void ENET_IRQHandler(void)
/* phy write */
static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
{
unsigned int tout;
unsigned int tout;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MWTD = Value;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MWTD = Value;
/* Wait utill operation completed */
tout = 0;
for (tout = 0; tout < MII_WR_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
/* Wait utill operation completed */
tout = 0;
for (tout = 0; tout < MII_WR_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
}
/* phy read */
static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
{
rt_uint32_t tout;
rt_uint32_t tout;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MCMD = MCMD_READ;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MCMD = MCMD_READ;
/* Wait until operation completed */
tout = 0;
for (tout = 0; tout < MII_RD_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
LPC_EMAC->MCMD = 0;
return (LPC_EMAC->MRDD);
/* Wait until operation completed */
tout = 0;
for (tout = 0; tout < MII_RD_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
LPC_EMAC->MCMD = 0;
return (LPC_EMAC->MRDD);
}
/* init rx descriptor */
rt_inline void rx_descr_init (void)
{
rt_uint32_t i;
rt_uint32_t i;
for (i = 0; i < NUM_RX_FRAG; i++)
{
RX_DESC_PACKET(i) = RX_BUF(i);
RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
RX_STAT_INFO(i) = 0;
RX_STAT_HASHCRC(i) = 0;
}
for (i = 0; i < NUM_RX_FRAG; i++)
{
RX_DESC_PACKET(i) = RX_BUF(i);
RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
RX_STAT_INFO(i) = 0;
RX_STAT_HASHCRC(i) = 0;
}
/* Set EMAC Receive Descriptor Registers. */
LPC_EMAC->RxDescriptor = RX_DESC_BASE;
LPC_EMAC->RxStatus = RX_STAT_BASE;
LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
/* Set EMAC Receive Descriptor Registers. */
LPC_EMAC->RxDescriptor = RX_DESC_BASE;
LPC_EMAC->RxStatus = RX_STAT_BASE;
LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
/* Rx Descriptors Point to 0 */
LPC_EMAC->RxConsumeIndex = 0;
/* Rx Descriptors Point to 0 */
LPC_EMAC->RxConsumeIndex = 0;
}
/* init tx descriptor */
rt_inline void tx_descr_init (void)
{
rt_uint32_t i;
rt_uint32_t i;
for (i = 0; i < NUM_TX_FRAG; i++)
{
TX_DESC_PACKET(i) = TX_BUF(i);
TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
TX_STAT_INFO(i) = 0;
}
for (i = 0; i < NUM_TX_FRAG; i++)
{
TX_DESC_PACKET(i) = TX_BUF(i);
TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
TX_STAT_INFO(i) = 0;
}
/* Set EMAC Transmit Descriptor Registers. */
LPC_EMAC->TxDescriptor = TX_DESC_BASE;
LPC_EMAC->TxStatus = TX_STAT_BASE;
LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
/* Set EMAC Transmit Descriptor Registers. */
LPC_EMAC->TxDescriptor = TX_DESC_BASE;
LPC_EMAC->TxStatus = TX_STAT_BASE;
LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
/* Tx Descriptors Point to 0 */
LPC_EMAC->TxProduceIndex = 0;
/* Tx Descriptors Point to 0 */
LPC_EMAC->TxProduceIndex = 0;
}
static rt_err_t lpc17xx_emac_init(rt_device_t dev)
{
/* Initialize the EMAC ethernet controller. */
rt_uint32_t regv, tout, id1, id2;
/* Initialize the EMAC ethernet controller. */
rt_uint32_t regv, tout, id1, id2;
/* Power Up the EMAC controller. */
LPC_SC->PCONP |= 0x40000000;
/* Power Up the EMAC controller. */
LPC_SC->PCONP |= 0x40000000;
/* Enable P1 Ethernet Pins. */
LPC_PINCON->PINSEL2 = 0x50150105;
LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
/* Enable P1 Ethernet Pins. */
LPC_PINCON->PINSEL2 = 0x50150105;
LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
/* A short delay after reset. */
for (tout = 100; tout; tout--);
/* A short delay after reset. */
for (tout = 100; tout; tout--);
/* Initialize MAC control registers. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
/* Initialize MAC control registers. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
/* Enable Reduced MII interface. */
LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
for (tout = 100; tout; tout--);
LPC_EMAC->MCFG = MCFG_CLK_DIV20;
/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
/* Enable Reduced MII interface. */
LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
for (tout = 100; tout; tout--);
LPC_EMAC->MCFG = MCFG_CLK_DIV20;
/* Enable Reduced MII interface. */
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
/* Enable Reduced MII interface. */
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
/* Reset Reduced MII Logic. */
LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
for (tout = 100; tout; tout--);
LPC_EMAC->SUPP = SUPP_SPEED;
/* Reset Reduced MII Logic. */
LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
for (tout = 100; tout; tout--);
LPC_EMAC->SUPP = SUPP_SPEED;
/* Put the PHY in reset mode */
write_PHY (PHY_REG_BMCR, 0x8000);
for (tout = 1000; tout; tout--);
/* Put the PHY in reset mode */
write_PHY (PHY_REG_BMCR, 0x8000);
for (tout = 1000; tout; tout--);
/* Wait for hardware reset to end. */
for (tout = 0; tout < 10000; tout++)
{
regv = read_PHY (PHY_REG_BMCR);
if (!(regv & 0x8000))
{
/* Reset complete */
break;
}
}
if (tout >= 10000)
{
//return -RT_ERROR; /* reset failed */
rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
}
/* Wait for hardware reset to end. */
for (tout = 0; tout < 10000; tout++)
{
regv = read_PHY (PHY_REG_BMCR);
if (!(regv & 0x8000))
{
/* Reset complete */
break;
}
}
if (tout >= 10000)
{
//return -RT_ERROR; /* reset failed */
rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
}
/* Check if this is a DP83848C PHY. */
id1 = read_PHY (PHY_REG_IDR1);
id2 = read_PHY (PHY_REG_IDR2);
/* Check if this is a DP83848C PHY. */
id1 = read_PHY (PHY_REG_IDR1);
id2 = read_PHY (PHY_REG_IDR2);
if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
{
// return -RT_ERROR;
rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
}
else
{
/* Configure the PHY device */
/* Configure the PHY device */
switch (lpc17xx_emac_device.phy_mode)
{
case EMAC_PHY_AUTO:
/* Use auto negotiation about the link speed. */
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
for (tout = 0; tout < 200000; tout++)
{
regv = read_PHY (PHY_REG_BMSR);
if (regv & 0x0020)
{
/* Auto negotiation Complete. */
break;
}
}
if(tout >= 200000)
{
rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
}
break;
case EMAC_PHY_10MBIT:
/* Connect at 10MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
break;
case EMAC_PHY_100MBIT:
/* Connect at 100MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
break;
}
}
//if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
{
// return -RT_ERROR;
rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
}
else
{
/* Configure the PHY device */
/* Configure the PHY device */
switch (lpc17xx_emac_device.phy_mode)
{
case EMAC_PHY_AUTO:
/* Use auto negotiation about the link speed. */
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
for (tout = 0; tout < 200000; tout++)
{
regv = read_PHY (PHY_REG_BMSR);
if (regv & 0x0020)
{
/* Auto negotiation Complete. */
break;
}
}
if(tout >= 200000)
{
rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
}
break;
case EMAC_PHY_10MBIT:
/* Connect at 10MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
break;
case EMAC_PHY_100MBIT:
/* Connect at 100MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
break;
}
}
//if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
/* Check the link status. */
for (tout = 0; tout < 100; tout++)
{
regv = read_PHY (PHY_REG_STS);
if (regv & 0x0001)
{
/* Link is on. */
break;
}
}
if (tout >= 100)
{
//return -RT_ERROR;
rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
}
/* Configure Full/Half Duplex mode. */
if (regv & 0x0004)
{
/* Full duplex is enabled. */
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
}
else
{
/* Half duplex mode. */
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
/* Check the link status. */
for (tout = 0; tout < 100; tout++)
{
regv = read_PHY (PHY_REG_STS);
if (regv & 0x0001)
{
/* Link is on. */
break;
}
}
if (tout >= 100)
{
//return -RT_ERROR;
rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
}
/* Configure Full/Half Duplex mode. */
if (regv & 0x0004)
{
/* Full duplex is enabled. */
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
}
else
{
/* Half duplex mode. */
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002)
{
/* 10MBit mode. */
LPC_EMAC->SUPP = 0;
}
else
{
/* 100MBit mode. */
LPC_EMAC->SUPP = SUPP_SPEED;
}
/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002)
{
/* 10MBit mode. */
LPC_EMAC->SUPP = 0;
}
else
{
/* 100MBit mode. */
LPC_EMAC->SUPP = SUPP_SPEED;
}
/* Set the Ethernet MAC Address registers */
LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
/* Set the Ethernet MAC Address registers */
LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();
/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();
/* Receive Broadcast and Perfect Match Packets */
LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
/* Receive Broadcast and Perfect Match Packets */
LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
/* Reset all interrupts */
LPC_EMAC->IntClear = 0xFFFF;
/* Reset all interrupts */
LPC_EMAC->IntClear = 0xFFFF;
/* Enable EMAC interrupts. */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
/* Enable EMAC interrupts. */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
/* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
LPC_EMAC->MAC1 |= MAC1_REC_EN;
/* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
LPC_EMAC->MAC1 |= MAC1_REC_EN;
/* Enable the ENET Interrupt */
NVIC_EnableIRQ(ENET_IRQn);
/* Enable the ENET Interrupt */
NVIC_EnableIRQ(ENET_IRQn);
return RT_EOK;
return RT_EOK;
}
static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t lpc17xx_emac_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
else return -RT_ERROR;
break;
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
default :
break;
}
return RT_EOK;
return RT_EOK;
}
/* EtherNet Device Interface */
/* transmit packet. */
rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
{
rt_uint32_t Index, IndexNext;
struct pbuf *q;
rt_uint8_t *ptr;
rt_uint32_t Index, IndexNext;
struct pbuf *q;
rt_uint8_t *ptr;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
/* check whether block is full */
while (IndexNext == LPC_EMAC->TxConsumeIndex)
{
rt_err_t result;
rt_uint32_t recved;
/* there is no block yet, wait a flag */
result = rt_event_recv(&tx_event, 0x01,
RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
/* check whether block is full */
while (IndexNext == LPC_EMAC->TxConsumeIndex)
{
rt_err_t result;
rt_uint32_t recved;
RT_ASSERT(result == RT_EOK);
}
/* there is no block yet, wait a flag */
result = rt_event_recv(&tx_event, 0x01,
RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
}
/* get produce index */
Index = LPC_EMAC->TxProduceIndex;
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber)
IndexNext = 0;
/* get produce index */
Index = LPC_EMAC->TxProduceIndex;
/* copy data to tx buffer */
q = p;
ptr = (rt_uint8_t*)TX_BUF(Index);
while (q)
{
memcpy(ptr, q->payload, q->len);
ptr += q->len;
q = q->next;
}
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber)
IndexNext = 0;
TX_DESC_CTRL(Index) &= ~0x7ff;
TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
/* copy data to tx buffer */
q = p;
ptr = (rt_uint8_t*)TX_BUF(Index);
while (q)
{
memcpy(ptr, q->payload, q->len);
ptr += q->len;
q = q->next;
}
/* change index to the next */
LPC_EMAC->TxProduceIndex = IndexNext;
TX_DESC_CTRL(Index) &= ~0x7ff;
TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
/* unlock EMAC device */
rt_sem_release(&sem_lock);
/* change index to the next */
LPC_EMAC->TxProduceIndex = IndexNext;
return RT_EOK;
/* unlock EMAC device */
rt_sem_release(&sem_lock);
return RT_EOK;
}
/* reception packet. */
struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t size;
rt_uint32_t Index;
struct pbuf* p;
rt_uint32_t size;
rt_uint32_t Index;
/* init p pointer */
p = RT_NULL;
/* init p pointer */
p = RT_NULL;
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
Index = LPC_EMAC->RxConsumeIndex;
if(Index != LPC_EMAC->RxProduceIndex)
{
size = (RX_STAT_INFO(Index) & 0x7ff)+1;
if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
Index = LPC_EMAC->RxConsumeIndex;
if(Index != LPC_EMAC->RxProduceIndex)
{
size = (RX_STAT_INFO(Index) & 0x7ff)+1;
if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_uint8_t *ptr;
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_uint8_t *ptr;
ptr = (rt_uint8_t*)RX_BUF(Index);
for (q = p; q != RT_NULL; q= q->next)
{
memcpy(q->payload, ptr, q->len);
ptr += q->len;
}
}
/* move Index to the next */
if(++Index > LPC_EMAC->RxDescriptorNumber)
Index = 0;
ptr = (rt_uint8_t*)RX_BUF(Index);
for (q = p; q != RT_NULL; q= q->next)
{
memcpy(q->payload, ptr, q->len);
ptr += q->len;
}
}
/* set consume index */
LPC_EMAC->RxConsumeIndex = Index;
}
else
{
/* Enable RxDone interrupt */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
}
/* move Index to the next */
if(++Index > LPC_EMAC->RxDescriptorNumber)
Index = 0;
/* unlock EMAC device */
rt_sem_release(&sem_lock);
/* set consume index */
LPC_EMAC->RxConsumeIndex = Index;
}
else
{
/* Enable RxDone interrupt */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
}
return p;
/* unlock EMAC device */
rt_sem_release(&sem_lock);
return p;
}
int lpc17xx_emac_hw_init(void)
{
rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
/* set auto negotiation mode */
lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
/* set auto negotiation mode */
lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
// OUI 00-60-37 NXP Semiconductors
lpc17xx_emac_device.dev_addr[0] = 0x00;
lpc17xx_emac_device.dev_addr[1] = 0x60;
lpc17xx_emac_device.dev_addr[2] = 0x37;
/* set mac address: (only for test) */
lpc17xx_emac_device.dev_addr[3] = 0x12;
lpc17xx_emac_device.dev_addr[4] = 0x34;
lpc17xx_emac_device.dev_addr[5] = 0x56;
// OUI 00-60-37 NXP Semiconductors
lpc17xx_emac_device.dev_addr[0] = 0x00;
lpc17xx_emac_device.dev_addr[1] = 0x60;
lpc17xx_emac_device.dev_addr[2] = 0x37;
/* set mac address: (only for test) */
lpc17xx_emac_device.dev_addr[3] = 0x12;
lpc17xx_emac_device.dev_addr[4] = 0x34;
lpc17xx_emac_device.dev_addr[5] = 0x56;
lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
eth_device_init(&(lpc17xx_emac_device.parent), "e0");
return 0;
eth_device_init(&(lpc17xx_emac_device.parent), "e0");
return 0;
}
INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init);

11
bsp/lpc176x/drivers/emac.h
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE 0x20080000
#define RX_DESC_BASE 0x20080000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)

2
bsp/lpc176x/drivers/led.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/lpc176x/drivers/sd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
{
struct rt_device_blk_geometry *geometry;
geometry = (struct rt_device_blk_geometry *)args;
if (geometry == RT_NULL) return -RT_ERROR;
if (dev->user_data == RT_NULL) return -RT_ERROR;
geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize;
geometry->block_size = ((SDCFG *)dev->user_data)->blocksize;
geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt;

229
bsp/lpc176x/drivers/spi.c
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include "LPC17xx.h" /* LPC17xx definitions */
#include "spi.h"
@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
/* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
void LPC17xx_SPI_Init (void)
{
uint32_t dummy;
uint32_t dummy;
dummy = dummy; // avoid warning
dummy = dummy; // avoid warning
#if 0
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect (); /* set P0.16 high (SSEL inactiv) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
#else
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1->FIODIR |= (1<<21); /* P1.21 is output */
LPC_GPIO1->FIOPIN |= (1<<21); /* set P1.21 high (SSEL inact.)*/
LPC_PINCON->PINSEL3 &= ~(0<<10); /* P1.21 SSEL (used as GPIO) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3->FIODIR |= (1<<26); /* P3.26 is output */
LPC_GPIO3->FIOPIN &= ~(1<<26); /* set P3.26 low(enable power) */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 |= (3UL<<8); /* P1.20 SCK0 */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16)); /* P1.23 MISO0, P1.24 MOSI0 */
#endif
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
/* PCLK_SSP0=CCLK */
LPC_SC->PCLKSEL1 &= ~(3<<10); /* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC->PCLKSEL1 |= (1<<10); /* PCLKSP0 = CCLK (72MHz) */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC_SSP0->CR0 = 0x0007; /* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0->CR1 = 0x0002; /* SSP0 enable, master */
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for busy gone */
while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
/* drain SPI RX FIFO */
while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
{
dummy = LPC_SSP0->DR;
}
}
/* Close SSP0 */
void LPC17xx_SPI_DeInit( void )
{
// disable SPI
LPC_SSP0->CR1 = 0;
// disable SPI
LPC_SSP0->CR1 = 0;
#if 0
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
#else
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
LPC_PINCON->PINSEL3 &= ~(3UL<<8); /* P1.20 cleared */
LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16)); /* P1.23, P1.24 cleared */
#endif
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
// disable SSP power
LPC_SC->PCONP &= ~(1 << 21);
}
/* Set a SSP0 clock speed to desired value. */
void LPC17xx_SPI_SetSpeed (uint8_t speed)
{
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
speed &= 0xFE;
if ( speed < 2 ) {
speed = 2 ;
}
LPC_SSP0->CPSR = speed;
}
/* SSEL: low */
void LPC17xx_SPI_Select ()
{
#if 0
LPC_GPIO0->FIOPIN &= ~(1<<16);
LPC_GPIO0->FIOPIN &= ~(1<<16);
#else
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN &= ~(1<<21); /* SSEL is GPIO, set to high. */
#endif
}
@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
void LPC17xx_SPI_DeSelect ()
{
#if 0
LPC_GPIO0->FIOPIN |= (1<<16);
LPC_GPIO0->FIOPIN |= (1<<16);
#else
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
LPC_GPIO1->FIOPIN |= (1<<21); /* SSEL is GPIO, set to high. */
#endif
}
/* Send one byte then recv one byte of response. */
static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s)
{
uint8_t byte_r;
uint8_t byte_r;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
LPC_SSP0->DR = byte_s;
while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); /* Wait for transfer to finish */
byte_r = LPC_SSP0->DR;
return byte_r; /* Return received value */
return byte_r; /* Return received value */
}
/* Send one byte */
void LPC17xx_SPI_SendByte (uint8_t data)
{
LPC17xx_SPI_SendRecvByte (data);
LPC17xx_SPI_SendRecvByte (data);
}
/* Recv one byte */
uint8_t LPC17xx_SPI_RecvByte ()
{
return LPC17xx_SPI_SendRecvByte (0xFF);
return LPC17xx_SPI_SendRecvByte (0xFF);
}
/* Release SSP0 */
void LPC17xx_SPI_Release (void)
{
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
LPC17xx_SPI_DeSelect ();
LPC17xx_SPI_RecvByte ();
}
@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
#define FIFO_ELEM 8
/* Receive btr (must be multiple of 4) bytes of data and store in buff. */
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
{
uint32_t hwtr, startcnt, i, rec;
uint32_t hwtr, startcnt, i, rec;
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
hwtr = btr/2; /* byte number in unit of short */
if ( btr < FIFO_ELEM ) {
startcnt = hwtr;
} else {
startcnt = FIFO_ELEM;
}
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0 -> CR0 |= 0x0f; /* DSS to 16 bit */
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
for ( i = startcnt; i; i-- ) {
LPC_SSP0 -> DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
do {
while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
// wait for data in RX FIFO (RNE set)
}
rec = LPC_SSP0->DR;
if ( i < ( hwtr - startcnt ) ) {
LPC_SSP0->DR = 0xffff; /* fill TX FIFO, prepare clk for receive */
}
*buff++ = (uint8_t)(rec>>8);
*buff++ = (uint8_t)(rec);
i++;
} while ( i < hwtr );
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
/* Send 512 bytes of data block (stored in buff). */
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff)
{
uint32_t cnt;
uint16_t data;
uint32_t cnt;
uint16_t data;
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
LPC_SSP0->CR0 |= 0x0f; /* DSS to 16 bit */
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
/* fill the FIFO unless it is full */
for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
{
/* wait for TX FIFO not full (TNF) */
while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
data = (*buff++) << 8;
data |= *buff++;
LPC_SSP0->DR = data;
}
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* wait for BSY gone */
while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
/* drain receive FIFO */
while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
data = LPC_SSP0->DR;
}
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
LPC_SSP0->CR0 &= ~0x08; /* DSS to 8 bit */
}
#endif /* USE_FIFO */

25
bsp/lpc176x/drivers/spi.h
View File

@ -1,17 +1,26 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_SPI_H__
#define __LPC17XX_SPI_H__
#include <stdint.h>
#include <stdbool.h>
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
// if not use FIFO, R: 600kB/s, W: 500kB/s
// if use FIFO, R: 1.2MB/s, W: 800kB/s
#define USE_FIFO 1
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
#define SPI_SPEED_20MHz 4 /* => 18MHz */
#define SPI_SPEED_25MHz 4 /* => 18MHz */
#define SPI_SPEED_400kHz 180 /* => 400kHz */
/* external functions */
void LPC17xx_SPI_Init (void);
@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
uint8_t LPC17xx_SPI_RecvByte (void);
#if USE_FIFO
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff);
#endif
#endif // __LPC17XX_SPI_H__
#endif // __LPC17XX_SPI_H__

10
bsp/lpc176x/drivers/uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
struct rt_uart_lpc *uart = &uart_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = LPC_UART->IIR;
@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
{
iir = LPC_UART->LSR; //oe pe fe oe read for clear interrupt
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
}

52
bsp/lpc176x/rtconfig.h
View File

@ -4,17 +4,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@ -29,11 +29,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@ -67,15 +67,15 @@
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@ -87,7 +87,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@ -102,16 +102,16 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
// <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
// <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
@ -142,7 +142,7 @@
// </integer>
#define RT_DFS_ELM_CODE_PAGE 437
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@ -152,7 +152,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@ -168,29 +168,29 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR "192.168.1.30"
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />

84
bsp/lpc178x/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter)
#ifdef RT_USING_RTGUI
{
extern void rtgui_system_server_init(void);
extern void application_init(void);
extern void rtgui_system_server_init(void);
extern void application_init(void);
rt_device_t lcd;
rt_device_t lcd;
/* init lcd */
rt_hw_lcd_init();
/* init lcd */
rt_hw_lcd_init();
/* find lcd device */
lcd = rt_device_find("lcd");
if (lcd != RT_NULL)
{
/* set lcd device as rtgui graphic driver */
rtgui_graphic_set_device(lcd);
/* find lcd device */
lcd = rt_device_find("lcd");
if (lcd != RT_NULL)
{
/* set lcd device as rtgui graphic driver */
rtgui_graphic_set_device(lcd);
/* init rtgui system server */
rtgui_system_server_init();
/* init rtgui system server */
rtgui_system_server_init();
/* startup rtgui in demo of RT-Thread/GUI examples */
application_init();
}
/* startup rtgui in demo of RT-Thread/GUI examples */
application_init();
}
}
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
/* initialize finsh */
finsh_system_init();
#endif
}
@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter)
int rt_application_init(void)
{
rt_thread_t tid;
rt_thread_t tid;
rt_thread_init(&thread_led,
"led",
rt_thread_entry_led,
RT_NULL,
&thread_led_stack[0],
sizeof(thread_led_stack),11,5);
rt_thread_startup(&thread_led);
rt_thread_init(&thread_led,
"led",
rt_thread_entry_led,
RT_NULL,
&thread_led_stack[0],
sizeof(thread_led_stack),11,5);
rt_thread_startup(&thread_led);
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL) rt_thread_startup(tid);
return 0;
return 0;
}
#if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH)
@ -170,20 +170,20 @@ int rt_application_init(void)
void key(rt_uint32_t key)
{
struct rtgui_event_kbd ekbd;
struct rtgui_event_kbd ekbd;
RTGUI_EVENT_KBD_INIT(&ekbd);
ekbd.mod = RTGUI_KMOD_NONE;
ekbd.unicode = 0;
ekbd.key = key;
RTGUI_EVENT_KBD_INIT(&ekbd);
ekbd.mod = RTGUI_KMOD_NONE;
ekbd.unicode = 0;
ekbd.key = key;
ekbd.type = RTGUI_KEYDOWN;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
ekbd.type = RTGUI_KEYDOWN;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
rt_thread_delay(2);
rt_thread_delay(2);
ekbd.type = RTGUI_KEYUP;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
ekbd.type = RTGUI_KEYUP;
rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
}
FINSH_FUNCTION_EXPORT(key, send a key to gui server);
#endif

64
bsp/lpc178x/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -37,11 +37,11 @@ extern int __bss_end;
*******************************************************************************/
void assert_failed(u8* file, u32 line)
{
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
rt_kprintf("\n\r Wrong parameter value detected on\r\n");
rt_kprintf(" file %s\r\n", file);
rt_kprintf(" line %d\r\n", line);
while (1) ;
while (1) ;
}
#endif
@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line)
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
#else
rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
#endif
/* initialize memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
#elif __ICCARM__
rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
#else
rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize application */
rt_application_init();
/* initialize application */
rt_application_init();
/* initialize timer */
rt_system_timer_init();
@ -79,23 +79,23 @@ void rtthread_startup(void)
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
return 0;
}

2
bsp/lpc178x/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc178x/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -31,7 +31,7 @@
//#define RT_USING_UART2
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_CONSOLE_DEVICE_NAME "uart0"
// </RDTConfigurator>

340
bsp/lpc178x/drivers/drv_glcd.c
View File

@ -37,14 +37,14 @@
#define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
#define C_GLCD_PIX_CLK (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME)
//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_LCD_TypeDef * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define SDRAM_BASE_ADDR SDRAM_BASE
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define SDRAM_BASE_ADDR SDRAM_BASE
#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800)
#define LCD_VRAM_BASE_ADDR ((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_CURSOR_BASE_ADDR ((unsigned long)0x20088800)
static pFontType_t pCurrFont = NULL;
@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y)
*************************************************************************/
void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
{
unsigned long i ;
unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
unsigned long i ;
unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
pDst += cursor*64;
pDst += cursor*64;
for(i = 0; i < size ; i++)
// *pDst++ = *pCursor++;
{
*pDst = *pCursor;
pDst++;
pCursor++;
}
for(i = 0; i < size ; i++)
// *pDst++ = *pCursor++;
{
*pDst = *pCursor;
pDst++;
pCursor++;
}
}
/*************************************************************************
* Function Name: GLCD_Init
@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
*************************************************************************/
void GLCD_Init (void* VRAMBase)
{
// unsigned long i;
// Assign pins
LPC_IOCON->P2_9 = 0x06; // VD3, R0
LPC_IOCON->P2_6 = 0x07; // VD4, R1
LPC_IOCON->P2_7 = 0x07; // VD5, R2
LPC_IOCON->P4_28 = 0x05; // VD6, R3
LPC_IOCON->P4_29 = 0x05; // VD7, R4
// unsigned long i;
// Assign pins
LPC_IOCON->P2_9 = 0x06; // VD3, R0
LPC_IOCON->P2_6 = 0x07; // VD4, R1
LPC_IOCON->P2_7 = 0x07; // VD5, R2
LPC_IOCON->P4_28 = 0x05; // VD6, R3
LPC_IOCON->P4_29 = 0x05; // VD7, R4
LPC_IOCON->P1_20 = 0x07; // VD10, G0
LPC_IOCON->P1_21 = 0x07; // VD11, G1
LPC_IOCON->P1_22 = 0x07; // VD12, G2
LPC_IOCON->P1_23 = 0x07; // VD13, G3
LPC_IOCON->P1_24 = 0x07; // VD14, G4
LPC_IOCON->P1_25 = 0x07; // VD15, G5
LPC_IOCON->P1_20 = 0x07; // VD10, G0
LPC_IOCON->P1_21 = 0x07; // VD11, G1
LPC_IOCON->P1_22 = 0x07; // VD12, G2
LPC_IOCON->P1_23 = 0x07; // VD13, G3
LPC_IOCON->P1_24 = 0x07; // VD14, G4
LPC_IOCON->P1_25 = 0x07; // VD15, G5
LPC_IOCON->P2_13 = 0x07; // VD19, B0
LPC_IOCON->P1_26 = 0x07; // VD20, B1
LPC_IOCON->P1_27 = 0x07; // VD21, B2
LPC_IOCON->P1_28 = 0x07; // VD22, B3
LPC_IOCON->P1_29 = 0x07; // VD23, B4
LPC_IOCON->P2_13 = 0x07; // VD19, B0
LPC_IOCON->P1_26 = 0x07; // VD20, B1
LPC_IOCON->P1_27 = 0x07; // VD21, B2
LPC_IOCON->P1_28 = 0x07; // VD22, B3
LPC_IOCON->P1_29 = 0x07; // VD23, B4
LPC_IOCON->P2_2 = 0x07; // DCLK
LPC_IOCON->P2_0 = 0x07; // DSIP(power)
LPC_IOCON->P2_5 = 0x07; // HSYNC
LPC_IOCON->P2_3 = 0x07; // VSYNC
LPC_IOCON->P2_4 = 0x07; // DataEn
LPC_IOCON->P2_2 = 0x07; // DCLK
LPC_IOCON->P2_0 = 0x07; // DSIP(power)
LPC_IOCON->P2_5 = 0x07; // HSYNC
LPC_IOCON->P2_3 = 0x07; // VSYNC
LPC_IOCON->P2_4 = 0x07; // DataEn
// LPC_IOCON->P5_4 = 0x00; // Backlight
// LPC_IOCON->P5_4 = 0x00; // Backlight
// >>> debug >>>
// >>> debug >>>
// <<< debug <<<
// <<< debug <<<
/*Back light enable*/
// LPC_GPIO5->DIR = (1<<4);
// LPC_GPIO5->SET= (5<<4);
/*Back light enable*/
// LPC_GPIO5->DIR = (1<<4);
// LPC_GPIO5->SET= (5<<4);
//Turn on LCD clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
//Turn on LCD clock
CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
// Disable cursor
LPC_LCD->CRSR_CTRL &=~(1<<0);
// Disable cursor
LPC_LCD->CRSR_CTRL &=~(1<<0);
// disable GLCD controller
LPC_LCD->CTRL = 0;
// RGB888
LPC_LCD->CTRL &= ~(0x07 <<1);
LPC_LCD->CTRL |= (6<<1);
// disable GLCD controller
LPC_LCD->CTRL = 0;
// RGB888
LPC_LCD->CTRL &= ~(0x07 <<1);
LPC_LCD->CTRL |= (6<<1);
// TFT panel
LPC_LCD->CTRL |= (1<<5);
// single panel
LPC_LCD->CTRL &= ~(1<<7);
// notmal output
LPC_LCD->CTRL &= ~(1<<8);
// little endian byte order
LPC_LCD->CTRL &= ~(1<<9);
// little endian pix order
LPC_LCD->CTRL &= ~(1<<10);
// disable power
LPC_LCD->CTRL &= ~(1<<11);
// init pixel clock
// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
// bypass inrenal clk divider
LPC_LCD->POL |=(1<<26);
// clock source for the LCD block is HCLK
LPC_LCD->POL &= ~(1<<5);
// LCDFP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<11);
// LCDLP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<12);
// data is driven out into the LCD on the falling edge
LPC_LCD->POL &= ~(1<<13);
// active high
LPC_LCD->POL &= ~(1<<14);
LPC_LCD->POL &= ~(0x3FF <<16);
LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
// TFT panel
LPC_LCD->CTRL |= (1<<5);
// single panel
LPC_LCD->CTRL &= ~(1<<7);
// notmal output
LPC_LCD->CTRL &= ~(1<<8);
// little endian byte order
LPC_LCD->CTRL &= ~(1<<9);
// little endian pix order
LPC_LCD->CTRL &= ~(1<<10);
// disable power
LPC_LCD->CTRL &= ~(1<<11);
// init pixel clock
// g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
// bypass inrenal clk divider
LPC_LCD->POL |=(1<<26);
// clock source for the LCD block is HCLK
LPC_LCD->POL &= ~(1<<5);
// LCDFP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<11);
// LCDLP pin is active LOW and inactive HIGH
LPC_LCD->POL |= (1<<12);
// data is driven out into the LCD on the falling edge
LPC_LCD->POL &= ~(1<<13);
// active high
LPC_LCD->POL &= ~(1<<14);
LPC_LCD->POL &= ~(0x3FF <<16);
LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
// init Horizontal Timing
LPC_LCD->TIMH = 0; //reset TIMH before set value
LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
// init Horizontal Timing
LPC_LCD->TIMH = 0; //reset TIMH before set value
LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
// init Vertical Timing
LPC_LCD->TIMV = 0; //reset TIMV value before setting
LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
// Frame Base Address doubleword aligned
LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
// init Vertical Timing
LPC_LCD->TIMV = 0; //reset TIMV value before setting
LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
// Frame Base Address doubleword aligned
LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
}
/*************************************************************************
@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase)
*************************************************************************/
void GLCD_SetPallet (const unsigned long * pPallete)
{
unsigned long i;
unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
// //assert(pPallete);
for (i = 0; i < 128; i++)
{
*pDst++ = *pPallete++;
}
unsigned long i;
unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
// //assert(pPallete);
for (i = 0; i < 128; i++)
{
*pDst++ = *pPallete++;
}
}
/*************************************************************************
@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete)
*************************************************************************/
void GLCD_Ctrl (Bool bEna)
{
volatile unsigned long i;
volatile unsigned long i;
if (bEna)
{
// LCD_CTRL_bit.LcdEn = 1;
@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR,
*pXR = XL_Win + ((TextX_Pos+1)*pCurrFont->H_Size) - 1;
if(*pXR > XR_Win)
{
*pH_Size -= *pXR - XR_Win;
*pH_Size -= *pXR - XR_Win;
*pXR = XR_Win;
}
@ -514,19 +514,19 @@ unsigned long i, j, k;
++TextY_Pos;
break;
case '\r': // go to begin of this line (Carriage Return)
// clear from current position to end of line
while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
// clear from current position to end of line
while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
LCD_SET_WINDOW(xl,xr,yu,yd);
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
TextX_Pos = 0;
break;
case '\b': // go back one position (BackSpace)
@ -534,45 +534,45 @@ unsigned long i, j, k;
{
--TextX_Pos;
// del current position
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
LCD_SET_WINDOW(xl,xr,yu,yd);
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
}
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
}
}
break;
case '\t': // go to next Horizontal Tab stop
WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
for(k = 0; k < WhiteSpaceNumb; ++k)
{
WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
for(k = 0; k < WhiteSpaceNumb; ++k)
{
LCD_SET_WINDOW(xl,xr,yu,yd);
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
else
{
break;
}
}
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
for(i = 0; i < V_Size; ++i)
{
for(j = 0; j < H_Size; ++j)
{
LCD_WRITE_PIXEL(TextBackgndColour);
}
}
++TextX_Pos;
}
else
{
break;
}
}
break;
case '\f': // go to top of page (Form Feed)
// clear entire window
H_Size = XR_Win - XL_Win;
V_Size = YD_Win - YU_Win;
// clear entire window
H_Size = XR_Win - XL_Win;
V_Size = YD_Win - YU_Win;
// set character window X left, Y right
LCD_SET_WINDOW(XL_Win,XR_Win,YU_Win,YD_Win);
// Fill window with background font color
@ -584,7 +584,7 @@ unsigned long i, j, k;
}
}
TextX_Pos = TextY_Pos = 0;
TextX_Pos = TextY_Pos = 0;
break;
case '\a': // signal an alert (BELl)
TEXT_BEL1_FUNC();
@ -593,37 +593,37 @@ unsigned long i, j, k;
// Calculate the current character base address from stream
// and the character position
if((c < pCurrFont->CharacterOffset) &&
(c >= pCurrFont->CharactersNuber))
{
c = 0;
(c >= pCurrFont->CharactersNuber))
{
c = 0;
}
else
{
c -= pCurrFont->CharacterOffset;
c -= pCurrFont->CharacterOffset;
}
pSrc = pCurrFont->pFontStream + (H_Line * pCurrFont->V_Size * c);
// Calculate character window and fit it in the text window
if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
{
// set character window X left, Y right
LCD_SET_WINDOW(xl,xr,yu,yd);
// Send char data
for(i = 0; i < V_Size; ++i)
{
// set character window X left, Y right
LCD_SET_WINDOW(xl,xr,yu,yd);
// Send char data
for(i = 0; i < V_Size; ++i)
{
SrcInc = H_Line;
for(j = 0; j < H_Size; ++j)
{
Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
LCD_WRITE_PIXEL(Temp);
if((j&0x7) == 7)
{
++pSrc;
{
Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
LCD_WRITE_PIXEL(Temp);
if((j&0x7) == 7)
{
++pSrc;
--SrcInc;
}
}
}
}
// next line of character
pSrc += SrcInc;
}
pSrc += SrcInc;
}
}
++TextX_Pos;
}

12
bsp/lpc178x/drivers/drv_glcd.h
View File

@ -33,7 +33,7 @@ typedef unsigned long Boolean;
/**
* @brief A struct for Bitmap on LCD screen
*/
typedef struct _Bmp_t
typedef struct _Bmp_t
{
U32 H_Size;
U32 V_Size;
@ -47,8 +47,8 @@ typedef struct _Bmp_t
/**
* @brief A struct for Font Type on LCD screen
*/
typedef struct _FontType_t
typedef struct _FontType_t
{
U32 H_Size;
U32 V_Size;
@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t;
#define C_GLCD_REFRESH_FREQ (60HZ)
#define C_GLCD_H_SIZE 480
#define C_GLCD_H_PULSE 2 //
#define C_GLCD_H_FRONT_PORCH 5 //
#define C_GLCD_H_BACK_PORCH 40 //
#define C_GLCD_H_PULSE 2 //
#define C_GLCD_H_FRONT_PORCH 5 //
#define C_GLCD_H_BACK_PORCH 40 //
#define C_GLCD_V_SIZE 272
#define C_GLCD_V_PULSE 2
#define C_GLCD_V_FRONT_PORCH 8

712
bsp/lpc178x/drivers/emac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,20 +14,20 @@
#include "lwipopts.h"
#include <netif/ethernetif.h>
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6
struct lpc17xx_emac
{
/* inherit from ethernet device */
struct eth_device parent;
/* inherit from ethernet device */
struct eth_device parent;
rt_uint8_t phy_mode;
rt_uint8_t phy_mode;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct lpc17xx_emac lpc17xx_emac_device;
static struct rt_semaphore sem_lock;
@ -39,39 +39,39 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
void ENET_IRQHandler(void)
{
rt_uint32_t status;
rt_uint32_t status;
/* enter interrupt */
rt_interrupt_enter();
status = LPC_EMAC->IntStatus;
status = LPC_EMAC->IntStatus;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* leave interrupt */
rt_interrupt_leave();
@ -80,84 +80,84 @@ void ENET_IRQHandler(void)
/* phy write */
static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
{
unsigned int tout;
unsigned int tout;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MWTD = Value;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MWTD = Value;
/* Wait utill operation completed */
tout = 0;
for (tout = 0; tout < MII_WR_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
/* Wait utill operation completed */
tout = 0;
for (tout = 0; tout < MII_WR_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
}
/* phy read */
static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
{
rt_uint32_t tout;
rt_uint32_t tout;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MCMD = MCMD_READ;
LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
LPC_EMAC->MCMD = MCMD_READ;
/* Wait until operation completed */
tout = 0;
for (tout = 0; tout < MII_RD_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
LPC_EMAC->MCMD = 0;
return (LPC_EMAC->MRDD);
/* Wait until operation completed */
tout = 0;
for (tout = 0; tout < MII_RD_TOUT; tout++)
{
if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
{
break;
}
}
LPC_EMAC->MCMD = 0;
return (LPC_EMAC->MRDD);
}
/* init rx descriptor */
rt_inline void rx_descr_init (void)
{
rt_uint32_t i;
rt_uint32_t i;
for (i = 0; i < NUM_RX_FRAG; i++)
{
RX_DESC_PACKET(i) = RX_BUF(i);
RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
RX_STAT_INFO(i) = 0;
RX_STAT_HASHCRC(i) = 0;
}
for (i = 0; i < NUM_RX_FRAG; i++)
{
RX_DESC_PACKET(i) = RX_BUF(i);
RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
RX_STAT_INFO(i) = 0;
RX_STAT_HASHCRC(i) = 0;
}
/* Set EMAC Receive Descriptor Registers. */
LPC_EMAC->RxDescriptor = RX_DESC_BASE;
LPC_EMAC->RxStatus = RX_STAT_BASE;
LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
/* Set EMAC Receive Descriptor Registers. */
LPC_EMAC->RxDescriptor = RX_DESC_BASE;
LPC_EMAC->RxStatus = RX_STAT_BASE;
LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
/* Rx Descriptors Point to 0 */
LPC_EMAC->RxConsumeIndex = 0;
/* Rx Descriptors Point to 0 */
LPC_EMAC->RxConsumeIndex = 0;
}
/* init tx descriptor */
rt_inline void tx_descr_init (void)
{
rt_uint32_t i;
rt_uint32_t i;
for (i = 0; i < NUM_TX_FRAG; i++)
{
TX_DESC_PACKET(i) = TX_BUF(i);
TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
TX_STAT_INFO(i) = 0;
}
for (i = 0; i < NUM_TX_FRAG; i++)
{
TX_DESC_PACKET(i) = TX_BUF(i);
TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
TX_STAT_INFO(i) = 0;
}
/* Set EMAC Transmit Descriptor Registers. */
LPC_EMAC->TxDescriptor = TX_DESC_BASE;
LPC_EMAC->TxStatus = TX_STAT_BASE;
LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
/* Set EMAC Transmit Descriptor Registers. */
LPC_EMAC->TxDescriptor = TX_DESC_BASE;
LPC_EMAC->TxStatus = TX_STAT_BASE;
LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
/* Tx Descriptors Point to 0 */
LPC_EMAC->TxProduceIndex = 0;
/* Tx Descriptors Point to 0 */
LPC_EMAC->TxProduceIndex = 0;
}
/*
@ -178,375 +178,375 @@ REF_CLK P1_15
*/
static rt_err_t lpc17xx_emac_init(rt_device_t dev)
{
/* Initialize the EMAC ethernet controller. */
rt_uint32_t regv, tout;
/* Initialize the EMAC ethernet controller. */
rt_uint32_t regv, tout;
/* Power Up the EMAC controller. */
LPC_SC->PCONP |= (1UL<<30);
/* Power Up the EMAC controller. */
LPC_SC->PCONP |= (1UL<<30);
/* config RESET */
PINSEL_ConfigPin(3, 19, 0);
PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
LPC_GPIO3->DIR |= 1<<19;
LPC_GPIO3->CLR = 1<<19;
/* config RESET */
PINSEL_ConfigPin(3, 19, 0);
PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
LPC_GPIO3->DIR |= 1<<19;
LPC_GPIO3->CLR = 1<<19;
/* Enable P1 Ethernet Pins. */
PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */
PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */
PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */
PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */
PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */
PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
/* Enable P1 Ethernet Pins. */
PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */
PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */
PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */
PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */
PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */
PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
LPC_GPIO3->SET = 1<<19;
LPC_GPIO3->SET = 1<<19;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
/* Reset all EMAC internal modules. */
LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
/* A short delay after reset. */
for (tout = 100; tout; tout--);
/* A short delay after reset. */
for (tout = 100; tout; tout--);
/* Initialize MAC control registers. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
/* Initialize MAC control registers. */
LPC_EMAC->MAC1 = MAC1_PASS_ALL;
LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
LPC_EMAC->MAXF = ETH_MAX_FLEN;
LPC_EMAC->CLRT = CLRT_DEF;
LPC_EMAC->IPGR = IPGR_DEF;
/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
/* Enable Reduced MII interface. */
LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
for (tout = 100; tout; tout--);
LPC_EMAC->MCFG = MCFG_CLK_DIV20;
/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
/* Enable Reduced MII interface. */
LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
for (tout = 100; tout; tout--);
LPC_EMAC->MCFG = MCFG_CLK_DIV20;
/* Enable Reduced MII interface. */
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
/* Enable Reduced MII interface. */
LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
/* Reset Reduced MII Logic. */
LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
for (tout = 100; tout; tout--);
LPC_EMAC->SUPP = SUPP_SPEED;
/* Reset Reduced MII Logic. */
LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
for (tout = 100; tout; tout--);
LPC_EMAC->SUPP = SUPP_SPEED;
/* Put the PHY in reset mode */
write_PHY (PHY_REG_BMCR, 0x8000);
for (tout = 1000; tout; tout--);
/* Put the PHY in reset mode */
write_PHY (PHY_REG_BMCR, 0x8000);
for (tout = 1000; tout; tout--);
// /* Wait for hardware reset to end. */
// for (tout = 0; tout < 0x100000; tout++)
// {
// regv = read_PHY (PHY_REG_BMCR);
// if (!(regv & 0x8000))
// {
// /* Reset complete */
// break;
// }
// }
// if (tout >= 0x100000)
// /* Wait for hardware reset to end. */
// for (tout = 0; tout < 0x100000; tout++)
// {
// regv = read_PHY (PHY_REG_BMCR);
// if (!(regv & 0x8000))
// {
// /* Reset complete */
// break;
// }
// }
// if (tout >= 0x100000)
// {
// rt_kprintf("reset failed\r\n");
// return -RT_ERROR; /* reset failed */
// }
// /* Check if this is a DP83848C PHY. */
// id1 = read_PHY (PHY_REG_IDR1);
// id2 = read_PHY (PHY_REG_IDR2);
// /* Check if this is a DP83848C PHY. */
// id1 = read_PHY (PHY_REG_IDR1);
// id2 = read_PHY (PHY_REG_IDR2);
//
// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
// return -RT_ERROR;
// if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
// return -RT_ERROR;
/* Configure the PHY device */
/* Configure the PHY device */
switch (lpc17xx_emac_device.phy_mode)
{
case EMAC_PHY_AUTO:
/* Use autonegotiation about the link speed. */
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
// for (tout = 0; tout < 0x100000; tout++)
// {
// regv = read_PHY (PHY_REG_BMSR);
// if (regv & 0x0020)
// {
// /* Autonegotiation Complete. */
// break;
// }
// }
break;
case EMAC_PHY_10MBIT:
/* Connect at 10MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
break;
case EMAC_PHY_100MBIT:
/* Connect at 100MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
break;
}
if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
/* Configure the PHY device */
/* Configure the PHY device */
switch (lpc17xx_emac_device.phy_mode)
{
case EMAC_PHY_AUTO:
/* Use autonegotiation about the link speed. */
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
// for (tout = 0; tout < 0x100000; tout++)
// {
// regv = read_PHY (PHY_REG_BMSR);
// if (regv & 0x0020)
// {
// /* Autonegotiation Complete. */
// break;
// }
// }
break;
case EMAC_PHY_10MBIT:
/* Connect at 10MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
break;
case EMAC_PHY_100MBIT:
/* Connect at 100MBit */
write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
break;
}
if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
// /* Check the link status. */
// for (tout = 0; tout < 0x10000; tout++)
// {
// regv = read_PHY (PHY_REG_STS);
// if (regv & 0x0001)
// {
// /* Link is on. */
// break;
// }
// }
// if (tout >= 0x10000) return -RT_ERROR;
// /* Check the link status. */
// for (tout = 0; tout < 0x10000; tout++)
// {
// regv = read_PHY (PHY_REG_STS);
// if (regv & 0x0001)
// {
// /* Link is on. */
// break;
// }
// }
// if (tout >= 0x10000) return -RT_ERROR;
regv = 0x0004;
/* Configure Full/Half Duplex mode. */
if (regv & 0x0004)
{
/* Full duplex is enabled. */
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
}
else
{
/* Half duplex mode. */
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
regv = 0x0004;
/* Configure Full/Half Duplex mode. */
if (regv & 0x0004)
{
/* Full duplex is enabled. */
LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
LPC_EMAC->Command |= CR_FULL_DUP;
LPC_EMAC->IPGT = IPGT_FULL_DUP;
}
else
{
/* Half duplex mode. */
LPC_EMAC->IPGT = IPGT_HALF_DUP;
}
/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002)
{
/* 10MBit mode. */
LPC_EMAC->SUPP = 0;
}
else
{
/* 100MBit mode. */
LPC_EMAC->SUPP = SUPP_SPEED;
}
/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002)
{
/* 10MBit mode. */
LPC_EMAC->SUPP = 0;
}
else
{
/* 100MBit mode. */
LPC_EMAC->SUPP = SUPP_SPEED;
}
/* Set the Ethernet MAC Address registers */
LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
/* Set the Ethernet MAC Address registers */
LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();
/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();
/* Receive Broadcast and Perfect Match Packets */
LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
/* Receive Broadcast and Perfect Match Packets */
LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
/* Reset all interrupts */
LPC_EMAC->IntClear = 0xFFFF;
/* Reset all interrupts */
LPC_EMAC->IntClear = 0xFFFF;
/* Enable EMAC interrupts. */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
/* Enable EMAC interrupts. */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
/* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
LPC_EMAC->MAC1 |= MAC1_REC_EN;
/* Enable receive and transmit mode of MAC Ethernet core */
LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
LPC_EMAC->MAC1 |= MAC1_REC_EN;
/* Enable the ENET Interrupt */
NVIC_EnableIRQ(ENET_IRQn);
/* Enable the ENET Interrupt */
NVIC_EnableIRQ(ENET_IRQn);
return RT_EOK;
return RT_EOK;
}
static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t lpc17xx_emac_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
else return -RT_ERROR;
break;
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
default :
break;
}
return RT_EOK;
return RT_EOK;
}
/* EtherNet Device Interface */
/* transmit packet. */
rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
{
rt_uint32_t Index, IndexNext;
struct pbuf *q;
rt_uint8_t *ptr;
rt_uint32_t Index, IndexNext;
struct pbuf *q;
rt_uint8_t *ptr;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
/* check whether block is full */
while (IndexNext == LPC_EMAC->TxConsumeIndex)
{
rt_err_t result;
rt_uint32_t recved;
/* check whether block is full */
while (IndexNext == LPC_EMAC->TxConsumeIndex)
{
rt_err_t result;
rt_uint32_t recved;
/* there is no block yet, wait a flag */
result = rt_event_recv(&tx_event, 0x01,
RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
/* there is no block yet, wait a flag */
result = rt_event_recv(&tx_event, 0x01,
RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
RT_ASSERT(result == RT_EOK);
}
RT_ASSERT(result == RT_EOK);
}
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* get produce index */
Index = LPC_EMAC->TxProduceIndex;
/* get produce index */
Index = LPC_EMAC->TxProduceIndex;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber)
IndexNext = 0;
/* calculate next index */
IndexNext = LPC_EMAC->TxProduceIndex + 1;
if(IndexNext > LPC_EMAC->TxDescriptorNumber)
IndexNext = 0;
/* copy data to tx buffer */
q = p;
ptr = (rt_uint8_t*)TX_BUF(Index);
while (q)
{
memcpy(ptr, q->payload, q->len);
ptr += q->len;
q = q->next;
}
/* copy data to tx buffer */
q = p;
ptr = (rt_uint8_t*)TX_BUF(Index);
while (q)
{
memcpy(ptr, q->payload, q->len);
ptr += q->len;
q = q->next;
}
TX_DESC_CTRL(Index) &= ~0x7ff;
TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
TX_DESC_CTRL(Index) &= ~0x7ff;
TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
/* change index to the next */
LPC_EMAC->TxProduceIndex = IndexNext;
/* change index to the next */
LPC_EMAC->TxProduceIndex = IndexNext;
/* unlock EMAC device */
rt_sem_release(&sem_lock);
/* unlock EMAC device */
rt_sem_release(&sem_lock);
return RT_EOK;
return RT_EOK;
}
/* reception packet. */
struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t size;
rt_uint32_t Index;
struct pbuf* p;
rt_uint32_t size;
rt_uint32_t Index;
/* init p pointer */
p = RT_NULL;
/* init p pointer */
p = RT_NULL;
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
/* lock EMAC device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
Index = LPC_EMAC->RxConsumeIndex;
if(Index != LPC_EMAC->RxProduceIndex)
{
size = (RX_STAT_INFO(Index) & 0x7ff)+1;
if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
Index = LPC_EMAC->RxConsumeIndex;
if(Index != LPC_EMAC->RxProduceIndex)
{
size = (RX_STAT_INFO(Index) & 0x7ff)+1;
if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_uint8_t *ptr;
/* allocate buffer */
p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
if (p != RT_NULL)
{
struct pbuf* q;
rt_uint8_t *ptr;
ptr = (rt_uint8_t*)RX_BUF(Index);
for (q = p; q != RT_NULL; q= q->next)
{
memcpy(q->payload, ptr, q->len);
ptr += q->len;
}
}
ptr = (rt_uint8_t*)RX_BUF(Index);
for (q = p; q != RT_NULL; q= q->next)
{
memcpy(q->payload, ptr, q->len);
ptr += q->len;
}
}
/* move Index to the next */
if(++Index > LPC_EMAC->RxDescriptorNumber)
Index = 0;
/* move Index to the next */
if(++Index > LPC_EMAC->RxDescriptorNumber)
Index = 0;
/* set consume index */
LPC_EMAC->RxConsumeIndex = Index;
}
else
{
/* Enable RxDone interrupt */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
}
/* set consume index */
LPC_EMAC->RxConsumeIndex = Index;
}
else
{
/* Enable RxDone interrupt */
LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
}
/* unlock EMAC device */
rt_sem_release(&sem_lock);
/* unlock EMAC device */
rt_sem_release(&sem_lock);
return p;
return p;
}
void lpc17xx_emac_hw_init(void)
{
rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
/* set autonegotiation mode */
lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
/* set autonegotiation mode */
lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
// OUI 00-60-37 NXP Semiconductors
lpc17xx_emac_device.dev_addr[0] = 0x00;
lpc17xx_emac_device.dev_addr[1] = 0x60;
lpc17xx_emac_device.dev_addr[2] = 0x37;
/* set mac address: (only for test) */
lpc17xx_emac_device.dev_addr[3] = 0x12;
lpc17xx_emac_device.dev_addr[4] = 0x34;
lpc17xx_emac_device.dev_addr[5] = 0x56;
// OUI 00-60-37 NXP Semiconductors
lpc17xx_emac_device.dev_addr[0] = 0x00;
lpc17xx_emac_device.dev_addr[1] = 0x60;
lpc17xx_emac_device.dev_addr[2] = 0x37;
/* set mac address: (only for test) */
lpc17xx_emac_device.dev_addr[3] = 0x12;
lpc17xx_emac_device.dev_addr[4] = 0x34;
lpc17xx_emac_device.dev_addr[5] = 0x56;
lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
eth_device_init(&(lpc17xx_emac_device.parent), "e0");
eth_device_init(&(lpc17xx_emac_device.parent), "e0");
}
#ifdef RT_USING_FINSH
#include <finsh.h>
void emac_dump()
{
rt_kprintf("Command : %08x\n", LPC_EMAC->Command);
rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
rt_kprintf("Command : %08x\n", LPC_EMAC->Command);
rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
}
FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
#endif

11
bsp/lpc178x/drivers/emac.h
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE 0x20000000
#define RX_DESC_BASE 0x20000000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)

376
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
View File

@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_clkpwr.c 2011-06-02
* $Id$ lpc177x_8x_clkpwr.c 2011-06-02
*//**
* @file lpc177x_8x_clkpwr.c
* @brief Contains all functions support for Clock and Power Control
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_clkpwr.c
* @brief Contains all functions support for Clock and Power Control
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0;
*/
/*********************************************************************//**
* @brief Set value of each Peripheral Clock Selection
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @param[in] DivVal Value of divider. This value should be set as follows:
* - CPU clock: DivVal must be in range: 0..31
* - Peripheral clock: DivVal must be in range: 0..31
* - EMC clock: DivVal must be:
* + 0: The EMC uses the same clock as the CPU
* + 1: The EMC uses a clock at half the rate of the CPU
* - USB clock: DivVal must be:
* + 0: the divider is turned off, no clock will
* be provided to the USB subsystem
* + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
* + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @brief Set value of each Peripheral Clock Selection
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @param[in] DivVal Value of divider. This value should be set as follows:
* - CPU clock: DivVal must be in range: 0..31
* - Peripheral clock: DivVal must be in range: 0..31
* - EMC clock: DivVal must be:
* + 0: The EMC uses the same clock as the CPU
* + 1: The EMC uses a clock at half the rate of the CPU
* - USB clock: DivVal must be:
* + 0: the divider is turned off, no clock will
* be provided to the USB subsystem
* + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
* + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @return none
* Note: Pls assign right DivVal, this function will not check if it is illegal.
**********************************************************************/
void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
{
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
LPC_SC->CCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_PER:
LPC_SC->PCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_EMC:
LPC_SC->EMCCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_USB:
LPC_SC->USBCLKSEL &= ~(0x0000001F);
LPC_SC->USBCLKSEL |= DivVal;
break;
default:
while(1);//Error Loop;
}
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
LPC_SC->CCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_PER:
LPC_SC->PCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_EMC:
LPC_SC->EMCCLKSEL = DivVal;
SystemCoreClockUpdate(); //Update clock
break;
case CLKPWR_CLKTYPE_USB:
LPC_SC->USBCLKSEL &= ~(0x0000001F);
LPC_SC->USBCLKSEL |= DivVal;
break;
default:
while(1);//Error Loop;
}
}
/*********************************************************************//**
* @brief Get current clock value
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
* @brief Get current clock value
* @param[in] ClkType clock type that will be divided, should be:
* - CLKPWR_CLKTYPE_CPU : CPU clock
* - CLKPWR_CLKTYPE_PER : Peripheral clock
* - CLKPWR_CLKTYPE_EMC : EMC clock
* - CLKPWR_CLKTYPE_USB : USB clock
**********************************************************************/
uint32_t CLKPWR_GetCLK (uint8_t ClkType)
{
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
return SystemCoreClock;
switch(ClkType)
{
case CLKPWR_CLKTYPE_CPU:
return SystemCoreClock;
case CLKPWR_CLKTYPE_PER:
return PeripheralClock;
case CLKPWR_CLKTYPE_PER:
return PeripheralClock;
case CLKPWR_CLKTYPE_EMC:
return EMCClock;
case CLKPWR_CLKTYPE_EMC:
return EMCClock;
case CLKPWR_CLKTYPE_USB:
return USBClock;
case CLKPWR_CLKTYPE_USB:
return USBClock;
default:
while(1);//error loop
}
default:
while(1);//error loop
}
}
/*********************************************************************//**
* @brief Configure power supply for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
- CLKPWR_PCONP_PCTIM1 : Timer 1
- CLKPWR_PCONP_PCUART0 : UART 0
- CLKPWR_PCONP_PCUART1 : UART 1
- CLKPWR_PCONP_PCPWM0 : PWM 0
- CLKPWR_PCONP_PCPWM1 : PWM 1
- CLKPWR_PCONP_PCI2C0 : I2C 0
- CLKPWR_PCONP_PCUART4 : UART4
- CLKPWR_PCONP_PCRTC : RTC
- CLKPWR_PCONP_PCSSP1 : SSP 1
- CLKPWR_PCONP_PCEMC : EMC
- CLKPWR_PCONP_PCADC : ADC
- CLKPWR_PCONP_PCAN1 : CAN 1
- CLKPWR_PCONP_PCAN2 : CAN 2
- CLKPWR_PCONP_PCGPIO : GPIO
- CLKPWR_PCONP_PCMC : MCPWM
- CLKPWR_PCONP_PCQEI : QEI
- CLKPWR_PCONP_PCI2C1 : I2C 1
- CLKPWR_PCONP_PCSSP2 : SSP 2
- CLKPWR_PCONP_PCSSP0 : SSP 0
- CLKPWR_PCONP_PCTIM2 : Timer 2
- CLKPWR_PCONP_PCTIM3 : Timer 3
- CLKPWR_PCONP_PCUART2 : UART 2
- CLKPWR_PCONP_PCUART3 : UART 3
- CLKPWR_PCONP_PCI2C2 : I2C 2
- CLKPWR_PCONP_PCI2S : I2S
- CLKPWR_PCONP_PCSDC : SDC
- CLKPWR_PCONP_PCGPDMA : GPDMA
- CLKPWR_PCONP_PCENET : Ethernet
- CLKPWR_PCONP_PCUSB : USB
* @brief Configure power supply for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_PCONP_PCLCD : LCD
* - CLKPWR_PCONP_PCTIM0 : Timer 0
- CLKPWR_PCONP_PCTIM1 : Timer 1
- CLKPWR_PCONP_PCUART0 : UART 0
- CLKPWR_PCONP_PCUART1 : UART 1
- CLKPWR_PCONP_PCPWM0 : PWM 0
- CLKPWR_PCONP_PCPWM1 : PWM 1
- CLKPWR_PCONP_PCI2C0 : I2C 0
- CLKPWR_PCONP_PCUART4 : UART4
- CLKPWR_PCONP_PCRTC : RTC
- CLKPWR_PCONP_PCSSP1 : SSP 1
- CLKPWR_PCONP_PCEMC : EMC
- CLKPWR_PCONP_PCADC : ADC
- CLKPWR_PCONP_PCAN1 : CAN 1
- CLKPWR_PCONP_PCAN2 : CAN 2
- CLKPWR_PCONP_PCGPIO : GPIO
- CLKPWR_PCONP_PCMC : MCPWM
- CLKPWR_PCONP_PCQEI : QEI
- CLKPWR_PCONP_PCI2C1 : I2C 1
- CLKPWR_PCONP_PCSSP2 : SSP 2
- CLKPWR_PCONP_PCSSP0 : SSP 0
- CLKPWR_PCONP_PCTIM2 : Timer 2
- CLKPWR_PCONP_PCTIM3 : Timer 3
- CLKPWR_PCONP_PCUART2 : UART 2
- CLKPWR_PCONP_PCUART3 : UART 3
- CLKPWR_PCONP_PCI2C2 : I2C 2
- CLKPWR_PCONP_PCI2S : I2S
- CLKPWR_PCONP_PCSDC : SDC
- CLKPWR_PCONP_PCGPDMA : GPDMA
- CLKPWR_PCONP_PCENET : Ethernet
- CLKPWR_PCONP_PCUSB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
{
if (NewState == ENABLE)
{
LPC_SC->PCONP |= PPType;
}
else if (NewState == DISABLE)
{
LPC_SC->PCONP &= ~PPType;
}
if (NewState == ENABLE)
{
LPC_SC->PCONP |= PPType;
}
else if (NewState == DISABLE)
{
LPC_SC->PCONP &= ~PPType;
}
}
#if 0
// nxp21346
/*********************************************************************//**
* @brief Configure hardware reset for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_RSTCON0_LCD : LCD
* - CLKPWR_RSTCON0_TIM0 : Timer 0
- CLKPWR_RSTCON0_TIM1 : Timer 1
- CLKPWR_RSTCON0_UART0 : UART 0
- CLKPWR_RSTCON0_UART1 : UART 1
- CLKPWR_RSTCON0_PWM0 : PWM 0
- CLKPWR_RSTCON0_PWM1 : PWM 1
- CLKPWR_RSTCON0_I2C0 : I2C 0
- CLKPWR_RSTCON0_UART4 : UART 4
- CLKPWR_RSTCON0_RTC : RTC
- CLKPWR_RSTCON0_SSP1 : SSP 1
- CLKPWR_RSTCON0_EMC : EMC
- CLKPWR_RSTCON0_ADC : ADC
- CLKPWR_RSTCON0_CAN1 : CAN 1
- CLKPWR_RSTCON0_CAN2 : CAN 2
- CLKPWR_RSTCON0_GPIO : GPIO
- CLKPWR_RSTCON0_MCPWM : MCPWM
- CLKPWR_RSTCON0_QEI : QEI
- CLKPWR_RSTCON0_I2C1 : I2C 1
- CLKPWR_RSTCON0_SSP2 : SSP 2
- CLKPWR_RSTCON0_SSP0 : SSP 0
- CLKPWR_RSTCON0_TIM2 : Timer 2
- CLKPWR_RSTCON0_TIM3 : Timer 3
- CLKPWR_RSTCON0_UART2 : UART 2
- CLKPWR_RSTCON0_UART3 : UART 3
- CLKPWR_RSTCON0_I2C2 : I2C 2
- CLKPWR_RSTCON0_I2S : I2S
- CLKPWR_RSTCON0_SDC : SDC
- CLKPWR_RSTCON0_GPDMA : GPDMA
- CLKPWR_RSTCON0_ENET : Ethernet
- CLKPWR_RSTCON0_USB : USB
* @brief Configure hardware reset for each peripheral according to NewState
* @param[in] PPType Type of peripheral used to enable power,
* should be one of the following:
* - CLKPWR_RSTCON0_LCD : LCD
* - CLKPWR_RSTCON0_TIM0 : Timer 0
- CLKPWR_RSTCON0_TIM1 : Timer 1
- CLKPWR_RSTCON0_UART0 : UART 0
- CLKPWR_RSTCON0_UART1 : UART 1
- CLKPWR_RSTCON0_PWM0 : PWM 0
- CLKPWR_RSTCON0_PWM1 : PWM 1
- CLKPWR_RSTCON0_I2C0 : I2C 0
- CLKPWR_RSTCON0_UART4 : UART 4
- CLKPWR_RSTCON0_RTC : RTC
- CLKPWR_RSTCON0_SSP1 : SSP 1
- CLKPWR_RSTCON0_EMC : EMC
- CLKPWR_RSTCON0_ADC : ADC
- CLKPWR_RSTCON0_CAN1 : CAN 1
- CLKPWR_RSTCON0_CAN2 : CAN 2
- CLKPWR_RSTCON0_GPIO : GPIO
- CLKPWR_RSTCON0_MCPWM : MCPWM
- CLKPWR_RSTCON0_QEI : QEI
- CLKPWR_RSTCON0_I2C1 : I2C 1
- CLKPWR_RSTCON0_SSP2 : SSP 2
- CLKPWR_RSTCON0_SSP0 : SSP 0
- CLKPWR_RSTCON0_TIM2 : Timer 2
- CLKPWR_RSTCON0_TIM3 : Timer 3
- CLKPWR_RSTCON0_UART2 : UART 2
- CLKPWR_RSTCON0_UART3 : UART 3
- CLKPWR_RSTCON0_I2C2 : I2C 2
- CLKPWR_RSTCON0_I2S : I2S
- CLKPWR_RSTCON0_SDC : SDC
- CLKPWR_RSTCON0_GPDMA : GPDMA
- CLKPWR_RSTCON0_ENET : Ethernet
- CLKPWR_RSTCON0_USB : USB
*
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
* @param[in] NewState New state of Peripheral Power, should be:
* - ENABLE : Enable power for this peripheral
* - DISABLE : Disable power for this peripheral
*
* @return none
**********************************************************************/
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
{
if(PType < 32)
{
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
else
LPC_SC->RSTCON0 &=~(1<<PType);
}
else
{
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
if(PType < 32)
{
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
else
LPC_SC->RSTCON0 &=~(1<<PType);
}
else
{
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
}
// nxp21346
#endif
/*********************************************************************//**
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_Sleep(void)
{
LPC_SC->PCON = 0x00;
/* Sleep Mode*/
__WFI();
LPC_SC->PCON = 0x00;
/* Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepSleep(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x8;
/* Deep Sleep Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x8;
/* Deep Sleep Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_PowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x09;
/* Power Down Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x09;
/* Power Down Mode*/
__WFI();
}
/*********************************************************************//**
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in] None
* @return None
**********************************************************************/
void CLKPWR_DeepPowerDown(void)
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB->SCR = 0x4;
LPC_SC->PCON = 0x03;
/* Deep Power Down Mode*/
__WFI();
SCB->SCR = 0x4;
LPC_SC->PCON = 0x03;
/* Deep Power Down Mode*/
__WFI();
}
/**

172
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
View File

@ -1,14 +1,14 @@
/**********************************************************************
* $Id$ lpc177x_8x_clkpwr.h 2011-06-02
* $Id$ lpc177x_8x_clkpwr.h 2011-06-02
*//**
* @file lpc177x_8x_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on
* LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_clkpwr.h
* @brief Contains all macro definitions and function prototypes
* support for Clock and Power Control firmware library on
* LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -26,7 +26,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR Clock Power
/** @defgroup CLKPWR Clock Power
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@ -52,163 +52,163 @@ extern "C"
/********************************************************************
* Clock Source Selection Definitions
**********************************************************************/
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
/********************************************************************
* Clock type/domain Definitions (calculated from input and pre-configuration
* parameter(s)
**********************************************************************/
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
/** LCD controller power/clock control bit */
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
/** Timer/Counter 0 power/clock control bit */
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
/* Timer/Counter 1 power/clock control bit */
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
/** UART0 power/clock control bit */
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
/** UART1 power/clock control bit */
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
/** PWM0 power/clock control bit */
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
/** PWM1 power/clock control bit */
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
/** The I2C0 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
/** UART4 power/clock control bit */
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
/** The RTC power/clock control bit */
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
/** The SSP1 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
/** External Memory controller power/clock control bit */
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
/** A/D converter 0 (ADC0) power/clock control bit */
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
/** CAN Controller 1 power/clock control bit */
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
/** CAN Controller 2 power/clock control bit */
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
/** GPIO power/clock control bit */
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
/** Motor Control PWM */
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
/** Quadrature Encoder Interface power/clock control bit */
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
/** The I2C1 interface power/clock control bit */
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
/** The SSP2 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
/** The SSP0 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
/** Timer 2 power/clock control bit */
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
/** Timer 3 power/clock control bit */
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
/** UART 2 power/clock control bit */
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
/** UART 3 power/clock control bit */
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
/** I2C interface 2 power/clock control bit */
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
/** I2S interface power/clock control bit*/
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
/** SD card interface power/clock control bit */
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
/** GP DMA function power/clock control bit*/
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
/** Ethernet block power/clock control bit*/
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
/** USB interface power/clock control bit*/
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
/********************************************************************
* Power Control for Peripherals Definitions
**********************************************************************/
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
/**
* @}
*/
/* External clock variable from system_LPC177x_8x.h */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
/* External clock variable from lpc177x_8x_clkpwr.h */
extern uint32_t USBClock; /*!< USB Frequency */
extern uint32_t USBClock; /*!< USB Frequency */
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions

496
bsp/lpc178x/drivers/lpc177x_8x_emc.c
View File

@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_emc.c 2011-06-02
* $Id$ lpc177x_8x_emc.c 2011-06-02
*//**
* @file lpc177x_8x_emc.c
* @brief Contains all functions support for EMC firmware library
* on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_emc.c
* @brief Contains all functions support for EMC firmware library
* on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -30,23 +30,23 @@
/*********************************************************************//**
* @brief EMC initialize
* @param[in] None
* @return None
* @brief EMC initialize
* @param[in] None
* @return None
**********************************************************************/
void EMC_Init(void)
{
uint8_t i;
uint8_t i;
/* Enable clock for EMC */
// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
// LPC_EMC->Control = 0x00000001;
// LPC_EMC->Config = 0x00000000;
/* Enable clock for EMC */
// CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
// LPC_EMC->Control = 0x00000001;
// LPC_EMC->Config = 0x00000000;
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
LPC_EMC->Control = 0x00000001;
LPC_EMC->Config = 0x00000000;
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
LPC_EMC->Control = 0x00000001;
LPC_EMC->Config = 0x00000000;
/* Pin configuration:
* P2.14 - /EMC_CS2
@ -81,40 +81,40 @@ void EMC_Init(void)
* P4.30 - /EMC_CS0
* P4.31 - /EMC_CS1
*/
PINSEL_ConfigPin(2,14,1);
PINSEL_ConfigPin(2,15,1);
PINSEL_ConfigPin(2,16,1);
PINSEL_ConfigPin(2,17,1);
PINSEL_ConfigPin(2,18,1);
PINSEL_ConfigPin(2,19,1);
PINSEL_ConfigPin(2,20,1);
PINSEL_ConfigPin(2,21,1);
PINSEL_ConfigPin(2,22,1);
PINSEL_ConfigPin(2,23,1);
PINSEL_ConfigPin(2,24,1);
PINSEL_ConfigPin(2,25,1);
PINSEL_ConfigPin(2,26,1);
PINSEL_ConfigPin(2,27,1);
PINSEL_ConfigPin(2,28,1);
PINSEL_ConfigPin(2,29,1);
PINSEL_ConfigPin(2,30,1);
PINSEL_ConfigPin(2,31,1);
PINSEL_ConfigPin(2,14,1);
PINSEL_ConfigPin(2,15,1);
PINSEL_ConfigPin(2,16,1);
PINSEL_ConfigPin(2,17,1);
PINSEL_ConfigPin(2,18,1);
PINSEL_ConfigPin(2,19,1);
PINSEL_ConfigPin(2,20,1);
PINSEL_ConfigPin(2,21,1);
PINSEL_ConfigPin(2,22,1);
PINSEL_ConfigPin(2,23,1);
PINSEL_ConfigPin(2,24,1);
PINSEL_ConfigPin(2,25,1);
PINSEL_ConfigPin(2,26,1);
PINSEL_ConfigPin(2,27,1);
PINSEL_ConfigPin(2,28,1);
PINSEL_ConfigPin(2,29,1);
PINSEL_ConfigPin(2,30,1);
PINSEL_ConfigPin(2,31,1);
PINSEL_ConfigPin(5,0,1);
PINSEL_ConfigPin(5,1,1);
PINSEL_ConfigPin(5,0,1);
PINSEL_ConfigPin(5,1,1);
for(i = 0; i < 32; i++)
{
PINSEL_ConfigPin(3,i,1);
PINSEL_ConfigPin(4,i,1);
}
for(i = 0; i < 32; i++)
{
PINSEL_ConfigPin(3,i,1);
PINSEL_ConfigPin(4,i,1);
}
}
/*********************************************************************//**
* @brief Configure Little Endian/Big Endian mode for EMC
* @param[in] endia_mode Endian mode, should be:
* - EMC_LITTLE_ENDIAN_MODE: Little-endian mode
* - EMC_BIG_ENDIAN_MODE : Big-endian mode
* @return None
* @brief Configure Little Endian/Big Endian mode for EMC
* @param[in] endia_mode Endian mode, should be:
* - EMC_LITTLE_ENDIAN_MODE: Little-endian mode
* - EMC_BIG_ENDIAN_MODE : Big-endian mode
* @return None
**********************************************************************/
void EMC_ConfigEndianMode(uint32_t endian_mode)
{
@ -123,12 +123,12 @@ void EMC_ConfigEndianMode(uint32_t endian_mode)
/****************** Group of Dynamic control functions************************/
/*********************************************************************//**
* @brief Set the value for dynamic clock enable bit
* @param[in] clock_enable clock enable mode, should be:
* - 0: Clock enable of idle devices are deasserted to
* save power
* - 1: All clock enables are driven HIGH continuously
* @return None
* @brief Set the value for dynamic clock enable bit
* @param[in] clock_enable clock enable mode, should be:
* - 0: Clock enable of idle devices are deasserted to
* save power
* - 1: All clock enables are driven HIGH continuously
* @return None
**********************************************************************/
void EMC_DynCtrlClockEnable(uint32_t clock_enable)
{
@ -136,13 +136,13 @@ void EMC_DynCtrlClockEnable(uint32_t clock_enable)
}
/*********************************************************************//**
* @brief Set the value for dynamic memory clock control:
* stops or runs continuously
* @param[in] clock_control clock control mode, should be:
* - 0: CLKOUT stops when all SDRAMs are idle and
* during self-refresh mode
* - 1: CLKOUT runs continuously
* @return None
* @brief Set the value for dynamic memory clock control:
* stops or runs continuously
* @param[in] clock_control clock control mode, should be:
* - 0: CLKOUT stops when all SDRAMs are idle and
* during self-refresh mode
* - 1: CLKOUT runs continuously
* @return None
**********************************************************************/
void EMC_DynCtrlClockControl(int32_t clock_control)
{
@ -151,11 +151,11 @@ void EMC_DynCtrlClockControl(int32_t clock_control)
}
/*********************************************************************//**
* @brief Switch the Self-refresh mode between normal and self-refresh mode
* @param[in] self_refresh_mode self refresh mode, should be:
* - 0: Normal mode
* - 1: Enter self-refresh mode
* @return None
* @brief Switch the Self-refresh mode between normal and self-refresh mode
* @param[in] self_refresh_mode self refresh mode, should be:
* - 0: Normal mode
* - 1: Enter self-refresh mode
* @return None
**********************************************************************/
void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
{
@ -164,11 +164,11 @@ void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
}
/*********************************************************************//**
* @brief Enable/disable CLKOUT
* @param[in] MMC_val Memory clock control mode, should be:
* - 0: CLKOUT enabled
* - 1: CLKOUT disabled
* @return None
* @brief Enable/disable CLKOUT
* @param[in] MMC_val Memory clock control mode, should be:
* - 0: CLKOUT enabled
* - 1: CLKOUT disabled
* @return None
**********************************************************************/
void EMC_DynCtrlMMC(uint32_t MMC_val)
{
@ -177,13 +177,13 @@ void EMC_DynCtrlMMC(uint32_t MMC_val)
}
/*********************************************************************//**
* @brief Issue SDRAM command
* @param[in] SDRAM_command Command mode, should be:
* - 0x00: Issue SDRAM NORMAL operation command
* - 0x01: Issue SDRAM MODE command
* - 0x02: Issue SDRAM PALL (precharge all) command
* - 0x03: Issue SRAM NOP (no operation) command
* @return None
* @brief Issue SDRAM command
* @param[in] SDRAM_command Command mode, should be:
* - 0x00: Issue SDRAM NORMAL operation command
* - 0x01: Issue SDRAM MODE command
* - 0x02: Issue SDRAM PALL (precharge all) command
* - 0x03: Issue SRAM NOP (no operation) command
* @return None
**********************************************************************/
void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
{
@ -192,11 +192,11 @@ void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
}
/*********************************************************************//**
* @brief Switch between Normal operation and deep sleep power mode
* @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
* - 0: Normal operation
* - 1: Enter deep-sleep mode
* @return None
* @brief Switch between Normal operation and deep sleep power mode
* @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
* - 0: Normal operation
* - 1: Enter deep-sleep mode
* @return None
**********************************************************************/
void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
{
@ -205,22 +205,22 @@ void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
}
/*********************************************************************//**
* @brief Set the value of EMC dynamic memory registers
* @param[in] par EMC register that will set value, should be:
* - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
* - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
* - EMC_DYN_MEM_TRP: Dynamic RP register
* - EMC_DYN_MEM_TRAS: Dynamic RAS register
* - EMC_DYN_MEM_TSREX: Dynamic SREX register
* - EMC_DYN_MEM_TAPR: Dynamic APR register
* - EMC_DYN_MEM_TDAL: Dynamic DAL register
* - EMC_DYN_MEM_TWR: Dynamic WR register
* - EMC_DYN_MEM_TRC: Dynamic RC register
* - EMC_DYN_MEM_TRFC: Dynamic RFC register
* - EMC_DYN_MEM_TXSR: Dynamic XSR register
* - EMC_DYN_MEM_TRRD: Dynamic RRD register
* - EMC_DYN_MEM_TMRD: Dynamic MRD register
* @return None
* @brief Set the value of EMC dynamic memory registers
* @param[in] par EMC register that will set value, should be:
* - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
* - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
* - EMC_DYN_MEM_TRP: Dynamic RP register
* - EMC_DYN_MEM_TRAS: Dynamic RAS register
* - EMC_DYN_MEM_TSREX: Dynamic SREX register
* - EMC_DYN_MEM_TAPR: Dynamic APR register
* - EMC_DYN_MEM_TDAL: Dynamic DAL register
* - EMC_DYN_MEM_TWR: Dynamic WR register
* - EMC_DYN_MEM_TRC: Dynamic RC register
* - EMC_DYN_MEM_TRFC: Dynamic RFC register
* - EMC_DYN_MEM_TXSR: Dynamic XSR register
* - EMC_DYN_MEM_TRRD: Dynamic RRD register
* - EMC_DYN_MEM_TMRD: Dynamic MRD register
* @return None
**********************************************************************/
void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
{
@ -269,9 +269,9 @@ void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
}
/*********************************************************************//**
* @brief Set extended wait time out for accessing static memory
* @param[in] Extended_wait_time_out timeout value that will be set
* @return None
* @brief Set extended wait time out for accessing static memory
* @param[in] Extended_wait_time_out timeout value that will be set
* @return None
**********************************************************************/
void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
{
@ -279,13 +279,13 @@ void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
}
/*********************************************************************//**
* @brief Configure the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] mem_dev Memory device, should be:
* - 0x00: SDRAM
* - 0x01: Low-power SDRAM
* - 0x02: Micron Syncflash
* @return None
* @brief Configure the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] mem_dev Memory device, should be:
* - 0x00: SDRAM
* - 0x01: Low-power SDRAM
* - 0x02: Micron Syncflash
* @return None
**********************************************************************/
void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
{
@ -294,24 +294,24 @@ void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
{
case 0:
LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
break;
break;
case 1:
LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
break;
break;
case 2:
LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
break;
break;
case 3:
LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
break;
break;
}
}
/*********************************************************************//**
* @brief Map the address for the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] add_mapped address where the memory will be mapped
* @return None
* @brief Map the address for the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] add_mapped address where the memory will be mapped
* @return None
**********************************************************************/
void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
{
@ -321,26 +321,26 @@ void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
{
case 0:
LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped;
break;
break;
case 1:
LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped;
break;
break;
case 2:
LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped;
break;
break;
case 3:
LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped;
break;
break;
}
}
/*********************************************************************//**
* @brief Enable/disable the buffer
* @param[in] index index number, should be from 0 to 3
* @param[in] buff_control buffer control mode, should be:
* - ENABLE
* - DISABLE
* @return None
* @brief Enable/disable the buffer
* @param[in] index index number, should be from 0 to 3
* @param[in] buff_control buffer control mode, should be:
* - ENABLE
* - DISABLE
* @return None
**********************************************************************/
void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
{
@ -349,27 +349,27 @@ void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
{
case 0:
LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control;
break;
break;
case 1:
LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control;
break;
break;
case 2:
LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control;
break;
break;
case 3:
LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure write permission: protect or not
* @param[in] index index number, should be from 0 to 3
* @param[in] permission permission mode, should be:
* - ENABLE: protect
* - DISABLE: not protect
* @return None
* @brief Configure write permission: protect or not
* @param[in] index index number, should be from 0 to 3
* @param[in] permission permission mode, should be:
* - ENABLE: protect
* - DISABLE: not protect
* @return None
**********************************************************************/
void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
{
@ -378,24 +378,24 @@ void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
{
case 0:
LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission;
break;
break;
case 1:
LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission;
break;
break;
case 2:
LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission;
break;
break;
case 3:
LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission;
break;
break;
}
}
/*********************************************************************//**
* @brief Set value for RAS latency
* @param[in] index index number, should be from 0 to 3
* @param[in] ras_val RAS value should be in range: 0..3
* @return None
* @brief Set value for RAS latency
* @param[in] index index number, should be from 0 to 3
* @param[in] ras_val RAS value should be in range: 0..3
* @return None
**********************************************************************/
void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
{
@ -405,24 +405,24 @@ void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
{
case 0:
LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val;
break;
break;
case 1:
LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val;
break;
break;
case 2:
LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val;
break;
break;
case 3:
LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Set value for CAS latency
* @param[in] index index number, should be from 0 to 3
* @param[in] ras_val CAS value should be in range: 0..3
* @return None
* @brief Set value for CAS latency
* @param[in] index index number, should be from 0 to 3
* @param[in] ras_val CAS value should be in range: 0..3
* @return None
**********************************************************************/
void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
{
@ -431,26 +431,26 @@ void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
{
case 0:
LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
break;
break;
case 1:
LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
break;
break;
case 2:
LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
break;
break;
case 3:
LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the memory width
* @param[in] index index number, should be from 0 to 3
* @param[in] mem_width memory width, should be:
* - 0x00: 8-bits
* - 0x01: 16-bits
* - 0x02: 32-bits
* @return None
* @brief Configure the memory width
* @param[in] index index number, should be from 0 to 3
* @param[in] mem_width memory width, should be:
* - 0x00: 8-bits
* - 0x01: 16-bits
* - 0x02: 32-bits
* @return None
**********************************************************************/
void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
{
@ -459,25 +459,25 @@ void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the page mode
* @param[in] index index number, should be from 0 to 3
* @param[in] page_mode page mode, should be:
* - 0: disable
* - 1: asynchronous page mode enable
* @return None
* @brief Configure the page mode
* @param[in] index index number, should be from 0 to 3
* @param[in] page_mode page mode, should be:
* - 0: disable
* - 1: asynchronous page mode enable
* @return None
**********************************************************************/
void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
{
@ -486,25 +486,25 @@ void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| page_mode;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| page_mode;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the chip select polarity
* @param[in] index index number, should be from 0 to 3
* @param[in] pagepol_val_mode page mode, should be:
* - 0: Active LOW ship select
* - 1: Active HIGH chip select
* @return None
* @brief Configure the chip select polarity
* @param[in] index index number, should be from 0 to 3
* @param[in] pagepol_val_mode page mode, should be:
* - 0: Active LOW ship select
* - 1: Active HIGH chip select
* @return None
**********************************************************************/
void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
{
@ -513,26 +513,26 @@ void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pol_val;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the byte lane state
* @param[in] index index number, should be from 0 to 3
* @param[in] pb_val Byte lane state, should be:
* - 0: For reads all bits in BLSn[3:0] are HIGH.
* - 1: For reads all bits in BLSn[3:0] are LOW.
* @return None
* @brief Configure the byte lane state
* @param[in] index index number, should be from 0 to 3
* @param[in] pb_val Byte lane state, should be:
* - 0: For reads all bits in BLSn[3:0] are HIGH.
* - 1: For reads all bits in BLSn[3:0] are LOW.
* @return None
**********************************************************************/
void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
{
@ -541,26 +541,26 @@ void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)| pb_val;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)| pb_val;
break;
break;
case 2:
LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2 & mask)| pb_val;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)| pb_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the extended wait value
* @param[in] index index number, should be from 0 to 3
* @param[in] ex_wait Extended wait mode, should be:
* - 0: Extended wait disabled.
* - 1: Extended wait enabled.
* @return None
* @brief Configure the extended wait value
* @param[in] index index number, should be from 0 to 3
* @param[in] ex_wait Extended wait mode, should be:
* - 0: Extended wait disabled.
* - 1: Extended wait enabled.
* @return None
**********************************************************************/
void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
{
@ -569,26 +569,26 @@ void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait;
break;
break;
case 3:
LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the buffer enable value
* @param[in] index index number, should be from 0 to 3
* @param[in] buf_val Buffer mode, should be:
* - 0: Buffer disabled.
* - 1: Buffer enabled.
* @return None
* @brief Configure the buffer enable value
* @param[in] index index number, should be from 0 to 3
* @param[in] buf_val Buffer mode, should be:
* - 0: Buffer disabled.
* - 1: Buffer enabled.
* @return None
**********************************************************************/
void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
{
@ -597,26 +597,26 @@ void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Configure the write permission
* @param[in] index index number, should be from 0 to 3
* @param[in] per_val Permission mode, should be:
* - 0: Write not protected.
* - 1: Write protected.
* @return None
* @brief Configure the write permission
* @param[in] index index number, should be from 0 to 3
* @param[in] per_val Permission mode, should be:
* - 0: Write not protected.
* - 1: Write protected.
* @return None
**********************************************************************/
void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
{
@ -625,36 +625,36 @@ void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
{
case 0:
LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | per_val;
break;
break;
case 1:
LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | per_val;
break;
break;
case 2:
LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | per_val;
break;
break;
case 3:
LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | per_val;
break;
break;
}
}
/*********************************************************************//**
* @brief Set the value of LPC_EMC static memory registers
* @param[in] index index number, should be from 0 to 3
* @param[in] EMC_STA_MEM_PAR Static register, should be:
* - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
* - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
* - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
* - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
* - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
* - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
* @return None
* @brief Set the value of LPC_EMC static memory registers
* @param[in] index index number, should be from 0 to 3
* @param[in] EMC_STA_MEM_PAR Static register, should be:
* - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
* - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
* - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
* - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
* - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
* - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
* @return None
**********************************************************************/
void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val)
{
switch (index)
{
case 0:
case 0:
switch ( par)
{
case EMC_STA_MEM_WAITWEN:
@ -676,8 +676,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
LPC_EMC->StaticWaitTurn0 = val;
break;
}
break;
case 1:
break;
case 1:
switch ( par)
{
case EMC_STA_MEM_WAITWEN:
@ -699,8 +699,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
LPC_EMC->StaticWaitTurn1 = val;
break;
}
break;
case 2:
break;
case 2:
switch ( par)
{
case EMC_STA_MEM_WAITWEN:
@ -722,8 +722,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
LPC_EMC->StaticWaitTurn2 = val;
break;
}
break;
case 3:
break;
case 3:
switch ( par)
{
case EMC_STA_MEM_WAITWEN:
@ -745,7 +745,7 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
LPC_EMC->StaticWaitTurn3 = val;
break;
}
break;
break;
}
}

142
bsp/lpc178x/drivers/lpc177x_8x_emc.h
View File

@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_emc.h 2011-06-02
* $Id$ lpc177x_8x_emc.h 2011-06-02
*//**
* @file lpc177x_8x_emc.h
* @brief Contains all macro definitions and function prototypes
* support for EMC firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_emc.h
* @brief Contains all macro definitions and function prototypes
* support for EMC firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -25,7 +25,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMC EMC (External Memory Controller)
/** @defgroup EMC EMC (External Memory Controller)
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@ -45,233 +45,233 @@
* EMC Control Register (EMCControl)
**********************************************************************/
/* Control register mask */
#define EMC_Control_MASK ((uint32_t )0x07)
#define EMC_Control_MASK ((uint32_t )0x07)
/* Control register EMC: Enable control. */
#define EMC_Control_E ((uint32_t )(1<<0))
#define EMC_Control_E ((uint32_t )(1<<0))
/* Control register EMC: Address mirror control. */
#define EMC_Control_M ((uint32_t )(1<<1))
#define EMC_Control_M ((uint32_t )(1<<1))
/* Control register EMC: Low-power mode control. */
#define EMC_Control_L ((uint32_t )(1<<2))
#define EMC_Control_L ((uint32_t )(1<<2))
/***********************************************************************
* EMC Status Register (EMCStatus)
**********************************************************************/
/* Status register mask */
#define EMC_Status_MASK ((uint32_t )0x07)
#define EMC_Status_MASK ((uint32_t )0x07)
/* Status register EMC: Busy. */
#define EMC_Status_B ((uint32_t )(1<<0))
#define EMC_Status_B ((uint32_t )(1<<0))
/* Status register EMC: Write buffer status. */
#define EMC_Status_S ((uint32_t )(1<<1))
#define EMC_Status_S ((uint32_t )(1<<1))
/* Status register EMC: Self-refresh acknowledge.. */
#define EMC_Status_SA ((uint32_t )(1<<2))
#define EMC_Status_SA ((uint32_t )(1<<2))
/***********************************************************************
* EMC Configuration register (EMCConfig)
**********************************************************************/
/* EMC Configuration register : Enable control. */
#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
#define EMC_Config_Endian_Mode ((uint32_t )(1<<0))
/* EMC Configuration register: CCLK. */
#define EMC_Config_CCLK ((uinr32_t)(1<<8))
#define EMC_Config_CCLK ((uinr32_t)(1<<8))
/* EMC Configuration register mask */
#define EMC_Config_MASK ((uint32_t)(0x101))
#define EMC_Config_MASK ((uint32_t)(0x101))
/***********************************************************************
* Dynamic Memory Control register (EMCDynamicControl)
**********************************************************************/
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
#define EMC_DynamicControl_CE ((uint32_t )(1<<0))
/* Dynamic Memory Control register EMC: Dynamic memory clock control */
#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
#define EMC_DynamicControl_CS ((uint32_t )(1<<1))
/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
#define EMC_DynamicControl_SR ((uint32_t )(1<<2))
/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
#define EMC_DynamicControl_MMC ((uint32_t )(1<<5))
/* Dynamic Memory Control register EMC: SDRAM initialization*/
#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
#define EMC_DynamicControl_I(n) ((uint32_t )(n<<7))
/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
#define EMC_DynamicControl_DP ((uint32_t ) (1<<13))
/***********************************************************************
* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
**********************************************************************/
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
#define EMC_DynamicRefresh_REFRESH(n) ((uint32_t ) (n & 0x3ff))
/***********************************************************************
* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
**********************************************************************/
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
#define EMC_DynamicReadConfig_RD(n) ((uint32_t )(n & 0x03))
/***********************************************************************
* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
**********************************************************************/
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRP(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
**********************************************************************/
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRAS(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
**********************************************************************/
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictAPR_tAPR(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
**********************************************************************/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictDAL_tDAL(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
**********************************************************************/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
#define EMC_DynamictWR_tWR(n) (uint32_t )(n & 0x0f)
/***********************************************************************
* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
**********************************************************************/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
#define EMC_DynamictRC_tRC(n) (uint32_t )(n & 0x1f)
/***********************************************************************
* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
**********************************************************************/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictRFC_tRFC(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
**********************************************************************/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictXSR_tXSR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
**********************************************************************/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
#define EMC_DynamictRRD_tRRD(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
**********************************************************************/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
#define EMC_DynamictMRD_tMRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Extended Wait Register (EMCStaticExtendedWait)
**********************************************************************/
/* StaticExtendedWait register EMC: External wait time out. */
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n) ((uint32_t )(n & 0x3ff))
/***********************************************************************
* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
**********************************************************************/
/* DynamicConfig register EMC: Memory device (MD). */
#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
#define EMC_DynamicConfig_MD(n) ((uint32_t )(n << 3))
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
#define EMC_DynamicConfig_AM1(n) ((uint32_t )(n << 7))
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
#define EMC_DynamicConfig_AM2(n) ((uint32_t )(1 << 14))
/* DynamicConfig register EMC: Buffer enable */
#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
#define EMC_DynamicConfig_B ((uint32_t )(1 << 19))
/* DynamicConfig register EMC: Write protect (P) */
#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
#define EMC_DynamicConfig_P ((uint32_t )(1 << 20))
/***********************************************************************
* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
**********************************************************************/
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
#define EMC_DynamicConfig_RAS(n) ((uint32_t )(n & 0x03))
/* DynamicRASCAS register EMC: CAS latency (CAS)*/
#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
#define EMC_DynamicConfig_CAS(n) ((uint32_t )(n << 8))
/***********************************************************************
* Static Memory Configuration registers (EMCStaticConfig0-3)
**********************************************************************/
/* StaticConfig register EMC: Memory width (MW). */
#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
#define EMC_StaticConfig_MW(n) ((uint32_t )(n & 0x03))
/* StaticConfig register EMC: Memory width 8bit . */
#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
#define EMC_StaticConfig_MW_8BITS (EMC_StaticConfig_MW(0))
/* StaticConfig register EMC: Memory width 16bit . */
#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
#define EMC_StaticConfig_MW_16BITS (EMC_StaticConfig_MW(1))
/* StaticConfig register EMC: Memory width 32bit . */
#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
#define EMC_StaticConfig_MW_32BITS (EMC_StaticConfig_MW(2))
/* StaticConfig register EMC: Page mode (PM) */
#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
#define EMC_StaticConfig_PM ((uint32_t )(1 << 3))
/* StaticConfig register EMC: Chip select polarity (PC) */
#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
#define EMC_StaticConfig_PC ((uint32_t )(1 << 6))
/* StaticConfig register EMC: Byte lane state (PB) */
#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
#define EMC_StaticConfig_PB ((uint32_t )(1 << 7))
/* StaticConfig register EMC: Extended wait (EW) */
#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
#define EMC_StaticConfig_EW ((uint32_t )(1 << 8))
/* StaticConfig register EMC: Buffer enable (B) */
#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
#define EMC_StaticConfig_B ((uint32_t )(1 << 19))
/* StaticConfig register EMC: Write protect (P) */
#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
#define EMC_StaticConfig_P ((uint32_t )(1 << 20))
/***********************************************************************
* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
**********************************************************************/
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitWen_WAITWEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
**********************************************************************/
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitOen_WAITOEN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
**********************************************************************/
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
read first access wait state (WAITRD) */
#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticWaitRd_WAITRD(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
**********************************************************************/
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
read wait states (WAITPAGE). */
#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticwaitPage_WAITPAGE(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
**********************************************************************/
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
#define EMC_StaticWaitwr_WAITWR(n) ((uint32_t )(n & 0x1f))
/***********************************************************************
* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
**********************************************************************/
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
#define EMC_StaticWaitTurn_WAITTURN(n) ((uint32_t )(n & 0x0f))
/***********************************************************************
* Delay Control register (EMCDLYCTL)
**********************************************************************/
#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
#define EMC_DLYCTL_CMDDLY(n) ((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n) ((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n) ((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n) ((uint32_t)((n&0x1F)<<24))
/***********************************************************************
* EMC Calibration register (EMCCAL)
**********************************************************************/
#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
#define EMC_CAL_START ((uint32_t)(1<<14))
#define EMC_CAL_DONE ((uint32_t)(1<<15))
#define EMC_CAL_CALVALUE(n) ((uint32_t)(n&0xFF))
#define EMC_CAL_START ((uint32_t)(1<<14))
#define EMC_CAL_DONE ((uint32_t)(1<<15))
#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
#define EMC_LITTLE_ENDIAN_MODE ((uint32_t)(0))
#define EMC_BIG_ENDIAN_MODE ((uint32_t)(1))
/**
* @}

418
bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
View File

@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_pinsel.c 2011-06-02
* $Id$ lpc177x_8x_pinsel.c 2011-06-02
*//**
* @file lpc177x_8x_pinsel.c
* @brief Contains all functions support for Pin-connection block
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_pinsel.c
* @brief Contains all functions support for Pin-connection block
* firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -32,39 +32,39 @@
/* Includes ------------------------------------------------------------------- */
#include "lpc177x_8x_pinsel.h"
#define PINSEL_I2C_MODE_POS (8)
#define PINSEL_I2C_MODE_NUMBITS (2)
#define PINSEL_I2C_MODE_BITMASK (0x03)
#define PINSEL_I2C_MODE_POS (8)
#define PINSEL_I2C_MODE_NUMBITS (2)
#define PINSEL_I2C_MODE_BITMASK (0x03)
#define PINSEL_BASIC_MODE_POS (3)
#define PINSEL_BASIC_MODE_NUMBITS (2)
#define PINSEL_BASIC_MODE_BITMASK (0x03)
#define PINSEL_BASIC_MODE_POS (3)
#define PINSEL_BASIC_MODE_NUMBITS (2)
#define PINSEL_BASIC_MODE_BITMASK (0x03)
#define PINSEL_DACEN_POS (16)
#define PINSEL_DACEN_BITMASK (0x01)
#define PINSEL_DACEN_NUMBITS (1)
#define PINSEL_DACEN_POS (16)
#define PINSEL_DACEN_BITMASK (0x01)
#define PINSEL_DACEN_NUMBITS (1)
#define PINSEL_GLITCH_FILTER_POS (8)
#define PINSEL_GLITCH_FILTER_BITMASK (0x01)
#define PINSEL_GLITCH_FILTER_NUMBITS (1)
#define PINSEL_GLITCH_FILTER_POS (8)
#define PINSEL_GLITCH_FILTER_BITMASK (0x01)
#define PINSEL_GLITCH_FILTER_NUMBITS (1)
#define PINSEL_ADMODE_POS (7)
#define PINSEL_ADMODE_BITMASK (0x01)
#define PINSEL_ADMODE_NUMBITS (1)
#define PINSEL_ADMODE_POS (7)
#define PINSEL_ADMODE_BITMASK (0x01)
#define PINSEL_ADMODE_NUMBITS (1)
/* Private Functions ---------------------------------------------------------- */
/*********************************************************************//**
* @brief Get pointer to GPIO peripheral due to GPIO port
* @param[in] portnum Port Number value, should be in range from 0..3.
* @param[in] pinnum Pin number value, should be in range from 0..31
* @return Pointer to GPIO peripheral
* @brief Get pointer to GPIO peripheral due to GPIO port
* @param[in] portnum Port Number value, should be in range from 0..3.
* @param[in] pinnum Pin number value, should be in range from 0..31
* @return Pointer to GPIO peripheral
**********************************************************************/
static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
{
uint32_t *pPIN = NULL;
pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
return pPIN;
uint32_t *pPIN = NULL;
pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
return pPIN;
}
/* Public Functions ----------------------------------------------------------- */
@ -73,268 +73,268 @@ static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
*/
/*********************************************************************//**
* @brief Setup the pin selection function
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] funcnum Function number, should be range: 0..7
* - 0: Select GPIO (Default)
* - 1: Selects the 1st alternate function
* - 2: Selects the 2nd alternate function
* ...
* - 7: Selects the 7th alternate function
* @return None
* @brief Setup the pin selection function
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] funcnum Function number, should be range: 0..7
* - 0: Select GPIO (Default)
* - 1: Selects the 1st alternate function
* - 2: Selects the 2nd alternate function
* ...
* - 7: Selects the 7th alternate function
* @return None
**********************************************************************/
void PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
*pPIN &= 0x00000007;//Clear function bits
*pPIN |= funcnum;
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
*pPIN &= 0x00000007;//Clear function bits
*pPIN |= funcnum;
}
/*********************************************************************//**
* @brief Setup resistor mode for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] modenum: Mode number, should be in range: 0..3
- IOCON_MODE_PLAIN: Plain output
- IOCON_MODE_PULLDOWN: Pull-down enable
- IOCON_MODE_PULLUP: Pull-up enable
- IOCON_MODE_REPEATER: Repeater mode
* @return None
* @brief Setup resistor mode for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] modenum: Mode number, should be in range: 0..3
- IOCON_MODE_PLAIN: Plain output
- IOCON_MODE_PULLDOWN: Pull-down enable
- IOCON_MODE_PULLUP: Pull-up enable
- IOCON_MODE_REPEATER: Repeater mode
* @return None
**********************************************************************/
void PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
*(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
*(uint32_t *)pPIN |= modenum;
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
*(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
*(uint32_t *)pPIN |= modenum;
}
/*********************************************************************//**
* @brief Setup hysteresis for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Hysteresis mode, should be:
* - ENABLE: Hysteresis enable
* - DISABLE: Hysteresis disable
* @return None
* @brief Setup hysteresis for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Hysteresis mode, should be:
* - ENABLE: Hysteresis enable
* - DISABLE: Hysteresis disable
* @return None
**********************************************************************/
void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_HYS;
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_HYS;
}
/*********************************************************************//**
* @brief Setup Slew rate for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Slew rate control, should be:
* - ENABLE: Output slew rate control is enable
* - DISABLE: Output slew rate control is disable
* @return None
* @brief Setup Slew rate for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Slew rate control, should be:
* - ENABLE: Output slew rate control is enable
* - DISABLE: Output slew rate control is disable
* @return None
**********************************************************************/
void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_SLEW;
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_SLEW;
}
/*********************************************************************//**
* @brief Setup Input Buffer for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Input buffer mode, should be:
* - ENABLE: The input buffer is enable
* - DISABLE: The input buffer is disable
* @return None
* @brief Setup Input Buffer for each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Input buffer mode, should be:
* - ENABLE: The input buffer is enable
* - DISABLE: The input buffer is disable
* @return None
**********************************************************************/
void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_INBUF;
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
}
else
*(uint32_t *)pPIN |= IOCON_INBUF;
}
/*********************************************************************//**
* @brief Setup I2CMode for only pins that provide special I2C functionality
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] I2CMode I2C mode, should be:
* - IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
* - IOCON_I2CMODE_OPENDRAIN: Open drain I/O
* - IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
* - IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
* @return None
* @brief Setup I2CMode for only pins that provide special I2C functionality
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] I2CMode I2C mode, should be:
* - IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
* - IOCON_I2CMODE_OPENDRAIN: Open drain I/O
* - IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
* - IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
* @return None
**********************************************************************/
void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
*(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
*(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
*(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
*(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
}
/*********************************************************************//**
* @brief Setup Open-drain mode in each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Open-drain mode:
* - DISABLE: Normal pin I/O mode
* - ENABLE: Open-drain enable
* @return None
* @brief Setup Open-drain mode in each pin
* @param[in] portnum Port number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] NewState new state of Open-drain mode:
* - DISABLE: Normal pin I/O mode
* - ENABLE: Open-drain enable
* @return None
**********************************************************************/
void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
{
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
}
else
{
*(uint32_t *)pPIN |= IOCON_ODMODE;
}
uint32_t *pPIN = NULL;
pPIN = PIN_GetPointer(portnum, pinnum);
if(NewState == DISABLE)
{
*(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
}
else
{
*(uint32_t *)pPIN |= IOCON_ODMODE;
}
}
/*********************************************************************//**
* @brief Enable the Analog mode for each pin (default is as Digital pins)
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return None
* @brief Enable the Analog mode for each pin (default is as Digital pins)
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return None
**********************************************************************/
void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
uint32_t *pPIN = NULL;
uint8_t condition = 0;
uint8_t condition = 0;
condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
| ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
| ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
| ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
| ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
if(!condition)
{
return;
}
if(!condition)
{
return;
}
pPIN = PIN_GetPointer(portnum, pinnum);
pPIN = PIN_GetPointer(portnum, pinnum);
//Clear this bit to set the pin to Analog mode
*(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
//Clear this bit to set the pin to Analog mode
*(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
if(enable)
{
if(enable)
{
}
else
{
*(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
}
}
else
{
*(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
}
return;
return;
}
/*********************************************************************//**
* @brief Choose the DAC mode for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return None
* @brief Choose the DAC mode for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: Enable the DAC mode of the pin
- DISABLE: Disable the DAC mode
* @return None
**********************************************************************/
void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
uint32_t *pPIN = NULL;
// This setting is only for DAC pin (output pin)
if(!((portnum == 0) && (pinnum == 26)))
{
return;
}
// This setting is only for DAC pin (output pin)
if(!((portnum == 0) && (pinnum == 26)))
{
return;
}
pPIN = PIN_GetPointer(portnum, pinnum);
pPIN = PIN_GetPointer(portnum, pinnum);
//Clear DAC Enable function bits
*(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
//Clear DAC Enable function bits
*(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
if(enable)
{
*(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
}
else
{
if(enable)
{
*(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
}
else
{
}
}
return;
return;
}
/*********************************************************************//**
* @brief Control the glitch filter for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: The noise pulses below approximately 10ns are filtered out
- DISABLE: No input filtering is done.
* @return None
* @brief Control the glitch filter for each pin
* @param[in] portnum PORT number, should be in range: 0..3
* @param[in] pinnum Pin number, should be in range: 0..31
* @param[in] enable: the state of the pin that is expected to run
- ENABLE: The noise pulses below approximately 10ns are filtered out
- DISABLE: No input filtering is done.
* @return None
**********************************************************************/
void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
{
uint32_t *pPIN = NULL;
uint32_t *pPIN = NULL;
// This setting is only for DAC pin (output pin)
if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
{
return;
}
// This setting is only for DAC pin (output pin)
if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
{
return;
}
pPIN = PIN_GetPointer(portnum, pinnum);
pPIN = PIN_GetPointer(portnum, pinnum);
*(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
*(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
//Clear Filter bits
*(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
//Clear Filter bits
*(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
if(!enable)
{
*(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
}
else
{
if(!enable)
{
*(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
}
else
{
}
}
*pPIN = *pPIN;
*pPIN = *pPIN;
return;
return;
}
/**

348
bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
View File

@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_pinsel.h 2011-06-02
* $Id$ lpc177x_8x_pinsel.h 2011-06-02
*//**
* @file lpc177x_8x_pinsel.h
* @brief Contains all macro definitions and function prototypes
* support for Pin-connection block firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_pinsel.h
* @brief Contains all macro definitions and function prototypes
* support for Pin-connection block firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -25,7 +25,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup PINSEL Pin Selection
/** @defgroup PINSEL Pin Selection
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@ -44,160 +44,160 @@
*/
/* Macros define IOCON bits */
#define IOCON_MODE_PLAIN ((0<<3))
#define IOCON_MODE_PULLDOWN ((1<<3))
#define IOCON_MODE_PULLUP ((2<<3))
#define IOCON_MODE_REPEATER ((3<<3))
#define IOCON_HYS ((1<<5))
#define IOCON_SLEW ((1<<6))
#define IOCON_INBUF ((1<<7))
#define IOCON_I2CMODE_FAST ((0<<8))
#define IOCON_I2CMODE_OPENDRAIN ((1<<8))
#define IOCON_I2CMODE_FASTPLUS ((2<<8))
#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8))
#define IOCON_ODMODE ((1<<10))
#define IOCON_MODE_PLAIN ((0<<3))
#define IOCON_MODE_PULLDOWN ((1<<3))
#define IOCON_MODE_PULLUP ((2<<3))
#define IOCON_MODE_REPEATER ((3<<3))
#define IOCON_HYS ((1<<5))
#define IOCON_SLEW ((1<<6))
#define IOCON_INBUF ((1<<7))
#define IOCON_I2CMODE_FAST ((0<<8))
#define IOCON_I2CMODE_OPENDRAIN ((1<<8))
#define IOCON_I2CMODE_FASTPLUS ((2<<8))
#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8))
#define IOCON_ODMODE ((1<<10))
/* Macros define for LOC registers */
#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */
#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */
#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */
#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */
#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */
#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */
#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */
#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */
#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */
#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */
#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */
#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */
#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */
#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */
#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */
#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */
#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */
#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */
#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */
#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */
#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */
#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */
#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */
#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */
#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */
#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */
#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */
#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */
#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */
#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */
#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */
#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */
#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */
#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */
#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */
#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */
#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */
#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */
#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */
#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */
#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */
#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */
#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */
#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */
#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */
#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */
#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */
#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */
#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */
#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */
#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */
#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */
#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */
#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */
#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */
#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */
#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */
#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */
#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */
#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */
#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */
#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */
#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */
#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */
#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */
#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */
#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */
#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */
#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */
#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */
#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */
#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */
#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */
#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */
#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */
#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */
#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */
#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */
#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */
#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */
#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */
#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */
#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */
#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */
#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */
#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */
#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */
#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */
#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */
#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */
#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */
#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */
#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */
#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */
#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */
#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */
#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */
#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */
#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */
#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */
#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */
#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */
#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */
#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */
#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */
#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */
#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */
#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */
#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */
#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */
#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */
#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */
#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */
#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */
#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */
#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */
#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */
#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */
#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */
#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */
#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */
#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */
#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */
#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */
#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */
#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */
#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */
#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */
#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */
#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */
#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */
#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */
#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */
#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */
#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */
#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */
#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */
#define LOC_CAN_RD_1_P0_0 ((0)) /**< Input for CAN_RD_1 comes from P0.0 */
#define LOC_CAN_RD_1_P0_21 ((1)) /**< Input for CAN_RD_1 comes from P0.21 */
#define LOC_CAN_RD_2_P2_7 ((0)) /**< Input for CAN_RD_2 comes from P2.7 */
#define LOC_CAN_RD_2_P0_4 ((1)) /**< Input for CAN_RD_2 comes from P0.4 */
#define LOC_ENET_MDIO_P2_9 ((0)) /**< Input for ENET_MDIO comes from P2.9 */
#define LOC_ENET_MDIO_P1_17 ((1)) /**< Input for ENET_MDIO comes from P1.17 */
#define LOC_EINT_0_P0_29 ((0)) /**< Input for EINT_0 comes from P0.29 */
#define LOC_EINT_0_P2_10 ((1)) /**< Input for EINT_0 comes from P2.10 */
#define LOC_EINT_1_P0_30 ((0)) /**< Input for EINT_1 comes from P0.30 */
#define LOC_EINT_1_P2_11 ((1)) /**< Input for EINT_1 comes from P2.11 */
#define LOC_I2C0_SCL_P1_31 ((0)) /**< Input for I2C0_SCL comes from P1.31 */
#define LOC_I2C0_SCL_P0_28 ((1)) /**< Input for I2C0_SCL comes from P0.28 */
#define LOC_I2C0_SCL_P5_3 ((2)) /**< Input for I2C0_SCL comes from P5.3 */
#define LOC_I2C0_SDA_P1_30 ((0)) /**< Input for I2C0_SDA comes from P1.30 */
#define LOC_I2C0_SDA_P0_27 ((1)) /**< Input for I2C0_SDA comes from P0.27 */
#define LOC_I2C0_SDA_P5_2 ((2)) /**< Input for I2C0_SDA comes from P5.2 */
#define LOC_I2C1_SCL_P0_1 ((0)) /**< Input for I2C1_SCL comes from P0.1 */
#define LOC_I2C1_SCL_P2_15 ((1)) /**< Input for I2C1_SCL comes from P2.15 */
#define LOC_I2C1_SCL_P0_20 ((2)) /**< Input for I2C1_SCL comes from P0.20 */
#define LOC_I2C1_SDA_P2_14 ((0)) /**< Input for I2C1_SDA comes from P2.14 */
#define LOC_I2C1_SDA_P0_0 ((1)) /**< Input for I2C1_SDA comes from P0.0 */
#define LOC_I2C1_SDA_P0_19 ((2)) /**< Input for I2C1_SDA comes from P0.19 */
#define LOC_I2C2_SCL_P2_31 ((0)) /**< Input for I2C2_SCL comes from P2.31 */
#define LOC_I2C2_SCL_P0_11 ((1)) /**< Input for I2C2_SCL comes from P0.11 */
#define LOC_I2C2_SCL_P4_21 ((2)) /**< Input for I2C2_SCL comes from P4.21 */
#define LOC_I2C2_SCL_P4_29 ((3)) /**< Input for I2C2_SCL comes from P4.29 */
#define LOC_I2C2_SDA_P2_30 ((0)) /**< Input for I2C2_SDA comes from P2.30 */
#define LOC_I2C2_SDA_P0_10 ((1)) /**< Input for I2C2_SDA comes from P0.10 */
#define LOC_I2C2_SDA_P4_20 ((2)) /**< Input for I2C2_SDA comes from P4.20 */
#define LOC_I2C2_SDA_P1_15 ((3)) /**< Input for I2C2_SDA comes from P1.15 */
#define LOC_I2S_RX_SCK_P0_23 ((0)) /**< Input for I2S_RX_SCK comes from P0.23 */
#define LOC_I2S_RX_SCK_P0_4 ((1)) /**< Input for I2S_RX_SCK comes from P0.4 */
#define LOC_I2S_RX_SDA_P0_25 ((0)) /**< Input for I2S_RX_SDA comes from P0.25 */
#define LOC_I2S_RX_SDA_P0_6 ((1)) /**< Input for I2S_RX_SDA comes from P0.6 */
#define LOC_I2S_RX_WS_P0_24 ((0)) /**< Input for I2S_RX_WS comes from P0.24 */
#define LOC_I2S_RX_WS_P0_5 ((1)) /**< Input for I2S_RX_WS comes from P0.5 */
#define LOC_I2S_TX_SCK_P2_11 ((0)) /**< Input for I2S_TX_SCK comes from P2.11 */
#define LOC_I2S_TX_SCK_P0_7 ((1)) /**< Input for I2S_TX_SCK comes from P0.7 */
#define LOC_I2S_TX_WS_P2_12 ((0)) /**< Input for I2S_TX_WS comes from P2.12 */
#define LOC_I2S_TX_WS_P0_8 ((1)) /**< Input for I2S_TX_WS comes from P0.8 */
#define LOC_PWM0_CAP_0_P1_12 ((0)) /**< Input for PWM0_CAP_0 comes from P1.12 */
#define LOC_PWM0_CAP_0_P3_22 ((1)) /**< Input for PWM0_CAP_0 comes from P3.22 */
#define LOC_PWM1_CAP_0_P3_23 ((0)) /**< Input for PWM1_CAP_0 comes from P3.23 */
#define LOC_PWM1_CAP_0_P1_28 ((1)) /**< Input for PWM1_CAP_0 comes from P1.28 */
#define LOC_PWM1_CAP_0_P2_6 ((2)) /**< Input for PWM1_CAP_0 comes from P2.6 */
#define LOC_SD_CMD_P0_20 ((0)) /**< Input for SD_CMD comes from P0.20 */
#define LOC_SD_CMD_P1_3 ((1)) /**< Input for SD_CMD comes from P1.3 */
#define LOC_SD_DAT_0_P0_22 ((0)) /**< Input for SD_DAT_0 comes from P0.22 */
#define LOC_SD_DAT_0_P1_6 ((1)) /**< Input for SD_DAT_0 comes from P1.6 */
#define LOC_SD_DAT_1_P2_11 ((0)) /**< Input for SD_DAT_1 comes from P2.11 */
#define LOC_SD_DAT_1_P1_7 ((1)) /**< Input for SD_DAT_1 comes from P1.7 */
#define LOC_SD_DAT_2_P2_12 ((0)) /**< Input for SD_DAT_2 comes from P2.12 */
#define LOC_SD_DAT_2_P1_11 ((1)) /**< Input for SD_DAT_2 comes from P1.11 */
#define LOC_SD_DAT_3_P2_13 ((0)) /**< Input for SD_DAT_3 comes from P2.13 */
#define LOC_SD_DAT_3_P1_12 ((1)) /**< Input for SD_DAT_3 comes from P1.12 */
#define LOC_SSP0_MISO_P2_26 ((0)) /**< Input for SSP0_MISO comes from P2.26 */
#define LOC_SSP0_MISO_P1_23 ((1)) /**< Input for SSP0_MISO comes from P1_23 */
#define LOC_SSP0_MISO_P0_17 ((2)) /**< Input for SSP0_MISO comes from P0_17 */
#define LOC_SSP0_MOSI_P2_27 ((0)) /**< Input for SSP0_MOSI comes from P2.27 */
#define LOC_SSP0_MOSI_P1_24 ((1)) /**< Input for SSP0_MOSI comes from P1.24 */
#define LOC_SSP0_MOSI_P0_18 ((2)) /**< Input for SSP0_MOSI comes from P0.18 */
#define LOC_SSP0_SCK_P1_20 ((0)) /**< Input for SSP0_SCK comes from P1.20 */
#define LOC_SSP0_SCK_P2_22 ((1)) /**< Input for SSP0_SCK comes from P2.22 */
#define LOC_SSP0_SCK_P0_15 ((2)) /**< Input for SSP0_SCK comes from P0_15 */
#define LOC_SSP0_SSEL_P2_23 ((0)) /**< Input for SSP0_SSEL comes from P2.23 */
#define LOC_SSP0_SSEL_P1_21 ((1)) /**< Input for SSP0_SSEL comes from P1.21 */
#define LOC_SSP0_SSEL_P1_28 ((2)) /**< Input for SSP0_SSEL comes from P1.28 */
#define LOC_SSP0_SSEL_P0_16 ((3)) /**< Input for SSP0_SSEL comes from P0.16 */
#define LOC_SSP1_MISO_P0_12 ((0)) /**< Input for SSP1_MISO comes from P0.12 */
#define LOC_SSP1_MISO_P1_18 ((1)) /**< Input for SSP1_MISO comes from P1.18 */
#define LOC_SSP1_MISO_P4_22 ((2)) /**< Input for SSP1_MISO comes from P4_22 */
#define LOC_SSP1_MISO_P0_8 ((3)) /**< Input for SSP1_MISO comes from P0.8 */
#define LOC_SSP1_MOSI_P0_13 ((0)) /**< Input for SSP1_MOSI comes from P0.13 */
#define LOC_SSP1_MOSI_P1_22 ((1)) /**< Input for SSP1_MOSI comes from P1.22 */
#define LOC_SSP1_MOSI_P4_23 ((2)) /**< Input for SSP1_MOSI comes from P4.23 */
#define LOC_SSP1_MOSI_P0_9 ((3)) /**< Input for SSP1_MOSI comes from P0.9 */
#define LOC_SSP1_SCK_P1_31 ((0)) /**< Input for SSP1_SCK comes from P1.31 */
#define LOC_SSP1_SCK_P1_19 ((1)) /**< Input for SSP1_SCK comes from P1.19 */
#define LOC_SSP1_SCK_P4_20 ((2)) /**< Input for SSP1_SCK comes from P4_20 */
#define LOC_SSP1_SCK_P0_7 ((3)) /**< Input for SSP1_SCK comes from P0_7 */
#define LOC_SSP1_SSEL_P0_14 ((0)) /**< Input for SSP1_SSEL comes from P0.14 */
#define LOC_SSP1_SSEL_P1_26 ((1)) /**< Input for SSP1_SSEL comes from P1.26 */
#define LOC_SSP1_SSEL_P4_21 ((2)) /**< Input for SSP1_SSEL comes from P4.21 */
#define LOC_SSP1_SSEL_P0_6 ((3)) /**< Input for SSP1_SSEL comes from P0.6 */
#define LOC_SSP2_MISO_P1_4 ((1)) /**< Input for SSP2_MISO comes from P1.4 */
#define LOC_SSP2_MOSI_P1_1 ((1)) /**< Input for SSP2_MOSI comes from P1.1 */
#define LOC_SSP2_SCK_P1_0 ((1)) /**< Input for SSP2_SCK comes from P1.0 */
#define LOC_SSP2_SSEL_P1_8 ((1)) /**< Input for SSP2_SSEL comes from P1.8 */
#define LOC_T0_CAP_0_P3_23 ((0)) /**< Input for T0_CAP_0 comes from P3.23 */
#define LOC_T0_CAP_0_P1_26 ((1)) /**< Input for T0_CAP_0 comes from P1.26 */
#define LOC_T0_CAP_1_P3_24 ((0)) /**< Input for T0_CAP_1 comes from P3.24 */
#define LOC_T0_CAP_1_P1_27 ((1)) /**< Input for T0_CAP_1 comes from P1.27 */
#define LOC_T1_CAP_0_P1_18 ((0)) /**< Input for T1_CAP_0 comes from P1.18 */
#define LOC_T1_CAP_0_P3_27 ((1)) /**< Input for T1_CAP_0 comes from P3.27 */
#define LOC_T1_CAP_1_P3_28 ((0)) /**< Input for T1_CAP_1 comes from P3.28 */
#define LOC_T1_CAP_1_P1_19 ((1)) /**< Input for T1_CAP_1 comes from P1.19 */
#define LOC_T2_CAP_0_P2_14 ((0)) /**< Input for T2_CAP_0 comes from P2.14 */
#define LOC_T2_CAP_0_P2_6 ((1)) /**< Input for T2_CAP_0 comes from P2.6 */
#define LOC_T2_CAP_0_P0_4 ((2)) /**< Input for T2_CAP_0 comes from P0.4 */
#define LOC_T2_CAP_0_P1_14 ((3)) /**< Input for T2_CAP_0 comes from P1.14 */
#define LOC_T2_CAP_1_P2_15 ((0)) /**< Input for T2_CAP_1 comes from P2.15 */
#define LOC_T2_CAP_1_P0_5 ((1)) /**< Input for T2_CAP_1 comes from P0.5 */
#define LOC_T3_CAP_0_P0_23 ((0)) /**< Input for T3_CAP_0 comes from P0.23 */
#define LOC_T3_CAP_0_P2_22 ((1)) /**< Input for T3_CAP_0 comes from P2.22 */
#define LOC_T3_CAP_0_P1_10 ((2)) /**< Input for T3_CAP_0 comes from P1.10 */
#define LOC_T3_CAP_1_P0_24 ((0)) /**< Input for T3_CAP_1 comes from P0.24 */
#define LOC_T3_CAP_1_P2_23 ((1)) /**< Input for T3_CAP_1 comes from P2.23 */
#define LOC_T3_CAP_1_P1_0 ((2)) /**< Input for T3_CAP_1 comes from P1.0 */
#define LOC_U0_RXD_P0_1 ((0)) /**< Input for U0_RXD comes from P0.1 */
#define LOC_U0_RXD_P0_3 ((1)) /**< Input for U0_RXD comes from P0.3 */
#define LOC_U1_CTS_P0_17 ((0)) /**< Input for U1_CTS comes from P0.17 */
#define LOC_U1_CTS_P2_8 ((1)) /**< Input for U1_CTS comes from P2.8 */
#define LOC_U1_CTS_P2_2 ((2)) /**< Input for U1_CTS comes from P2.2 */
#define LOC_U1_CTS_P3_18 ((3)) /**< Input for U1_CTS comes from P3.18 */
#define LOC_U1_DCD_P0_18 ((0)) /**< Input for U1_DCD comes from P0.18 */
#define LOC_U1_DCD_P2_3 ((1)) /**< Input for U1_DCD comes from P2.3 */
#define LOC_U1_DCD_P3_19 ((2)) /**< Input for U1_DCD comes from P3_19 */
#define LOC_U1_DSR_P0_19 ((0)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_DSR_P2_4 ((1)) /**< Input for U1_DSR comes from P2.4 */
#define LOC_U1_DSR_P3_20 ((2)) /**< Input for U1_DSR comes from P0.19 */
#define LOC_U1_RI_P0_21 ((0)) /**< Input for U1_RI comes from P0.21 */
#define LOC_U1_RI_P2_6 ((1)) /**< Input for U1_RI comes from P2.6 */
#define LOC_U1_RI_P3_22 ((2)) /**< Input for U1_RI comes from P3.22 */
#define LOC_U1_RXD_P0_16 ((0)) /**< Input for U1_RXD comes from P0.16 */
#define LOC_U1_RXD_P3_17 ((1)) /**< Input for U1_RXD comes from P3.17 */
#define LOC_U1_RXD_P2_1 ((2)) /**< Input for U1_RXD comes from P2.1 */
#define LOC_U2_RXD_P0_11 ((0)) /**< Input for U2_RXD comes from P0.11 */
#define LOC_U2_RXD_P4_23 ((1)) /**< Input for U2_RXD comes from P4.23 */
#define LOC_U2_RXD_P2_9 ((2)) /**< Input for U2_RXD comes from P2.9 */
#define LOC_U3_RXD_P0_26 ((0)) /**< Input for U3_RXD comes from P0.26 */
#define LOC_U3_RXD_P0_1 ((1)) /**< Input for U3_RXD comes from P0.1 */
#define LOC_U3_RXD_P4_29 ((2)) /**< Input for U3_RXD comes from P4.29 */
#define LOC_U3_RXD_P0_3 ((3)) /**< Input for U3_RXD comes from P0.3 */
#define LOC_U4_RXD_P2_9 ((0)) /**< Input for U4_RXD comes from P2.9 */
#define LOC_U4_RXD_P5_3 ((1)) /**< Input for U4_RXD comes from P5.3 */
#define LOC_USB_SCL_P0_28 ((0)) /**< Input for USB_SCL comes from P0.28 */
#define LOC_USB_SCL_P1_28 ((1)) /**< Input for USB_SCL comes from P1.28 */
#define LOC_USB_SDA_P0_27 ((0)) /**< Input for USB_SDA comes from P0.27 */
#define LOC_USB_SDA_P1_29 ((1)) /**< Input for USB_SDA comes from P1.29 */
/**
* @}
@ -206,32 +206,32 @@
/** @defgroup PINSEL_Public_Types PINSEL Public Types
* @{
*/
typedef enum
{
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
}PinSel_BasicMode;
typedef enum
{
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
PINSEL_I2CMODE_FAST_STANDARD = 0,
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
PINSEL_I2CMODE_OPENDRAINIO,
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
PINSEL_I2CMODE_FASTMODEPLUS,
/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
PINSEL_I2CMODE_FAST_STANDARD = 0,
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
PINSEL_I2CMODE_OPENDRAINIO,
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
PINSEL_I2CMODE_FASTMODEPLUS,
/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
}PinSel_I2cMode;
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup PINSEL_Public_Functions

1914
bsp/lpc178x/drivers/lpc177x_8x_uart.c
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514
bsp/lpc178x/drivers/lpc177x_8x_uart.h
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@ -1,13 +1,13 @@
/**********************************************************************
* $Id$ lpc177x_8x_uart.h 2011-06-02
* $Id$ lpc177x_8x_uart.h 2011-06-02
*//**
* @file lpc177x_8x_uart.h
* @brief Contains all macro definitions and function prototypes
* support for UART firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc177x_8x_uart.h
* @brief Contains all macro definitions and function prototypes
* support for UART firmware library on LPC177x_8x
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -25,7 +25,7 @@
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter)
/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter)
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
@ -51,7 +51,7 @@ extern "C"
/** UART time-out definitions in case of using Read() and Write function
* with Blocking Flag mode
*/
#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
/**
* @}
@ -63,7 +63,7 @@ extern "C"
*/
/* Accepted Error baud rate value (in percent unit) */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
@ -71,27 +71,27 @@ extern "C"
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
/** UART Received Buffer mask bit (8 bits) */
#define UART_RBR_MASKBIT ((uint8_t)0xFF)
#define UART_RBR_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
/** UART Transmit Holding mask bit (8 bits) */
#define UART_THR_MASKBIT ((uint8_t)0xFF)
#define UART_THR_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
/** Macro for loading least significant halfs of divisors */
#define UART_LOAD_DLL(div) ((div) & 0xFF)
#define UART_LOAD_DLL(div) ((div) & 0xFF)
/** Divisor latch LSB bit mask */
#define UART_DLL_MASKBIT ((uint8_t)0xFF)
#define UART_DLL_MASKBIT ((uint8_t)0xFF)
/*********************************************************************//**
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
/** Divisor latch MSB bit mask */
#define UART_DLM_MASKBIT ((uint8_t)0xFF)
#define UART_DLM_MASKBIT ((uint8_t)0xFF)
/** Macro for loading most significant halfs of divisors */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
@ -99,258 +99,258 @@ extern "C"
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
/** RBR Interrupt enable*/
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0))
#define UART_IER_RBRINT_EN ((uint32_t)(1<<0))
/** THR Interrupt enable*/
#define UART_IER_THREINT_EN ((uint32_t)(1<<1))
#define UART_IER_THREINT_EN ((uint32_t)(1<<1))
/** RX line status interrupt enable*/
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2))
#define UART_IER_RLSINT_EN ((uint32_t)(1<<2))
/** Modem status interrupt enable */
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3))
#define UART1_IER_MSINT_EN ((uint32_t)(1<<3))
/** CTS1 signal transition interrupt enable */
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7))
#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7))
/** Enables the end of auto-baud interrupt */
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8))
#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8))
/** Enables the auto-baud time-out interrupt */
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9))
#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9))
/** UART interrupt enable register bit mask */
#define UART_IER_BITMASK ((uint32_t)(0x307))
#define UART_IER_BITMASK ((uint32_t)(0x307))
/** UART1 interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F))
#define UART1_IER_BITMASK ((uint32_t)(0x38F))
/*********************************************************************//**
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
/** Interrupt Status - Active low */
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0))
#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0))
/** Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1))
#define UART_IIR_INTID_RLS ((uint32_t)(3<<1))
/** Interrupt identification: Receive data available*/
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1))
#define UART_IIR_INTID_RDA ((uint32_t)(2<<1))
/** Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1))
#define UART_IIR_INTID_CTI ((uint32_t)(6<<1))
/** Interrupt identification: THRE interrupt*/
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1))
#define UART_IIR_INTID_THRE ((uint32_t)(1<<1))
/** Interrupt identification: Modem interrupt*/
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1))
#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1))
/** Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1))
#define UART_IIR_INTID_MASK ((uint32_t)(7<<1))
/** These bits are equivalent to UnFCR[0] */
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6))
#define UART_IIR_FIFO_EN ((uint32_t)(3<<6))
/** End of auto-baud interrupt */
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8))
#define UART_IIR_ABEO_INT ((uint32_t)(1<<8))
/** Auto-baud time-out interrupt */
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9))
#define UART_IIR_ABTO_INT ((uint32_t)(1<<9))
/** UART interrupt identification register bit mask */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
/** UART FIFO enable */
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0))
#define UART_FCR_FIFO_EN ((uint8_t)(1<<0))
/** UART FIFO RX reset */
#define UART_FCR_RX_RS ((uint8_t)(1<<1))
#define UART_FCR_RX_RS ((uint8_t)(1<<1))
/** UART FIFO TX reset */
#define UART_FCR_TX_RS ((uint8_t)(1<<2))
#define UART_FCR_TX_RS ((uint8_t)(1<<2))
/** UART DMA mode selection */
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3))
#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3))
/** UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV0 ((uint8_t)(0))
#define UART_FCR_TRG_LEV0 ((uint8_t)(0))
/** UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6))
#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6))
/** UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6))
#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6))
/** UART FIFO trigger level 3: 14 character */
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6))
#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6))
/** UART FIFO control bit mask */
#define UART_FCR_BITMASK ((uint8_t)(0xCF))
#define UART_FCR_BITMASK ((uint8_t)(0xCF))
#define UART_TX_FIFO_SIZE (16)
#define UART_TX_FIFO_SIZE (16)
/*********************************************************************//**
* Macro defines for Macro defines for UART line control register
**********************************************************************/
/** UART 5 bit data mode */
#define UART_LCR_WLEN5 ((uint8_t)(0))
#define UART_LCR_WLEN5 ((uint8_t)(0))
/** UART 6 bit data mode */
#define UART_LCR_WLEN6 ((uint8_t)(1<<0))
#define UART_LCR_WLEN6 ((uint8_t)(1<<0))
/** UART 7 bit data mode */
#define UART_LCR_WLEN7 ((uint8_t)(2<<0))
#define UART_LCR_WLEN7 ((uint8_t)(2<<0))
/** UART 8 bit data mode */
#define UART_LCR_WLEN8 ((uint8_t)(3<<0))
#define UART_LCR_WLEN8 ((uint8_t)(3<<0))
/** UART Two Stop Bits Select */
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2))
#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2))
/** UART Parity Enable */
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3))
#define UART_LCR_PARITY_EN ((uint8_t)(1<<3))
/** UART Odd Parity Select */
#define UART_LCR_PARITY_ODD ((uint8_t)(0))
#define UART_LCR_PARITY_ODD ((uint8_t)(0))
/** UART Even Parity Select */
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4))
#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4))
/** UART force 1 stick parity */
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4))
#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4))
/** UART force 0 stick parity */
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4))
#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4))
/** UART Transmission Break enable */
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6))
#define UART_LCR_BREAK_EN ((uint8_t)(1<<6))
/** UART Divisor Latches Access bit enable */
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7))
#define UART_LCR_DLAB_EN ((uint8_t)(1<<7))
/** UART line control bit mask */
#define UART_LCR_BITMASK ((uint8_t)(0xFF))
#define UART_LCR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART1 Modem Control Register
**********************************************************************/
/** Source for modem output pin DTR */
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0))
#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0))
/** Source for modem output pin RTS */
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1))
#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1))
/** Loop back mode select */
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4))
#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4))
/** Enable Auto RTS flow-control */
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6))
#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6))
/** Enable Auto CTS flow-control */
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7))
#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7))
/** UART1 bit mask value */
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3))
#define UART1_MCR_BITMASK ((uint8_t)(0x0F3))
/*********************************************************************//**
* Macro defines for Macro defines for UART line status register
**********************************************************************/
/** Line status register: Receive data ready*/
#define UART_LSR_RDR ((uint8_t)(1<<0))
#define UART_LSR_RDR ((uint8_t)(1<<0))
/** Line status register: Overrun error*/
#define UART_LSR_OE ((uint8_t)(1<<1))
#define UART_LSR_OE ((uint8_t)(1<<1))
/** Line status register: Parity error*/
#define UART_LSR_PE ((uint8_t)(1<<2))
#define UART_LSR_PE ((uint8_t)(1<<2))
/** Line status register: Framing error*/
#define UART_LSR_FE ((uint8_t)(1<<3))
#define UART_LSR_FE ((uint8_t)(1<<3))
/** Line status register: Break interrupt*/
#define UART_LSR_BI ((uint8_t)(1<<4))
#define UART_LSR_BI ((uint8_t)(1<<4))
/** Line status register: Transmit holding register empty*/
#define UART_LSR_THRE ((uint8_t)(1<<5))
#define UART_LSR_THRE ((uint8_t)(1<<5))
/** Line status register: Transmitter empty*/
#define UART_LSR_TEMT ((uint8_t)(1<<6))
#define UART_LSR_TEMT ((uint8_t)(1<<6))
/** Error in RX FIFO*/
#define UART_LSR_RXFE ((uint8_t)(1<<7))
#define UART_LSR_RXFE ((uint8_t)(1<<7))
/** UART Line status bit mask */
#define UART_LSR_BITMASK ((uint8_t)(0xFF))
#define UART_LSR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Modem (UART1 only) status register
**********************************************************************/
/** Set upon state change of input CTS */
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0))
#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0))
/** Set upon state change of input DSR */
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1))
#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1))
/** Set upon low to high transition of input RI */
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2))
#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2))
/** Set upon state change of input DCD */
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3))
#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3))
/** Clear To Send State */
#define UART1_MSR_CTS ((uint8_t)(1<<4))
#define UART1_MSR_CTS ((uint8_t)(1<<4))
/** Data Set Ready State */
#define UART1_MSR_DSR ((uint8_t)(1<<5))
#define UART1_MSR_DSR ((uint8_t)(1<<5))
/** Ring Indicator State */
#define UART1_MSR_RI ((uint8_t)(1<<6))
#define UART1_MSR_RI ((uint8_t)(1<<6))
/** Data Carrier Detect State */
#define UART1_MSR_DCD ((uint8_t)(1<<7))
#define UART1_MSR_DCD ((uint8_t)(1<<7))
/** MSR register bit-mask value */
#define UART1_MSR_BITMASK ((uint8_t)(0xFF))
#define UART1_MSR_BITMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
/** UART Scratch Pad bit mask */
#define UART_SCR_BIMASK ((uint8_t)(0xFF))
#define UART_SCR_BIMASK ((uint8_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
/** UART Auto-baud start */
#define UART_ACR_START ((uint32_t)(1<<0))
#define UART_ACR_START ((uint32_t)(1<<0))
/** UART Auto baudrate Mode 1 */
#define UART_ACR_MODE ((uint32_t)(1<<1))
#define UART_ACR_MODE ((uint32_t)(1<<1))
/** UART Auto baudrate restart */
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2))
#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2))
/** UART End of auto-baud interrupt clear */
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8))
#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8))
/** UART Auto-baud time-out interrupt clear */
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9))
#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9))
/** UART Auto Baudrate register bit mask */
#define UART_ACR_BITMASK ((uint32_t)(0x307))
#define UART_ACR_BITMASK ((uint32_t)(0x307))
/*********************************************************************//**
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
/** IrDA mode enable */
#define UART_ICR_IRDAEN ((uint32_t)(1<<0))
#define UART_ICR_IRDAEN ((uint32_t)(1<<0))
/** IrDA serial input inverted */
#define UART_ICR_IRDAINV ((uint32_t)(1<<1))
#define UART_ICR_IRDAINV ((uint32_t)(1<<1))
/** IrDA fixed pulse width mode */
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2))
#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2))
/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
/** UART IRDA bit mask */
#define UART_ICR_BITMASK ((uint32_t)(0x3F))
#define UART_ICR_BITMASK ((uint32_t)(0x3F))
/*********************************************************************//**
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
/** Baud-rate generation pre-scaler divisor */
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
/** Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
/** UART Fractional Divider register bit mask */
#define UART_FDR_BITMASK ((uint32_t)(0xFF))
#define UART_FDR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************//**
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
/** Transmit enable bit */
#define UART_TER_TXEN ((uint8_t)(1<<7))
#define UART_TER_TXEN ((uint8_t)(1<<7))
/** UART Transmit Enable Register bit mask */
#define UART_TER_BITMASK ((uint8_t)(0x80))
#define UART_TER_BITMASK ((uint8_t)(0x80))
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS485 Control register
**********************************************************************/
/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0))
#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0))
/** The receiver is disabled */
#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1))
#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1))
/** Auto Address Detect (AAD) is enabled */
#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2))
#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2))
/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3))
#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3))
/** Enable Auto Direction Control */
#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))
/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))
/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5))
#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5))
/** RS485 control bit-mask value */
#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F))
#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F))
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Address Match register
**********************************************************************/
#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART1 RS-485 Delay value register
**********************************************************************/
/* Macro defines for UART1 RS-485 Delay value register */
#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
/*********************************************************************//**
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
/** Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F))
#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F))
/** Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F))
#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F))
/** UART FIFO Level Register bit mask */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
/**
@ -367,199 +367,199 @@ The direction control pin will be driven to logic "1" when the transmitter has d
* @brief UART Databit type definitions
*/
typedef enum {
UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
UART_DATABIT_6, /*!< UART 6 bit data mode */
UART_DATABIT_7, /*!< UART 7 bit data mode */
UART_DATABIT_8 /*!< UART 8 bit data mode */
UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
UART_DATABIT_6, /*!< UART 6 bit data mode */
UART_DATABIT_7, /*!< UART 7 bit data mode */
UART_DATABIT_8 /*!< UART 8 bit data mode */
} UART_DATABIT_Type;
/**
* @brief UART Stop bit type definitions
*/
typedef enum {
UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
UART_STOPBIT_2, /*!< UART Two Stop Bits Select */
} UART_STOPBIT_Type;
/**
* @brief UART Parity type definitions
*/
typedef enum {
UART_PARITY_NONE = 0, /*!< No parity */
UART_PARITY_ODD, /*!< Odd parity */
UART_PARITY_EVEN, /*!< Even parity */
UART_PARITY_SP_1, /*!< Forced "1" stick parity */
UART_PARITY_SP_0 /*!< Forced "0" stick parity */
UART_PARITY_NONE = 0, /*!< No parity */
UART_PARITY_ODD, /*!< Odd parity */
UART_PARITY_EVEN, /*!< Even parity */
UART_PARITY_SP_1, /*!< Forced "1" stick parity */
UART_PARITY_SP_0 /*!< Forced "0" stick parity */
} UART_PARITY_Type;
/**
* @brief FIFO Level type definitions
*/
typedef enum {
UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
} UART_FITO_LEVEL_Type;
/********************************************************************//**
* @brief UART Interrupt Type definitions
**********************************************************************/
typedef enum {
UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
UART_INTCFG_THRE, /*!< THR Interrupt enable*/
UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
UART_INTCFG_THRE, /*!< THR Interrupt enable*/
UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
} UART_INT_Type;
/**
* @brief UART Line Status Type definition
*/
typedef enum {
UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
} UART_LS_Type;
/**
* @brief UART Auto-baudrate mode type definition
*/
typedef enum {
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */
} UART_AB_MODE_Type;
/**
* @brief Auto Baudrate mode configuration type definition
*/
typedef struct {
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
FunctionalState AutoRestart; /**< Auto Restart state */
UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
FunctionalState AutoRestart; /**< Auto Restart state */
} UART_AB_CFG_Type;
/**
* @brief UART End of Auto-baudrate type definition
*/
typedef enum {
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
}UART_ABEO_Type;
/**
* UART IrDA Control type Definition
*/
typedef enum
typedef enum
{
/** Pulse width = 2 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV2 = 0,
/** Pulse width = 2 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV2 = 0,
/** Pulse width = 4 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV4,
/** Pulse width = 4 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV4,
/** Pulse width = 8 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV8,
/** Pulse width = 8 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV8,
/** Pulse width = 16 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV16,
/** Pulse width = 16 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV16,
/** Pulse width = 32 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV32,
/** Pulse width = 32 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV32,
/**< Pulse width = 64 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV64,
/**< Pulse width = 64 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV64,
/**< Pulse width = 128 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV128,
/**< Pulse width = 128 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV128,
/**< Pulse width = 256 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV256
/**< Pulse width = 256 * Tpclk
- Configures the pulse when FixPulseEn = 1 */
UART_IrDA_PULSEDIV256
} UART_IrDA_PULSE_Type;
/********************************************************************//**
* @brief UART1 Full modem - Signal states definition
**********************************************************************/
typedef enum {
INACTIVE = 0, /* In-active state */
ACTIVE = !INACTIVE /* Active state */
INACTIVE = 0, /* In-active state */
ACTIVE = !INACTIVE /* Active state */
}UART1_SignalState;
/**
* @brief UART modem status type definition
*/
typedef enum {
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
} UART_MODEM_STAT_type;
/**
* @brief Modem output pin type definition
*/
typedef enum {
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
} UART_MODEM_PIN_Type;
/**
* @brief UART Modem mode type definition
*/
typedef enum {
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
} UART_MODEM_MODE_Type;
/**
* @brief UART Direction Control Pin type definition
*/
typedef enum {
UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
} UART_RS485_DIRCTRL_PIN_Type;
/********************************************************************//**
* @brief UART Configuration Structure definition
**********************************************************************/
typedef struct {
uint32_t Baud_rate; /**< UART baud rate */
UART_PARITY_Type Parity; /**< Parity selection, should be:
- UART_PARITY_NONE: No parity
- UART_PARITY_ODD: Odd parity
- UART_PARITY_EVEN: Even parity
- UART_PARITY_SP_1: Forced "1" stick parity
- UART_PARITY_SP_0: Forced "0" stick parity
*/
uint32_t Baud_rate; /**< UART baud rate */
UART_PARITY_Type Parity; /**< Parity selection, should be:
- UART_PARITY_NONE: No parity
- UART_PARITY_ODD: Odd parity
- UART_PARITY_EVEN: Even parity
- UART_PARITY_SP_1: Forced "1" stick parity
- UART_PARITY_SP_0: Forced "0" stick parity
*/
UART_DATABIT_Type Databits; /**< Number of data bits, should be:
- UART_DATABIT_5: UART 5 bit data mode
- UART_DATABIT_6: UART 6 bit data mode
- UART_DATABIT_7: UART 7 bit data mode
- UART_DATABIT_8: UART 8 bit data mode
*/
- UART_DATABIT_5: UART 5 bit data mode
- UART_DATABIT_6: UART 6 bit data mode
- UART_DATABIT_7: UART 7 bit data mode
- UART_DATABIT_8: UART 8 bit data mode
*/
UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
- UART_STOPBIT_1: UART 1 Stop Bits Select
- UART_STOPBIT_2: UART 2 Stop Bits Select
*/
- UART_STOPBIT_1: UART 1 Stop Bits Select
- UART_STOPBIT_2: UART 2 Stop Bits Select
*/
} UART_CFG_Type;
/********************************************************************//**
@ -567,55 +567,55 @@ typedef struct {
**********************************************************************/
typedef struct {
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
- ENABLE: Reset Rx FIFO in UART
- DISABLE: Do not reset Rx FIFO in UART
*/
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
- ENABLE: Reset Tx FIFO in UART
- DISABLE: Do not reset Tx FIFO in UART
*/
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
- ENABLE: Enable DMA mode in UART
- DISABLE: Disable DMA mode in UART
*/
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
*/
FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
- ENABLE: Reset Rx FIFO in UART
- DISABLE: Do not reset Rx FIFO in UART
*/
FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
- ENABLE: Reset Tx FIFO in UART
- DISABLE: Do not reset Tx FIFO in UART
*/
FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
- ENABLE: Enable DMA mode in UART
- DISABLE: Disable DMA mode in UART
*/
UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
*/
} UART_FIFO_CFG_Type;
/********************************************************************//**
* @brief UART1 Full modem - RS485 Control configuration type
**********************************************************************/
typedef struct {
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
FunctionalState Rx_State; /*!< Receiver State:
- ENABLE: Enable Receiver.
- DISABLE: Disable Receiver. */
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
- ENABLE: ENABLE this function.
- DISABLE: Disable this function. */
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
- UART1_RS485_DIRCTRL_RTS:
pin RTS is used for direction control.
- UART1_RS485_DIRCTRL_DTR:
pin DTR is used for direction control. */
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
the RTS (or DTR) pin:
- RESET: The direction control pin will be driven
to logic "0" when the transmitter has data to be sent.
- SET: The direction control pin will be driven
to logic "1" when the transmitter has data to be sent. */
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
FunctionalState Rx_State; /*!< Receiver State:
- ENABLE: Enable Receiver.
- DISABLE: Disable Receiver. */
FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
- ENABLE: ENABLE this function.
- DISABLE: Disable this function. */
FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
- ENABLE: Enable this function.
- DISABLE: Disable this function. */
UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
- UART1_RS485_DIRCTRL_RTS:
pin RTS is used for direction control.
- UART1_RS485_DIRCTRL_DTR:
pin DTR is used for direction control. */
SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
the RTS (or DTR) pin:
- RESET: The direction control pin will be driven
to logic "0" when the transmitter has data to be sent.
- SET: The direction control pin will be driven
to logic "1" when the transmitter has data to be sent. */
uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
} UART1_RS485_CTRLCFG_Type;
/**
@ -636,9 +636,9 @@ void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
uint32_t buflen, TRANSFER_BLOCK_Type flag);
uint32_t buflen, TRANSFER_BLOCK_Type flag);
/* UART FIFO functions ----------------------------------------------------------*/
void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
@ -650,7 +650,7 @@ uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
/* UART operate functions -------------------------------------------------------*/
void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
FunctionalState NewState);
FunctionalState NewState);
void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
@ -658,18 +658,18 @@ void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
/* UART Auto-baud functions -----------------------------------------------------*/
void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
FunctionalState NewState);
FunctionalState NewState);
/* UART1 FullModem functions ----------------------------------------------------*/
void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
UART1_SignalState NewState);
UART1_SignalState NewState);
void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
FunctionalState NewState);
FunctionalState NewState);
uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
/* UART RS485 functions ----------------------------------------------------------*/
void UART_RS485Config(LPC_UART_TypeDef *UARTx,
UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr);
uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size);

90
bsp/lpc178x/drivers/lpc17xx_lcd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,8 +13,8 @@
#include "drv_glcd.h"
#define RT_HW_LCD_WIDTH 480
#define RT_HW_LCD_HEIGHT 272
#define RT_HW_LCD_WIDTH 480
#define RT_HW_LCD_HEIGHT 272
static struct rt_device_graphic_info _lcd_info;
static struct rt_device lcd;
@ -23,38 +23,38 @@ static struct rt_device lcd;
static rt_err_t rt_lcd_init (rt_device_t dev)
{
PINSEL_ConfigPin(5, 4, 0);
LPC_GPIO5->DIR |= 1<<4;
LPC_GPIO5->CLR = 1<<4;
LPC_GPIO5->SET = 1<<4;
LPC_GPIO5->DIR |= 1<<4;
LPC_GPIO5->CLR = 1<<4;
LPC_GPIO5->SET = 1<<4;
/*Disable LCD controller*/
GLCD_Ctrl (FALSE);
/*Init LCD and copy picture in video RAM*/
GLCD_Init (_lcd_info.framebuffer);
/*Enable LCD*/
GLCD_Ctrl (TRUE);
/*Disable LCD controller*/
GLCD_Ctrl (FALSE);
/*Init LCD and copy picture in video RAM*/
GLCD_Init (_lcd_info.framebuffer);
/*Enable LCD*/
GLCD_Ctrl (TRUE);
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
return RT_EOK;
}
@ -63,27 +63,27 @@ void rt_hw_lcd_init(void)
{
rt_uint16_t * _rt_framebuffer = RT_NULL;
// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
_rt_framebuffer = (rt_uint16_t *)0xA0000000;
_rt_framebuffer = (rt_uint16_t *)0xA0000000;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
_lcd_info.framebuffer = (void*)_rt_framebuffer;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
/* init device structure */
lcd.type = RT_Device_Class_Graphic;
lcd.init = rt_lcd_init;
lcd.open = RT_NULL;
lcd.close = RT_NULL;
lcd.control = rt_lcd_control;
lcd.user_data = (void*)&_lcd_info;
/* init device structure */
lcd.type = RT_Device_Class_Graphic;
lcd.init = rt_lcd_init;
lcd.open = RT_NULL;
lcd.close = RT_NULL;
lcd.control = rt_lcd_control;
lcd.user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
/* register lcd device to RT-Thread */
rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}
void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel)

36
bsp/lpc178x/drivers/lpc_types.h
View File

@ -1,15 +1,15 @@
/**********************************************************************
* $Id$ lpc_types.h 2011-06-02
* $Id$ lpc_types.h 2011-06-02
*//**
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* @file lpc_types.h
* @brief Contains the NXP ABL typedefs for C standard types.
* It is intended to be used in ISO C conforming development
* environments and checks for this insofar as it is possible
* to do so.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
@ -37,7 +37,7 @@
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
*/
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types Basic Public Data Types
* @{
@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
*/
typedef enum
{
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_Type;
@ -98,7 +98,7 @@ typedef int32_t(*PFI)();
*/
#undef _BIT
/** Set bit macro */
#define _BIT(n) (1<<n)
#define _BIT(n) (1<<n)
/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
@ -161,16 +161,16 @@ typedef uint8_t UNS_8;
typedef int8_t INT_8;
/** SMA type for 16 bit unsigned value */
typedef uint16_t UNS_16;
typedef uint16_t UNS_16;
/** SMA type for 16 bit signed value */
typedef int16_t INT_16;
typedef int16_t INT_16;
/** SMA type for 32 bit unsigned value */
typedef uint32_t UNS_32;
typedef uint32_t UNS_32;
/** SMA type for 32 bit signed value */
typedef int32_t INT_32;
typedef int32_t INT_32;
/** SMA type for 64 bit signed value */
typedef int64_t INT_64;

112
bsp/lpc178x/drivers/sdram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,10 +12,10 @@
#include "LPC177x_8x.h"
#include "sdram.h"
//LPC_EMC_TypeDef * const g_pEMC = ((LPC_EMC_TypeDef*) LPC_EMC_BASE);
//LPC_IOCON_TypeDef * const LPC_IOCON = ((LPC_IOCON_TypeDef*) LPC_IOCON_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define EMC_NS2CLK(ns, nsPerClk) ((ns + nsPerClk - 1) / nsPerClk)
//LPC_EMC_TypeDef * const g_pEMC = ((LPC_EMC_TypeDef*) LPC_EMC_BASE);
//LPC_IOCON_TypeDef * const LPC_IOCON = ((LPC_IOCON_TypeDef*) LPC_IOCON_BASE);
#define SDRAM_BASE 0xA0000000 /* CS0 */
#define EMC_NS2CLK(ns, nsPerClk) ((ns + nsPerClk - 1) / nsPerClk)
static void delayMs(int a,int b)
{
@ -24,65 +24,65 @@ static void delayMs(int a,int b)
}
/*****************************************************************************
** Function name: delayMs
** Function name: delayMs
**
** Descriptions: Start the timer delay in milo seconds
** until elapsed
** Descriptions: Start the timer delay in milo seconds
** until elapsed
**
** parameters: timer number, Delay value in milo second
** parameters: timer number, Delay value in milo second
**
** Returned value: None
** Returned value: None
**
*****************************************************************************/
//void delayMs(uint8_t timer_num, uint32_t delayInMs)
//{
// if ( timer_num == 0 )
// {
// LPC_TIM0->TCR = 0x02; /* reset timer */
// LPC_TIM0->PR = 0x00; /* set prescaler to zero */
// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM0->IR = 0xff; /* reset all interrrupts */
// LPC_TIM0->MCR = 0x04; /* stop timer on match */
// LPC_TIM0->TCR = 0x01; /* start timer */
// LPC_TIM0->TCR = 0x02; /* reset timer */
// LPC_TIM0->PR = 0x00; /* set prescaler to zero */
// LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM0->IR = 0xff; /* reset all interrrupts */
// LPC_TIM0->MCR = 0x04; /* stop timer on match */
// LPC_TIM0->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM0->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM0->TCR & 0x01);
// }
// else if ( timer_num == 1 )
// {
// LPC_TIM1->TCR = 0x02; /* reset timer */
// LPC_TIM1->PR = 0x00; /* set prescaler to zero */
// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM1->IR = 0xff; /* reset all interrrupts */
// LPC_TIM1->MCR = 0x04; /* stop timer on match */
// LPC_TIM1->TCR = 0x01; /* start timer */
// LPC_TIM1->TCR = 0x02; /* reset timer */
// LPC_TIM1->PR = 0x00; /* set prescaler to zero */
// LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM1->IR = 0xff; /* reset all interrrupts */
// LPC_TIM1->MCR = 0x04; /* stop timer on match */
// LPC_TIM1->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM1->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM1->TCR & 0x01);
// }
// else if ( timer_num == 2 )
// {
// LPC_TIM2->TCR = 0x02; /* reset timer */
// LPC_TIM2->PR = 0x00; /* set prescaler to zero */
// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM2->IR = 0xff; /* reset all interrrupts */
// LPC_TIM2->MCR = 0x04; /* stop timer on match */
// LPC_TIM2->TCR = 0x01; /* start timer */
// LPC_TIM2->TCR = 0x02; /* reset timer */
// LPC_TIM2->PR = 0x00; /* set prescaler to zero */
// LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM2->IR = 0xff; /* reset all interrrupts */
// LPC_TIM2->MCR = 0x04; /* stop timer on match */
// LPC_TIM2->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM2->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM2->TCR & 0x01);
// }
// else if ( timer_num == 3 )
// {
// LPC_TIM3->TCR = 0x02; /* reset timer */
// LPC_TIM3->PR = 0x00; /* set prescaler to zero */
// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM3->IR = 0xff; /* reset all interrrupts */
// LPC_TIM3->MCR = 0x04; /* stop timer on match */
// LPC_TIM3->TCR = 0x01; /* start timer */
// LPC_TIM3->TCR = 0x02; /* reset timer */
// LPC_TIM3->PR = 0x00; /* set prescaler to zero */
// LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
// LPC_TIM3->IR = 0xff; /* reset all interrrupts */
// LPC_TIM3->MCR = 0x04; /* stop timer on match */
// LPC_TIM3->TCR = 0x01; /* start timer */
//
// /* wait until delay time has elapsed */
// while (LPC_TIM3->TCR & 0x01);
// /* wait until delay time has elapsed */
// while (LPC_TIM3->TCR & 0x01);
// }
// return;
//}
@ -204,7 +204,7 @@ void SDRAM_Init (void)
{
uint32_t i, dwtemp = dwtemp;
uint16_t wtemp = wtemp;
uint32_t mhz, nsPerClk;
uint32_t mhz, nsPerClk;
/* Enable External Memory Controller power/clock */
LPC_SC->PCONP |= 0x00000800;
LPC_SC->EMCDLYCTL = 0x00001010;
@ -213,10 +213,10 @@ void SDRAM_Init (void)
EMC_GPIO_Init();
mhz = SystemCoreClock / 1000000;
if (LPC_SC->EMCCLKSEL)
mhz >>= 1;
nsPerClk = 1000 / mhz;
mhz = SystemCoreClock / 1000000;
if (LPC_SC->EMCCLKSEL)
mhz >>= 1;
nsPerClk = 1000 / mhz;
LPC_EMC->DynamicRP = EMC_NS2CLK(20, nsPerClk); /* 20ns, */
LPC_EMC->DynamicRAS = /*EMC_NS2CLK(42, nsPerClk);*/ 15; /* 42ns to 100K ns, */
LPC_EMC->DynamicSREX = 1 - 1; /* tSRE, 1clk, */
@ -225,7 +225,7 @@ void SDRAM_Init (void)
LPC_EMC->DynamicWR = 2 - 1; /* 2CLK, */
LPC_EMC->DynamicRC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRC=63ns(min)*/
LPC_EMC->DynamicRFC = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRFC=tRC */
LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, ²»ÖªµÀ£¬ÉèΪ×î¾Ã */
LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, 不知道，设为最久 */
LPC_EMC->DynamicRRD = EMC_NS2CLK(63, nsPerClk); /* 3clk, tRRD=15ns(min) */
LPC_EMC->DynamicMRD = 2 - 1; /* 2clk, tMRD=2clk(min) */
@ -249,22 +249,22 @@ void SDRAM_Init (void)
#ifdef SDRAM_CONFIG_16BIT
LPC_EMC->DynamicConfig0 = 0x680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
#elif defined SDRAM_CONFIG_32BIT
LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
#endif
delayMs(0, 100);
LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
delayMs(0, 200); /* wait 200ms */
delayMs(0, 200); /* wait 200ms */
LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
/* 64ms/8192=7.8125us, nx16x8.33ns<7.8125us, n<58.6*/
wtemp = 64000000 / (1 << 13);
wtemp -= 16;
wtemp >>= 4;
wtemp = wtemp * mhz / 1000;
wtemp = 64000000 / (1 << 13);
wtemp -= 16;
wtemp >>= 4;
wtemp = wtemp * mhz / 1000;
LPC_EMC->DynamicRefresh = wtemp;
LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
@ -273,7 +273,7 @@ void SDRAM_Init (void)
wtemp = *((volatile uint16_t *)(SDRAM_BASE | (0x33<<12))); /* 8 burst, 3 CAS latency */
#elif defined SDRAM_CONFIG_32BIT
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */
#endif
LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */

9
bsp/lpc178x/drivers/sdram.h
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef SDRAM_H_INCLUDED
#define SDRAM_H_INCLUDED

310
bsp/lpc178x/drivers/uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -25,14 +25,14 @@
struct rt_uart_lpc
{
struct rt_device parent;
struct rt_device parent;
LPC_UART_TypeDef * UART;
IRQn_Type UART_IRQn;
LPC_UART_TypeDef * UART;
IRQn_Type UART_IRQn;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
};
#ifdef RT_USING_UART0
@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device;
#ifdef RT_USING_UART0
void UART0_IRQHandler(void)
{
rt_ubase_t level, iir;
rt_ubase_t level, iir;
struct rt_uart_lpc* uart = &uart0_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = uart->UART->IIR;
iir = uart->UART->IIR;
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
level = rt_hw_interrupt_disable();
uart->save_index ++;
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
}
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
return;
}
#endif
#ifdef RT_USING_UART1
void UART1_IRQHandler(void)
{
rt_ubase_t level, iir;
rt_ubase_t level, iir;
struct rt_uart_lpc* uart = &uart1_device;
/* enter interrupt */
rt_interrupt_enter();
/* enter interrupt */
rt_interrupt_enter();
/* read IIR and clear it */
iir = uart->UART->IIR;
iir = uart->UART->IIR;
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
{
/* Receive Data Available */
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
level = rt_hw_interrupt_disable();
uart->save_index ++;
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
}
}
/* leave interrupt */
rt_interrupt_leave();
/* leave interrupt */
rt_interrupt_leave();
return;
return;
}
#endif
static rt_err_t rt_uart_init (rt_device_t dev)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
UART_CFG_Type UART_ConfigStruct;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
UART_CFG_Type UART_ConfigStruct;
#ifdef RT_USING_UART0
if( uart->UART == LPC_UART0 )
if( uart->UART == LPC_UART0 )
{
/*
* Initialize UART0 pin connect
@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev)
#endif
#ifdef RT_USING_UART2
if( uart->UART == LPC_UART2 )
if( uart->UART == LPC_UART2 )
{
}
#endif
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
NVIC_EnableIRQ( uart->UART_IRQn );
}
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
NVIC_EnableIRQ( uart->UART_IRQn );
}
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ( uart->UART_IRQn );
}
RT_ASSERT(dev != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
NVIC_DisableIRQ( uart->UART_IRQn );
}
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(uart != RT_NULL);
rt_uint8_t* ptr;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
char *ptr;
ptr = (char*)buffer;
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
char *ptr;
ptr = (char*)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->UART->LSR & UART_LSR_THRE));
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,'\r');
}
}
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,*ptr);
ptr ++;
size --;
}
}
else
{
while (!(uart->UART->LSR & UART_LSR_THRE));
UART_SendByte( uart->UART,*ptr);
ptr ++;
size --;
}
}
else
{
UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING);
}
return (rt_size_t) ptr - (rt_size_t) buffer;
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_lpc* uart;
struct rt_uart_lpc* uart;
#ifdef RT_USING_UART0
/* get uart device */
uart = &uart0_device;
uart0_device.UART = LPC_UART0;
uart0_device.UART_IRQn = UART0_IRQn;
/* get uart device */
uart = &uart0_device;
uart0_device.UART = LPC_UART0;
uart0_device.UART_IRQn = UART0_IRQn;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&uart->parent,
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
#endif
#ifdef RT_USING_UART1
/* get uart device */
uart = &uart1_device;
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
uart1_device.UART_IRQn = UART1_IRQn;
/* get uart device */
uart = &uart1_device;
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
uart1_device.UART_IRQn = UART1_IRQn;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&uart->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
#endif
}

56
bsp/lpc178x/rtconfig.h
View File

@ -5,17 +5,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@ -30,11 +30,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@ -66,13 +66,13 @@
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@ -84,7 +84,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@ -99,18 +99,18 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@ -120,7 +120,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@ -136,31 +136,31 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 2048
#define RT_LWIP_TCP_SND_BUF 2048
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
#define RT_LWIP_TCP_SEG_NUM 4
#define RT_LWIP_TCP_SEG_NUM 4
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
@ -181,7 +181,7 @@
// <section name="RT_USING_RTGUI" description="RT-Thread/GUI" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="the name size of RT-Thread/GUI widget/objects" default="12" />
#define RTGUI_NAME_MAX 12
#define RTGUI_NAME_MAX 12
// <bool name="RTGUI_USING_SMALL_SIZE" description="use small size in RT-Thread/GUI" default="true" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_FONT16" description="support 16 weight font" default="true" />
@ -191,7 +191,7 @@
// <bool name="RTGUI_USING_FONTHZ" description="support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <integer name="RTGUI_DEFAULT_FONT_SIZE" description="default font size in RT-Thread/GUI" default="16" />
#define RTGUI_DEFAULT_FONT_SIZE 16
#define RTGUI_DEFAULT_FONT_SIZE 16
// <bool name="RTGUI_USING_DFS_FILERW" description="use RT-Thread/DFS as file interface" default="true" />
// #define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_BMP" description="use Chinese font bitmap engine" default="true" />

2
bsp/lpc2148/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc2148/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

82
bsp/lpc2148/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -25,13 +25,13 @@
*/
void rt_hw_timer_handler(int vector, void *param)
{
rt_tick_increase();
rt_tick_increase();
/* clear interrupt flag */
T0IR |= 0x01;
/* clear interrupt flag */
T0IR |= 0x01;
/* acknowledge Interrupt */
VICVectAddr = 0;
/* acknowledge Interrupt */
VICVectAddr = 0;
}
/**
@ -42,37 +42,37 @@ void rt_hw_timer_handler(int vector, void *param)
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
if (*str=='\n')
{
while (!(U0LSR & 0x20));
U0THR = '\r';
}
while (*str)
{
if (*str=='\n')
{
while (!(U0LSR & 0x20));
U0THR = '\r';
}
while (!(U0LSR & 0x20));
U0THR = *str;
while (!(U0LSR & 0x20));
U0THR = *str;
str ++;
}
str ++;
}
}
#define BAUD_RATE 115200
#define U0PINS 0x05
#define BAUD_RATE 115200
#define U0PINS 0x05
void rt_hw_console_init()
{
/* Enable RxD and TxD pins */
PINSEL0 = U0PINS;
/* Enable RxD and TxD pins */
PINSEL0 = U0PINS;
/* 8 bits, no Parity, 1 Stop bit */
U0LCR = 0x83;
/* 8 bits, no Parity, 1 Stop bit */
U0LCR = 0x83;
/* Setup Baudrate */
U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
/* Setup Baudrate */
U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
/* DLAB = 0 */
U0LCR = 0x03;
/* DLAB = 0 */
U0LCR = 0x03;
}
/**
@ -80,23 +80,23 @@ void rt_hw_console_init()
*/
void rt_hw_board_init(void)
{
/* console init */
rt_hw_console_init();
/* console init */
rt_hw_console_init();
/* prescaler = 0*/
T0PR = 0;
T0PC = 0;
/* prescaler = 0*/
T0PR = 0;
T0PC = 0;
/* reset and enable MR0 interrupt */
T0MCR = 0x3;
T0MR0 = PCLK / RT_TICK_PER_SECOND;
/* reset and enable MR0 interrupt */
T0MCR = 0x3;
T0MR0 = PCLK / RT_TICK_PER_SECOND;
/* enable timer 0 */
T0TCR = 1;
/* enable timer 0 */
T0TCR = 1;
/* install timer handler */
rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
rt_hw_interrupt_umask(TIMER0_INT);
/* install timer handler */
rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
rt_hw_interrupt_umask(TIMER0_INT);
}
/*@}*/

8
bsp/lpc2148/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,13 +12,13 @@
#define __BOARD_H__
#include <rtthread.h>
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
/* RT_USING_UART */
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
void rt_hw_board_init(void);

88
bsp/lpc2148/drivers/dm9000.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,11 +15,11 @@
#define MAX_ADDR_LEN 6
struct rt_dm9000_eth
{
/* inherit from ethernet device */
struct eth_device parent;
/* inherit from ethernet device */
struct eth_device parent;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
};
static struct rt_dm9000_eth dm9000_device;
@ -52,67 +52,67 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_dm9000_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args)
{
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
default :
break;
}
return RT_EOK;
return RT_EOK;
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
{
struct pbuf* q;
rt_uint32_t len;
rt_uint8_t* ptr;
struct pbuf* q;
rt_uint32_t len;
rt_uint8_t* ptr;
for (q = p; q != NULL; q = q->next)
{
len = q->len;
ptr = q->payload;
for (q = p; q != NULL; q = q->next)
{
len = q->len;
ptr = q->payload;
/* write data to device */
}
/* write data to device */
}
return RT_EOK;
return RT_EOK;
}
/* reception packet. */
struct pbuf *rt_dm9000_rx(rt_device_t dev)
{
struct pbuf* p;
rt_uint32_t len;
rt_uint32_t len;
/* init p pointer */
p = RT_NULL;
@ -149,17 +149,17 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
void rt_hw_dm9000_init()
{
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.parent.init = rt_dm9000_init;
dm9000_device.parent.parent.open = rt_dm9000_open;
dm9000_device.parent.parent.close = rt_dm9000_close;
dm9000_device.parent.parent.read = rt_dm9000_read;
dm9000_device.parent.parent.write = rt_dm9000_write;
dm9000_device.parent.parent.control = rt_dm9000_control;
dm9000_device.parent.parent.user_data = RT_NULL;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
dm9000_device.parent.eth_rx = rt_dm9000_rx;
dm9000_device.parent.eth_tx = rt_dm9000_tx;
rt_device_register((rt_device_t)&dm9000_device,
"E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
rt_device_register((rt_device_t)&dm9000_device,
"E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
}

82
bsp/lpc2148/drivers/sd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -22,12 +22,12 @@ static rt_err_t rt_sdcard_init(rt_device_t dev)
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_sdcard_close(rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
@ -48,54 +48,54 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
return RT_EOK;
}
void rt_hw_sdcard_init()
{
rt_size_t length;
rt_uint8_t* sector;
rt_uint8_t* sector;
/* sdcard hardware init */
sd.type = RT_Device_Class_Block;
sd.init = rt_sdcard_init;
sd.open = rt_sdcard_open;
sd.close = rt_sdcard_close;
sd.read = rt_sdcard_read;
sd.write = rt_sdcard_write;
sd.control = rt_sdcard_control;
sd.user_data = RT_NULL;
sd.type = RT_Device_Class_Block;
sd.init = rt_sdcard_init;
sd.open = rt_sdcard_open;
sd.close = rt_sdcard_close;
sd.read = rt_sdcard_read;
sd.write = rt_sdcard_write;
sd.control = rt_sdcard_control;
sd.user_data = RT_NULL;
/* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return;
}
/* get the first sector to read partition table */
sector = (rt_uint8_t*) rt_malloc (512);
if (sector == RT_NULL)
{
rt_kprintf("allocate partition sector buffer failed\n");
return;
}
length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
if (length == 512)
{
rt_err_t status;
length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
if (length == 512)
{
rt_err_t status;
/* get the first partition */
status = dfs_filesystem_get_partition(&part, sector, 0);
if (status != RT_EOK)
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
/* get the first partition */
status = dfs_filesystem_get_partition(&part, sector, 0);
if (status != RT_EOK)
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
}
else
{
/* there is no partition table */
part.offset = 0;
part.size = 0;
}
rt_device_register(&sd,
"sd", RT_DEVICE_FLAG_RDWR);
rt_device_register(&sd,
"sd", RT_DEVICE_FLAG_RDWR);
}

450
bsp/lpc2148/drivers/serial.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,8 +15,8 @@
#include "board.h"
/* serial hardware register */
#define REG8(d) (*((volatile unsigned char *)(d)))
#define REG32(d) (*((volatile unsigned long *)(d)))
#define REG8(d) (*((volatile unsigned char *)(d)))
#define REG32(d) (*((volatile unsigned long *)(d)))
#define UART_RBR(base) REG8(base + 0x00)
#define UART_THR(base) REG8(base + 0x00)
@ -37,16 +37,16 @@
/* LPC serial device */
struct rt_lpcserial
{
/* inherit from device */
struct rt_device parent;
/* inherit from device */
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irqno;
rt_uint32_t baudrate;
rt_uint32_t hw_base;
rt_uint32_t irqno;
rt_uint32_t baudrate;
/* reception field */
rt_uint16_t save_index, read_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
/* reception field */
rt_uint16_t save_index, read_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
};
#ifdef RT_USING_UART1
@ -58,70 +58,70 @@ struct rt_lpcserial serial2;
void rt_hw_serial_init(void);
#define U0PINS 0x00000005
#define U0PINS 0x00000005
void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
{
RT_UNUSED rt_uint32_t iir;
RT_UNUSED rt_uint32_t iir;
RT_ASSERT(lpc_serial != RT_NULL)
RT_ASSERT(lpc_serial != RT_NULL)
if (UART_LSR(lpc_serial->hw_base) & 0x01)
{
rt_base_t level;
if (UART_LSR(lpc_serial->hw_base) & 0x01)
{
rt_base_t level;
while (UART_LSR(lpc_serial->hw_base) & 0x01)
{
/* disable interrupt */
level = rt_hw_interrupt_disable();
while (UART_LSR(lpc_serial->hw_base) & 0x01)
{
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* read character */
lpc_serial->rx_buffer[lpc_serial->save_index] =
UART_RBR(lpc_serial->hw_base);
lpc_serial->save_index ++;
if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->save_index = 0;
/* read character */
lpc_serial->rx_buffer[lpc_serial->save_index] =
UART_RBR(lpc_serial->hw_base);
lpc_serial->save_index ++;
if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (lpc_serial->save_index == lpc_serial->read_index)
{
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
/* if the next position is read index, discard this 'read char' */
if (lpc_serial->save_index == lpc_serial->read_index)
{
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if(lpc_serial->parent.rx_indicate != RT_NULL)
{
lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
}
}
/* invoke callback */
if(lpc_serial->parent.rx_indicate != RT_NULL)
{
lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
}
}
/* clear interrupt source */
iir = UART_IIR(lpc_serial->hw_base);
/* clear interrupt source */
iir = UART_IIR(lpc_serial->hw_base);
/* acknowledge Interrupt */
VICVectAddr = 0;
/* acknowledge Interrupt */
VICVectAddr = 0;
}
#ifdef RT_USING_UART1
void rt_hw_uart_isr_1(int irqno, void *param)
{
/* get lpc serial device */
rt_hw_uart_isr(&serial1);
}
/* get lpc serial device */
rt_hw_uart_isr(&serial1);
}
#endif
#ifdef RT_USING_UART2
void rt_hw_uart_isr_2(int irqno, void *param)
{
/* get lpc serial device */
rt_hw_uart_isr(&serial2);
}
/* get lpc serial device */
rt_hw_uart_isr(&serial2);
}
#endif
/**
@ -131,256 +131,256 @@ void rt_hw_uart_isr_2(int irqno, void *param)
static rt_err_t rt_serial_init (rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
RT_ASSERT(lpc_serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* init UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x01;
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
/* install ISR */
if (lpc_serial->irqno == UART0_INT)
{
RT_ASSERT(lpc_serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* init UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x01;
/* install ISR */
if (lpc_serial->irqno == UART0_INT)
{
#ifdef RT_USING_UART1
rt_hw_interrupt_install(lpc_serial->irqno,
rt_hw_interrupt_install(lpc_serial->irqno,
rt_hw_uart_isr_1, &serial1, "UART1");
#endif
}
else
{
}
else
{
#ifdef RT_USING_UART2
rt_hw_interrupt_install(lpc_serial->irqno,
rt_hw_interrupt_install(lpc_serial->irqno,
rt_hw_uart_isr_2, &serial2, "UART2");
#endif
}
}
rt_hw_interrupt_umask(lpc_serial->irqno);
}
rt_hw_interrupt_umask(lpc_serial->irqno);
}
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
RT_ASSERT(lpc_serial != RT_NULL);
RT_ASSERT(lpc_serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* disable UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x00;
}
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* disable UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x00;
}
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
RT_ASSERT(lpc_serial != RT_NULL);
rt_uint8_t* ptr;
struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
RT_ASSERT(lpc_serial != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (lpc_serial->read_index != lpc_serial->save_index)
{
*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (lpc_serial->read_index != lpc_serial->save_index)
{
*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
else
{
/* no data in rx buffer */
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++; size --;
}
ptr ++; size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
{
/* not support right now */
RT_ASSERT(0);
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
{
/* not support right now */
RT_ASSERT(0);
}
/* polling mode */
while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
{
/* Read Character */
*ptr = UART_RBR(lpc_serial->hw_base);
/* polling mode */
while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
{
/* Read Character */
*ptr = UART_RBR(lpc_serial->hw_base);
ptr ++;
size --;
}
ptr ++;
size --;
}
return (rt_size_t)ptr - (rt_size_t)buffer;
return (rt_size_t)ptr - (rt_size_t)buffer;
}
static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
struct rt_lpcserial* lpc_serial;
char *ptr;
struct rt_lpcserial* lpc_serial;
char *ptr;
lpc_serial = (struct rt_lpcserial*) dev;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* not support */
RT_ASSERT(0);
}
lpc_serial = (struct rt_lpcserial*) dev;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* not support */
RT_ASSERT(0);
}
/* polling write */
ptr = (char *)buffer;
/* polling write */
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = '\r';
}
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = '\r';
}
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size)
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size)
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
ptr ++;
size --;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_serial_init(void)
{
struct rt_lpcserial* lpc_serial;
struct rt_lpcserial* lpc_serial;
#ifdef RT_USING_UART1
lpc_serial = &serial1;
lpc_serial = &serial1;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->hw_base = 0xE000C000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART0_INT;
lpc_serial->hw_base = 0xE000C000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART0_INT;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
/* Enable UART0 RxD and TxD pins */
/* Enable UART0 RxD and TxD pins */
PINSEL0 |= 0x05;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
rt_device_register(&lpc_serial->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&lpc_serial->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
#endif
#ifdef RT_USING_UART2
lpc_serial = &serial2;
lpc_serial = &serial2;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->hw_base = 0xE0010000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART1_INT;
lpc_serial->hw_base = 0xE0010000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART1_INT;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
/* Enable UART1 RxD and TxD pins */
PINSEL0 |= 0x05 << 16;
/* Enable UART1 RxD and TxD pins */
PINSEL0 |= 0x05 << 16;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
rt_device_register(&lpc_serial->parent,
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
rt_device_register(&lpc_serial->parent,
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
#endif
}

46
bsp/lpc2148/rtconfig.h
View File

@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
@ -62,12 +62,12 @@
#define RT_USING_DEVICE
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */
/* Using FinSH as Shell*/
@ -87,11 +87,11 @@
/* SECTION: DFS options */
/* #define RT_USING_DFS */
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 8
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 8
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* Using lighweight TCP/IP protocol stack*/
@ -119,21 +119,21 @@
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#endif

2
bsp/lpc2478/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc2478/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

28
bsp/lpc2478/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,7 +14,7 @@
#include <LPC24xx.h>
#include "board.h"
#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */
#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */
extern void rt_hw_serial_init(void);
@ -25,9 +25,9 @@ extern void rt_hw_serial_init(void);
void rt_timer_handler(int vector, void* param)
{
T0IR |= 0x01; /* clear interrupt flag */
rt_tick_increase();
VICVectAddr = 0; /* Acknowledge Interrupt */
T0IR |= 0x01; /* clear interrupt flag */
rt_tick_increase();
VICVectAddr = 0; /* Acknowledge Interrupt */
}
/**
@ -36,19 +36,19 @@ void rt_timer_handler(int vector, void* param)
void rt_hw_board_init(void)
{
#if defined(RT_USING_DEVICE) && defined(RT_USING_UART1)
rt_hw_serial_init();
rt_console_set_device("uart1");
rt_hw_serial_init();
rt_console_set_device("uart1");
#endif
T0IR = 0xff;
T0TC = 0;
T0MCR = 0x03;
T0MR0 = (DATA_COUNT);
T0IR = 0xff;
T0TC = 0;
T0MCR = 0x03;
T0MR0 = (DATA_COUNT);
rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick");
rt_hw_interrupt_umask(TIMER0_INT);
rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick");
rt_hw_interrupt_umask(TIMER0_INT);
T0TCR = 0x01; //enable timer0 counter
T0TCR = 0x01; //enable timer0 counter
}
/*@}*/

132
bsp/lpc2478/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,7 +14,7 @@
/* RT_USING_UART */
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_UART_RX_BUFFER_SIZE 64
#define RT_UART_RX_BUFFER_SIZE 64
void rt_hw_board_init(void);
void rt_hw_led_set(rt_uint32_t led);
void rt_hw_led_flash(void);
@ -23,93 +23,93 @@ void rt_hw_led_flash(void);
void rt_hw_finsh_init(void);
#endif
#define USE_USB 0
#define USE_USB 0
#if USE_USB /* 1 is USB, 0 is non-USB related */
#define PLL_MValue 11
#define PLL_NValue 0
#define CCLKDivValue 4
#define USBCLKDivValue 5
#if USE_USB /* 1 is USB, 0 is non-USB related */
#define PLL_MValue 11
#define PLL_NValue 0
#define CCLKDivValue 4
#define USBCLKDivValue 5
#define Fosc 12000000
#define Fcclk 57600000
#define Fcco 288000000
#define Fosc 12000000
#define Fcclk 57600000
#define Fcco 288000000
#else
#define PLL_MValue 12
#define PLL_NValue 1
#define CCLKDivValue 5
#define PLL_MValue 12
#define PLL_NValue 1
#define CCLKDivValue 5
#define Fosc 12000000
#define Fcclk 72000000
#define Fcco 360000000
#define Fosc 12000000
#define Fcclk 72000000
#define Fcco 360000000
#endif
#if USE_USB
#define Fpclk (Fcclk / 2)
#define Fpclk (Fcclk / 2)
#else
#define Fpclk (Fcclk / 4)
#define Fpclk (Fcclk / 4)
#endif
/* IRQ define */
#define SYS32Mode 0x1F
#define IRQ32Mode 0x12
#define FIQ32Mode 0x11
#define SYS32Mode 0x1F
#define IRQ32Mode 0x12
#define FIQ32Mode 0x11
#define HIGHEST_PRIORITY 0x01
#define LOWEST_PRIORITY 0x0F
#define HIGHEST_PRIORITY 0x01
#define LOWEST_PRIORITY 0x0F
#define WDT_INT 0
#define SWI_INT 1
#define ARM_CORE0_INT 2
#define ARM_CORE1_INT 3
#define TIMER0_INT 4
#define TIMER1_INT 5
#define UART0_INT 6
#define UART1_INT 7
#define PWM0_1_INT 8
#define I2C0_INT 9
#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */
#define SSP0_INT 10
#define SSP1_INT 11
#define PLL_INT 12
#define RTC_INT 13
#define EINT0_INT 14
#define EINT1_INT 15
#define EINT2_INT 16
#define EINT3_INT 17
#define ADC0_INT 18
#define I2C1_INT 19
#define BOD_INT 20
#define EMAC_INT 21
#define USB_INT 22
#define CAN_INT 23
#define MCI_INT 24
#define GPDMA_INT 25
#define TIMER2_INT 26
#define TIMER3_INT 27
#define UART2_INT 28
#define UART3_INT 29
#define I2C2_INT 30
#define I2S_INT 31
#define WDT_INT 0
#define SWI_INT 1
#define ARM_CORE0_INT 2
#define ARM_CORE1_INT 3
#define TIMER0_INT 4
#define TIMER1_INT 5
#define UART0_INT 6
#define UART1_INT 7
#define PWM0_1_INT 8
#define I2C0_INT 9
#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */
#define SSP0_INT 10
#define SSP1_INT 11
#define PLL_INT 12
#define RTC_INT 13
#define EINT0_INT 14
#define EINT1_INT 15
#define EINT2_INT 16
#define EINT3_INT 17
#define ADC0_INT 18
#define I2C1_INT 19
#define BOD_INT 20
#define EMAC_INT 21
#define USB_INT 22
#define CAN_INT 23
#define MCI_INT 24
#define GPDMA_INT 25
#define TIMER2_INT 26
#define TIMER3_INT 27
#define UART2_INT 28
#define UART3_INT 29
#define I2C2_INT 30
#define I2S_INT 31
#define VIC_SIZE 32
#define VIC_SIZE 32
#define VECT_ADDR_INDEX 0x100
#define VECT_ADDR_INDEX 0x100
#define VECT_CNTL_INDEX 0x200
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
#define CCLK 60000000 /* Fosc = 12MHz, M = 5 */
#define PCLK 15000000 /* CCLK/4, use default */
/******************************************************************************
** Function name: TargetInit
** Function name: TargetInit
**
** Descriptions: Initialize the target board; it is called in a
** necessary place, change it as needed
** Descriptions: Initialize the target board; it is called in a
** necessary place, change it as needed
**
** parameters: None
** Returned value: None
** parameters: None
** Returned value: None
**
******************************************************************************/
extern void TargetInit(void);

458
bsp/lpc2478/drivers/serial.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,8 +15,8 @@
#include "board.h"
/* serial hardware register */
#define REG8(d) (*((volatile unsigned char *)(d)))
#define REG32(d) (*((volatile unsigned long *)(d)))
#define REG8(d) (*((volatile unsigned char *)(d)))
#define REG32(d) (*((volatile unsigned long *)(d)))
#define UART_RBR(base) REG8(base + 0x00)
#define UART_THR(base) REG8(base + 0x00)
@ -37,16 +37,16 @@
/* LPC serial device */
struct rt_lpcserial
{
/* inherit from device */
struct rt_device parent;
/* inherit from device */
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irqno;
rt_uint32_t baudrate;
rt_uint32_t hw_base;
rt_uint32_t irqno;
rt_uint32_t baudrate;
/* reception field */
rt_uint16_t save_index, read_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
/* reception field */
rt_uint16_t save_index, read_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
};
#ifdef RT_USING_UART1
@ -58,55 +58,55 @@ struct rt_lpcserial serial2;
void rt_hw_serial_init(void);
#define U0PINS 0x00000005
#define U0PINS 0x00000005
void rt_hw_uart_isr(int irqno, void *param)
{
RT_UNUSED rt_uint32_t iir;
struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
RT_UNUSED rt_uint32_t iir;
struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
RT_ASSERT(lpc_serial != RT_NULL)
if (UART_LSR(lpc_serial->hw_base) & 0x01)
{
rt_base_t level;
RT_ASSERT(lpc_serial != RT_NULL)
while (UART_LSR(lpc_serial->hw_base) & 0x01)
{
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (UART_LSR(lpc_serial->hw_base) & 0x01)
{
rt_base_t level;
/* read character */
lpc_serial->rx_buffer[lpc_serial->save_index] =
UART_RBR(lpc_serial->hw_base);
lpc_serial->save_index ++;
if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->save_index = 0;
/* if the next position is read index, discard this 'read char' */
if (lpc_serial->save_index == lpc_serial->read_index)
{
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
while (UART_LSR(lpc_serial->hw_base) & 0x01)
{
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* read character */
lpc_serial->rx_buffer[lpc_serial->save_index] =
UART_RBR(lpc_serial->hw_base);
lpc_serial->save_index ++;
if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->save_index = 0;
/* invoke callback */
if(lpc_serial->parent.rx_indicate != RT_NULL)
{
lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
}
}
/* if the next position is read index, discard this 'read char' */
if (lpc_serial->save_index == lpc_serial->read_index)
{
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
/* clear interrupt source */
iir = UART_IIR(lpc_serial->hw_base);
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
/* acknowledge Interrupt */
VICVectAddr = 0;
/* invoke callback */
if(lpc_serial->parent.rx_indicate != RT_NULL)
{
lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
}
}
/* clear interrupt source */
iir = UART_IIR(lpc_serial->hw_base);
/* acknowledge Interrupt */
VICVectAddr = 0;
}
@ -117,243 +117,243 @@ void rt_hw_uart_isr(int irqno, void *param)
static rt_err_t rt_serial_init (rt_device_t dev)
{
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
RT_ASSERT(lpc_serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* init UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x01;
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
/* install ISR */
rt_hw_interrupt_install(lpc_serial->irqno,
RT_ASSERT(lpc_serial != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* init UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x01;
/* install ISR */
rt_hw_interrupt_install(lpc_serial->irqno,
rt_hw_uart_isr, lpc_serial, RT_NULL);
rt_hw_interrupt_umask(lpc_serial->irqno);
}
rt_hw_interrupt_umask(lpc_serial->irqno);
}
return RT_EOK;
return RT_EOK;
}
static rt_err_t rt_serial_close(rt_device_t dev)
{
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
RT_ASSERT(lpc_serial != RT_NULL);
struct rt_lpcserial* lpc_serial;
lpc_serial = (struct rt_lpcserial*) dev;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* disable UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x00;
}
RT_ASSERT(lpc_serial != RT_NULL);
return RT_EOK;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* disable UART rx interrupt */
UART_IER(lpc_serial->hw_base) = 0x00;
}
return RT_EOK;
}
static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
return RT_EOK;
}
static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
RT_ASSERT(lpc_serial != RT_NULL);
rt_uint8_t* ptr;
struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
RT_ASSERT(lpc_serial != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (lpc_serial->read_index != lpc_serial->save_index)
{
*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (lpc_serial->read_index != lpc_serial->save_index)
{
*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
else
{
/* no data in rx buffer */
lpc_serial->read_index ++;
if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
lpc_serial->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++; size --;
}
ptr ++; size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
{
/* not support right now */
RT_ASSERT(0);
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
{
/* not support right now */
RT_ASSERT(0);
}
/* polling mode */
while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
{
/* Read Character */
*ptr = UART_RBR(lpc_serial->hw_base);
ptr ++;
size --;
}
/* polling mode */
while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
{
/* Read Character */
*ptr = UART_RBR(lpc_serial->hw_base);
return (rt_size_t)ptr - (rt_size_t)buffer;
ptr ++;
size --;
}
return (rt_size_t)ptr - (rt_size_t)buffer;
}
static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
struct rt_lpcserial* lpc_serial;
char *ptr;
struct rt_lpcserial* lpc_serial;
char *ptr;
lpc_serial = (struct rt_lpcserial*) dev;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* not support */
RT_ASSERT(0);
}
lpc_serial = (struct rt_lpcserial*) dev;
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
{
/* not support */
RT_ASSERT(0);
}
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
{
/* not support */
RT_ASSERT(0);
}
/* polling write */
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = '\r';
}
/* polling write */
ptr = (char *)buffer;
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size)
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = '\r';
}
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size)
{
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
UART_THR(lpc_serial->hw_base) = *ptr;
ptr ++;
size --;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_serial_init(void)
{
struct rt_lpcserial* lpc_serial;
struct rt_lpcserial* lpc_serial;
#ifdef RT_USING_UART1
lpc_serial = &serial1;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->hw_base = 0xE000C000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART0_INT;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
lpc_serial = &serial1;
/* Enable UART0 RxD and TxD pins */
PINSEL0 |= 0x50;
lpc_serial->parent.type = RT_Device_Class_Char;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
lpc_serial->hw_base = 0xE000C000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART0_INT;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
/* Enable UART0 RxD and TxD pins */
PINSEL0 |= 0x50;
rt_device_register(&lpc_serial->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
rt_device_register(&lpc_serial->parent,
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
#endif
#ifdef RT_USING_UART2
lpc_serial = &serial2;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial = &serial2;
lpc_serial->hw_base = 0xE0010000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART1_INT;
lpc_serial->parent.type = RT_Device_Class_Char;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
lpc_serial->hw_base = 0xE0010000;
lpc_serial->baudrate = 115200;
lpc_serial->irqno = UART1_INT;
/* Enable UART1 RxD and TxD pins */
PINSEL0 |= 0x05 << 16;
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
lpc_serial->read_index = lpc_serial->save_index = 0;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
/* Enable UART1 RxD and TxD pins */
PINSEL0 |= 0x05 << 16;
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
/* 8 bits, no Parity, 1 Stop bit */
UART_LCR(lpc_serial->hw_base) = 0x83;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
/* Setup Baudrate */
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
rt_device_register(&lpc_serial->parent,
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
/* DLAB = 0 */
UART_LCR(lpc_serial->hw_base) = 0x03;
lpc_serial->parent.type = RT_Device_Class_Char;
lpc_serial->parent.init = rt_serial_init;
lpc_serial->parent.open = rt_serial_open;
lpc_serial->parent.close = rt_serial_close;
lpc_serial->parent.read = rt_serial_read;
lpc_serial->parent.write = rt_serial_write;
lpc_serial->parent.control = rt_serial_control;
lpc_serial->parent.user_data = RT_NULL;
rt_device_register(&lpc_serial->parent,
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
#endif
}

38
bsp/lpc2478/rtconfig.h
View File

@ -3,22 +3,22 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
#define RT_THREAD_PRIORITY_MAX 256
#define RT_THREAD_PRIORITY_MAX 256
/* Tick per Second*/
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_PRIO 1
/* Rate at which timer management task runs (Hz) */
#define RT_TIMER_EX_TICKS_PER_SEC 10
#define RT_TIMER_EX_TICKS_PER_SEC 10
/* SECTION: RT_DEBUG */
@ -67,7 +67,7 @@
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */
/* Using FinSH as Shell*/
@ -102,21 +102,21 @@
/* #define RT_LWIP_DHCP */
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 0
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 0
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
#endif

8
bsp/lpc408x/applications/main.c
View File

@ -1,11 +1,11 @@
/*
* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 armink first version
* 2018-12-10 armink first version
*/
#include <rtthread.h>
@ -14,6 +14,6 @@
int main(void)
{
rt_kprintf("Hello RT-Thread!\n");
return RT_EOK;
}
}

2
bsp/lpc408x/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_emac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_emac.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_hwtimer.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_led.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_led.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_sdram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_sdram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc408x/drivers/drv_uart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M0/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M0/applications/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M0/applications/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M0/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc43xx/M0/applications/vbus_drv.c
View File

@ -1,6 +1,6 @@
/*
* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
* Change Logs:
* Date Author Notes

4
bsp/lpc43xx/M0/applications/vbus_hw.h
View File

@ -1,6 +1,6 @@
/*
* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
* Change Logs:
* Date Author Notes

6
bsp/lpc43xx/M4/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -32,10 +32,10 @@ static void _boot_M0(void)
LPC_CREG->M0APPMEMMAP = (uint32_t)&_M0_CODE[0];
// Release Slave from reset, first read status
// Release Slave from reset, first read status
u32REG = LPC_RGU->RESET_ACTIVE_STATUS1;
// If the M0 is being held in reset, release it...
// If the M0 is being held in reset, release it...
// 1 = no reset, 0 = reset
while(!(u32REG & (1u << 24)))
{

2
bsp/lpc43xx/M4/applications/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M4/applications/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/M4/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc43xx/M4/applications/vbus_drv.c
View File

@ -1,6 +1,6 @@
/*
* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
* Change Logs:
* Date Author Notes

4
bsp/lpc43xx/M4/applications/vbus_hw.h
View File

@ -1,6 +1,6 @@
/*
* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
* Change Logs:
* Date Author Notes

2
bsp/lpc43xx/drivers/drv_emac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/drivers/drv_emac.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc43xx/drivers/drv_led.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/lpc43xx/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -179,7 +179,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial0.ops = &lpc_uart_ops;
serial0.config = config;
@ -230,7 +230,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial2.ops = &lpc_uart_ops;
serial2.config = config;
@ -282,7 +282,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial3.ops = &lpc_uart_ops;
serial3.config = config;

2
bsp/lpc5410x/applications/application.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc5410x/applications/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -46,7 +46,7 @@ void rt_hw_board_init()
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK);
#endif
SystemCoreClockUpdate();
/* init systick 1 systick = 1/(100M / 100) 100¸ösystick = 1s*/
/* init systick 1 systick = 1/(100M / 100) 100个systick = 1s*/
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);

2
bsp/lpc5410x/applications/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

56
bsp/lpc5410x/applications/demo_thread.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -10,47 +10,47 @@
#include "drv_led.h"
#include "drv_uart.h"
static void thread1_entry(void* parameter)
static void thread1_entry(void* parameter)
{
while(1)
{
Led_Control(0,1);
rt_thread_delay(RT_TICK_PER_SECOND);
Led_Control(0,0);
rt_thread_delay(RT_TICK_PER_SECOND);
Led_Control(0,1);
rt_thread_delay(RT_TICK_PER_SECOND);
Led_Control(0,0);
rt_thread_delay(RT_TICK_PER_SECOND);
}
}
static void thread2_entry(void* parameter)
static void thread2_entry(void* parameter)
{
while(1)
{
Led_Control(1,1);
rt_thread_delay(RT_TICK_PER_SECOND);
Led_Control(1,0);
rt_thread_delay(RT_TICK_PER_SECOND);
}
Led_Control(1,1);
rt_thread_delay(RT_TICK_PER_SECOND);
Led_Control(1,0);
rt_thread_delay(RT_TICK_PER_SECOND);
}
}
int demo_init(void)
{
rt_thread_t thread1 = RT_NULL;
rt_thread_t thread2 = RT_NULL;
rt_led_hw_init();
thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5);
if (thread1 != RT_NULL)
rt_thread_startup(thread1);
rt_thread_t thread1 = RT_NULL;
rt_thread_t thread2 = RT_NULL;
thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5);
if (thread2 != RT_NULL)
rt_thread_startup(thread2);
return 0;
rt_led_hw_init();
thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5);
if (thread1 != RT_NULL)
rt_thread_startup(thread1);
thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5);
if (thread2 != RT_NULL)
rt_thread_startup(thread2);
return 0;
}

2
bsp/lpc5410x/applications/startup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/lpc5410x/drivers/drv_led.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

9
bsp/lpc5410x/drivers/drv_led.h
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __DRV_LED_H__
#define __DRV_LED_H__

2
bsp/lpc5410x/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

9
bsp/lpc5410x/drivers/drv_uart.h
View File

@ -1,3 +1,12 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __DRV_UART_H_
#define __DRV_UART_H_

52
bsp/lpc5410x/rtconfig.h
View File

@ -5,17 +5,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 8
#define RT_NAME_MAX 8
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration, enable it to open assertions for run-time checking" default="true" >
#define RT_DEBUG
#define RT_DEBUG_COLOR
@ -30,11 +30,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
@ -75,7 +75,7 @@
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
@ -87,7 +87,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
@ -102,18 +102,18 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
@ -123,7 +123,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
@ -139,29 +139,29 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 2048
#define RT_LWIP_TCP_SND_BUF 2048
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
@ -182,7 +182,7 @@
// <section name="RT_USING_RTGUI" description="RT-Thread/GUI" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="the name size of RT-Thread/GUI widget/objects" default="12" />
#define RTGUI_NAME_MAX 12
#define RTGUI_NAME_MAX 12
// <bool name="RTGUI_USING_SMALL_SIZE" description="use small size in RT-Thread/GUI" default="true" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_FONT16" description="support 16 weight font" default="true" />
@ -192,7 +192,7 @@
// <bool name="RTGUI_USING_FONTHZ" description="support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <integer name="RTGUI_DEFAULT_FONT_SIZE" description="default font size in RT-Thread/GUI" default="16" />
#define RTGUI_DEFAULT_FONT_SIZE 16
#define RTGUI_DEFAULT_FONT_SIZE 16
// <bool name="RTGUI_USING_DFS_FILERW" description="use RT-Thread/DFS as file interface" default="true" />
// #define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_BMP" description="use Chinese font bitmap engine" default="true" />

6
bsp/lpc54114-lite/applications/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,9 +14,9 @@
int main(void)
{
/* user app entry */
/* user app entry */
rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN));

10
bsp/lpc54114-lite/applications/mnt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -24,15 +24,15 @@ int mnt_init(void)
{
rt_kprintf("spi flash mount '%s' failed.\n", BSP_FLASH_MOUNT_PATH);
}
#endif
#endif
#if defined(BSP_USING_SDCARD)
if(dfs_mount("sd0", BSP_SDCARD_MOUNT_PATH, "elm", 0, 0) != 0)
{
rt_kprintf("sdcard mount '%s' failed.\n", BSP_SDCARD_MOUNT_PATH);
}
#endif
#endif
return 0;
}
INIT_APP_EXPORT(mnt_init);
INIT_APP_EXPORT(mnt_init);

4
bsp/lpc54114-lite/drivers/audio/drv_mic.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -160,4 +160,4 @@ int rt_hw_mic_init(void)
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_mic_init);
INIT_DEVICE_EXPORT(rt_hw_mic_init);

2
bsp/lpc54114-lite/drivers/audio/drv_mic.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/lpc54114-lite/drivers/audio/drv_sound.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -358,4 +358,4 @@ int rt_hw_sound_init(void)
rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_sound_init);
INIT_DEVICE_EXPORT(rt_hw_sound_init);

2
bsp/lpc54114-lite/drivers/audio/drv_sound.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/lpc54114-lite/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -57,15 +57,15 @@ void rt_hw_board_init()
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
/* initialization board with RT-Thread Components */
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

2
bsp/lpc54114-lite/drivers/board.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

130
bsp/lpc54114-lite/drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -35,7 +35,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static rt_base_t lpc_pin_get(const char *name)
@ -85,46 +85,46 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
int portx, piny, dir;
uint32_t pin_cfg;
if(pin > PIN_MAX_VAL)
return;
portx = get_port(pin);
piny = get_pin(pin);
piny = get_pin(pin);
switch(mode)
{
case PIN_MODE_OUTPUT:
case PIN_MODE_OUTPUT:
dir = kGPIO_DigitalOutput;
pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN;
break;
case PIN_MODE_OUTPUT_OD:
dir = kGPIO_DigitalOutput;
pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
dir = kGPIO_DigitalOutput;
pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
break;
case PIN_MODE_INPUT:
case PIN_MODE_INPUT:
dir = kGPIO_DigitalInput;
pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN;
break;
break;
case PIN_MODE_INPUT_PULLUP:
dir = kGPIO_DigitalInput;
dir = kGPIO_DigitalInput;
pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
break;
case PIN_MODE_INPUT_PULLDOWN:
case PIN_MODE_INPUT_PULLDOWN:
dir = kGPIO_DigitalInput;
pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
break;
default: break;
}
CLOCK_EnableClock(kCLOCK_Iocon);
IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
GPIO_PortInit(GPIO, portx);
}
CLOCK_EnableClock(kCLOCK_Iocon);
IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
GPIO_PortInit(GPIO, portx);
gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0};
GPIO_PinInit(GPIO, portx, piny, &pin_config);
GPIO_PinInit(GPIO, portx, piny, &pin_config);
CLOCK_DisableClock(kCLOCK_Iocon);
}
@ -133,27 +133,27 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
int portx, piny;
portx = get_port(pin);
piny = get_pin(pin);
piny = get_pin(pin);
if(pin > PIN_MAX_VAL)
return;
GPIO_PinWrite(GPIO, portx, piny, value);
GPIO_PinWrite(GPIO, portx, piny, value);
}
static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
{
int portx, piny, value;
int portx, piny, value;
if(pin > PIN_MAX_VAL)
return RT_ERROR;
return RT_ERROR;
portx = get_port(pin);
piny = get_pin(pin);
piny = get_pin(pin);
value = (int)(GPIO_PinRead(GPIO, portx, piny));
return value;
return value;
}
static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
@ -166,10 +166,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
break;
}
}
if(irqno >= IRQ_MAX_VAL)
return;
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
@ -184,14 +184,14 @@ void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
if(pin > PIN_MAX_VAL)
return RT_ERROR;
return RT_ERROR;
portx = get_port(pin);
piny = get_pin(pin);
piny = get_pin(pin);
switch (mode)
{
case PIN_IRQ_MODE_RISING:
@ -210,10 +210,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
trigger_mode = kPINT_PinIntEnableLowLevel;
break;
}
/* Get inputmux_connection_t */
/* Get inputmux_connection_t */
pintsel = (pin + (0xC0U << 20));
for(i = 0; i < IRQ_MAX_VAL; i++)
{
if(pin_irq_hdr_tab[i].pin == -1)
@ -226,40 +226,40 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
break;
}
}
if(i >= IRQ_MAX_VAL)
return RT_ERROR;
/* open clk */
CLOCK_EnableClock(kCLOCK_InputMux);
CLOCK_EnableClock(kCLOCK_Iocon);
/* AttachSignal */
/* AttachSignal */
INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
pin_cfg = ((IOCON->PIO[portx][piny] &
(~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
| IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
| IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */
| IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
/* PINT_PinInterruptConfig */
PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
CLOCK_DisableClock(kCLOCK_InputMux);
CLOCK_DisableClock(kCLOCK_Iocon);
return RT_EOK;
}
static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
int i;
int i;
if(pin > PIN_MAX_VAL)
return RT_ERROR;
return RT_ERROR;
for(i = 0; i < IRQ_MAX_VAL; i++)
{
if(pin_irq_hdr_tab[i].pin == pin)
@ -270,18 +270,18 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
pin_irq_hdr_tab[i].args = RT_NULL;
break;
}
}
}
return RT_EOK;
}
static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
{
int irqn_type, i;
if(pin > PIN_MAX_VAL)
return RT_ERROR;
return RT_ERROR;
for(i = 0; i < IRQ_MAX_VAL; i++)
{
if(pin_irq_hdr_tab[i].pin == pin)
@ -315,8 +315,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
break;
}
}
}
if(i >= IRQ_MAX_VAL)
return RT_ERROR;

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