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update Stellaris Peripheral Driver Library to r8264. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1869 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2011-12-23 03:20:26 +00:00
parent 315fffcfcb
commit 646c1443db
203 changed files with 77918 additions and 41464 deletions
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9
bsp/lm3s8962/Libraries/SConscript
View File

@ -6,9 +6,13 @@ from building import *
cwd = GetCurrentDir()
src = Glob('driverlib/*.c')
# cortex-m3 no FPU.
if rtconfig.PART_TYPE.startswith('PART_LM4F') != True:
SrcRemove(src, 'fpu.c')
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/gcc/startup_LPC17xx.s']
src += ['startup/gcc/start_gcc.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup/arm/start_rvds.S']
elif rtconfig.CROSS_TOOL == 'iar':
@ -16,6 +20,7 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
CPPDEFINES = [rtconfig.PART_TYPE]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')

256
bsp/lm3s8962/Libraries/driverlib/adc.c
View File

@ -2,7 +2,7 @@
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -33,6 +33,7 @@
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_sysctl.h"
#include "driverlib/adc.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
@ -46,6 +47,7 @@
#define ADC_SEQ (ADC_O_SSMUX0)
#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0)
#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
@ -70,10 +72,10 @@ static unsigned char g_pucOversampleFactor[3];
//! ADC sample sequence interrupt occurs.
//!
//! This function sets the handler to be called when a sample sequence
//! interrupt occurs. This will enable the global interrupt in the interrupt
//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source via
//! ADCIntClear().
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; the sequence interrupt must be enabled with
//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the
//! interrupt source via ADCIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -117,9 +119,9 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller; the sequence interrupt must
//! be disabled via ADCIntDisable().
//! This function unregisters the interrupt handler. This function disables
//! the global interrupt in the interrupt controller; the sequence interrupt
//! must be disabled via ADCIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -225,9 +227,9 @@ ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified sample sequence.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//! This function returns the interrupt status for the specified sample
//! sequence. Either the raw interrupt status or the status of interrupts that
//! are allowed to reflect to the processor can be returned.
//!
//! \return The current raw or masked interrupt status.
//
@ -257,7 +259,7 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
//
// If the digital comparator status bit is set, reflect it to the
// If the digital comparator status bit is set, reflect it to the
// appropriate sequence bit.
//
if(ulTemp & 0x10000)
@ -281,17 +283,17 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulSequenceNum is the sample sequence number.
//!
//! The specified sample sequence interrupt is cleared, so that it no longer
//! asserts. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//! asserts. This function must be called in the interrupt handler to keep
//! the interrupt from being triggered again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -379,10 +381,10 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//! respect to the other sample sequences.
//!
//! This function configures the initiation criteria for a sample sequence.
//! Valid sample sequences range from zero to three; sequence zero will capture
//! up to eight samples, sequences one and two will capture up to four samples,
//! and sequence three will capture a single sample. The trigger condition and
//! priority (with respect to other sample sequence execution) is set.
//! Valid sample sequencers range from zero to three; sequencer zero captures
//! up to eight samples, sequencers one and two capture up to four samples,
//! and sequencer three captures a single sample. The trigger condition and
//! priority (with respect to other sample sequencer execution) are set.
//!
//! The \e ulTrigger parameter can take on the following values:
//!
@ -395,7 +397,9 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
//! B4 pin.
//! B4 pin. Note that some microcontrollers can
//! select from any GPIO using the
//! GPIOADCTriggerEnable() function.
//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
//! TimerControlTrigger().
//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
@ -472,42 +476,40 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step; must be a logical OR of
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
//! with the digital comparator feature, the follow values may also be OR'd
//! into the \e ulConfig value to enable the digital comparater feature:
//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
//! \b ADC_CTL_CMP7).
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of
//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7).
//!
//! This function will set the configuration of the ADC for one step of a
//! sample sequence. The ADC can be configured for single-ended or
//! differential operation (the \b ADC_CTL_D bit selects differential
//! operation when set), the channel to be sampled can be chosen (the
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
//! bit) and it can be configured to cause an interrupt when the step is
//! complete (the \b ADC_CTL_IE bit). If the digital comparators are present
//! on the device, this step may also be configured send the ADC sample to
//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
//! ADC at the appropriate time when the trigger for this sequence occurs.
//! This function configures the ADC for one step of a sample sequence. The
//! ADC can be configured for single-ended or differential operation
//! (the \b ADC_CTL_D bit selects differential operation when set), the
//! channel to be sampled can be chosen (the \b ADC_CTL_CH0 through
//! \b ADC_CTL_CH23 values), and the internal temperature sensor can be
//! selected (the \b ADC_CTL_TS bit). Additionally, this step can be defined
//! as the last in the sequence (the \b ADC_CTL_END bit) and it can be
//! configured to cause an interrupt when the step is complete (the
//! \b ADC_CTL_IE bit). If the digital comparators are present on the device,
//! this step may also be configured to send the ADC sample to the selected
//! comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration
//! is used by the ADC at the appropriate time when the trigger for
//! this sequence occurs.
//!
//! \note If the Digitial Comparator is present and enabled using the
//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
//! sequence data FIFO.
//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT
//! written into the ADC sequence data FIFO.
//!
//! The \e ulStep parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
//! seven for the first sample sequence, from zero to three for the second and
//! third sample sequence, and can only be zero for the fourth sample sequence.
//! seven for the first sample sequencer, from zero to three for the second and
//! third sample sequencer, and can only be zero for the fourth sample
//! sequencer.
//!
//! Differential mode only works with adjacent channel pairs (for example, 0
//! and 1). The channel select must be the number of the channel pair to
//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
//! and 3) or undefined results will be returned by the ADC. Additionally, if
//! and 3) or undefined results are returned by the ADC. Additionally, if
//! differential mode is selected when the temperature sensor is being sampled,
//! undefined results will be returned by the ADC.
//! undefined results are returned by the ADC.
//!
//! It is the responsibility of the caller to ensure that a valid configuration
//! is specified; this function does not check the validity of the specified
@ -549,6 +551,13 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf00) >> 8) << ulStep));
//
// Set the control value for this step.
//
@ -595,9 +604,9 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence overflow has occurred. This will
//! happen if the captured samples are not read from the FIFO before the next
//! trigger occurs.
//! This function determines if a sample sequence overflow has occurred.
//! Overflow happens if the captured samples are not read from the FIFO before
//! the next trigger occurs.
//!
//! \return Returns zero if there was not an overflow, and non-zero if there
//! was.
@ -625,9 +634,9 @@ ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an overflow condition on one of the sample sequences. The
//! overflow condition must be cleared in order to detect a subsequent overflow
//! condition (it otherwise causes no harm).
//! This function clears an overflow condition on one of the sample sequences.
//! The overflow condition must be cleared in order to detect a subsequent
//! overflow condition (it otherwise causes no harm).
//!
//! \return None.
//
@ -654,8 +663,8 @@ ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence underflow has occurred. This will
//! happen if too many samples are read from the FIFO.
//! This function determines if a sample sequence underflow has occurred.
//! Underflow happens if too many samples are read from the FIFO.
//!
//! \return Returns zero if there was not an underflow, and non-zero if there
//! was.
@ -683,8 +692,8 @@ ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an underflow condition on one of the sample sequences. The
//! underflow condition must be cleared in order to detect a subsequent
//! This function clears an underflow condition on one of the sample sequencers.
//! The underflow condition must be cleared in order to detect a subsequent
//! underflow condition (it otherwise causes no harm).
//!
//! \return None.
@ -713,12 +722,12 @@ ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer. The number of samples available in the hardware
//! FIFO are copied into the buffer, which is assumed to be large enough to
//! hold that many samples. This will only return the samples that are
//! presently available, which may not be the entire sample sequence if it is
//! in the process of being executed.
//! This function copies data from the specified sample sequencer output FIFO
//! to a memory resident buffer. The number of samples available in the
//! hardware FIFO are copied into the buffer, which is assumed to be large
//! enough to hold that many samples. This function only returns the samples
//! that are presently available, which may not be the entire sample sequence
//! if it is in the process of being executed.
//!
//! \return Returns the number of samples copied to the buffer.
//
@ -794,8 +803,8 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Generate a processor trigger for this sample sequence.
//
HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) |
(1 << (ulSequenceNum & 0xf)));
HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) |
(1 << (ulSequenceNum & 0xf)));
}
//*****************************************************************************
@ -905,6 +914,13 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf00) >> 8) << ulStep));
//
// Set the control value for this step.
//
@ -936,9 +952,9 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer with software oversampling applied. The requested
//! number of samples are copied into the data buffer; if there are not enough
//! samples in the hardware FIFO to satisfy this many oversampled data items
//! then incorrect results will be returned. It is the caller's responsibility
//! to read only the samples that are available and wait until enough data is
//! samples in the hardware FIFO to satisfy this many oversampled data items,
//! then incorrect results are returned. It is the caller's responsibility to
//! read only the samples that are available and wait until enough data is
//! available, for example as a result of receiving an interrupt.
//!
//! \return None.
@ -999,21 +1015,18 @@ ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input. Six
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
//! Specifying an oversampling factor of zero will disable hardware
//! Specifying an oversampling factor of zero disables hardware
//! oversampling.
//!
//! Hardware oversampling applies uniformly to all sample sequencers. It does
//! not reduce the depth of the sample sequencers like the software
//! oversampling APIs; each sample written into the sample sequence FIFO is a
//! oversampling APIs; each sample written into the sample sequencer FIFO is a
//! fully oversampled analog input reading.
//!
//! Enabling hardware averaging increases the precision of the ADC at the cost
//! of throughput. For example, enabling 4x oversampling reduces the
//! throughput of a 250 Ksps ADC to 62.5 Ksps.
//!
//! \note Hardware oversampling is available beginning with Rev C0 of the
//! Stellaris microcontroller.
//!
//! \return None.
//
//*****************************************************************************
@ -1051,7 +1064,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! This function configures a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
//! \b ADC_COMP_INT_xxx values.
//!
@ -1178,7 +1191,7 @@ ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
//!
//! Because the digital comparator uses current and previous ADC values, this
//! function is provide to allow the comparator to be reset to its initial
//! function allows the comparator to be reset to its initial
//! value to prevent stale data from being used when a sequence is enabled.
//!
//! \return None.
@ -1272,8 +1285,8 @@ ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//!
//! \param ulBase is the base address of the ADC module.
//!
//! This returns the digitial comparator interrupt status bits. This status
//! is sequence agnostic.
//! This function returns the digitial comparator interrupt status bits. This
//! status is sequence agnostic.
//!
//! \return The current comparator interrupt status.
//
@ -1326,10 +1339,12 @@ ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
//! \param ulRef is the reference to use.
//!
//! The ADC reference is set as specified by \e ulRef. It must be one of
//! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference.
//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and
//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then a 3V
//! reference must be supplied to the AVREF pin.
//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V
//! reference is used and no external reference is needed. If
//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external referece
//! must be supplied to the AVREF pin.
//!
//! \note The ADC reference can only be selected on parts that have an external
//! reference. Consult the data sheet for your part to determine if there is
@ -1345,12 +1360,13 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V));
ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V) ||
(ulRef == ADC_REF_EXT_1V));
//
// Set the reference.
//
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) |
ulRef;
}
@ -1360,8 +1376,8 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
//!
//! \param ulBase is the base address of the ADC module.
//!
//! Returns the value of the ADC reference setting. The returned value will be
//! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V.
//! Returns the value of the ADC reference setting. The returned value is one
//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
//!
//! \note The value returned by this function is only meaningful if used on a
//! part that is capable of using an external reference. Consult the data
@ -1381,7 +1397,71 @@ ADCReferenceGet(unsigned long ulBase)
//
// Return the value of the reference.
//
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M);
}
//*****************************************************************************
//
//! Selects the ADC resolution.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulResolution is the ADC bit resolution.
//!
//! The ADC resolution is set as specified by \e ulResolution. It must be one
//! of \b ADC_RES_12BIT or \b ADC_RES_10BIT.
//!
//! \note The ADC resolution can only be set on parts that are capable of
//! changing ADC resolution mode. Consult the data sheet for your part to
//! determine if it is capable of operating in more than one resolution mode.
//!
//! \return None.
//
//*****************************************************************************
void
ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT((ulResolution == ADC_RES_10BIT) || (ulResolution == ADC_RES_12BIT));
//
// Set the resolution.
//
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) |
ulResolution;
}
//*****************************************************************************
//
//! Gets the setting of ADC resolution.
//!
//! \param ulBase is the base address of the ADC module.
//!
//! The ADC resolution is returned as one of \b ADC_RES_12BIT or
//! \b ADC_RES_10BIT.
//!
//! \note The value returned by this function is only meaningful if used on a
//! part that is capable of changing ADC resolution mode. Consult the
//! data sheet for your part to determine if it is capable of operating in
//! more than one resolution mode.
//!
//! \return The current setting of the ADC resolution.
//
//*****************************************************************************
unsigned long
ADCResolutionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
//
// Get the resolution and return it to the caller.
//
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES);
}
//*****************************************************************************

23
bsp/lm3s8962/Libraries/driverlib/adc.h
View File

@ -2,7 +2,7 @@
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -80,6 +80,14 @@ extern "C"
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
@ -173,6 +181,15 @@ extern "C"
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
//*****************************************************************************
//
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
//
//*****************************************************************************
#define ADC_RES_10BIT 0x00000000 // 10-bit resolution
#define ADC_RES_12BIT 0x00000010 // 12-bit resolution
//*****************************************************************************
//
@ -243,6 +260,8 @@ extern void ADCComparatorIntClear(unsigned long ulBase,
unsigned long ulStatus);
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
extern unsigned long ADCReferenceGet(unsigned long ulBase);
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
extern unsigned long ADCResolutionGet(unsigned long ulBase);
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);

308
bsp/lm3s8962/Libraries/driverlib/can.c
View File

@ -2,7 +2,7 @@
//
// can.c - Driver for the CAN module.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -151,8 +151,8 @@ CANBaseValid(unsigned long ulBase)
//!
//! \param ulBase is the base address of the selected CAN controller
//!
//! Given a CAN controller base address, returns the corresponding interrupt
//! number.
//! Given a CAN controller base address, this function returns the
//! corresponding interrupt number.
//!
//! This function replaces the original CANGetIntNumber() API and performs the
//! same actions. A macro is provided in <tt>can.h</tt> to map the original
@ -233,7 +233,7 @@ CANIntNumberGet(unsigned long ulBase)
static unsigned long
CANRegRead(unsigned long ulRegAddress)
{
volatile int iDelay;
volatile unsigned long ulDelay;
unsigned long ulRetVal;
unsigned long ulIntNumber;
unsigned long ulReenableInts;
@ -271,7 +271,7 @@ CANRegRead(unsigned long ulRegAddress)
//
// This delay is necessary for the CAN have the correct data on the bus.
//
for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++)
{
}
@ -317,7 +317,7 @@ CANRegRead(unsigned long ulRegAddress)
static void
CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
{
volatile int iDelay;
volatile unsigned long ulDelay;
//
// Trigger the initial write to the CAN controller. The value will not make
@ -328,7 +328,7 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
//
// Delay to allow the CAN controller to receive the new data.
//
for(iDelay = 0; iDelay < CAN_RW_DELAY; iDelay++)
for(ulDelay = 0; ulDelay < CAN_RW_DELAY; ulDelay++)
{
}
}
@ -360,29 +360,29 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
//
//*****************************************************************************
static void
CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister,
unsigned long ulSize)
{
int iIdx;
unsigned long ulValue;
unsigned long ulIdx, ulValue;
//
// Loop always copies 1 or 2 bytes per iteration.
//
for(iIdx = 0; iIdx < iSize; )
for(ulIdx = 0; ulIdx < ulSize; )
{
//
// Write out the data 16 bits at a time since this is how the registers
// are aligned in memory.
//
ulValue = pucData[iIdx++];
ulValue = pucData[ulIdx++];
//
// Only write the second byte if needed otherwise it will be zero.
//
if(iIdx < iSize)
if(ulIdx < ulSize)
{
ulValue |= (pucData[iIdx++] << 8);
ulValue |= (pucData[ulIdx++] << 8);
}
CANRegWrite((unsigned long)(pulRegister++), ulValue);
}
@ -415,15 +415,15 @@ CANDataRegWrite(unsigned char *pucData, unsigned long *pulRegister, int iSize)
//
//*****************************************************************************
static void
CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister,
unsigned long ulSize)
{
int iIdx;
unsigned long ulValue;
unsigned long ulIdx, ulValue;
//
// Loop always copies 1 or 2 bytes per iteration.
//
for(iIdx = 0; iIdx < iSize; )
for(ulIdx = 0; ulIdx < ulSize; )
{
//
// Read out the data 16 bits at a time since this is how the registers
@ -434,14 +434,14 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
//
// Store the first byte.
//
pucData[iIdx++] = (unsigned char)ulValue;
pucData[ulIdx++] = (unsigned char)ulValue;
//
// Only read the second byte if needed.
//
if(iIdx < iSize)
if(ulIdx < ulSize)
{
pucData[iIdx++] = (unsigned char)(ulValue >> 8);
pucData[ulIdx++] = (unsigned char)(ulValue >> 8);
}
}
}
@ -465,7 +465,7 @@ CANDataRegRead(unsigned char *pucData, unsigned long *pulRegister, int iSize)
void
CANInit(unsigned long ulBase)
{
int iMsg;
unsigned long ulMsg;
//
// Check the arguments.
@ -499,7 +499,7 @@ CANInit(unsigned long ulBase)
//
// Loop through to program all 32 message objects
//
for(iMsg = 1; iMsg <= 32; iMsg++)
for(ulMsg = 1; ulMsg <= 32; ulMsg++)
{
//
// Wait for busy bit to clear
@ -511,7 +511,7 @@ CANInit(unsigned long ulBase)
//
// Initiate programming the message object
//
CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg);
}
//
@ -524,7 +524,7 @@ CANInit(unsigned long ulBase)
//
// Loop through to program all 32 message objects
//
for(iMsg = 1; iMsg <= 32; iMsg++)
for(ulMsg = 1; ulMsg <= 32; ulMsg++)
{
//
// Wait for busy bit to clear.
@ -536,7 +536,7 @@ CANInit(unsigned long ulBase)
//
// Initiate programming the message object
//
CANRegWrite(ulBase + CAN_O_IF1CRQ, iMsg);
CANRegWrite(ulBase + CAN_O_IF1CRQ, ulMsg);
}
//
@ -552,7 +552,7 @@ CANInit(unsigned long ulBase)
//! \param ulBase is the base address of the CAN controller to enable.
//!
//! Enables the CAN controller for message processing. Once enabled, the
//! controller will automatically transmit any pending frames, and process any
//! controller automatically transmits any pending frames, and processes any
//! received frames. The controller can be stopped by calling CANDisable().
//! Prior to calling CANEnable(), CANInit() should have been called to
//! initialize the controller and the CAN bus clock should be configured by
@ -583,7 +583,7 @@ CANEnable(unsigned long ulBase)
//! \param ulBase is the base address of the CAN controller to disable.
//!
//! Disables the CAN controller for message processing. When disabled, the
//! controller will no longer automatically process data on the CAN bus. The
//! controller no longer automatically processes data on the CAN bus. The
//! controller can be restarted by calling CANEnable(). The state of the CAN
//! controller and the message objects in the controller are left as they were
//! before this call was made.
@ -614,7 +614,7 @@ CANDisable(unsigned long ulBase)
//! \param pClkParms is a pointer to a structure to hold the timing parameters.
//!
//! This function reads the current configuration of the CAN controller bit
//! clock timing, and stores the resulting information in the structure
//! clock timing and stores the resulting information in the structure
//! supplied by the caller. Refer to CANBitTimingSet() for the meaning of the
//! values that are returned in the structure pointed to by \e pClkParms.
//!
@ -628,7 +628,7 @@ CANDisable(unsigned long ulBase)
void
CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
{
unsigned int uBitReg;
unsigned long ulBitReg;
//
// Check the arguments.
@ -639,53 +639,53 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
//
// Read out all the bit timing values from the CAN controller registers.
//
uBitReg = CANRegRead(ulBase + CAN_O_BIT);
ulBitReg = CANRegRead(ulBase + CAN_O_BIT);
//
// Set the phase 2 segment.
//
pClkParms->uPhase2Seg =
((uBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1;
pClkParms->ulPhase2Seg =
((ulBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1;
//
// Set the phase 1 segment.
//
pClkParms->uSyncPropPhase1Seg =
((uBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1;
pClkParms->ulSyncPropPhase1Seg =
((ulBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1;
//
// Set the synchronous jump width.
//
pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1;
pClkParms->ulSJW = ((ulBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1;
//
// Set the pre-divider for the CAN bus bit clock.
//
pClkParms->uQuantumPrescaler =
((uBitReg & CAN_BIT_BRP_M) |
pClkParms->ulQuantumPrescaler =
((ulBitReg & CAN_BIT_BRP_M) |
((CANRegRead(ulBase + CAN_O_BRPE) & CAN_BRPE_BRPE_M) << 6)) + 1;
}
//*****************************************************************************
//
//! This function is used to set the CAN bit timing values to a nominal setting
//! based on a desired bit rate.
//! Sets the CAN bit timing values to a nominal setting based on a desired
//! bit rate.
//!
//! \param ulBase is the base address of the CAN controller.
//! \param ulSourceClock is the system clock for the device in Hz.
//! \param ulBitRate is the desired bit rate.
//!
//! This function will set the CAN bit timing for the bit rate passed in the
//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Since the
//! CAN clock is based off of the system clock the calling function should pass
//! This function sets the CAN bit timing for the bit rate passed in the
//! \e ulBitRate parameter based on the \e ulSourceClock parameter. Because the
//! CAN clock is based off of the system clock, the calling function should pass
//! in the source clock rate either by retrieving it from SysCtlClockGet() or
//! using a specific value in Hz. The CAN bit timing is calculated assuming a
//! minimal amount of propagation delay, which will work for most cases where
//! minimal amount of propagation delay, which works for most cases where
//! the network length is short. If tighter timing requirements or longer
//! network lengths are needed, then the CANBitTimingSet() function is
//! available for full customization of all of the CAN bit timing values.
//! Since not all bit rates can be matched exactly, the bit rate is set to the
//! value closest to the desired bit rate without being higher than the
//! Because not all bit rates can be matched exactly, the bit rate is set to
//! the value closest to the desired bit rate without being higher than the
//! \e ulBitRate value.
//!
//! \note On some devices the source clock is fixed at 8MHz so the
@ -826,27 +826,27 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
//! Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and
//! the Synchronization Jump Width. The values for Propagation and Phase
//! Buffer 1 segments are derived from the combination
//! \e pClkParms->uSyncPropPhase1Seg parameter. Phase Buffer 2 is determined
//! from the \e pClkParms->uPhase2Seg parameter. These two parameters, along
//! with \e pClkParms->uSJW are based in units of bit time quanta. The actual
//! quantum time is determined by the \e pClkParms->uQuantumPrescaler value,
//! \e pClkParms->ulSyncPropPhase1Seg parameter. Phase Buffer 2 is determined
//! from the \e pClkParms->ulPhase2Seg parameter. These two parameters, along
//! with \e pClkParms->ulSJW are based in units of bit time quanta. The actual
//! quantum time is determined by the \e pClkParms->ulQuantumPrescaler value,
//! which specifies the divisor for the CAN module clock.
//!
//! The total bit time, in quanta, will be the sum of the two Seg parameters,
//! The total bit time, in quanta, is the sum of the two Seg parameters,
//! as follows:
//!
//! bit_time_q = uSyncPropPhase1Seg + uPhase2Seg + 1
//! bit_time_q = ulSyncPropPhase1Seg + ulPhase2Seg + 1
//!
//! Note that the Sync_Seg is always one quantum in duration, and will be added
//! Note that the Sync_Seg is always one quantum in duration, and is added
//! to derive the correct duration of Prop_Seg and Phase1_Seg.
//!
//! The equation to determine the actual bit rate is as follows:
//!
//! CAN Clock /
//! ((\e uSyncPropPhase1Seg + \e uPhase2Seg + 1) * (\e uQuantumPrescaler))
//! ((\e ulSyncPropPhase1Seg + \e ulPhase2Seg + 1) * (\e ulQuantumPrescaler))
//!
//! This means that with \e uSyncPropPhase1Seg = 4, \e uPhase2Seg = 1,
//! \e uQuantumPrescaler = 2 and an 8 MHz CAN clock, that the bit rate will be
//! Thus with \e ulSyncPropPhase1Seg = 4, \e ulPhase2Seg = 1,
//! \e ulQuantumPrescaler = 2 and an 8 MHz CAN clock, the bit rate is
//! (8 MHz) / ((5 + 2 + 1) * 2) or 500 Kbit/sec.
//!
//! This function replaces the original CANSetBitTiming() API and performs the
@ -859,8 +859,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
void
CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
{
unsigned int uBitReg;
unsigned int uSavedInit;
unsigned long ulBitReg, ulSavedInit;
//
// Check the arguments.
@ -871,63 +870,63 @@ CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
//
// The phase 1 segment must be in the range from 2 to 16.
//
ASSERT((pClkParms->uSyncPropPhase1Seg >= 2) &&
(pClkParms->uSyncPropPhase1Seg <= 16));
ASSERT((pClkParms->ulSyncPropPhase1Seg >= 2) &&
(pClkParms->ulSyncPropPhase1Seg <= 16));
//
// The phase 2 segment must be in the range from 1 to 8.
//
ASSERT((pClkParms->uPhase2Seg >= 1) && (pClkParms->uPhase2Seg <= 8));
ASSERT((pClkParms->ulPhase2Seg >= 1) && (pClkParms->ulPhase2Seg <= 8));
//
// The synchronous jump windows must be in the range from 1 to 4.
//
ASSERT((pClkParms->uSJW >= 1) && (pClkParms->uSJW <= 4));
ASSERT((pClkParms->ulSJW >= 1) && (pClkParms->ulSJW <= 4));
//
// The CAN clock pre-divider must be in the range from 1 to 1024.
//
ASSERT((pClkParms->uQuantumPrescaler <= 1024) &&
(pClkParms->uQuantumPrescaler >= 1));
ASSERT((pClkParms->ulQuantumPrescaler <= 1024) &&
(pClkParms->ulQuantumPrescaler >= 1));
//
// To set the bit timing register, the controller must be placed in init
// mode (if not already), and also configuration change bit enabled. State
// of the init bit should be saved so it can be restored at the end.
//
uSavedInit = CANRegRead(ulBase + CAN_O_CTL);
CANRegWrite(ulBase + CAN_O_CTL, uSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
ulSavedInit = CANRegRead(ulBase + CAN_O_CTL);
CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit | CAN_CTL_INIT | CAN_CTL_CCE);
//
// Set the bit fields of the bit timing register according to the parms.
//
uBitReg = (((pClkParms->uPhase2Seg - 1) << CAN_BIT_TSEG2_S) &
CAN_BIT_TSEG2_M);
uBitReg |= (((pClkParms->uSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) &
CAN_BIT_TSEG1_M);
uBitReg |= ((pClkParms->uSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M;
uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M;
CANRegWrite(ulBase + CAN_O_BIT, uBitReg);
ulBitReg = (((pClkParms->ulPhase2Seg - 1) << CAN_BIT_TSEG2_S) &
CAN_BIT_TSEG2_M);
ulBitReg |= (((pClkParms->ulSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) &
CAN_BIT_TSEG1_M);
ulBitReg |= ((pClkParms->ulSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M;
ulBitReg |= (pClkParms->ulQuantumPrescaler - 1) & CAN_BIT_BRP_M;
CANRegWrite(ulBase + CAN_O_BIT, ulBitReg);
//
// Set the divider upper bits in the extension register.
//
CANRegWrite(ulBase + CAN_O_BRPE,
((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
((pClkParms->ulQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
//
// Clear the config change bit, and restore the init bit.
//
uSavedInit &= ~CAN_CTL_CCE;
ulSavedInit &= ~CAN_CTL_CCE;
//
// If Init was not set before, then clear it.
//
if(uSavedInit & CAN_CTL_INIT)
if(ulSavedInit & CAN_CTL_INIT)
{
uSavedInit &= ~CAN_CTL_INIT;
ulSavedInit &= ~CAN_CTL_INIT;
}
CANRegWrite(ulBase + CAN_O_CTL, uSavedInit);
CANRegWrite(ulBase + CAN_O_CTL, ulSavedInit);
}
//*****************************************************************************
@ -988,7 +987,7 @@ CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//! \param ulBase is the base address of the controller.
//!
//! This function unregisters the previously registered interrupt handler and
//! disables the interrupt on the interrupt controller.
//! disables the interrupt in the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -1011,15 +1010,15 @@ CANIntUnregister(unsigned long ulBase)
//
ulIntNumber = CANIntNumberGet(ulBase);
//
// Register the interrupt handler.
//
IntUnregister(ulIntNumber);
//
// Disable the CAN interrupt.
//
IntDisable(ulIntNumber);
//
// Register the interrupt handler.
//
IntUnregister(ulIntNumber);
}
//*****************************************************************************
@ -1029,8 +1028,8 @@ CANIntUnregister(unsigned long ulBase)
//! \param ulBase is the base address of the CAN controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables specific interrupt sources of the CAN controller. Only enabled
//! sources will cause a processor interrupt.
//! This function enables specific interrupt sources of the CAN controller.
//! Only enabled sources cause a processor interrupt.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
@ -1044,7 +1043,7 @@ CANIntUnregister(unsigned long ulBase)
//! an interrupt, that message object must have interrupts enabled (see
//! CANMessageSet()). \b CAN_INT_ERROR will generate an interrupt if the
//! controller enters the ``bus off'' condition, or if the error counters reach
//! a limit. \b CAN_INT_STATUS will generate an interrupt under quite a few
//! a limit. \b CAN_INT_STATUS generates an interrupt under quite a few
//! status conditions and may provide more interrupts than the application
//! needs to handle. When an interrupt occurs, use CANIntStatus() to determine
//! the cause.
@ -1107,19 +1106,19 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase is the base address of the CAN controller.
//! \param eIntStsReg indicates which interrupt status register to read
//!
//! Returns the value of one of two interrupt status registers. The interrupt
//! status register read is determined by the \e eIntStsReg parameter, which
//! can have one of the following values:
//! This function returns the value of one of two interrupt status registers.
//! The interrupt status register read is determined by the \e eIntStsReg
//! parameter, which can have one of the following values:
//!
//! - \b CAN_INT_STS_CAUSE - indicates the cause of the interrupt
//! - \b CAN_INT_STS_OBJECT - indicates pending interrupts of all message
//! objects
//!
//! \b CAN_INT_STS_CAUSE returns the value of the controller interrupt register
//! and indicates the cause of the interrupt. It will be a value of
//! and indicates the cause of the interrupt. The value returned is
//! \b CAN_INT_INTID_STATUS if the cause is a status interrupt. In this case,
//! the status register should be read with the CANStatusGet() function.
//! Calling this function to read the status will also clear the status
//! Calling this function to read the status also clears the status
//! interrupt. If the value of the interrupt register is in the range 1-32,
//! then this indicates the number of the highest priority message object that
//! has an interrupt pending. The message object interrupt can be cleared by
@ -1129,9 +1128,9 @@ CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! cleared before returning from the interrupt.
//!
//! \b CAN_INT_STS_OBJECT returns a bit mask indicating which message objects
//! have pending interrupts. This can be used to discover all of the pending
//! interrupts at once, as opposed to repeatedly reading the interrupt register
//! by using \b CAN_INT_STS_CAUSE.
//! have pending interrupts. This value can be used to discover all of the
//! pending interrupts at once, as opposed to repeatedly reading the interrupt
//! register by using \b CAN_INT_STS_CAUSE.
//!
//! \return Returns the value of one of the interrupt status registers.
//
@ -1185,6 +1184,7 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
break;
}
}
//
// Return the interrupt status value
//
@ -1205,21 +1205,21 @@ CANIntStatus(unsigned long ulBase, tCANIntStsReg eIntStsReg)
//! - 1-32 - Clears the specified message object interrupt
//!
//! It is not necessary to use this function to clear an interrupt. This
//! should only be used if the application wants to clear an interrupt source
//! without taking the normal interrupt action.
//! function should only be used if the application wants to clear an interrupt
//! source without taking the normal interrupt action.
//!
//! Normally, the status interrupt is cleared by reading the controller status
//! using CANStatusGet(). A specific message object interrupt is normally
//! cleared by reading the message object using CANMessageGet().
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -1277,9 +1277,9 @@ CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
//! \param ulBase is the base address of the CAN controller.
//! \param bAutoRetry enables automatic retransmission.
//!
//! Enables or disables automatic retransmission of messages with detected
//! errors. If \e bAutoRetry is \b true, then automatic retransmission is
//! enabled, otherwise it is disabled.
//! This function enables or disables automatic retransmission of messages with
//! detected errors. If \e bAutoRetry is \b true, then automatic retransmission
//! is enabled, otherwise it is disabled.
//!
//! \return None.
//
@ -1326,7 +1326,7 @@ CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry)
//!
//! \param ulBase is the base address of the CAN controller.
//!
//! Reads the current setting for the automatic retransmission in the CAN
//! This function reads the current setting for automatic retransmission in the CAN
//! controller and returns it to the caller.
//!
//! \return Returns \b true if automatic retransmission is enabled, \b false
@ -1365,7 +1365,8 @@ CANRetryGet(unsigned long ulBase)
//! \param ulBase is the base address of the CAN controller.
//! \param eStatusReg is the status register to read.
//!
//! Reads a status register of the CAN controller and returns it to the caller.
//! This function reads a status register of the CAN controller and returns it
//! to the caller.
//! The different status registers are:
//!
//! - \b CAN_STS_CONTROL - the main controller status
@ -1374,9 +1375,9 @@ CANRetryGet(unsigned long ulBase)
//! - \b CAN_STS_MSGVAL - bit mask of objects with valid configuration
//!
//! When reading the main controller status register, a pending status
//! interrupt will be cleared. This should be used in the interrupt handler
//! for the CAN controller if the cause is a status interrupt. The controller
//! status register fields are as follows:
//! interrupt is cleared. This parameter should be used in the interrupt
//! handler for the CAN controller if the cause is a status interrupt. The
//! controller status register fields are as follows:
//!
//! - \b CAN_STATUS_BUS_OFF - controller is in bus-off condition
//! - \b CAN_STATUS_EWARN - an error counter has reached a limit of at least 96
@ -1396,20 +1397,21 @@ CANRetryGet(unsigned long ulBase)
//! dominant mode
//! - \b CAN_STATUS_LEC_CRC - CRC error in received message
//!
//! The remaining status registers are 32-bit bit maps to the message objects.
//! They can be used to quickly obtain information about the status of all the
//! message objects without needing to query each one. They contain the
//! following information:
//! The remaining status registers consist of 32-bit-wide bit maps to the
//! message objects. They can be used to quickly obtain information about the
//! status of all the message objects without needing to query each one. They
//! contain the following information:
//!
//! - \b CAN_STS_TXREQUEST - if a message object's TxRequest bit is set, that
//! means that a transmission is pending on that object. The application can
//! use this to determine which objects are still waiting to send a message.
//! - \b CAN_STS_NEWDAT - if a message object's NewDat bit is set, that means
//! that a new message has been received in that object, and has not yet been
//! picked up by the host application
//! - \b CAN_STS_MSGVAL - if a message object's MsgVal bit is set, that means
//! it has a valid configuration programmed. The host application can use this
//! to determine which message objects are empty/unused.
//! - \b CAN_STS_TXREQUEST - if a message object's TXRQST bit is set, a
//! transmission is pending on that object. The application can use this
//! information to determine which objects are still waiting to send a
//! message.
//! - \b CAN_STS_NEWDAT - if a message object's NEWDAT bit is set, a new
//! message has been received in that object, and has not yet been picked up
//! by the host application
//! - \b CAN_STS_MSGVAL - if a message object's MSGVAL bit is set, the object
//! has a valid configuration programmed. The host application can use this
//! information to determine which message objects are empty/unused.
//!
//! \return Returns the value of the status register.
//
@ -1488,14 +1490,14 @@ CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg)
//! \param pulRxCount is a pointer to storage for the receive error counter.
//! \param pulTxCount is a pointer to storage for the transmit error counter.
//!
//! Reads the error counter register and returns the transmit and receive error
//! counts to the caller along with a flag indicating if the controller receive
//! counter has reached the error passive limit. The values of the receive and
//! transmit error counters are returned through the pointers provided as
//! parameters.
//! This function reads the error counter register and returns the transmit and
//! receive error counts to the caller along with a flag indicating if the
//! controller receive counter has reached the error passive limit. The values
//! of the receive and transmit error counters are returned through the pointers
//! provided as parameters.
//!
//! After this call, \e *pulRxCount will hold the current receive error count
//! and \e *pulTxCount will hold the current transmit error count.
//! After this call, \e *pulRxCount holds the current receive error count
//! and \e *pulTxCount holds the current transmit error count.
//!
//! \return Returns \b true if the receive error count has reached the error
//! passive limit, and \b false if the error count is below the error passive
@ -1542,10 +1544,10 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
//! \param eMsgType indicates the type of message for this object.
//!
//! This function is used to configure any one of the 32 message objects in the
//! CAN controller. A message object can be configured as any type of CAN
//! message object as well as several options for automatic transmission and
//! reception. This call also allows the message object to be configured to
//! generate interrupts on completion of message receipt or transmission. The
//! CAN controller. A message object can be configured to be any type of CAN
//! message object as well as to use automatic transmission and reception.
//! This call also allows the message object to be configured to generate
//! interrupts on completion of message receipt or transmission. The
//! message object can also be configured with a filter/mask so that actions
//! are only taken when a message that meets certain parameters is seen on the
//! CAN bus.
@ -1570,13 +1572,13 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to enable interrupt on receipt.
//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable filtering based on the
//! identifier mask specified by \e ulMsgIDMask.
//! - \e ulMsgLen - the number of bytes in the message data. This should be
//! non-zero even for a remote frame; it should match the expected bytes of the
//! data responding data frame.
//! - \e ulMsgLen - the number of bytes in the message data. This parameter
//! should be non-zero even for a remote frame; it should match the expected
//! bytes of data in the responding data frame.
//! - \e pucMsgData - points to a buffer containing up to 8 bytes of data for a
//! data frame.
//!
//! \b Example: To send a data frame or remote frame(in response to a remote
//! \b Example: To send a data frame or remote frame (in response to a remote
//! request), take the following steps:
//!
//! -# Set \e eMsgType to \b MSG_OBJ_TYPE_TX.
@ -1598,7 +1600,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
//! -# Set \e pMsgObject->ulFlags as follows:
//! - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame
//! is received.
//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
//! - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier-based filtering.
//! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data
//! frame.
//! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this
@ -1606,7 +1608,7 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
//! -# Call this function with \e ulObjID set to one of the 32 object buffers.
//!
//! If you specify a message object buffer that already contains a message
//! definition, it will be overwritten.
//! definition, it is overwritten.
//!
//! \return None.
//
@ -1928,11 +1930,9 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl);
//
// Transfer the message object to the message object specifiec by ulObjID.
// Transfer the message object to the message object specified by ulObjID.
//
CANRegWrite(ulBase + CAN_O_IF1CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
return;
}
//*****************************************************************************
@ -1946,27 +1946,27 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
//! cleared.
//!
//! This function is used to read the contents of one of the 32 message objects
//! in the CAN controller, and return it to the caller. The data returned is
//! in the CAN controller and return it to the caller. The data returned is
//! stored in the fields of the caller-supplied structure pointed to by
//! \e pMsgObject. The data consists of all of the parts of a CAN message,
//! plus some control and status information.
//!
//! Normally this is used to read a message object that has received and stored
//! a CAN message with a certain identifier. However, this could also be used
//! to read the contents of a message object in order to load the fields of the
//! structure in case only part of the structure needs to be changed from a
//! previous setting.
//! Normally, this function is used to read a message object that has received
//! and stored a CAN message with a certain identifier. However, this function
//! could also be used to read the contents of a message object in order to
//! load the fields of the structure in case only part of the structure must
//! be changed from a previous setting.
//!
//! When using CANMessageGet, all of the same fields of the structure are
//! When using CANMessageGet(), all of the same fields of the structure are
//! populated in the same way as when the CANMessageSet() function is used,
//! with the following exceptions:
//!
//! \e pMsgObject->ulFlags:
//!
//! - \b MSG_OBJ_NEW_DATA indicates if this is new data since the last time it
//! - \b MSG_OBJ_NEW_DATA indicates if this data is new since the last time it
//! was read
//! - \b MSG_OBJ_DATA_LOST indicates that at least one message was received on
//! this message object, and not read by the host before being overwritten.
//! this message object and not read by the host before being overwritten.
//!
//! \return None.
//
@ -2206,8 +2206,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
//! \param ulObjID is the message object number to disable (1-32).
//!
//! This function frees the specified message object from use. Once a message
//! object has been ``cleared,'' it will no longer automatically send or
//! receive messages, or generate interrupts.
//! object has been ``cleared,'' it no longer automatically sends or
//! receives messages, nor does it generate interrupts.
//!
//! \return None.
//

12
bsp/lm3s8962/Libraries/driverlib/can.h
View File

@ -2,7 +2,7 @@
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -179,25 +179,25 @@ typedef struct
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
unsigned long ulSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
unsigned long ulPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
unsigned long ulSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
unsigned long ulQuantumPrescaler;
}
tCANBitClkParms;

44
bsp/lm3s8962/Libraries/driverlib/comp.c
View File

@ -2,7 +2,7 @@
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -45,8 +45,8 @@
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b COMP_TRIG_xxx,
//! This function configures a comparator. The \e ulConfig parameter is the
//! result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
@ -117,8 +117,8 @@ ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
//! \param ulBase is the base address of the comparator module.
//! \param ulRef is the desired reference voltage.
//!
//! This function will set the internal reference voltage value. The voltage
//! is specified as one of the following values:
//! This function sets the internal reference voltage value. The voltage is
//! specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
@ -212,9 +212,9 @@ ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This sets the handler to be called when the comparator interrupt occurs.
//! This will enable the interrupt in the interrupt controller; it is the
//! interrupt-handler's responsibility to clear the interrupt source via
//! This function sets the handler to be called when the comparator interrupt occurs
//! and enables the interrupt in the interrupt controller. It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
@ -256,9 +256,9 @@ ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function will clear the handler to be called when a comparator
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//! This function clears the handler to be called when a comparator interrupt
//! occurs. This function also masks off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -299,7 +299,7 @@ ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
//! \param ulComp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
@ -328,7 +328,7 @@ ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
//! \param ulComp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
@ -358,7 +358,7 @@ ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the comparator. Either the raw or
//! This function returns the interrupt status for the comparator. Either the raw or
//! the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
@ -397,18 +397,18 @@ ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
//! \param ulComp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! must be done in the interrupt handler to keep it from being called again
//! immediately upon exit. Note that for a level triggered interrupt, the
//! interrupt cannot be cleared until it stops asserting.
//! fucntion must be called in the interrupt handler to keep the handler from
//! being called again immediately upon exit. Note that for a level-triggered
//! interrupt, the interrupt cannot be cleared until it stops asserting.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//

4
bsp/lm3s8962/Libraries/driverlib/comp.h
View File

@ -2,7 +2,7 @@
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

7
bsp/lm3s8962/Libraries/driverlib/cpu.c
View File

@ -3,7 +3,7 @@
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -19,7 +19,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -360,8 +360,7 @@ CPUbasepriSet(unsigned long ulNewBasepri)
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" bx lr\n");
__asm(" msr BASEPRI, r0\n");
}
#endif

4
bsp/lm3s8962/Libraries/driverlib/cpu.h
View File

@ -2,7 +2,7 @@
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

4
bsp/lm3s8962/Libraries/driverlib/debug.h
View File

@ -2,7 +2,7 @@
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

1110
bsp/lm3s8962/Libraries/driverlib/eeprom.c Normal file
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File diff suppressed because it is too large Load Diff

264
bsp/lm3s8962/Libraries/driverlib/eeprom.h Normal file
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@ -0,0 +1,264 @@
//*****************************************************************************
//
// eeprom.h - Prototypes for the EEPROM driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __EEPROM_H__
#define __EEPROM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup eeprom_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Values returned by EEPROMInit.
//
//*****************************************************************************
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! no previous write operations were interrupted by a reset event and that the
//! EEPROM peripheral is ready for use.
//
#define EEPROM_INIT_OK 0
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! a previous data or protection write operation was interrupted by a reset
//! event. The EEPROM peripheral has recovered its state but the last write
//! operation may have been lost. The application must check the validity of
//! data it has written and retry any writes as required.
//
#define EEPROM_INIT_RETRY 1
//
//! This value may be returned from a call to EEPROMInit(). It indicates that a
//! previous data or protection write operation was interrupted by a reset
//! event and that the EEPROM peripheral was unable to clean up after the
//! problem. This situation may be resolved with another reset or may be fatal
//! depending upon the cause of the problem. For example, if the voltage to
//! the part is unstable, retrying once the voltage has stabilized may clear
//! the error.
//
#define EEPROM_INIT_ERROR 2
//*****************************************************************************
//
// Error indicators returned by various EEPROM API calls. These will be ORed
// together into the final return code.
//
//*****************************************************************************
//
//! This return code bit indicates that the EEPROM programming state machine
//! failed to write a value due to the voltage level dropping below that
//! required for EEPROM programming. The operation may be retried once the
//! voltage stabilizes.
//
#define EEPROM_RC_INVPL 0x00000100
//
//! This return code bit indicates that an attempt was made to read from
//! the EEPROM while a write operation was in progress.
//
#define EEPROM_RC_WRBUSY 0x00000020
//
//! This return code bit indicates that an attempt was made to write a
//! value but the destination permissions disallow write operations. This
//! may be due to the destination block being locked, access protection set
//! to prohibit writes or an attempt to write a password when one is already
//! written.
//
#define EEPROM_RC_NOPERM 0x00000010
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently copying to or from the internal copy buffer to make room for
//! a newly written value. It is provided as a status indicator and does not
//! indicate an error.
//
#define EEPROM_RC_WKCOPY 0x00000008
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently erasing the internal copy buffer. It is provided as a
//! status indicator and does not indicate an error.
//
#define EEPROM_RC_WKERASE 0x00000004
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently working. No new write operations should be attempted until
//! this bit is clear.
//
#define EEPROM_RC_WORKING 0x00000001
//*****************************************************************************
//
// Values that can be passed to EEPROMBlockProtectSet() in the ulProtect
// parameter, and returned by EEPROMBlockProtectGet().
//
//*****************************************************************************
//
//! This bit may be ORed with the protection option passed to
//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It
//! restricts EEPROM access to threads running in supervisor mode and prevents
//! access to an EEPROM block when the CPU is in user mode.
//
#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read/write access when no password is set or when a password is set and
//! the block is unlocked, and read-only access when a password is set but
//! the block is locked.
//
#define EEPROM_PROT_RW_LRO_URW 0x00000000
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer neither
//! read nor write access unless it is protected by a password and unlocked.
//
#define EEPROM_PROT_NA_LNA_URW 0x00000001
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read-only access when no password is set or when a password is set and the
//! block is unlocked. When a password is set and the block is locked, neither
//! read nor write access is permitted.
//
#define EEPROM_PROT_RO_LNA_URO 0x00000002
//*****************************************************************************
//
//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
//! signaled.
//
//*****************************************************************************
#define EEPROM_INT_PROGRAM 0x00000004
//*****************************************************************************
//
//! Returns the EEPROM block number containing a given offset address.
//!
//! \param ulAddr is the linear, byte address of the EEPROM location whose
//! block number is to be returned. This is a zero-based offset from the start
//! of the EEPROM storage.
//!
//! This macro may be used to translate an EEPROM address offset into a
//! block number suitable for use in any of the driver's block protection
//! functions. The address provided is expressed as a byte offset from the
//! base of the EEPROM.
//!
//! \return Returns the zero-based block number which contains the passed
//! address.
//
//*****************************************************************************
#define EEPROMBlockFromAddr(ulAddr) ((ulAddr) >> 6)
//*****************************************************************************
//
//! Returns the offset address of the first word in an EEPROM block.
//!
//! \param ulBlock is the index of the EEPROM block whose first word address
//! is to be returned.
//!
//! This macro may be used to determine the address of the first word in a
//! given EEPROM block. The address returned is expressed as a byte offset
//! from the base of EEPROM storage.
//!
//! \return Returns the address of the first word in the given EEPROM block.
//
//*****************************************************************************
#define EEPROMAddrFromBlock(ulBlock) ((ulBlock) << 6)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long EEPROMInit(void);
extern unsigned long EEPROMSizeGet(void);
extern unsigned long EEPROMBlockCountGet(void);
extern void EEPROMRead(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgram(unsigned long *pulData,
unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgramNonBlocking(unsigned long ulData,
unsigned long ulAddress);
extern unsigned long EEPROMStatusGet(void);
extern unsigned long EEPROMMassErase(void);
extern unsigned long EEPROMBlockProtectGet(unsigned long ulBlock);
extern unsigned long EEPROMBlockProtectSet(unsigned long ulBlock,
unsigned long ulProtect);
extern unsigned long EEPROMBlockPasswordSet(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern unsigned long EEPROMBlockLock(unsigned long ulBlock);
extern unsigned long EEPROMBlockUnlock(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern void EEPROMBlockHide(unsigned long ulBlock);
extern void EEPROMIntEnable(unsigned long ulIntFlags);
extern void EEPROMIntDisable(unsigned long ulIntFlags);
extern unsigned long EEPROMIntStatus(tBoolean bMasked);
extern void EEPROMIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EEPROM_H__

178
bsp/lm3s8962/Libraries/driverlib/epi.c
View File

@ -2,7 +2,7 @@
//
// epi.c - Driver for the EPI module.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -50,9 +50,10 @@
//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
//! - \b EPI_MODE_SDRAM - use with SDRAM device
//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface
//! - \b EPI_MODE_DISABLE - disable the EPI module
//!
//! Selection of any of the above modes will enable the EPI module, except
//! Selection of any of the above modes enables the EPI module, except
//! for \b EPI_MODE_DISABLE which should be used to disable the module.
//!
//! \return None.
@ -68,6 +69,7 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
ASSERT((ulMode == EPI_MODE_GENERAL) ||
(ulMode == EPI_MODE_SDRAM) ||
(ulMode == EPI_MODE_HB8) ||
(ulMode == EPI_MODE_HB16) ||
(ulMode == EPI_MODE_DISABLE));
//
@ -84,15 +86,15 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
//! \param ulDivider is the value of the clock divider to be applied to
//! the external interface (0-65535).
//!
//! This functions sets the clock divider(s) that will be used to determine the
//! This function sets the clock divider(s) that is used to determine the
//! clock rate of the external interface. The \e ulDivider value is used to
//! derive the EPI clock rate from the system clock based upon the following
//! derive the EPI clock rate from the system clock based on the following
//! formula.
//!
//! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
//!
//! For example, a divider value of 1 results in an EPI clock rate of half
//! the system clock, value of 2 or 3 yield one quarter of the system clock and
//! the system clock, value of 2 or 3 yields one quarter of the system clock and
//! a value of 4 results in one sixth of the system clock rate.
//!
//! In cases where a dual chip select mode is in use and different clock rates
@ -213,16 +215,15 @@ EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
//! rate resulting from the divider in the lower 16 bits of the parameter passed
//! to EPIDividerSet().
//! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE,
//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL. \b EPI_HB8_CSCFG_CS
//! sets EPI30 to operate as a Chip Select (CSn) signal. When using this mode,
//! \b EPI_HB8_MODE_ADMUX must not be specified. \b EPI_HB8_CSCFG_ALE sets
//! EPI30 to operate as an address latch (ALE). \b EPI_HB8_CSCFG_DUAL_CS sets
//! EPI30 to operate as CS0n and EPI27 as CS1n with the asserted chip select
//! determined from the most significant address bit for the respective external
//! address map. \b EPI_HB8_CSCFG_DUAL_ALE sets EPI30 as an address latch (ALE),
//! EPI27 as CS0n and EPI26 as CS1n with the asserted chip select determined
//! from the most significant address bit for the respective external address
//! map.
//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL_CS.
//! \b EPI_HB8_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal.
//! \b EPI_HB8_CSCFG_ALE sets EPI30 to operate as an address latch (ALE).
//! \b EPI_HB8_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n
//! with the asserted chip select determined from the most significant address
//! bit for the respective external address map. \b EPI_HB8_CSCFG_ALE_DUAL_CS
//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with
//! the asserted chip select determined from the most significant address bit
//! for the respective external address map.
//!
//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
@ -248,7 +249,9 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//
HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ?
EPI_HB8CFG2_WORD : 0) |
((ulConfig & EPI_HB8_CSBAUD_DUAL) ? EPI_HB8CFG2_CSBAUD : 0) | ((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
((ulConfig & EPI_HB8_CSBAUD_DUAL) ?
EPI_HB8CFG2_CSBAUD : 0) |
((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
//
// Fill in the max wait field of the configuration word.
//
@ -261,6 +264,96 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
}
//*****************************************************************************
//
//! Configures the interface for Host-bus 16 operation.
//!
//! \param ulBase is the EPI module base address.
//! \param ulConfig is the interface configuration.
//! \param ulMaxWait is the maximum number of external clocks to wait
//! if a FIFO ready signal is holding off the transaction.
//!
//! This function is used to configure the interface when used in Host-bus 16
//! operation as chosen with the function EPIModeSet(). The parameter
//! \e ulConfig is the logical OR of any of the following:
//!
//! - one of \b EPI_HB16_MODE_ADMUX, \b EPI_HB16_MODE_ADDEMUX,
//! \b EPI_HB16_MODE_SRAM, or \b EPI_HB16_MODE_FIFO to select the HB16 mode
//! - \b EPI_HB16_USE_TXEMPTY - enable TXEMPTY signal with FIFO
//! - \b EPI_HB16_USE_RXFULL - enable RXFULL signal with FIFO
//! - \b EPI_HB16_WRHIGH - use active high write strobe, otherwise it is
//! active low
//! - \b EPI_HB16_RDHIGH - use active high read strobe, otherwise it is
//! active low
//! - one of \b EPI_HB16_WRWAIT_0, \b EPI_HB16_WRWAIT_1, \b EPI_HB16_WRWAIT_2,
//! or \b EPI_HB16_WRWAIT_3 to select the number of write wait states (default
//! is 0 wait states)
//! - one of \b EPI_HB16_RDWAIT_0, \b EPI_HB16_RDWAIT_1, \b EPI_HB16_RDWAIT_2,
//! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default
//! is 0 wait states)
//! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the
//! correct byte lanes allowing data to be stored in bits [31:16]. If absent,
//! all data transfers use bits [15:0].
//! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals
//! operate as byte selects allowing 8-bit transfers. If this flag is not
//! specified, data must be read and written using only 16-bit transfers.
//! - \b EPI_HB16_CSBAUD_DUAL - use different baud rates when accessing devices
//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
//! upper 16 bits. If this option is absent, both chip selects use the baud
//! rate resulting from the divider in the lower 16 bits of the parameter passed
//! to EPIDividerSet().
//! - one of \b EPI_HB16_CSCFG_CS, \b EPI_HB16_CSCFG_ALE,
//! \b EPI_HB16_CSCFG_DUAL_CS or \b EPI_HB16_CSCFG_ALE_DUAL_CS.
//! \b EPI_HB16_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal.
//! \b EPI_HB16_CSCFG_ALE sets EPI30 to operate as an address latch (ALE).
//! \b EPI_HB16_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n
//! with the asserted chip select determined from the most significant address
//! bit for the respective external address map. \b EPI_HB16_CSCFG_ALE_DUAL_CS
//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with
//! the asserted chip select determined from the most significant address bit
//! for the respective external address map.
//!
//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
//! parameter determines the maximum number of clocks to wait when the
//! transaction is being held off by by the FIFO using one of these ready
//! signals. A value of 0 means to wait forever.
//!
//! \return None.
//
//*****************************************************************************
void
EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait)
{
//
// Check the arguments.
//
ASSERT(ulBase == EPI0_BASE);
ASSERT(ulMaxWait < 256);
//
// Determine the CS and word access modes.
//
HWREG(ulBase + EPI_O_HB16CFG2) = (((ulConfig & EPI_HB16_WORD_ACCESS) ?
EPI_HB16CFG2_WORD : 0) |
((ulConfig & EPI_HB16_CSBAUD_DUAL) ?
EPI_HB16CFG2_CSBAUD : 0) |
((ulConfig & EPI_HB16_CSCFG_MASK) << 15));
//
// Fill in the max wait field of the configuration word.
//
ulConfig &= ~EPI_HB16CFG_MAXWAIT_M;
ulConfig |= ulMaxWait << EPI_HB16CFG_MAXWAIT_S;
//
// Write the main HostBus16 configuration register.
//
HWREG(ulBase + EPI_O_HB16CFG) = ulConfig;
}
//*****************************************************************************
//
//! Configures the interface for general-purpose mode operation.
@ -274,9 +367,8 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//!
//! This function is used to configure the interface when used in
//! general-purpose operation as chosen with the function EPIModeSet(). The
//! parameter
//! \e ulConfig is the logical OR of any of the following:
//!
//! parameter \e ulConfig is the logical OR of any of the following:
//!
//! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin
//! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction,
//! otherwise it is free-running
@ -288,13 +380,13 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
//! is a pulse
//! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins
//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
//! - \b EPI_GPMODE_WRITE2CYCLE - a two-cycle write is used, otherwise a
//! single-cycle write is used
//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a
//! - \b EPI_GPMODE_READ2CYCLE - a two-cycle read is used, otherwise a
//! single-cycle read is used
//! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4,
//! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address
//! bus, or and address bus size of 4, 12, or 20 bits
//! bus or an address bus size of 4, 12, or 20 bits
//! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16,
//! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus
//! size of 8, 16, 24, or 32 bits
@ -313,7 +405,7 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//! external clock enable is used, this parameter determines the maximum
//! number of clocks to wait when the external clock enable signal is holding
//! off a transaction. A value of 0 means to wait forever. If a non-zero
//! value is used and exceeded, an interrupt will occur and the transaction
//! value is used and exceeded, an interrupt occurs and the transaction
//! aborted.
//!
//! \return None.
@ -422,7 +514,7 @@ EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap)
//! Once configured, the non-blocking read is started by calling
//! EPINonBlockingReadStart(). If the addresses to be read from the device
//! are in a sequence, it is not necessary to call this function multiple
//! times. Until it is changed, the EPI module will remember the last address
//! times. Until it is changed, the EPI module stores the last address
//! that was used for a non-blocking read (per channel).
//!
//! \return None.
@ -468,9 +560,9 @@ EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
//!
//! This function starts a non-blocking read that was previously configured
//! with the function EPINonBlockingReadConfigure(). Once this function is
//! called, the EPI module will begin reading data from the external device
//! into the read FIFO. The EPI will stop reading when the FIFO fills up
//! and resume reading when the application drains the FIFO, until the
//! called, the EPI module begins reading data from the external device
//! into the read FIFO. The EPI stops reading when the FIFO fills up
//! and resumes reading when the application drains the FIFO, until the
//! total specified count of data items has been read.
//!
//! Once a read transaction is completed and the FIFO drained, another
@ -534,7 +626,7 @@ EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel)
ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
//
// Write a 0 to the read count register, which will cancel the transaction.
// Write a 0 to the read count register, which cancels the transaction.
//
HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0;
}
@ -612,10 +704,10 @@ EPINonBlockingReadAvail(unsigned long ulBase)
//! be stored.
//!
//! This function reads 32-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@ -634,8 +726,8 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
ASSERT(pulBuf);
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// Read from the FIFO while there are any items to read and
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
@ -663,14 +755,14 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
//!
//! \param ulBase is the EPI module base address.
//! \param ulCount is the maximum count of items to read.
//! \param pusBuf is the caller supplied buffer where the read data should
//! \param pusBuf is the caller-supplied buffer where the read data should
//! be stored.
//!
//! This function reads 16-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@ -690,12 +782,12 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
//
// Read from the FIFO and store in the caller supplied buffer.
// Read from the FIFO and store in the caller-supplied buffer.
//
*pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO);
@ -718,14 +810,14 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
//!
//! \param ulBase is the EPI module base address.
//! \param ulCount is the maximum count of items to read.
//! \param pucBuf is the caller supplied buffer where the read data should
//! \param pucBuf is the caller-supplied buffer where the read data should
//! be stored.
//!
//! This function reads 8-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@ -745,7 +837,7 @@ EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
@ -1047,7 +1139,7 @@ EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the EPI module base address.
//!
//! This function will disable and clear the handler to be called when the
//! This function disables and clears the handler to be called when the
//! EPI interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt

38
bsp/lm3s8962/Libraries/driverlib/epi.h
View File

@ -2,7 +2,7 @@
//
// epi.h - Prototypes and macros for the EPI module.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -44,6 +44,7 @@ extern "C"
#define EPI_MODE_GENERAL 0x00000010
#define EPI_MODE_SDRAM 0x00000011
#define EPI_MODE_HB8 0x00000012
#define EPI_MODE_HB16 0x00000013
#define EPI_MODE_DISABLE 0x00000000
//*****************************************************************************
@ -115,6 +116,37 @@ extern "C"
#define EPI_HB8_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB16ModeSet()
//
//*****************************************************************************
#define EPI_HB16_USE_TXEMPTY 0x00800000
#define EPI_HB16_USE_RXFULL 0x00400000
#define EPI_HB16_WRHIGH 0x00200000
#define EPI_HB16_RDHIGH 0x00100000
#define EPI_HB16_WRWAIT_0 0x00000000
#define EPI_HB16_WRWAIT_1 0x00000040
#define EPI_HB16_WRWAIT_2 0x00000080
#define EPI_HB16_WRWAIT_3 0x000000C0
#define EPI_HB16_RDWAIT_0 0x00000000
#define EPI_HB16_RDWAIT_1 0x00000010
#define EPI_HB16_RDWAIT_2 0x00000020
#define EPI_HB16_RDWAIT_3 0x00000030
#define EPI_HB16_MODE_ADMUX 0x00000000
#define EPI_HB16_MODE_ADDEMUX 0x00000001
#define EPI_HB16_MODE_SRAM 0x00000002
#define EPI_HB16_MODE_FIFO 0x00000003
#define EPI_HB16_BSEL 0x00000004
#define EPI_HB16_WORD_ACCESS 0x00000100
#define EPI_HB16_CSCFG_ALE 0x00000000
#define EPI_HB16_CSCFG_CS 0x00000200
#define EPI_HB16_CSCFG_DUAL_CS 0x00000400
#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600
#define EPI_HB16_CSBAUD_DUAL 0x00000800
#define EPI_HB16_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
@ -196,6 +228,8 @@ extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
extern void EPINonBlockingReadConfigure(unsigned long ulBase,
unsigned long ulChannel,

229
bsp/lm3s8962/Libraries/driverlib/ethernet.c
View File

@ -2,7 +2,7 @@
//
// ethernet.c - Driver for the Integrated Ethernet Controller
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -44,14 +44,14 @@
//! \param ulBase is the base address of the controller.
//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
//!
//! This function will prepare the Ethernet controller for first time use in
//! This function prepares the Ethernet controller for first-time use in
//! a given hardware/software configuration. This function should be called
//! before any other Ethernet API functions are called.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original EthernetInit() API and performs the
//! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
@ -112,14 +112,16 @@ EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
//!
//! The Ethernet controller provides three control registers that are used
//! to configure the controller's operation. The transmit control register
//! provides settings to enable full duplex operation, to auto-generate the
//! provides settings to enable full-duplex operation, to auto-generate the
//! frame check sequence, and to pad the transmit packets to the minimum
//! length as required by the IEEE standard. The receive control register
//! provides settings to enable reception of packets with bad frame check
//! sequence values and to enable multi-cast or promiscuous modes. The
//! timestamp control register provides settings that enable support logic in
//! the controller that allow the use of the General Purpose Timer 3 to capture
//! timestamps for the transmitted and received packets.
//! timestamps for the transmitted and received packets. Note that not all
//! devices support this functionality; see the data sheet to determine if
//! this feature is supported.
//!
//! The \e ulConfig parameter is the logical OR of the following values:
//!
@ -183,11 +185,11 @@ EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will query the control registers of the Ethernet controller
//! and return a bit-mapped configuration value.
//! This function queries the control registers of the Ethernet controller
//! and returns a bit-mapped configuration value.
//!
//! \sa The description of the EthernetConfigSet() function provides detailed
//! information for the bit-mapped configuration values that will be returned.
//! information for the bit-mapped configuration values that are returned.
//!
//! \return Returns the bit-mapped Ethernet controller configuration value.
//
@ -219,7 +221,7 @@ EthernetConfigGet(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
//!
//! This function will program the IEEE-defined MAC-48 address specified in
//! This function programs the IEEE-defined MAC-48 address specified in
//! \e pucMACAddr into the Ethernet controller. This address is used by the
//! Ethernet controller for hardware-level filtering of incoming Ethernet
//! packets (when promiscuous mode is not enabled).
@ -282,7 +284,7 @@ EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
//! \param pucMACAddr is the pointer to the location in which to store the
//! array of MAC-48 address octets.
//!
//! This function will read the currently programmed MAC address into the
//! This function reads the currently programmed MAC address into the
//! \e pucMACAddr buffer.
//!
//! \sa Refer to EthernetMACAddrSet() API description for more details about
@ -329,8 +331,8 @@ EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
//! the EthernetMACAddrSet() function, this API function can be called to
//! enable the controller for normal operation.
//!
//! This function will enable the controller's transmitter and receiver, and
//! will reset the receive FIFO.
//! This function enables the controller's transmitter and receiver, and
//! resets the receive FIFO.
//!
//! \return None.
//
@ -371,8 +373,8 @@ EthernetEnable(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//!
//! When terminating operations on the Ethernet interface, this function should
//! be called. This function will disable the transmitter and receiver, and
//! will clear out the receive FIFO.
//! be called. This function disables the transmitter and receiver, and
//! clears out the receive FIFO.
//!
//! \return None.
//
@ -416,8 +418,7 @@ EthernetDisable(unsigned long ulBase)
//! packets available in the receive FIFO. When the last bytes of a packet are
//! successfully received (that is, the frame check sequence bytes), the packet
//! count is incremented. Once the packet has been fully read (including the
//! frame check sequence bytes) from the FIFO, the packet count will be
//! decremented.
//! frame check sequence bytes) from the FIFO, the packet count is decremented.
//!
//! \return Returns \b true if there are one or more packets available in the
//! receive FIFO, including the current packet being read, and \b false
@ -448,7 +449,7 @@ EthernetPacketAvail(unsigned long ulBase)
//! packet at a time. After the packet has been written into the FIFO, the
//! transmit request bit must be set to enable the transmission of the packet.
//! Only after the packet has been transmitted can a new packet be written
//! into the FIFO. This function will simply check to see if a packet is
//! into the FIFO. This function simply checks to see if a packet is
//! in progress. If so, there is no space available in the transmit FIFO.
//!
//! \return Returns \b true if a space is available in the transmit FIFO, and
@ -609,20 +610,20 @@ EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf. If no packet is available the function will
//! return immediately. Otherwise, the function will read the entire packet
//! from the receive FIFO. If there are more bytes in the packet than will fit
//! into \e pucBuf (as specified by \e lBufLen), the function will return the
//! negated length of the packet and the buffer will contain \e lBufLen bytes
//! of the packet. Otherwise, the function will return the length of the
//! packet that was read and \e pucBuf will contain the entire packet
//! places it into \e pucBuf. If no packet is available the function
//! returns immediately. Otherwise, the function reads the entire packet
//! from the receive FIFO. If there are more bytes in the packet than can fit
//! into \e pucBuf (as specified by \e lBufLen), the function returns the
//! negated length of the packet and the buffer contains \e lBufLen bytes
//! of the packet. Otherwise, the function returns the length of the
//! packet that was read and \e pucBuf contains the entire packet
//! (excluding the frame check sequence bytes).
//!
//! This function replaces the original EthernetPacketNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
//! map the original API to this API.
//!
//! \note This function will return immediately if no packet is available.
//! \note This function returns immediately if no packet is available.
//!
//! \return Returns \b 0 if no packet is available, the negated packet length
//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
@ -663,16 +664,16 @@ EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf. The function will wait until a packet is
//! available in the FIFO. Then the function will read the entire packet
//! from the receive FIFO. If there are more bytes in the packet than will
//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
//! the negated length of the packet and the buffer will contain \e lBufLen
//! bytes of the packet. Otherwise, the function will return the length of
//! the packet that was read and \e pucBuf will contain the entire packet
//! places it into \e pucBuf. The function waits until a packet is
//! available in the FIFO. Then the function reads the entire packet
//! from the receive FIFO. If there are more bytes in the packet than can
//! fit into \e pucBuf (as specified by \e lBufLen), the function returns
//! the negated length of the packet and the buffer contains \e lBufLen
//! bytes of the packet. Otherwise, the function returns the length of
//! the packet that was read and \e pucBuf contains the entire packet
//! (excluding the frame check sequence bytes).
//!
//! \note This function is blocking and will not return until a packet arrives.
//! \note This function is blocking and does not return until a packet arrives.
//!
//! \return Returns the negated packet length \b -n if the packet is too large
//! for \e pucBuf, and returns the packet length \b n otherwise.
@ -832,10 +833,10 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the
//! transmitter for this packet. If no space is available in the FIFO, the
//! function will return immediately. If space is available, the
//! function will return once \e lBufLen bytes of the packet have been placed
//! into the FIFO and the transmitter has been started. The function will not
//! wait for the transmission to complete. The function will return the
//! function returns immediately. If space is available, the
//! function returns once \e lBufLen bytes of the packet have been placed
//! into the FIFO and the transmitter has been started. The function does not
//! wait for the transmission to complete. The function returns the
//! negated \e lBufLen if the length is larger than the space available in
//! the transmit FIFO.
//!
@ -843,7 +844,7 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
//! map the original API to this API.
//!
//! \note This function does not block and will return immediately if no space
//! \note This function does not block and returns immediately if no space
//! is available for the transmit packet.
//!
//! \return Returns \b 0 if no space is available in the transmit FIFO, the
@ -886,14 +887,14 @@ EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
//!
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the transmitter
//! for this packet. This function will wait until the transmit FIFO is empty.
//! Once space is available, the function will return once \e lBufLen bytes of
//! for this packet. This function waits until the transmit FIFO is empty.
//! Once space is available, the function returns once \e lBufLen bytes of
//! the packet have been placed into the FIFO and the transmitter has been
//! started. The function will not wait for the transmission to complete. The
//! function will return the negated \e lBufLen if the length is larger than
//! started. The function does not wait for the transmission to complete. The
//! function returns the negated \e lBufLen if the length is larger than
//! the space available in the transmit FIFO.
//!
//! \note This function blocks and will wait until space is available for the
//! \note This function blocks and waits until space is available for the
//! transmit packet before returning.
//!
//! \return Returns the negated packet length \b -lBufLen if the packet is too
@ -933,9 +934,10 @@ EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
//! enabled Ethernet interrupts occur.
//!
//! This function sets the handler to be called when the Ethernet interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source.
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific Ethernet interrupts must be enabled via
//! EthernetIntEnable(). It is the interrupt handler's responsibility to clear
//! the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -969,9 +971,9 @@ EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the base address of the controller.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller so that the interrupt handler
//! no longer is called.
//! This function unregisters the interrupt handler. This function disables
//! the global interrupt in the interrupt controller so that the interrupt
//! handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -1005,16 +1007,17 @@ EthernetIntUnregister(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated Ethernet interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//! This function enables the indicated Ethernet interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
//! must be read to determine which PHY interrupt has occurred. This register
//! can be read using the EthernetPHYRead() API function.
//! PHY supports a number of interrupt conditions. The appropriate PHY
//! register, PHY_MR17 or PHY_MR29 depending on the device class, must be read
//! to determine which PHY interrupt has occurred. This register can be read
//! using the EthernetPHYRead() API function.
//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
//! management interface has completed successfully.
//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
@ -1093,9 +1096,9 @@ EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true
//! if the masked interrupt status is required.
//!
//! This returns the interrupt status for the Ethernet controller. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//! This function returns the interrupt status for the Ethernet controller.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in EthernetIntEnable().
@ -1138,20 +1141,20 @@ EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified Ethernet interrupt sources are cleared so that they no longer
//! assert. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to EthernetIntEnable().
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -1173,6 +1176,42 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
}
//*****************************************************************************
//
//! Sets the PHY address.
//!
//! \param ulBase is the base address of the controller.
//! \param ucAddr is the address of the PHY.
//!
//! This function sets the address of the PHY that is accessed via
//! EthernetPHYRead() and EthernePHYWrite(). This configuration is only needed
//! when connecting to an external PHY via MII, and should not be used on
//! devices that have integrated PHYs.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr)
{
//
// Check the arguments.
//
ASSERT(ulBase == ETH_BASE);
//
// Wait for any pending transaction to complete.
//
while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
{
}
//
// Set the PHY address.
//
HWREG(ulBase + MAC_O_MADD) = ucAddr;
}
//*****************************************************************************
//
//! Writes to the PHY register.
@ -1181,7 +1220,7 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ucRegAddr is the address of the PHY register to be accessed.
//! \param ulData is the data to be written to the PHY register.
//!
//! This function will write the \e ulData to the PHY register specified by
//! This function writes the \e ulData to the PHY register specified by
//! \e ucRegAddr.
//!
//! \return None.
@ -1229,7 +1268,7 @@ EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
//! \param ulBase is the base address of the controller.
//! \param ucRegAddr is the address of the PHY register to be accessed.
//!
//! This function will return the contents of the PHY register specified by
//! This function returns the contents of the PHY register specified by
//! \e ucRegAddr.
//!
//! \return Returns the 16-bit value read from the PHY.
@ -1269,6 +1308,56 @@ EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
}
//*****************************************************************************
//
//! Powers off the Ethernet PHY.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function powers off the Ethernet PHY, reducing the current
//! consumption of the device. While in the powered off state, the Ethernet
//! controller is unable to connect to the Ethernet.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYPowerOff(unsigned long ulBase)
{
//
// Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into
// its low power mode.
//
EthernetPHYWrite(ulBase, PHY_MR0,
(EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) |
PHY_MR0_PWRDN);
}
//*****************************************************************************
//
//! Powers on the Ethernet PHY.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function powers on the Ethernet PHY, enabling it return to normal
//! operation. By default, the PHY is powered on, so this function is only
//! called if EthernetPHYPowerOff() has previously been called.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYPowerOn(unsigned long ulBase)
{
//
// Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
// normal operating mode.
//
EthernetPHYWrite(ulBase, PHY_MR0,
(EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) |
PHY_MR0_ANEGEN);
}
//*****************************************************************************
//
// Close the Doxygen group.

7
bsp/lm3s8962/Libraries/driverlib/ethernet.h
View File

@ -2,7 +2,7 @@
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -136,10 +136,13 @@ extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
extern void EthernetPHYPowerOff(unsigned long ulBase);
extern void EthernetPHYPowerOn(unsigned long ulBase);
//*****************************************************************************
//

633
bsp/lm3s8962/Libraries/driverlib/fan.c Normal file
View File

@ -0,0 +1,633 @@
//*****************************************************************************
//
// fan.c - Driver for the FAN controller.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_fan.h"
#include "inc/hw_ints.h"
#include "driverlib/fan.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
//! \addtogroup fan_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables a FAN channel for operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to enable.
//!
//! This function enables the specified FAN channel for operation.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelEnable(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Enable the requested channel
//
HWREG(ulBase + FAN_O_CTL) |= 1 << ulChannel;
}
//*****************************************************************************
//
//! Disables a FAN channel for operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to disable.
//!
//! This function disables the specified FAN channel for operation.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelDisable(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Disable the requested channel
//
HWREG(ulBase + FAN_O_CTL) &= ~(1 << ulChannel);
}
//*****************************************************************************
//
//! Gets the status of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for status.
//!
//! This function queries and returns the status of the specified channel.
//! The returned value is one of:
//!
//! - \b FAN_STATUS_STALLED if the cooling fan is stalled
//! - \b FAN_STATUS_CHANGING if the fan is changing to the commanded speed
//! - \b FAN_STATUS_LOCKED if the fan is locked at the commanded speed
//! - \b FAN_STATUS_NOATTAIN if the fan cannot achieve the commanded speed
//!
//! \return Returns the status of the specified FAN channel.
//
//*****************************************************************************
unsigned long
FanChannelStatus(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read and return the status for the specified fan channel
//
return((HWREG(ulBase + FAN_O_STS) >> (ulChannel * 2)) & FAN_STS_ST0_M);
}
//*****************************************************************************
//
//! Configures a FAN channel for manual operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to configure.
//! \param ulConfig is the logical OR of manual configuration flags.
//!
//! This function configures a specific FAN channel to operate in manual
//! mode. The \e ulConfig parameter is the logical OR of several choices of
//! configuration flags as follows:
//!
//! One of the following to select the number of tachometer pulses used for
//! speed averaging:
//!
//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging
//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging
//!
//! One of the following to select the tachometer pulses per revolution:
//!
//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution
//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution
//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution
//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Program the fan channel for manual mode with parameters.
//
HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = FAN_CH0_MAN | ulConfig;
}
//*****************************************************************************
//
//! Configures a FAN channel for automatic operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to configure.
//! \param ulConfig is the logical OR of configuration flags.
//!
//! This function configures a specific FAN channel to operate in automatic
//! mode. The \e ulConfig parameter is the logical OR of several choices of
//! configuration flags as follows:
//!
//! One of the following to select the automatic restart mode:
//!
//! - \b FAN_CONFIG_RESTART to enable automatic restart after stall
//! - \b FAN_CONFIG_NORESTART to disable automatic restart after stall
//!
//! One of the following to select the acceleration rate when changing speed:
//!
//! - \b FAN_CONFIG_ACCEL_FAST to select fast acceleration
//! - \b FAN_CONFIG_ACCEL_SLOW to select slow acceleration
//!
//! One of the following to select the number of tachometer pulses to use
//! for the hysteresis count:
//! \b FAN_CONFIG_HYST_1, \b FAN_CONFIG_HYST_2, \b FAN_CONFIG_HYST_4,
//! \b FAN_CONFIG_HYST_8, \b FAN_CONFIG_HYST_16, \b FAN_CONFIG_HYST_32,
//! \b FAN_CONFIG_HYST_64, or \b FAN_CONFIG_HYST_128
//!
//! One of the following to select the start period as the number of tachometer
//! pulses. The start period is the amount of time that a starting PWM duty
//! cycle is used after the FAN channel is commended to a certain speed:
//! \b FAN_CONFIG_START_2, \b FAN_CONFIG_START_4, \b FAN_CONFIG_START_8,
//! \b FAN_CONFIG_START_16, \b FAN_CONFIG_START_32, \b FAN_CONFIG_START_64,
//! \b FAN_CONFIG_START_128, or \b FAN_CONFIG_START_256
//!
//! One of the following to specify the duty cycle that is used when the FAN
//! channel is starting, during the starting period (above):
//!
//! - \b FAN_CONFIG_START_DUTY_OFF to disable the use of startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_50 to select 50% startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_75 to select 75% startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_100 to select 100% startup duty cycle
//!
//! One of the following to select the number of tachometer pulses used for
//! speed averaging:
//!
//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging
//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging
//!
//! One of the following to select the tachometer pulses per revolution:
//!
//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution
//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution
//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution
//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Program the fan channel for automatic mode with parameters.
//
HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = ~FAN_CH0_MAN & ulConfig;
}
//*****************************************************************************
//
//! Sets the duty cycle of a FAN channel when in manual mode.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to program the duty cycle.
//! \param ulDuty is the duty cycle in clocks from 0-511.
//!
//! This function sets the duty cycle of a FAN channel if the channel is
//! configured for manual mode. The duty cycle is specified in clocks from
//! 0-511 out of a 512 clock PWM period.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDuty)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
ASSERT(ulDuty < 512);
//
// Program the specified duty cycle for the specified channel
//
HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) =
(ulDuty << FAN_CMD0_DC_S) & FAN_CMD0_DC_M;
}
//*****************************************************************************
//
//! Reads the duty cycle of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for duty cycle.
//!
//! This function gets the duty cycle of a FAN channel. If the channel is in
//! manual mode, then this is the value that was programmed. If the FAN
//! channel is configured for automatic mode, then this is the value that is
//! calculated by the Fan Control peripheral.
//!
//! \return Returns the FAN channel duty cycle as a number of clocks from
//! 0-511, out of a 512 clock PWM period.
//
//*****************************************************************************
unsigned long
FanChannelDutyGet(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulDuty;
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read the duty cycle field from the command register and shift to
// lower bits for return value.
//
ulDuty = HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) & FAN_CMD0_DC_M;
ulDuty >>= FAN_CMD0_DC_S;
//
// Return the duty cycle for the specified channel.
//
return(ulDuty);
}
//*****************************************************************************
//
//! Sets the RPM of a FAN channel when in automatic mode.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to program the RPM.
//! \param ulRPM is the RPM as a value from 0-8191.
//!
//! This function sets the RPM of the fan channel if the fan channel is
//! configured for automatic mode. If configured for manual mode, then this
//! function has no effect.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulRPM)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
ASSERT(ulRPM < 8192);
//
// Program the specified RPM for the specified channel
//
HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = ulRPM;
}
//*****************************************************************************
//
//! Reads the RPM of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for RPM.
//!
//! This function gets the RPM of a FAN channel.
//!
//! \return Returns the FAN channel RPM as a number from 0-4095.
//
//*****************************************************************************
unsigned long
FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read and return the RPM for the specified channel.
//
return(HWREG(ulBase + FAN_O_CST0 + (ulChannel * 0x10)) & FAN_CST0_RPM_M);
}
//*****************************************************************************
//
//! Enables FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be enabled.
//!
//! This function enables one or more interrupts from the FAN module. The
//! \e ulFlags parameter is the logical OR of all the possible interrupts that
//! can be enabled. For each channel, the following interrupt flags are
//! available:
//!
//! - \b FAN_CHn_INT_STALL means that a stall was detected (in either mode).
//! - \b FAN_CHn_INT_AUTO_SPEED_ERROR means that in automatic mode, the cooling
//! fan cannot attain the commanded speed.
//! - \b FAN_CHn_INT_AUTO_SPEED_OK means that in automatic mode, the cooling
//! fan has attained the commanded speed.
//!
//! In the above flag names, the \b CHn placeholder should be replaced with
//! the actual channel number, 0-5 (for example, CH1).
//!
//! The interrupt flags have a different meaning if the FAN channel is
//! configured for manual mode. The following alternate set of flag names is
//! available for convenience to use in manual mode:
//!
//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode, the speed
//! was calculated.
//! - \b FAN_CHn_INT_MANUAL_SPEED_CHANGE means that in manual mode, the speed
//! changed.
//!
//! Note that even though the names are different for manual mode, the values
//! are the same. For example \b _AUTO_SPEED_ERROR is the same value as
//! \b _MANUAL_SPEED_UPDATE. The different names are provided just to make it
//! easier to associate a meaning with each interrupt flag.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntEnable(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Enable the requested interrupt sources.
//
HWREG(ulBase + FAN_O_IM) |= ulFlags;
}
//*****************************************************************************
//
//! Disables FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be disabled.
//!
//! This function disables one or more interrupts from the FAN module. The
//! \e ulFlags parameter is the logical OR of all the possible interrupts that
//! can be enabled. For a list of possible interrupt flags, refer to the
//! documentation for the function FanIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
FanIntDisable(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Disable the requested interrupt sources.
//
HWREG(ulBase + FAN_O_IM) &= ~ulFlags;
}
//*****************************************************************************
//
//! Gets the FAN module interrupt status.
//!
//! \param ulBase is the base address of the FAN module.
//! \param bMasked is set \b true to get the masked interrupt status, or
//! \b false to get the raw interrupt status.
//!
//! This function returns the interrupt status of the FAN module. It can
//! return either the raw or masked interrupt status.
//!
//! \return Returns the masked or raw FAN interrupt status, as a bit field
//! of multiple FAN interrupt flags. For a list of all the possible interrupt
//! flags, refer to the documentation for the function FanIntEnable().
//
//*****************************************************************************
unsigned long
FanIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + FAN_O_MIS));
}
else
{
return(HWREG(ulBase + FAN_O_RIS));
}
}
//*****************************************************************************
//
//! Clears pending FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be cleared.
//!
//! This function clears one or more interrupts from the FAN module. The
//! \e ulFlags parameter is the logical OR of all the possible interrupts that
//! can be cleared. For a list of possible interrupt flags, refer to the
//! documentation for the function FanIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
FanIntClear(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Clear the requested pending interrupts
//
HWREG(ulBase + FAN_O_IC) = ulFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for the FAN module.
//!
//! \param ulBase is the base address of the FAN module.
//! \param pfnHandler is a pointer to the function to be called when the
//! interrupt is activated.
//!
//! This function sets and enables the handler to be called when the FAN module
//! generates an interrupt. Specific FAN interrupts must still be enabled
//! with the FanIntEnable() function.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(pfnHandler);
//
// Register the interrupt handler.
//
IntRegister(INT_FAN0, pfnHandler);
//
// Enable the FAN peripheral interrupt.
//
IntEnable(INT_FAN0);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the FAN module.
//!
//! \param ulBase is the base address of the FAN module.
//!
//! This function disables and clears the handler to be called when the
//! FAN module interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Disable the FAN peripheral interrupt.
//
IntDisable(INT_FAN0);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FAN0);
}
//*****************************************************************************
//
//! Gets the number of supported FAN channels.
//!
//! \param ulBase is the base address of the FAN module.
//!
//! This function gets the number of FAN channels that are supported by the
//! Fan Control peripheral.
//!
//! \return Returns the number of FAN channels.
//
//*****************************************************************************
unsigned long
FanChannelsGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Read and return the fan channel count
//
return(HWREG(ulBase + FAN_O_PP) & FAN_PP_CHAN_M);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

168
bsp/lm3s8962/Libraries/driverlib/fan.h Normal file
View File

@ -0,0 +1,168 @@
//*****************************************************************************
//
// fan.h - Prototypes and macros for the Fan controller.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FAN_H__
#define __FAN_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Fan status values that can be returned from the FanChannelStatus() function.
//
//*****************************************************************************
#define FAN_STATUS_STALLED 0
#define FAN_STATUS_CHANGING 1
#define FAN_STATUS_LOCKED 2
#define FAN_STATUS_NOATTAIN 3
//*****************************************************************************
//
// Configuration flags to be used with FanChannelConfigManual() and
// FanChannelConfigAuto().
//
//*****************************************************************************
#define FAN_CONFIG_RESTART (1 << 15)
#define FAN_CONFIG_NORESTART (0 << 15)
#define FAN_CONFIG_ACCEL_FAST (1 << 14)
#define FAN_CONFIG_ACCEL_SLOW (0 << 14)
#define FAN_CONFIG_HYST_1 (0 << 11)
#define FAN_CONFIG_HYST_2 (1 << 11)
#define FAN_CONFIG_HYST_4 (2 << 11)
#define FAN_CONFIG_HYST_8 (3 << 11)
#define FAN_CONFIG_HYST_16 (4 << 11)
#define FAN_CONFIG_HYST_32 (5 << 11)
#define FAN_CONFIG_HYST_64 (6 << 11)
#define FAN_CONFIG_HYST_128 (7 << 11)
#define FAN_CONFIG_START_2 (0 << 8)
#define FAN_CONFIG_START_4 (1 << 8)
#define FAN_CONFIG_START_8 (2 << 8)
#define FAN_CONFIG_START_16 (3 << 8)
#define FAN_CONFIG_START_32 (4 << 8)
#define FAN_CONFIG_START_64 (5 << 8)
#define FAN_CONFIG_START_128 (6 << 8)
#define FAN_CONFIG_START_256 (7 << 8)
#define FAN_CONFIG_START_DUTY_OFF (0 << 6)
#define FAN_CONFIG_START_DUTY_50 (1 << 6)
#define FAN_CONFIG_START_DUTY_75 (2 << 6)
#define FAN_CONFIG_START_DUTY_100 (3 << 6)
#define FAN_CONFIG_AVG_NONE (0 << 4)
#define FAN_CONFIG_AVG_2 (1 << 4)
#define FAN_CONFIG_AVG_4 (2 << 4)
#define FAN_CONFIG_AVG_8 (3 << 4)
#define FAN_CONFIG_TACH_1 (0 << 2)
#define FAN_CONFIG_TACH_2 (1 << 2)
#define FAN_CONFIG_TACH_4 (2 << 2)
#define FAN_CONFIG_TACH_8 (3 << 2)
//*****************************************************************************
//
// Interrupt configuration/status flags to be used with the following
// functions: FanIntEnable(), FanIntDisable(), FanIntStatus(), FanIntClear().
//
//*****************************************************************************
#define FAN_CH5_INT_AUTO_SPEED_OK (1 << 22)
#define FAN_CH5_INT_MANUAL_SPEED_CHANGE (1 << 22)
#define FAN_CH5_INT_AUTO_SPEED_ERROR (1 << 21)
#define FAN_CH5_INT_MANUAL_SPEED_UPDATE (1 << 21)
#define FAN_CH5_INT_STALL (1 << 20)
#define FAN_CH4_INT_AUTO_SPEED_OK (1 << 18)
#define FAN_CH4_INT_MANUAL_SPEED_CHANGE (1 << 18)
#define FAN_CH4_INT_AUTO_SPEED_ERROR (1 << 17)
#define FAN_CH4_INT_MANUAL_SPEED_UPDATE (1 << 17)
#define FAN_CH4_INT_STALL (1 << 16)
#define FAN_CH3_INT_AUTO_SPEED_OK (1 << 14)
#define FAN_CH3_INT_MANUAL_SPEED_CHANGE (1 << 14)
#define FAN_CH3_INT_AUTO_SPEED_ERROR (1 << 13)
#define FAN_CH3_INT_MANUAL_SPEED_UPDATE (1 << 13)
#define FAN_CH3_INT_STALL (1 << 12)
#define FAN_CH2_INT_AUTO_SPEED_OK (1 << 10)
#define FAN_CH2_INT_MANUAL_SPEED_CHANGE (1 << 10)
#define FAN_CH2_INT_AUTO_SPEED_ERROR (1 << 9)
#define FAN_CH2_INT_MANUAL_SPEED_UPDATE (1 << 9)
#define FAN_CH2_INT_STALL (1 << 8)
#define FAN_CH1_INT_AUTO_SPEED_OK (1 << 6)
#define FAN_CH1_INT_MANUAL_SPEED_CHANGE (1 << 6)
#define FAN_CH1_INT_AUTO_SPEED_ERROR (1 << 5)
#define FAN_CH1_INT_MANUAL_SPEED_UPDATE (1 << 5)
#define FAN_CH1_INT_STALL (1 << 4)
#define FAN_CH0_INT_AUTO_SPEED_OK (1 << 2)
#define FAN_CH0_INT_MANUAL_SPEED_CHANGE (1 << 2)
#define FAN_CH0_INT_AUTO_SPEED_ERROR (1 << 1)
#define FAN_CH0_INT_MANUAL_SPEED_UPDATE (1 << 1)
#define FAN_CH0_INT_STALL (1 << 0)
#define FAN_CHx_INT_AUTO_SPEED_OK(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_MANUAL_SPEED_CHANGE(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_AUTO_SPEED_ERROR(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_MANUAL_SPEED_UPDATE(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_STALL(x) (1 << ((x) * 4))
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void FanChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void FanChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern unsigned long FanChannelStatus(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDuty);
extern unsigned long FanChannelDutyGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulRPM);
extern unsigned long FanChannelRPMGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanIntEnable(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntDisable(unsigned long ulBase, unsigned long ulFlags);
extern unsigned long FanIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void FanIntClear(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void FanIntUnregister(unsigned long ulBase);
extern unsigned long FanChannelsGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FAN_H__

140
bsp/lm3s8962/Libraries/driverlib/flash.c
View File

@ -2,7 +2,7 @@
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -70,7 +70,8 @@ static const unsigned long g_pulFMPRERegs[] =
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//! known by the flash controller. This function is only valid on Sandstorm-
//! and Fury-class devices.
//!
//! \return Returns the number of processor clocks per micro-second.
//
@ -93,7 +94,7 @@ FlashUsecGet(void)
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//! flash. This function is only valid on Sandstorm- and Fury-class devices.
//!
//! \return None.
//
@ -113,11 +114,11 @@ FlashUsecSet(unsigned long ulClocks)
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//! This function erases a 1-kB block of the on-chip flash. After erasing,
//! the block is filled with 0xFF bytes. Read-only and execute-only blocks
//! cannot be erased.
//!
//! This function will not return until the block has been erased.
//! This function does not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
@ -132,9 +133,10 @@ FlashErase(unsigned long ulAddress)
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC);
//
// Erase the block.
@ -150,9 +152,10 @@ FlashErase(unsigned long ulAddress)
}
//
// Return an error if an access violation occurred.
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS))
{
return(-1);
}
@ -173,19 +176,16 @@ FlashErase(unsigned long ulAddress)
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a word can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//! This function programs a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times results in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! Because the flash is programmed one word at a time, the starting address
//! and byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//! This function does not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
@ -201,9 +201,10 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
ASSERT(!(ulCount & 3));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
@ -280,7 +281,8 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
{
return(-1);
}
@ -297,7 +299,7 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
@ -390,17 +392,17 @@ FlashProtectGet(unsigned long ulAddress)
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! This function sets the protection for the specified 2-kB block of
//! flash. Blocks that are read/write can be made read-only or execute-only.
//! Blocks that are read-only can be made execute-only. Blocks that are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (that is, read-only to read/write) will
//! result in a failure (and be prevented by the hardware).
//! block protection less stringent (that is, read-only to read/write)
//! result in a failure (and are prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! This protocol allows the application to be executed in the desired flash
//! protection environment to check for inappropriate flash access (via the
//! flash interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
@ -536,7 +538,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
}
//
@ -555,11 +557,11 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//! This function makes the currently programmed flash protection settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -567,7 +569,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
long
FlashProtectSave(void)
{
int ulTemp, ulLimit;
unsigned long ulTemp, ulLimit;
//
// If running on a Sandstorm-class device, only trigger a save of the first
@ -604,8 +606,8 @@ FlashProtectSave(void)
//! \param pulUser0 is a pointer to the location to store USER Register 0.
//! \param pulUser1 is a pointer to the location to store USER Register 1.
//!
//! This function will read the contents of user registers (0 and 1), and
//! store them in the specified locations.
//! This function reads the contents of user registers (0 and 1), and
//! stores them in the specified locations.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -646,7 +648,7 @@ FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
//! \param ulUser0 is the value to store in USER Register 0.
//! \param ulUser1 is the value to store in USER Register 1.
//!
//! This function will set the contents of the user registers (0 and 1) to
//! This function sets the contents of the user registers (0 and 1) to
//! the specified values.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
@ -679,11 +681,11 @@ FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
//
//! Saves the user registers.
//!
//! This function will make the currently programmed user register settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change this setting.
//! This function makes the currently programmed user register settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change this setting.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@ -739,12 +741,12 @@ FlashUserSave(void)
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! This function sets the handler to be called when the flash interrupt occurs.
//! The flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//! program or erase operation has completed. The interrupt is automatically
//! enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -770,9 +772,9 @@ FlashIntRegister(void (*pfnHandler)(void))
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//! This function clears the handler to be called when the flash interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -801,9 +803,9 @@ FlashIntUnregister(void)
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//! This function enables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -824,9 +826,9 @@ FlashIntEnable(unsigned long ulIntFlags)
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function disables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -847,9 +849,9 @@ FlashIntDisable(unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the flash controller.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
@ -880,17 +882,17 @@ FlashIntStatus(tBoolean bMasked)
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//! no longer assert. This function must be called in the interrupt handler
//! to keep the interrupt from being triggered again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//

13
bsp/lm3s8962/Libraries/driverlib/flash.h
View File

@ -2,7 +2,7 @@
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -56,8 +56,13 @@ tFlashProtection;
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//

284
bsp/lm3s8962/Libraries/driverlib/fpu.c Normal file
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@ -0,0 +1,284 @@
//*****************************************************************************
//
// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
// processor.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup fpu_api
//! @{
//
//*****************************************************************************
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "fpu.h"
//*****************************************************************************
//
//! Enables the floating-point unit.
//!
//! This function enables the floating-point unit, allowing the floating-point
//! instructions to be executed. This function must be called prior to
//! performing any hardware floating-point operations; failure to do so results
//! in a NOCP usage fault.
//!
//! \return None.
//
//*****************************************************************************
void
FPUEnable(void)
{
//
// Enable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
}
//*****************************************************************************
//
//! Disables the floating-point unit.
//!
//! This function disables the floating-point unit, preventing floating-point
//! instructions from executing (generating a NOCP usage fault instead).
//!
//! \return None.
//
//*****************************************************************************
void
FPUDisable(void)
{
//
// Disable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS);
}
//*****************************************************************************
//
//! Enables the stacking of floating-point registers.
//!
//! This function enables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When enabled, space is reserved on the stack for
//! the floating-point context and the floating-point state is saved into this
//! stack space. Upon return from the interrupt, the floating-point context is
//! restored.
//!
//! If the floating-point registers are not stacked, floating-point
//! instructions cannot be safely executed in an interrupt handler because the
//! values of s0-s15 are not likely to be preserved for the interrupted code.
//! On the other hand, stacking the floating-point registers increases the
//! stacking operation from 8 words to 26 words, also increasing the interrupt
//! response latency.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingEnable(void)
{
//
// Enable automatic state preservation for the floating-point unit, and
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN;
}
//*****************************************************************************
//
//! Enables the lazy stacking of floating-point registers.
//!
//! This function enables the lazy stacking of floating-point registers s0-s15
//! when an interrupt is handled. When lazy stacking is enabled, space is
//! reserved on the stack for the floating-point context, but the
//! floating-point state is not saved. If a floating-point instruction is
//! executed from within the interrupt context, the floating-point context is
//! first saved into the space reserved on the stack. On completion of the
//! interrupt handler, the floating-point context is only restored if it was
//! saved (as the result of executing a floating-point instruction).
//!
//! This method provides a compromise between fast interrupt response (because
//! the floating-point state is not saved on interrupt entry) and the ability
//! to use floating-point in interrupt handlers (because the floating-point
//! state is saved if floating-point instructions are used).
//!
//! \return None.
//
//*****************************************************************************
void
FPULazyStackingEnable(void)
{
//
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN;
}
//*****************************************************************************
//
//! Disables the stacking of floating-point registers.
//!
//! This function disables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When floating-point context stacking is disabled,
//! floating-point operations performed in an interrupt handler destroy the
//! floating-point context of the main thread of execution.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingDisable(void)
{
//
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN);
}
//*****************************************************************************
//
//! Selects the format of half-precision floating-point values.
//!
//! \param ulMode is the format for half-precision floating-point value, which
//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
//!
//! This function selects between the IEEE half-precision floating-point
//! representation and the Cortex-M processor alternative representation. The
//! alternative representation has a larger range but does not have a way to
//! encode infinity (positive or negative) or NaN (quiet or signaling). The
//! default setting is the IEEE format.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUHalfPrecisionModeSet(unsigned long ulMode)
{
//
// Set the half-precision floating-point format.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode;
}
//*****************************************************************************
//
//! Selects the NaN mode.
//!
//! \param ulMode is the mode for NaN results; which is either
//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
//!
//! This function selects the handling of NaN results during floating-point
//! computations. NaNs can either propagate (the default), or they can return
//! the default NaN.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUNaNModeSet(unsigned long ulMode)
{
//
// Set the NaN mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode;
}
//*****************************************************************************
//
//! Selects the flush-to-zero mode.
//!
//! \param ulMode is the flush-to-zero mode; which is either
//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
//!
//! This function enables or disables the flush-to-zero mode of the
//! floating-point unit. When disabled (the default), the floating-point unit
//! is fully IEEE compliant. When enabled, values close to zero are treated as
//! zero, greatly improving the execution speed at the expense of some accuracy
//! (as well as IEEE compliance).
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUFlushToZeroModeSet(unsigned long ulMode)
{
//
// Set the flush-to-zero mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode;
}
//*****************************************************************************
//
//! Selects the rounding mode for floating-point results.
//!
//! \param ulMode is the rounding mode.
//!
//! This function selects the rounding mode for floating-point results. After
//! a floating-point operation, the result is rounded toward the specified
//! value. The default mode is \b FPU_ROUND_NEAREST.
//!
//! The following rounding modes are available (as specified by \e ulMode):
//!
//! - \b FPU_ROUND_NEAREST - round toward the nearest value
//! - \b FPU_ROUND_POS_INF - round toward positive infinity
//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
//! - \b FPU_ROUND_ZERO - round toward zero
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPURoundingModeSet(unsigned long ulMode)
{
//
// Set the rounding mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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@ -0,0 +1,97 @@
//*****************************************************************************
//
// fpu.h - Prototypes for the floatint point manipulation routines.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FPU_H__
#define __FPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void FPUEnable(void);
extern void FPUDisable(void);
extern void FPUStackingEnable(void);
extern void FPULazyStackingEnable(void);
extern void FPUStackingDisable(void);
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
extern void FPUNaNModeSet(unsigned long ulMode);
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
extern void FPURoundingModeSet(unsigned long ulMode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FPU_H__

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bsp/lm3s8962/Libraries/driverlib/gpio.h
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@ -2,7 +2,7 @@
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -72,6 +72,7 @@ extern "C"
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
@ -98,616 +99,6 @@ extern "C"
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
//
//*****************************************************************************
//
// GPIO pin A0
//
#define GPIO_PA0_U0RX 0x00000001
#define GPIO_PA0_I2C1SCL 0x00000008
#define GPIO_PA0_U1RX 0x00000009
//
// GPIO pin A1
//
#define GPIO_PA1_U0TX 0x00000401
#define GPIO_PA1_I2C1SDA 0x00000408
#define GPIO_PA1_U1TX 0x00000409
//
// GPIO pin A2
//
#define GPIO_PA2_SSI0CLK 0x00000801
#define GPIO_PA2_PWM4 0x00000804
#define GPIO_PA2_I2S0RXSD 0x00000809
//
// GPIO pin A3
//
#define GPIO_PA3_SSI0FSS 0x00000c01
#define GPIO_PA3_PWM5 0x00000c04
#define GPIO_PA3_I2S0RXMCLK 0x00000c09
//
// GPIO pin A4
//
#define GPIO_PA4_SSI0RX 0x00001001
#define GPIO_PA4_PWM6 0x00001004
#define GPIO_PA4_CAN0RX 0x00001005
#define GPIO_PA4_I2S0TXSCK 0x00001009
//
// GPIO pin A5
//
#define GPIO_PA5_SSI0TX 0x00001401
#define GPIO_PA5_PWM7 0x00001404
#define GPIO_PA5_CAN0TX 0x00001405
#define GPIO_PA5_I2S0TXWS 0x00001409
//
// GPIO pin A6
//
#define GPIO_PA6_I2C1SCL 0x00001801
#define GPIO_PA6_CCP1 0x00001802
#define GPIO_PA6_PWM0 0x00001804
#define GPIO_PA6_PWM4 0x00001805
#define GPIO_PA6_CAN0RX 0x00001806
#define GPIO_PA6_USB0EPEN 0x00001808
#define GPIO_PA6_U1CTS 0x00001809
//
// GPIO pin A7
//
#define GPIO_PA7_I2C1SDA 0x00001c01
#define GPIO_PA7_CCP4 0x00001c02
#define GPIO_PA7_PWM1 0x00001c04
#define GPIO_PA7_PWM5 0x00001c05
#define GPIO_PA7_CAN0TX 0x00001c06
#define GPIO_PA7_CCP3 0x00001c07
#define GPIO_PA7_USB0PFLT 0x00001c08
#define GPIO_PA7_U1DCD 0x00001c09
//
// GPIO pin B0
//
#define GPIO_PB0_CCP0 0x00010001
#define GPIO_PB0_PWM2 0x00010002
#define GPIO_PB0_U1RX 0x00010005
//
// GPIO pin B1
//
#define GPIO_PB1_CCP2 0x00010401
#define GPIO_PB1_PWM3 0x00010402
#define GPIO_PB1_CCP1 0x00010404
#define GPIO_PB1_U1TX 0x00010405
//
// GPIO pin B2
//
#define GPIO_PB2_I2C0SCL 0x00010801
#define GPIO_PB2_IDX0 0x00010802
#define GPIO_PB2_CCP3 0x00010804
#define GPIO_PB2_CCP0 0x00010805
#define GPIO_PB2_USB0EPEN 0x00010808
//
// GPIO pin B3
//
#define GPIO_PB3_I2C0SDA 0x00010c01
#define GPIO_PB3_FAULT0 0x00010c02
#define GPIO_PB3_FAULT3 0x00010c04
#define GPIO_PB3_USB0PFLT 0x00010c08
//
// GPIO pin B4
//
#define GPIO_PB4_U2RX 0x00011004
#define GPIO_PB4_CAN0RX 0x00011005
#define GPIO_PB4_IDX0 0x00011006
#define GPIO_PB4_U1RX 0x00011007
#define GPIO_PB4_EPI0S23 0x00011008
//
// GPIO pin B5
//
#define GPIO_PB5_C0O 0x00011401
#define GPIO_PB5_CCP5 0x00011402
#define GPIO_PB5_CCP6 0x00011403
#define GPIO_PB5_CCP0 0x00011404
#define GPIO_PB5_CAN0TX 0x00011405
#define GPIO_PB5_CCP2 0x00011406
#define GPIO_PB5_U1TX 0x00011407
#define GPIO_PB5_EPI0S22 0x00011408
//
// GPIO pin B6
//
#define GPIO_PB6_CCP1 0x00011801
#define GPIO_PB6_CCP7 0x00011802
#define GPIO_PB6_C0O 0x00011803
#define GPIO_PB6_FAULT1 0x00011804
#define GPIO_PB6_IDX0 0x00011805
#define GPIO_PB6_CCP5 0x00011806
#define GPIO_PB6_I2S0TXSCK 0x00011809
//
// GPIO pin B7
//
#define GPIO_PB7_NMI 0x00011c04
//
// GPIO pin C0
//
#define GPIO_PC0_TCK 0x00020003
//
// GPIO pin C1
//
#define GPIO_PC1_TMS 0x00020403
//
// GPIO pin C2
//
#define GPIO_PC2_TDI 0x00020803
//
// GPIO pin C3
//
#define GPIO_PC3_TDO 0x00020c03
//
// GPIO pin C4
//
#define GPIO_PC4_CCP5 0x00021001
#define GPIO_PC4_PHA0 0x00021002
#define GPIO_PC4_PWM6 0x00021004
#define GPIO_PC4_CCP2 0x00021005
#define GPIO_PC4_CCP4 0x00021006
#define GPIO_PC4_EPI0S2 0x00021008
#define GPIO_PC4_CCP1 0x00021009
//
// GPIO pin C5
//
#define GPIO_PC5_CCP1 0x00021401
#define GPIO_PC5_C1O 0x00021402
#define GPIO_PC5_C0O 0x00021403
#define GPIO_PC5_FAULT2 0x00021404
#define GPIO_PC5_CCP3 0x00021405
#define GPIO_PC5_USB0EPEN 0x00021406
#define GPIO_PC5_EPI0S3 0x00021408
//
// GPIO pin C6
//
#define GPIO_PC6_CCP3 0x00021801
#define GPIO_PC6_PHB0 0x00021802
#define GPIO_PC6_C2O 0x00021803
#define GPIO_PC6_PWM7 0x00021804
#define GPIO_PC6_U1RX 0x00021805
#define GPIO_PC6_CCP0 0x00021806
#define GPIO_PC6_USB0PFLT 0x00021807
#define GPIO_PC6_EPI0S4 0x00021808
//
// GPIO pin C7
//
#define GPIO_PC7_CCP4 0x00021c01
#define GPIO_PC7_PHB0 0x00021c02
#define GPIO_PC7_CCP0 0x00021c04
#define GPIO_PC7_U1TX 0x00021c05
#define GPIO_PC7_USB0PFLT 0x00021c06
#define GPIO_PC7_C1O 0x00021c07
#define GPIO_PC7_EPI0S5 0x00021c08
//
// GPIO pin D0
//
#define GPIO_PD0_PWM0 0x00030001
#define GPIO_PD0_CAN0RX 0x00030002
#define GPIO_PD0_IDX0 0x00030003
#define GPIO_PD0_U2RX 0x00030004
#define GPIO_PD0_U1RX 0x00030005
#define GPIO_PD0_CCP6 0x00030006
#define GPIO_PD0_I2S0RXSCK 0x00030008
#define GPIO_PD0_U1CTS 0x00030009
//
// GPIO pin D1
//
#define GPIO_PD1_PWM1 0x00030401
#define GPIO_PD1_CAN0TX 0x00030402
#define GPIO_PD1_PHA0 0x00030403
#define GPIO_PD1_U2TX 0x00030404
#define GPIO_PD1_U1TX 0x00030405
#define GPIO_PD1_CCP7 0x00030406
#define GPIO_PD1_I2S0RXWS 0x00030408
#define GPIO_PD1_U1DCD 0x00030409
#define GPIO_PD1_CCP2 0x0003040a
#define GPIO_PD1_PHB1 0x0003040b
//
// GPIO pin D2
//
#define GPIO_PD2_U1RX 0x00030801
#define GPIO_PD2_CCP6 0x00030802
#define GPIO_PD2_PWM2 0x00030803
#define GPIO_PD2_CCP5 0x00030804
#define GPIO_PD2_EPI0S20 0x00030808
//
// GPIO pin D3
//
#define GPIO_PD3_U1TX 0x00030c01
#define GPIO_PD3_CCP7 0x00030c02
#define GPIO_PD3_PWM3 0x00030c03
#define GPIO_PD3_CCP0 0x00030c04
#define GPIO_PD3_EPI0S21 0x00030c08
//
// GPIO pin D4
//
#define GPIO_PD4_CCP0 0x00031001
#define GPIO_PD4_CCP3 0x00031002
#define GPIO_PD4_I2S0RXSD 0x00031008
#define GPIO_PD4_U1RI 0x00031009
#define GPIO_PD4_EPI0S19 0x0003100a
//
// GPIO pin D5
//
#define GPIO_PD5_CCP2 0x00031401
#define GPIO_PD5_CCP4 0x00031402
#define GPIO_PD5_I2S0RXMCLK 0x00031408
#define GPIO_PD5_U2RX 0x00031409
#define GPIO_PD5_EPI0S28 0x0003140a
//
// GPIO pin D6
//
#define GPIO_PD6_FAULT0 0x00031801
#define GPIO_PD6_I2S0TXSCK 0x00031808
#define GPIO_PD6_U2TX 0x00031809
#define GPIO_PD6_EPI0S29 0x0003180a
//
// GPIO pin D7
//
#define GPIO_PD7_IDX0 0x00031c01
#define GPIO_PD7_C0O 0x00031c02
#define GPIO_PD7_CCP1 0x00031c03
#define GPIO_PD7_I2S0TXWS 0x00031c08
#define GPIO_PD7_U1DTR 0x00031c09
#define GPIO_PD7_EPI0S30 0x00031c0a
//
// GPIO pin E0
//
#define GPIO_PE0_PWM4 0x00040001
#define GPIO_PE0_SSI1CLK 0x00040002
#define GPIO_PE0_CCP3 0x00040003
#define GPIO_PE0_EPI0S8 0x00040008
#define GPIO_PE0_USB0PFLT 0x00040009
//
// GPIO pin E1
//
#define GPIO_PE1_PWM5 0x00040401
#define GPIO_PE1_SSI1FSS 0x00040402
#define GPIO_PE1_FAULT0 0x00040403
#define GPIO_PE1_CCP2 0x00040404
#define GPIO_PE1_CCP6 0x00040405
#define GPIO_PE1_EPI0S9 0x00040408
//
// GPIO pin E2
//
#define GPIO_PE2_CCP4 0x00040801
#define GPIO_PE2_SSI1RX 0x00040802
#define GPIO_PE2_PHB1 0x00040803
#define GPIO_PE2_PHA0 0x00040804
#define GPIO_PE2_CCP2 0x00040805
#define GPIO_PE2_EPI0S24 0x00040808
//
// GPIO pin E3
//
#define GPIO_PE3_CCP1 0x00040c01
#define GPIO_PE3_SSI1TX 0x00040c02
#define GPIO_PE3_PHA1 0x00040c03
#define GPIO_PE3_PHB0 0x00040c04
#define GPIO_PE3_CCP7 0x00040c05
#define GPIO_PE3_EPI0S25 0x00040c08
//
// GPIO pin E4
//
#define GPIO_PE4_CCP3 0x00041001
#define GPIO_PE4_FAULT0 0x00041004
#define GPIO_PE4_U2TX 0x00041005
#define GPIO_PE4_CCP2 0x00041006
#define GPIO_PE4_I2S0TXWS 0x00041009
//
// GPIO pin E5
//
#define GPIO_PE5_CCP5 0x00041401
#define GPIO_PE5_I2S0TXSD 0x00041409
//
// GPIO pin E6
//
#define GPIO_PE6_PWM4 0x00041801
#define GPIO_PE6_C1O 0x00041802
#define GPIO_PE6_U1CTS 0x00041809
//
// GPIO pin E7
//
#define GPIO_PE7_PWM5 0x00041c01
#define GPIO_PE7_C2O 0x00041c02
#define GPIO_PE7_U1DCD 0x00041c09
//
// GPIO pin F0
//
#define GPIO_PF0_CAN1RX 0x00050001
#define GPIO_PF0_PHB0 0x00050002
#define GPIO_PF0_PWM0 0x00050003
#define GPIO_PF0_I2S0TXSD 0x00050008
#define GPIO_PF0_U1DSR 0x00050009
//
// GPIO pin F1
//
#define GPIO_PF1_CAN1TX 0x00050401
#define GPIO_PF1_IDX1 0x00050402
#define GPIO_PF1_PWM1 0x00050403
#define GPIO_PF1_I2S0TXMCLK 0x00050408
#define GPIO_PF1_U1RTS 0x00050409
#define GPIO_PF1_CCP3 0x0005040a
//
// GPIO pin F2
//
#define GPIO_PF2_LED1 0x00050801
#define GPIO_PF2_PWM4 0x00050802
#define GPIO_PF2_PWM2 0x00050804
#define GPIO_PF2_SSI1CLK 0x00050809
//
// GPIO pin F3
//
#define GPIO_PF3_LED0 0x00050c01
#define GPIO_PF3_PWM5 0x00050c02
#define GPIO_PF3_PWM3 0x00050c04
#define GPIO_PF3_SSI1FSS 0x00050c09
//
// GPIO pin F4
//
#define GPIO_PF4_CCP0 0x00051001
#define GPIO_PF4_C0O 0x00051002
#define GPIO_PF4_FAULT0 0x00051004
#define GPIO_PF4_EPI0S12 0x00051008
#define GPIO_PF4_SSI1RX 0x00051009
//
// GPIO pin F5
//
#define GPIO_PF5_CCP2 0x00051401
#define GPIO_PF5_C1O 0x00051402
#define GPIO_PF5_EPI0S15 0x00051408
#define GPIO_PF5_SSI1TX 0x00051409
//
// GPIO pin F6
//
#define GPIO_PF6_CCP1 0x00051801
#define GPIO_PF6_C2O 0x00051802
#define GPIO_PF6_PHA0 0x00051804
#define GPIO_PF6_I2S0TXMCLK 0x00051809
#define GPIO_PF6_U1RTS 0x0005180a
//
// GPIO pin F7
//
#define GPIO_PF7_CCP4 0x00051c01
#define GPIO_PF7_PHB0 0x00051c04
#define GPIO_PF7_EPI0S12 0x00051c08
#define GPIO_PF7_FAULT1 0x00051c09
//
// GPIO pin G0
//
#define GPIO_PG0_U2RX 0x00060001
#define GPIO_PG0_PWM0 0x00060002
#define GPIO_PG0_I2C1SCL 0x00060003
#define GPIO_PG0_PWM4 0x00060004
#define GPIO_PG0_USB0EPEN 0x00060007
#define GPIO_PG0_EPI0S13 0x00060008
//
// GPIO pin G1
//
#define GPIO_PG1_U2TX 0x00060401
#define GPIO_PG1_PWM1 0x00060402
#define GPIO_PG1_I2C1SDA 0x00060403
#define GPIO_PG1_PWM5 0x00060404
#define GPIO_PG1_EPI0S14 0x00060408
//
// GPIO pin G2
//
#define GPIO_PG2_PWM0 0x00060801
#define GPIO_PG2_FAULT0 0x00060804
#define GPIO_PG2_IDX1 0x00060808
#define GPIO_PG2_I2S0RXSD 0x00060809
//
// GPIO pin G3
//
#define GPIO_PG3_PWM1 0x00060c01
#define GPIO_PG3_FAULT2 0x00060c04
#define GPIO_PG3_FAULT0 0x00060c08
#define GPIO_PG3_I2S0RXMCLK 0x00060c09
//
// GPIO pin G4
//
#define GPIO_PG4_CCP3 0x00061001
#define GPIO_PG4_FAULT1 0x00061004
#define GPIO_PG4_EPI0S15 0x00061008
#define GPIO_PG4_PWM6 0x00061009
#define GPIO_PG4_U1RI 0x0006100a
//
// GPIO pin G5
//
#define GPIO_PG5_CCP5 0x00061401
#define GPIO_PG5_IDX0 0x00061404
#define GPIO_PG5_FAULT1 0x00061405
#define GPIO_PG5_PWM7 0x00061408
#define GPIO_PG5_I2S0RXSCK 0x00061409
#define GPIO_PG5_U1DTR 0x0006140a
//
// GPIO pin G6
//
#define GPIO_PG6_PHA1 0x00061801
#define GPIO_PG6_PWM6 0x00061804
#define GPIO_PG6_FAULT1 0x00061808
#define GPIO_PG6_I2S0RXWS 0x00061809
#define GPIO_PG6_U1RI 0x0006180a
//
// GPIO pin G7
//
#define GPIO_PG7_PHB1 0x00061c01
#define GPIO_PG7_PWM7 0x00061c04
#define GPIO_PG7_CCP5 0x00061c08
#define GPIO_PG7_EPI0S31 0x00061c09
//
// GPIO pin H0
//
#define GPIO_PH0_CCP6 0x00070001
#define GPIO_PH0_PWM2 0x00070002
#define GPIO_PH0_EPI0S6 0x00070008
#define GPIO_PH0_PWM4 0x00070009
//
// GPIO pin H1
//
#define GPIO_PH1_CCP7 0x00070401
#define GPIO_PH1_PWM3 0x00070402
#define GPIO_PH1_EPI0S7 0x00070408
#define GPIO_PH1_PWM5 0x00070409
//
// GPIO pin H2
//
#define GPIO_PH2_IDX1 0x00070801
#define GPIO_PH2_C1O 0x00070802
#define GPIO_PH2_FAULT3 0x00070804
#define GPIO_PH2_EPI0S1 0x00070808
//
// GPIO pin H3
//
#define GPIO_PH3_PHB0 0x00070c01
#define GPIO_PH3_FAULT0 0x00070c02
#define GPIO_PH3_USB0EPEN 0x00070c04
#define GPIO_PH3_EPI0S0 0x00070c08
//
// GPIO pin H4
//
#define GPIO_PH4_USB0PFLT 0x00071004
#define GPIO_PH4_EPI0S10 0x00071008
#define GPIO_PH4_SSI1CLK 0x0007100b
//
// GPIO pin H5
//
#define GPIO_PH5_EPI0S11 0x00071408
#define GPIO_PH5_FAULT2 0x0007140a
#define GPIO_PH5_SSI1FSS 0x0007140b
//
// GPIO pin H6
//
#define GPIO_PH6_EPI0S26 0x00071808
#define GPIO_PH6_PWM4 0x0007180a
#define GPIO_PH6_SSI1RX 0x0007180b
//
// GPIO pin H7
//
#define GPIO_PH7_EPI0S27 0x00071c08
#define GPIO_PH7_PWM5 0x00071c0a
#define GPIO_PH7_SSI1TX 0x00071c0b
//
// GPIO pin J0
//
#define GPIO_PJ0_EPI0S16 0x00080008
#define GPIO_PJ0_PWM0 0x0008000a
#define GPIO_PJ0_I2C1SCL 0x0008000b
//
// GPIO pin J1
//
#define GPIO_PJ1_EPI0S17 0x00080408
#define GPIO_PJ1_USB0PFLT 0x00080409
#define GPIO_PJ1_PWM1 0x0008040a
#define GPIO_PJ1_I2C1SDA 0x0008040b
//
// GPIO pin J2
//
#define GPIO_PJ2_EPI0S18 0x00080808
#define GPIO_PJ2_CCP0 0x00080809
#define GPIO_PJ2_FAULT0 0x0008080a
//
// GPIO pin J3
//
#define GPIO_PJ3_EPI0S19 0x00080c08
#define GPIO_PJ3_U1CTS 0x00080c09
#define GPIO_PJ3_CCP6 0x00080c0a
//
// GPIO pin J4
//
#define GPIO_PJ4_EPI0S28 0x00081008
#define GPIO_PJ4_U1DCD 0x00081009
#define GPIO_PJ4_CCP4 0x0008100a
//
// GPIO pin J5
//
#define GPIO_PJ5_EPI0S29 0x00081408
#define GPIO_PJ5_U1DSR 0x00081409
#define GPIO_PJ5_CCP2 0x0008140a
//
// GPIO pin J6
//
#define GPIO_PJ6_EPI0S30 0x00081808
#define GPIO_PJ6_U1RTS 0x00081809
#define GPIO_PJ6_CCP1 0x0008180a
//
// GPIO pin J7
//
#define GPIO_PJ7_U1DTR 0x00081c09
#define GPIO_PJ7_CCP0 0x00081c0a
//*****************************************************************************
//
// Prototypes for the APIs.
@ -741,12 +132,18 @@ extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
@ -754,6 +151,25 @@ extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//****************************************************************************
//
// The definitions for GPIOPinConfigure previously resided in this file but
// have been moved to pin_map.h and made part-specific (in other words, only
// those definitions that are valid based on the selected part, as defined by
// PART_<partnum>, will be made available). For backwards compatibility,
// pin_map.h is included here so that the expected definitions will still be
// available (though part-specific now, so some that were previously available
// but inappropriate for the given part will not be available).
//
//*****************************************************************************
#ifndef DEPRECATED
#include "pin_map.h"
#endif
//*****************************************************************************
//

678
bsp/lm3s8962/Libraries/driverlib/hibernate.c
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48
bsp/lm3s8962/Libraries/driverlib/hibernate.h
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@ -2,7 +2,7 @@
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -41,34 +41,50 @@ extern "C"
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x04
#define HIBERNATE_CLOCK_SEL_DIV128 0x00
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x10
#define HIBERNATE_WAKE_RTC 0x08
#define HIBERNATE_WAKE_PIN 0x00000010
#define HIBERNATE_WAKE_RTC 0x00000008
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x20
#define HIBERNATE_LOW_BAT_ABORT 0xA0
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_PIN_WAKE 0x08
#define HIBERNATE_INT_LOW_BAT 0x04
#define HIBERNATE_INT_RTC_MATCH_0 0x01
#define HIBERNATE_INT_RTC_MATCH_1 0x02
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
#define HIBERNATE_INT_PIN_WAKE 0x00000008
#define HIBERNATE_INT_LOW_BAT 0x00000004
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
//*****************************************************************************
//
// Macros defining oscillator configuration options for the
// HibernateClockConfig() function.
//
//*****************************************************************************
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
#define HIBERNATE_OSC_DISABLE 0x00010000
//*****************************************************************************
//
@ -101,7 +117,13 @@ extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned int HibernateIsActive(void);
extern unsigned long HibernateIsActive(void);
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCSSMatch0Get(void);
extern unsigned long HibernateRTCSSGet(void);
extern void HibernateClockConfig(unsigned long ulConfig);
extern void HibernateBatCheckStart(void);
extern unsigned long HibernateBatCheckDone(void);
//*****************************************************************************
//

660
bsp/lm3s8962/Libraries/driverlib/i2c.c
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33
bsp/lm3s8962/Libraries/driverlib/i2c.h
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@ -2,7 +2,7 @@
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -65,6 +65,8 @@ extern "C"
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
@ -75,6 +77,8 @@ extern "C"
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
//*****************************************************************************
//
@ -95,6 +99,9 @@ extern "C"
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
@ -103,6 +110,14 @@ extern "C"
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// I2C Slave interrupts.
@ -133,6 +148,18 @@ extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterIntEnableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern void I2CMasterIntClearEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
@ -141,6 +168,8 @@ extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);

304
bsp/lm3s8962/Libraries/driverlib/i2s.c
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@ -2,7 +2,7 @@
//
// i2s.c - Driver for the I2S controller.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -45,7 +45,7 @@
//!
//! This function enables the transmit module for operation. The module
//! should be enabled after configuration. When the module is disabled,
//! no data or clocks will be generated on the I2S signals.
//! no data or clocks are generated on the I2S signals.
//!
//! \return None.
//
@ -77,7 +77,7 @@ I2STxEnable(unsigned long ulBase)
//!
//! This function disables the transmit module for operation. The module
//! should be disabled before configuration. When the module is disabled,
//! no data or clocks will be generated on the I2S signals.
//! no data or clocks are generated on the I2S signals.
//!
//! \return None.
//
@ -101,18 +101,19 @@ I2STxDisable(unsigned long ulBase)
//! Writes data samples to the I2S transmit FIFO with blocking.
//!
//! \param ulBase is the I2S module base address.
//! \param ulData is the single or dual channel I2S data.
//! \param ulData is the single- or dual-channel I2S data.
//!
//! This function writes a single channel sample or combined left-right
//! This function writes a single-channel sample or combined left-right
//! samples to the I2S transmit FIFO. The format of the sample is determined
//! by the configuration that was used with the function I2STxConfigSet().
//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
//! contains either the left or right sample. The left and right sample
//! alternate with each write to the FIFO, left sample first. If the transmit
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! \e ulData parameter contains both the left and right samples. If the
//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
//! contains the single channel sample.
//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData
//! parameter contains either the left or right sample. The left and right
//! sample alternate with each write to the FIFO, left sample first. If the
//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or
//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both
//! the left and right samples. If the transmit mode is
//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single
//! channel sample.
//!
//! For the compact modes, both the left and right samples are written at
//! the same time. If 16-bit compact mode is used, then the least significant
@ -121,7 +122,7 @@ I2STxDisable(unsigned long ulBase)
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no room in the transmit FIFO, then this function will wait
//! If there is no room in the transmit FIFO, then this function waits
//! in a polling loop until the data can be written.
//!
//! \return None.
@ -153,18 +154,19 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData)
//! Writes data samples to the I2S transmit FIFO without blocking.
//!
//! \param ulBase is the I2S module base address.
//! \param ulData is the single or dual channel I2S data.
//! \param ulData is the single- or dual-channel I2S data.
//!
//! This function writes a single channel sample or combined left-right
//! This function writes a single-channel sample or combined left-right
//! samples to the I2S transmit FIFO. The format of the sample is determined
//! by the configuration that was used with the function I2STxConfigSet().
//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
//! contains either the left or right sample. The left and right sample
//! alternate with each write to the FIFO, left sample first. If the transmit
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! \e ulData parameter contains both the left and right samples. If the
//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
//! contains the single channel sample.
//! If the transmit mode is \b I2S_MODE_DUAL_STEREO then the \e ulData
//! parameter contains either the left or right sample. The left and right
//! sample alternate with each write to the FIFO, left sample first. If the
//! transmit mode is \b I2S_MODE_COMPACT_STEREO_16 or
//! \b I2S_MODE_COMPACT_STEREO_8, then the \e ulData parameter contains both
//! the left and right samples. If the transmit mode is
//! \b I2S_MODE_SINGLE_MONO then the \e ulData parameter contains the single-
//! channel sample.
//!
//! For the compact modes, both the left and right samples are written at
//! the same time. If 16-bit compact mode is used, then the least significant
@ -173,7 +175,7 @@ I2STxDataPut(unsigned long ulBase, unsigned long ulData)
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no room in the transmit FIFO, then this function will return
//! If there is no room in the transmit FIFO, then this function returns
//! immediately without writing any data to the FIFO.
//!
//! \return The number of elements written to the I2S transmit FIFO (1 or 0).
@ -213,23 +215,23 @@ I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
//! options:
//!
//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
//! the I2S transmitter is the clock master or slave.
//! the I2S transmitter is the clock master or slave.
//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per sample.
//! to select the number of bits per sample.
//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per word that are transferred on the data
//! line.
//! to select the number of bits per word that are transferred on the data
//! line.
//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
//! the module transmits zeroes or repeats the last sample when the FIFO is
//! empty.
//! the module transmits zeroes or repeats the last sample when the FIFO is
//! empty.
//!
//! \return None.
//
@ -254,7 +256,7 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig)
//
// If compact 8 mode is used, then need to adjust some bits
// before writing the config register. Also set the FIFO
// config register for 8 bit compact samples.
// config register for 8-bit compact samples.
//
ulConfig &= ~I2S_CONFIG_MODE_MONO;
HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS;
@ -263,14 +265,14 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig)
{
//
// If compact 8 mode is not used, then set the FIFO config
// register for 16 bit. This is okay if a compact mode is
// not used.
// register for 16 bit. This setting is okay if a compact
// mode is not used.
//
HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
}
//
// Write the configuration register. Since all the fields are
// Write the configuration register. Because all the fields are
// specified by the configuration parameter, it is not necessary
// to do a read-modify-write.
//
@ -284,22 +286,21 @@ I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig)
//! \param ulBase is the I2S module base address.
//! \param ulLevel is the FIFO service request limit.
//!
//! This function is used to set the transmit FIFO fullness level at which
//! a service request will occur. The service request is used to generate
//! an interrupt or a DMA transfer request. The transmit FIFO will
//! generate a service request when the number of items in the FIFO is
//! less than the level specified in the \e ulLevel parameter. For example,
//! if \e ulLevel is 8, then a service request will be generated when
//! there are less than 8 samples remaining in the transmit FIFO.
//! This function is used to set the transmit FIFO fullness level at which a
//! service request occurs. The service request is used to generate an
//! interrupt or a DMA transfer request. The transmit FIFO generates a
//! service request when the number of items in the FIFO is less than the level
//! specified in the \e ulLevel parameter. For example, if \e ulLevel is 8,
//! then a service request is generated when there are less than 8 samples
//! remaining in the transmit FIFO.
//!
//! For the purposes of counting the FIFO level, a left-right sample pair
//! counts as 2, whether the mode is dual or compact stereo. When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2. Since the FIFO always deals
//! with sample pairs, the level must be an even number from 0 to 16. The
//! maximum value is 16, which will cause a service request when there
//! is any room in the FIFO. The minimum value is 0, which disables the
//! service request.
//! counts as 2, whether the mode is dual or compact stereo. When mono mode is
//! used, internally the mono sample is still treated as a sample pair, so a
//! single mono sample counts as 2. Because the FIFO always deals with sample
//! pairs, the level must be an even number from 0 to 16. The maximum value is
//! 16, which causes a service request when there is any room in the FIFO.
//! The minimum value is 0, which disables the service request.
//!
//! \return None.
//
@ -352,19 +353,18 @@ I2STxFIFOLimitGet(unsigned long ulBase)
//!
//! \param ulBase is the I2S module base address.
//!
//! This function is used to get the number of samples in the transmit
//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
//! pair counts as 2, whether the mode is dual or compact stereo. When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2. Since the FIFO always deals
//! with sample pairs, normally the level will be an even number from 0 to
//! 16. If dual stereo mode is used and only the left sample has been
//! written without the matching right sample, then the FIFO level will be an
//! odd value. If the FIFO level is odd, it indicates a left-right sample
//! mismatch.
//! This function is used to get the number of samples in the transmit FIFO.
//! For the purposes of measuring the FIFO level, a left-right sample pair
//! counts as 2, whether the mode is dual or compact stereo. When mono mode is
//! used, internally the mono sample is still treated as a sample pair, so a
//! single mono sample counts as 2. Because the FIFO always deals with sample
//! pairs, normally the level is an even number from 0 to 16. If dual stereo
//! mode is used and only the left sample has been written without the matching
//! right sample, then the FIFO level is an odd value. If the FIFO level is
//! odd, it indicates a left-right sample mismatch.
//!
//! \return Returns the number of samples in the transmit FIFO, which will
//! normally be an even number.
//! \return Returns the number of samples in the transmit FIFO, which is
//! normally an even number.
//
//*****************************************************************************
unsigned long
@ -387,9 +387,9 @@ I2STxFIFOLevelGet(unsigned long ulBase)
//!
//! \param ulBase is the I2S module base address.
//!
//! This function enables the receive module for operation. The module
//! should be enabled after configuration. When the module is disabled,
//! no data will be clocked in regardless of the signals on the I2S interface.
//! This function enables the receive module for operation. The module should
//! be enabled after configuration. When the module is disabled, no data is
//! clocked in regardless of the signals on the I2S interface.
//!
//! \return None.
//
@ -419,9 +419,9 @@ I2SRxEnable(unsigned long ulBase)
//!
//! \param ulBase is the I2S module base address.
//!
//! This function disables the receive module for operation. The module
//! should be disabled before configuration. When the module is disabled,
//! no data will be clocked in regardless of the signals on the I2S interface.
//! This function disables the receive module for operation. The module should
//! be disabled before configuration. When the module is disabled, no data is
//! clocked in regardless of the signals on the I2S interface.
//!
//! \return None.
//
@ -450,12 +450,12 @@ I2SRxDisable(unsigned long ulBase)
//! This function reads a single channel sample or combined left-right
//! samples from the I2S receive FIFO. The format of the sample is determined
//! by the configuration that was used with the function I2SRxConfigSet().
//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value
//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the returned value
//! contains either the left or right sample. The left and right sample
//! alternate with each read from the FIFO, left sample first. If the receive
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! returned data contains both the left and right samples. If the
//! receive mode is I2S_MODE_SINGLE_MONO then the returned data
//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then
//! the returned data contains both the left and right samples. If the
//! receive mode is \b I2S_MODE_SINGLE_MONO then the returned data
//! contains the single channel sample.
//!
//! For the compact modes, both the left and right samples are read at
@ -465,7 +465,7 @@ I2SRxDisable(unsigned long ulBase)
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no data in the receive FIFO, then this function will wait
//! If there is no data in the receive FIFO, then this function waits
//! in a polling loop until data is available.
//!
//! \return None.
@ -502,12 +502,12 @@ I2SRxDataGet(unsigned long ulBase, unsigned long *pulData)
//! This function reads a single channel sample or combined left-right
//! samples from the I2S receive FIFO. The format of the sample is determined
//! by the configuration that was used with the function I2SRxConfigSet().
//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data
//! If the receive mode is \b I2S_MODE_DUAL_STEREO then the received data
//! contains either the left or right sample. The left and right sample
//! alternate with each read from the FIFO, left sample first. If the receive
//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
//! received data contains both the left and right samples. If the
//! receive mode is I2S_MODE_SINGLE_MONO then the received data
//! mode is \b I2S_MODE_COMPACT_STEREO_16 or \b I2S_MODE_COMPACT_STEREO_8, then
//! the received data contains both the left and right samples. If the
//! receive mode is \b I2S_MODE_SINGLE_MONO then the received data
//! contains the single channel sample.
//!
//! For the compact modes, both the left and right samples are read at
@ -517,7 +517,7 @@ I2SRxDataGet(unsigned long ulBase, unsigned long *pulData)
//! contain the left sample, and the next 8 bits contain the right sample,
//! with the upper 16 bits unused.
//!
//! If there is no data in the receive FIFO, then this function will return
//! If there is no data in the receive FIFO, then this function returns
//! immediately without reading any data from the FIFO.
//!
//! \return The number of elements read from the I2S receive FIFO (1 or 0).
@ -557,20 +557,20 @@ I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//! options:
//!
//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
//! the I2S receiver is the clock master or slave.
//! the I2S receiver is the clock master or slave.
//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per sample.
//! to select the number of bits per sample.
//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per word that are transferred on the data
//! line.
//! to select the number of bits per word that are transferred on the data
//! line.
//!
//! \return None.
//
@ -608,14 +608,14 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
}
//
// The "mono" bits needs to be removed from the configuration word
// The "mono" bits must be removed from the configuration word
// prior to writing to hardware, because the RX configuration register
// does not actually use these bits.
//
ulConfig &= ~I2S_CONFIG_MODE_MONO;
//
// Write the configuration register. Since all the fields are
// Write the configuration register. Because all the fields are
// specified by the configuration parameter, it is not necessary
// to do a read-modify-write.
//
@ -629,23 +629,22 @@ I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
//! \param ulBase is the I2S module base address.
//! \param ulLevel is the FIFO service request limit.
//!
//! This function is used to set the receive FIFO fullness level at which
//! a service request will occur. The service request is used to generate
//! an interrupt or a DMA transfer request. The receive FIFO will
//! generate a service request when the number of items in the FIFO is
//! greater than the level specified in the \e ulLevel parameter. For example,
//! if \e ulLevel is 4, then a service request will be generated when
//! there are more than 4 samples available in the receive FIFO.
//! This function is used to set the receive FIFO fullness level at which a
//! service request occurs. The service request is used to generate an
//! interrupt or a DMA transfer request. The receive FIFO generates a
//! service request when the number of items in the FIFO is greater than the
//! level specified in the \e ulLevel parameter. For example, if \e ulLevel is
//! 4, then a service request is generated when there are more than 4 samples
//! available in the receive FIFO.
//!
//! For the purposes of counting the FIFO level, a left-right sample pair
//! counts as 2, whether the mode is dual or compact stereo. When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2. Since the FIFO always deals
//! with sample pairs, the level must be an even number from 0 to 16. The
//! minimum value is 0, which will cause a service request when there
//! is any data available in the FIFO. The maximum value is 16, which
//! disables the service request (because there cannot be more than 16
//! items in the FIFO).
//! counts as 2, whether the mode is dual or compact stereo. When mono mode is
//! used, internally the mono sample is still treated as a sample pair, so a
//! single mono sample counts as 2. Because the FIFO always deals with sample
//! pairs, the level must be an even number from 0 to 16. The minimum value is
//! 0, which causes a service request when there is any data available in
//! the FIFO. The maximum value is 16, which disables the service request
//! (because there cannot be more than 16 items in the FIFO).
//!
//! \return None.
//
@ -688,7 +687,7 @@ I2SRxFIFOLimitGet(unsigned long ulBase)
//
// Read and return the FIFO limit. The lower bit is masked
// because it always reads as 1, and has no meaning.
// because it always reads as 1 and has no meaning.
//
return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE);
}
@ -699,19 +698,18 @@ I2SRxFIFOLimitGet(unsigned long ulBase)
//!
//! \param ulBase is the I2S module base address.
//!
//! This function is used to get the number of samples in the receive
//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
//! pair counts as 2, whether the mode is dual or compact stereo. When mono
//! mode is used, internally the mono sample is still treated as a sample
//! pair, so a single mono sample counts as 2. Since the FIFO always deals
//! with sample pairs, normally the level will be an even number from 0 to
//! 16. If dual stereo mode is used and only the left sample has been
//! read without reading the matching right sample, then the FIFO level will
//! be an odd value. If the FIFO level is odd, it indicates a left-right
//! sample mismatch.
//! This function is used to get the number of samples in the receive FIFO.
//! For the purposes of measuring the FIFO level, a left-right sample pair
//! counts as 2, whether the mode is dual or compact stereo. When mono mode is
//! used, internally the mono sample is still treated as a sample pair, so a
//! single mono sample counts as 2. Because the FIFO always deals with sample
//! pairs, normally the level is an even number from 0 to 16. If dual stereo
//! mode is used and only the left sample has been read without reading the
//! matching right sample, then the FIFO level is an odd value. If the FIFO
//! level is odd, it indicates a left-right sample mismatch.
//!
//! \return Returns the number of samples in the transmit FIFO, which will
//! normally be an even number.
//! \return Returns the number of samples in the transmit FIFO, which is
//! normally an even number.
//
//*****************************************************************************
unsigned long
@ -737,7 +735,7 @@ I2SRxFIFOLevelGet(unsigned long ulBase)
//! This function simultaneously enables the transmit and receive modules for
//! operation, providing a synchronized SCLK and LRCLK. The module should be
//! enabled after configuration. When the module is disabled, no data or
//! clocks will be generated on the I2S signals.
//! clocks are generated on the I2S signals.
//!
//! \return None.
//
@ -773,7 +771,7 @@ I2STxRxEnable(unsigned long ulBase)
//! \param ulBase is the I2S module base address.
//!
//! This function simultaneously disables the transmit and receive modules.
//! When the module is disabled, no data or clocks will be generated on the I2S
//! When the module is disabled, no data or clocks are generated on the I2S
//! signals.
//!
//! \return None.
@ -805,23 +803,23 @@ I2STxRxDisable(unsigned long ulBase)
//! the logical OR of the following options:
//!
//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
//! - \b I2S_CONFIG_MODE_DUAL for dual-channel stereo,
//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
//! \b I2S_CONFIG_MODE_MONO for single-channel mono format.
//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
//! the I2S transmitter is the clock master or slave.
//! the I2S transmitter is the clock master or slave.
//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per sample.
//! to select the number of bits per sample.
//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
//! to select the number of bits per word that are transferred on the data
//! line.
//! to select the number of bits per word that are transferred on the data
//! line.
//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
//! the module transmits zeroes or repeats the last sample when the FIFO is
//! empty.
//! the module transmits zeroes or repeats the last sample when the FIFO is
//! empty.
//!
//! \return None.
//
@ -863,8 +861,8 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
}
//
// Write the configuration register. Since all the fields are specified by
// the configuration parameter, it is not necessary to do a
// Write the configuration register. Because all the fields are specified
// by the configuration parameter, it is not necessary to do a
// read-modify-write.
//
HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
@ -880,7 +878,7 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
//! choices.
//!
//! This function selects whether the master clock is sourced from the device
//! internal PLL, or comes from an external pin. The I2S serial bit clock
//! internal PLL or comes from an external pin. The I2S serial bit clock
//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master
//! clock. The transmit and receive modules can be configured independently.
//! The \e ulMClock parameter is chosen from the following:
@ -888,7 +886,7 @@ I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT
//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT
//!
//! \return Returns None.
//! \return None.
//
//*****************************************************************************
void
@ -926,7 +924,7 @@ I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock)
//! - \b I2S_INT_TXERR for transmit errors
//! - \b I2S_INT_TXREQ for transmit FIFO service requests
//!
//! \return Returns None.
//! \return None.
//
//*****************************************************************************
void
@ -957,7 +955,7 @@ I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
//!
//! \return Returns None.
//! \return None.
//
//*****************************************************************************
void
@ -1021,22 +1019,22 @@ I2SIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulBase is the I2S module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified pending I2S interrupts. This must
//! be done in the interrupt handler to keep the handler from being called
//! again immediately upon exit. The \e ulIntFlags parameter can be the
//! logical OR of any of the following values: \b I2S_INT_RXERR,
//! This function clears the specified pending I2S interrupts. This function
//! must be called in the interrupt handler to keep the interrupt from being
//! triggered again immediately upon exit. The \e ulIntFlags parameter can be
//! the logical OR of any of the following values: \b I2S_INT_RXERR,
//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return Returns None.
//! \return None.
//
//*****************************************************************************
void
@ -1063,9 +1061,9 @@ I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \param pfnHandler is a pointer to the function to be called when the
//! interrupt is activated.
//!
//! This sets and enables the handler to be called when the I2S controller
//! generates an interrupt. Specific I2S interrupts must still be enabled
//! with the I2SIntEnable() function. It is the responsibility of the
//! This function sets and enables the handler to be called when the I2S
//! controller generates an interrupt. Specific I2S interrupts must still be
//! enabled with the I2SIntEnable() function. It is the responsibility of the
//! interrupt handler to clear any pending interrupts with I2SIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
@ -1100,7 +1098,7 @@ I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the I2S module base address.
//!
//! This function will disable and clear the handler to be called when the
//! This function disables and clears the handler to be called when the
//! I2S interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt

4
bsp/lm3s8962/Libraries/driverlib/i2s.h
View File

@ -2,7 +2,7 @@
//
// i2s.h - Prototypes and macros for the I2S controller.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

196
bsp/lm3s8962/Libraries/driverlib/interrupt.c
View File

@ -2,7 +2,7 @@
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -59,7 +59,58 @@ static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
};
//*****************************************************************************
@ -97,30 +148,32 @@ IntDefaultHandler(void)
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#elif defined(sourcerygxx)
static __attribute__((section(".cs3.region-head.ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#elif defined(ccs)
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#elif defined(ccs) || defined(DOXYGEN)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function allows the processor to respond to interrupts. This function
//! does not affect the set of interrupts enabled in the interrupt controller;
//! it just gates the single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
@ -140,14 +193,15 @@ IntMasterEnable(void)
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function prevents the processor from receiving interrupts. This
//! function does not affect the set of interrupts enabled in the interrupt
//! controller; it just gates the single interrupt from the controller to the
//! processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
@ -172,22 +226,20 @@ IntMasterDisable(void)
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//! if it is enabled (via IntEnable()), the handler function is called in
//! interrupt context. Because the handler function can preempt other code,
//! care must be taken to protect memory or peripherals that are accessed by
//! the handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! otherwise the NVIC does not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts;
//! some tool chains, such as the evaluation version of RV-MDK, do not support
//! linker scripts and therefore will not produce a valid executable. See the
//! discussion of compile-time versus run-time interrupt handler registration
//! in the introduction to this chapter.
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! \return None.
//
@ -224,7 +276,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
}
//
// Point NVIC at the RAM vector table.
// Point the NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
@ -242,7 +294,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! given interrupt is asserted to the processor. The interrupt source is
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -348,7 +400,7 @@ IntPriorityGroupingGet(void)
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
@ -458,19 +510,13 @@ IntEnable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -526,19 +572,13 @@ IntDisable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -548,13 +588,13 @@ IntDisable(unsigned long ulInterrupt)
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//! The specified interrupt is pended in the interrupt controller. Pending an
//! interrupt causes the interrupt controller to execute the corresponding
//! interrupt handler at the next available time, based on the current
//! interrupt state priorities. For example, if called by a higher priority
//! interrupt handler, the specified interrupt handler is not called until
//! after the current interrupt handler has completed execution. The interrupt
//! must have been enabled for it to be called.
//!
//! \return None.
//
@ -591,19 +631,13 @@ IntPendSet(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -613,10 +647,10 @@ IntPendSet(unsigned long ulInterrupt)
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//! The specified interrupt is unpended in the interrupt controller. Unpending
//! an interrupt causes any previously generated interrupts that have not been
//! handled yet (due to higher priority interrupts or the interrupt not having
//! been enabled yet) to be discarded.
//!
//! \return None.
//
@ -646,19 +680,13 @@ IntPendClear(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@ -666,19 +694,19 @@ IntPendClear(unsigned long ulInterrupt)
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//! \param ulPriorityMask is the priority level that is masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! interrupts at the specified or lesser priority level are masked. Masking
//! interrupts can be used to globally disable a set of interrupts with
//! priority below a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
@ -701,10 +729,10 @@ IntPriorityMaskSet(unsigned long ulPriorityMask)
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!

4
bsp/lm3s8962/Libraries/driverlib/interrupt.h
View File

@ -2,7 +2,7 @@
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

1533
bsp/lm3s8962/Libraries/driverlib/lpc.c Normal file
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File diff suppressed because it is too large Load Diff

470
bsp/lm3s8962/Libraries/driverlib/lpc.h Normal file
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@ -0,0 +1,470 @@
//*****************************************************************************
//
// lpc.h - Prototypes for the Low Pin Count (LPC) driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __LPC_H__
#define __LPC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to LPCConfigSet as the ulConfig value, and
// returned from LPCConfigGet.
//
//*****************************************************************************
#define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus
//*****************************************************************************
//
// Values that can be returned from LPCStatus.
//
//*****************************************************************************
#define LPC_STATUS_RST 0x00000400 // LPC is in Reset
#define LPC_STATUS_BUSY 0x00000200 // LPC is Busy
#define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode
#define LPC_STATUS_CA7 0x00000080 // Channel 7 Active
#define LPC_STATUS_CA6 0x00000040 // Channel 6 Active
#define LPC_STATUS_CA5 0x00000020 // Channel 5 Active
#define LPC_STATUS_CA4 0x00000010 // Channel 4 Active
#define LPC_STATUS_CA3 0x00000008 // Channel 3 Active
#define LPC_STATUS_CA2 0x00000004 // Channel 2 Active
#define LPC_STATUS_CA1 0x00000002 // Channel 1 Active
#define LPC_STATUS_CA0 0x00000001 // Channel 0 Active
//*****************************************************************************
//
// Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ
// parameter and returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ15 0x80000000 // Serial IRQ15
#define LPC_IRQ14 0x40000000 // Serial IRQ14
#define LPC_IRQ13 0x20000000 // Serial IRQ13
#define LPC_IRQ12 0x10000000 // Serial IRQ12
#define LPC_IRQ11 0x08000000 // Serial IRQ11
#define LPC_IRQ10 0x04000000 // Serial IRQ10
#define LPC_IRQ9 0x02000000 // Serial IRQ9
#define LPC_IRQ8 0x01000000 // Serial IRQ8
#define LPC_IRQ7 0x00800000 // Serial IRQ7
#define LPC_IRQ6 0x00400000 // Serial IRQ6
#define LPC_IRQ5 0x00200000 // Serial IRQ5
#define LPC_IRQ4 0x00100000 // Serial IRQ4
#define LPC_IRQ3 0x00080000 // Serial IRQ3
#define LPC_IRQ2 0x00040000 // Serial IRQ2
#define LPC_IRQ1 0x00020000 // Serial IRQ1
#define LPC_IRQ0 0x00010000 // Serial IRQ0
//*****************************************************************************
//
// Addition values that can be returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress
#define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode
//*****************************************************************************
//
// Values that can be passed as the ulChannel parameter in LPCChannel...
// API calls.
//
//*****************************************************************************
#define LPC_CHAN_CH0 0 // LPC Channel 0
#define LPC_CHAN_CH1 1 // LPC Channel 1
#define LPC_CHAN_CH2 2 // LPC Channel 2
#define LPC_CHAN_CH3 3 // LPC Channel 3
#define LPC_CHAN_CH4 4 // LPC Channel 4
#define LPC_CHAN_CH5 5 // LPC Channel 5
#define LPC_CHAN_CH6 6 // LPC Channel 6
#define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx)
#define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx)
//*****************************************************************************
//
// Values that can be passed as part of the ulConfig parameter in the
// LPCChannelConfig... functions.
//
//*****************************************************************************
#define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled
#define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0
#define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1
#define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2
#define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3
#define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4
#define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5
#define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6
#define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7
#define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8
#define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9
#define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10
#define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11
#define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12
#define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13
#define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14
#define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15
#define LPC_CHAN_COMxIRQ_DISABLE \
0x00000000 // LCP Channel COMx IRQ Disabled
#define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled
#define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled
#define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0
#define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1
#define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2
#define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3
#define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4
#define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5
#define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6
#define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7
#define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8
#define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9
#define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10
#define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11
#define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12
#define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13
#define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14
#define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15
#define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled
#define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0
#define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1
#define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2
#define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3
#define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4
#define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5
#define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6
#define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7
#define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8
#define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9
#define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10
#define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11
#define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12
#define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13
#define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14
#define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15
#define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled
#define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1
#define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2
#define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3
#define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration
// enabled.
#define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration
// disabled.
#define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size
// is 4 Bytes.
//*****************************************************************************
//
// Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode
// parameter or returned from LPCChannelConfigGet in the pulCOMxMode
// parameter.
//
//*****************************************************************************
#define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model.
#define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data.
#define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to
// memory
#define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to
// UART1
//*****************************************************************************
//
// Additinal values that can be returned from LPCChannelConfigGet in the
// pulCOMxMode parameter.
//
//*****************************************************************************
#define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled.
//*****************************************************************************
//
// Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear
// as the ulIntFlags parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits
// Reset State.
#define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits
// Sleep State.
#define LPC_INT_COMx 0x20000000 // COMx has read/written
// data.
#define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed
#define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read.
#define LPC_INT_CH6_EP_FROM_DATA \
(2 << 24) // From-Host has been written as
// data.
#define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as
// command.
#define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST)
#define LPC_INT_CH6_MB_HOST_WRITE \
(2 << 24) // Host Wrote Last Byte.
#define LPC_INT_CH6_MB_HOST_READ \
(4 << 24) // Host Read Last Byte
#define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read.
#define LPC_INT_CH5_EP_FROM_DATA \
(2 << 20) // From-Host has been written as
// data.
#define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as
// command.
#define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST)
#define LPC_INT_CH5_MB_HOST_WRITE \
(2 << 20) // Host Wrote Last Byte.
#define LPC_INT_CH5_MB_HOST_READ \
(4 << 20) // Host Read Last Byte
#define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read.
#define LPC_INT_CH4_EP_FROM_DATA \
(2 << 16) // From-Host has been written as
// data.
#define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as
// command.
#define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST)
#define LPC_INT_CH4_MB_HOST_WRITE \
(2 << 16) // Host Wrote Last Byte.
#define LPC_INT_CH4_MB_HOST_READ \
(4 << 16) // Host Read Last Byte
#define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read.
#define LPC_INT_CH3_EP_FROM_DATA \
(2 << 12) // From-Host has been written as
// data.
#define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as
// command.
#define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST)
#define LPC_INT_CH3_MB_HOST_WRITE \
(2 << 12) // Host Wrote Last Byte.
#define LPC_INT_CH3_MB_HOST_READ \
(4 << 12) // Host Read Last Byte
#define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read.
#define LPC_INT_CH2_EP_FROM_DATA \
(2 << 8) // From-Host has been written as
// data.
#define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as
// command.
#define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST)
#define LPC_INT_CH2_MB_HOST_WRITE \
(2 << 8) // Host Wrote Last Byte.
#define LPC_INT_CH2_MB_HOST_READ \
(4 << 8) // Host Read Last Byte
#define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read.
#define LPC_INT_CH1_EP_FROM_DATA \
(2 << 4) // From-Host has been written as
// data.
#define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as
// command.
#define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST)
#define LPC_INT_CH1_MB_HOST_WRITE \
(2 << 4) // Host Wrote Last Byte.
#define LPC_INT_CH1_MB_HOST_READ \
(4 << 4) // Host Read Last Byte
#define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read.
#define LPC_INT_CH0_EP_FROM_DATA \
(2 << 0) // From-Host has been written as
// data.
#define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as
// command.
#define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST)
#define LPC_INT_CH0_MB_HOST_WRITE \
(2 << 0) // Host Wrote Last Byte.
#define LPC_INT_CH0_MB_HOST_READ \
(4 << 0) // Host Read Last Byte
#define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST).
//*****************************************************************************
//
// Values that can be passed to LPCCOMxInt... functions as the ulIntFlags
// parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx
#define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX
#define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX
#define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx
#define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX
#define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX
//*****************************************************************************
//
// Values that can be passed to the LPCChannelDMAConfigSet function as part
// of the ulConfig or ulMask parameter, or can be returned from the
// LPCChannelConfigGet function.
//
//*****************************************************************************
#define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host"
// data buffer is full.
//*****************************************************************************
//
// Values that can be passed to the LPCChannelStatusSet and
// LPCChannelStatusClear function, and returned by the LPCChannelStatusGet
// function.
//
//*****************************************************************************
#define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0
#define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1
#define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2
#define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3
#define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4
//*****************************************************************************
//
// Additinoal values that can be returned by the LPCChannelStatusGet function.
//
//*****************************************************************************
#define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH_ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH_ST_CMD 0x00000008 // Command or Data
#define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long LPCConfigGet(unsigned long ulBase);
extern unsigned long LPCStatusGet(unsigned long ulBase,
unsigned long *pulCount,
unsigned long *pulPoolSize);
extern void LPCStatusBlockAddressSet(unsigned long ulBase,
unsigned long ulAddress,
tBoolean bEnabled);
extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase);
extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount);
extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse,
tBoolean bIRQOnChange);
extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ);
extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ);
extern unsigned long LPCIRQGet(unsigned long ulBase);
extern void LPCIRQSend(unsigned long ulBase);
extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void LPCIntUnregister(unsigned long ulBase);
extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelConfigEPSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigMBSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigCOMxSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset,
unsigned long ulCOMxMode);
extern unsigned long LPCChannelConfigGet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long *pulAddress,
unsigned long *pulOffset,
unsigned long *pulCOMxMode);
extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long LPCChannelStatusGet(unsigned long ulBase,
unsigned long ulChannel);
extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelStatusClear(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelDMAConfigSet(unsigned long ulBase,
unsigned long ulConfig,
unsigned long ulMask);
extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase);
extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned char ucData);
extern unsigned short LPCHalfWordRead(unsigned long ulBase,
unsigned long ulOffset);
extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned short usData);
extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned long ulData);
extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __LPC_H__

67
bsp/lm3s8962/Libraries/driverlib/mpu.c
View File

@ -2,7 +2,7 @@
//
// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -42,14 +42,13 @@
//!
//! \param ulMPUConfig is the logical OR of the possible configurations.
//!
//! This function enables the Cortex-M3 memory protection unit. It also
//! configures the default behavior when in privileged mode and while
//! handling a hard fault or NMI. Prior to enabling the MPU, at least one
//! region must be set by calling MPURegionSet() or else by enabling the
//! default region for privileged mode by passing the
//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
//! Once the MPU is enabled, a memory management fault will be generated
//! for any memory access violations.
//! This function enables the Cortex-M memory protection unit. It also
//! configures the default behavior when in privileged mode and while handling
//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
//! be set by calling MPURegionSet() or else by enabling the default region for
//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
//! MPUEnable(). Once the MPU is enabled, a memory management fault is
//! generated for memory access violations.
//!
//! The \e ulMPUConfig parameter should be the logical OR of any of the
//! following:
@ -63,8 +62,8 @@
//! disabled while in one of these exception handlers and the default
//! memory map is applied.
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
//! no default memory map is provided in privileged mode, and the MPU will
//! not be enabled in the fault handlers.
//! no default memory map is provided in privileged mode, and the MPU isl
//! not enabled in the fault handlers.
//!
//! \return None.
//
@ -89,7 +88,7 @@ MPUEnable(unsigned long ulMPUConfig)
//
//! Disables the MPU for use.
//!
//! This function disables the Cortex-M3 memory protection unit. When the
//! This function disables the Cortex-M memory protection unit. When the
//! MPU is disabled, the default memory map is used and memory management
//! faults are not generated.
//!
@ -109,9 +108,8 @@ MPUDisable(void)
//
//! Gets the count of regions supported by the MPU.
//!
//! This function is used to get the number of regions that are supported by
//! the MPU. This is the total number that are supported, including regions
//! that are already programmed.
//! This function is used to get the total number of regions that are supported
//! by the MPU, including regions that are already programmed.
//!
//! \return The number of memory protection regions that are available
//! for programming using MPURegionSet().
@ -121,7 +119,7 @@ unsigned long
MPURegionCountGet(void)
{
//
// Read the DREGION field of the MPU type register, and mask off
// Read the DREGION field of the MPU type register and mask off
// the bits of interest to get the count of regions.
//
return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
@ -135,9 +133,9 @@ MPURegionCountGet(void)
//! \param ulRegion is the region number to enable.
//!
//! This function is used to enable a memory protection region. The region
//! should already be set up with the MPURegionSet() function. Once enabled,
//! the memory protection rules of the region will be applied and access
//! violations will cause a memory management fault.
//! should already be configured with the MPURegionSet() function. Once
//! enabled, the memory protection rules of the region are applied and access
//! violations cause a memory management fault.
//!
//! \return None.
//
@ -168,7 +166,7 @@ MPURegionEnable(unsigned long ulRegion)
//! \param ulRegion is the region number to disable.
//!
//! This function is used to disable a previously enabled memory protection
//! region. The region will remain configured if it is not overwritten with
//! region. The region remains configured if it is not overwritten with
//! another call to MPURegionSet(), and can be enabled again by calling
//! MPURegionEnable().
//!
@ -204,16 +202,16 @@ MPURegionDisable(unsigned long ulRegion)
//! \param ulFlags is a set of flags to define the attributes of the region.
//!
//! This function sets up the protection rules for a region. The region has
//! a base address and a set of attributes including the size, which must
//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
//! according to the size.
//! a base address and a set of attributes including the size. The base
//! address parameter, \e ulAddr, must be aligned according to the size, and
//! the size must be a power of 2.
//!
//! The \e ulFlags parameter is the logical OR of all of the attributes
//! of the region. It is a combination of choices for region size,
//! execute permission, read/write permissions, disabled sub-regions,
//! and a flag to determine if the region is enabled.
//!
//! The size flag determines the size of a region, and must be one of the
//! The size flag determines the size of a region and must be one of the
//! following:
//!
//! - \b MPU_RGN_SIZE_32B
@ -263,8 +261,8 @@ MPURegionDisable(unsigned long ulRegion)
//!
//! The region is automatically divided into 8 equally-sized sub-regions by
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
//! or larger. Any of these 8 sub-regions can be disabled. This allows
//! for creation of ``holes'' in a region which can be left open, or overlaid
//! or larger. Any of these 8 sub-regions can be disabled, allowing for
//! creation of ``holes'' in a region which can be left open, or overlaid
//! by another region with different attributes. Any of the 8 sub-regions
//! can be disabled with a logical OR of any of the following flags:
//!
@ -293,7 +291,7 @@ MPURegionDisable(unsigned long ulRegion)
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
//! </code>
//!
//! \note This function will write to multiple registers and is not protected
//! \note This function writes to multiple registers and is not protected
//! from interrupts. It is possible that an interrupt which accesses a
//! region may occur while that region is in the process of being changed.
//! The safest way to handle this is to disable a region before changing it.
@ -342,9 +340,9 @@ MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
//! meanings and format of the parameters is the same as that of the
//! MPURegionSet() function.
//!
//! This function can be used to save the configuration of a region for
//! later use with the MPURegionSet() function. The region's enable state
//! will be preserved in the attributes that are saved.
//! This function can be used to save the configuration of a region for later
//! use with the MPURegionSet() function. The region's enable state is
//! preserved in the attributes that are saved.
//!
//! \return None.
//
@ -383,8 +381,9 @@ MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
//! \param pfnHandler is a pointer to the function to be called when the
//! memory management fault occurs.
//!
//! This sets and enables the handler to be called when the MPU generates
//! a memory management fault due to a protection region access violation.
//! This function sets and enables the handler to be called when the MPU
//! generates a memory management fault due to a protection region access
//! violation.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -415,7 +414,7 @@ MPUIntRegister(void (*pfnHandler)(void))
//
//! Unregisters an interrupt handler for the memory management fault.
//!
//! This function will disable and clear the handler to be called when a
//! This function disables and clears the handler to be called when a
//! memory management fault occurs.
//!
//! \sa IntRegister() for important information about registering interrupt

4
bsp/lm3s8962/Libraries/driverlib/mpu.h
View File

@ -2,7 +2,7 @@
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

971
bsp/lm3s8962/Libraries/driverlib/peci.c Normal file
View File

@ -0,0 +1,971 @@
//*****************************************************************************
//
// peci.c - Driver for the Platform Environment Control Interface (PECI)
// module.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup peci_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_peci.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/peci.h"
//*****************************************************************************
//
// The following defines provide characteristics of the PECI module that are
// important to the driver but which can not be gleaned from the register
// definitions.
//
//*****************************************************************************
#define PECI_MAX_BAUD 2000000 // Maximum baud rate
#define PECI_MIN_BAUD 2000 // Minimum baud rate
#define PECI_MIN_RATIO 8 // Minimum baud rate divider
#define PECI_MAX_RATIO 65535 // Maximum baud rate divider
#define PECI_POLL_PRESCALE 4096 // Polling timer prescaler
#define PECI_MIN_POLL 2 // Minimum polling interval (ms)
#define PECI_MAX_POLL 1000 // Maximum polling interval (ms)
//*****************************************************************************
//
//! \internal
//! Checks a PECI domain.
//!
//! \param ulDomain is the PECI domain identifier.
//!
//! This function determines if a domain identifier is valid.
//!
//! \return Returns \b true if the domain identifier is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
PECIDomainValid(unsigned long ulDomain)
{
return((ulDomain == PECI_DOMAIN_M0D0) ||
(ulDomain == PECI_DOMAIN_M0D1) ||
(ulDomain == PECI_DOMAIN_M1D0) ||
(ulDomain == PECI_DOMAIN_M1D1));
}
#endif
//*****************************************************************************
//
//! Sets the configuration of the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulPECIClk is the rate of the clock supplied to the PECI module.
//! \param ulBaud is the bit rate that should be used for the PECI transfers.
//! \param ulPoll is the polling rate, in ms, that should be used for the
//! time between PECI polls.
//! \param ulOffset is the offset to be applied to all temperature values to
//! convert from relative to absolute.
//! \param ulRetry is the number of retry attempts for a PECI transaction.
//!
//! This function initializes operation of the PECI block. It programs the bit
//! rate, polling rate and retry counts for PECI transactions. It also
//! programs the offset value to be used to translate relative temperature
//! values from PECI transactions to absolute values. At the end of this
//! function, no host/domain combinations are enabled. Each desired
//! host/domain combination can be configured/enabled with a call to
//! PECIDomainEnable().
//!
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! The \e ulBaud parameter defines the bit rate for the PECI transactions.
//! This value is used to calculate a divisor value based on the specified
//! \e ulPECIClk. If the exact baud rate cannot be achieved (due to rounding),
//! the baud rate is programmed to the nearest value that is less than the
//! specified value.
//!
//! The \e ulPoll parameter defines the polling rate, in milliseconds, used
//! for PECI transactions. For generation of the polling rate, the \e
//! ulPECIClk is pre-divided by \b 4096. A value of 0 disables the polling
//! feature. If the exact polling rate cannot be achieved (due to rounding),
//! the polling rate is programmed to the nearest value that is greater than
//! the specified value.
//!
//! The \e ulRetry parameter defines the number of PECI transactions that are
//! attempted before indicating an error condition.
//!
//! \return None.
//
//*****************************************************************************
void
PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long ulBaud, unsigned long ulPoll,
unsigned long ulOffset, unsigned long ulRetry)
{
unsigned long ulTemp, ulDiv;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(ulPECIClk != 0);
ASSERT((ulBaud != 0) && (ulBaud <= PECI_MAX_BAUD) &&
(ulBaud >= PECI_MIN_BAUD) &&
((ulBaud * 4 * PECI_MIN_RATIO) < ulPECIClk));
ASSERT((ulPoll == 0) ||
((ulPoll >= PECI_MIN_POLL) && (ulPoll <= PECI_MAX_POLL)));
//
// Generate value for the PECI Control Register.
//
ulTemp = ((ulOffset << PECI_CTL_OFFSET_S) & PECI_CTL_OFFSET_M);
ulTemp |= ((ulRetry << PECI_CTL_CRETRY_S) & PECI_CTL_CRETRY_M);
HWREG(ulBase + PECI_O_CTL) = ulTemp;
//
// Compute the divisor for the PECI baud rate clock.
// Round up, to ensure programmed baud rate is <= specified rate.
// Ensure that proper ratio is maintained for clock:baud.
//
ulDiv = (ulPECIClk + (4 * ulBaud) - 1) / (4 * ulBaud);
ulDiv = (ulDiv < PECI_MIN_RATIO) ? PECI_MIN_RATIO : ulDiv;
ulDiv = (ulDiv > PECI_MAX_RATIO) ? PECI_MAX_RATIO : ulDiv;
ulTemp = ((ulDiv << PECI_DIV_BAUD_S) & PECI_DIV_BAUD_M);
//
// Compute the divisor for the PECI polling rate.
// Round up, to ensure programmed polling rate is >= specified rate.
//
ulDiv = ((ulPoll == 0) ? 0 : ((((ulPECIClk * ulPoll) / 1000) +
(PECI_POLL_PRESCALE - 1)) /
PECI_POLL_PRESCALE));
ulTemp |= ((ulDiv << PECI_DIV_POLL_S) & PECI_DIV_POLL_M);;
HWREG(ulBase + PECI_O_DIV) = ulTemp;
}
//*****************************************************************************
//
//! Gets the current configuration of the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulPECIClk is the rate of the clock supplied to the PECI module.
//! \param pulBaud is a pointer to storage for the bit rate.
//! \param pulPoll is a pointer to storage for the polling rate.
//! \param pulOffset is a pointer to stoarage for the offset.
//! \param pulRetry is a pointer to storage for the retry count.
//!
//! The baud rate and poll rate for the PECI module are determined, given an
//! explicitly provided peripheral clock. The returned rates are the actual
//! rates being used; they may not be the same as the requested rates, due to
//! rounding in the calculations.
//!
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! \return None.
//
//*****************************************************************************
void
PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long *pulBaud, unsigned long *pulPoll,
unsigned long *pulOffset, unsigned long *pulRetry)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(ulPECIClk != 0);
ASSERT(*pulBaud != 0);
ASSERT(*pulPoll != 0);
ASSERT(*pulOffset != 0);
ASSERT(*pulRetry != 0);
//
// Retrieve the Offset and Retry values
//
ulTemp = HWREG(ulBase + PECI_O_CTL);
*pulOffset = ((ulTemp & PECI_CTL_OFFSET_M) >> PECI_CTL_OFFSET_S);
*pulRetry = ((ulTemp & PECI_CTL_CRETRY_M) >> PECI_CTL_CRETRY_S);
//
// Calculate the baud rate.
//
ulTemp = HWREG(ulBase + PECI_O_DIV);
*pulBaud = ulPECIClk / ((ulTemp & PECI_DIV_BAUD_M) >> PECI_DIV_BAUD_S);
//
// Compute the divisor for the PECI polling rate.
// Round up, to ensure programmed polling rate is >= specified rate.
//
*pulPoll = ((((ulTemp & PECI_DIV_POLL_M) >> PECI_DIV_POLL_S) * 1000) /
(ulPECIClk / PECI_POLL_PRESCALE));
}
//*****************************************************************************
//
//! Enables bypassing of negotiation errors.
//!
//! \param ulBase is the base address of the PECI module.
//!
//! This function enables bypassing of negotiation errors that might occur
//! during a PECI transaction. When enabled, negotiation errors are ignored.
//!
//! \return None.
//
//*****************************************************************************
void
PECIBypassEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Enable bypass.
//
HWREG(ulBase + PECI_O_CTL) |= PECI_CTL_BYERR;
}
//*****************************************************************************
//
//! Disables bypassing of negotiation errors.
//!
//! \param ulBase is the base address of the PECI module.
//!
//! This function disables bypassing of negotiation errors that might occur
//! during a PECI transaction. When disabled, negotiation errors are reported
//! and the remainder of the transaction is aborted.
//!
//! \return None.
//
//*****************************************************************************
void
PECIBypassDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable bypass.
//
HWREG(ulBase + PECI_O_CTL) &= ~PECI_CTL_BYERR;
}
//*****************************************************************************
//
//! Sets the configuration of the specified PECI domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be configured.
//! \param ulHigh is the high temperature threshold value.
//! \param ulLow is the low temperature threshold value.
//!
//! This function configures the specified PECI domain for temperature
//! monitoring operations. The values for \e ulHigh and \e ulLow can be
//! specified as values relative to the maximum temperature allowed, or they
//! can be specified as absolute temperatures if an offset was programmed
//! in the PECIConfigSet() function.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain,
unsigned long ulHigh, unsigned long ulLow)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
ASSERT(ulHigh <= 0xFFFF);
ASSERT(ulLow <= 0xFFFF);
ASSERT(ulHigh > ulLow);
//
// Set the HTHRESH and LTHRESH fields in the domain control/status
// register.
//
HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)) =
(((ulHigh << PECI_M0D0C_HITHR_S) & PECI_M0D0C_HITHR_M) |
((ulLow << PECI_M0D0C_LOTHR_S) & PECI_M0D0C_LOTHR_M));
}
//*****************************************************************************
//
//! Gets the configuration of the specified PECI domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be configured.
//! \param pulHigh is a pointer to storage for the high threshold.
//! \param pulLow is a pointer to storage for the low threshold.
//!
//! This function configures the specified PECI domain for temperature
//! monitoring operations. The values for \e ulHigh and \e ulLow can be
//! specified as values relative to the maximum temperature allowed, or they
//! can be specified as absolute temperatures if an offset was programmed
//! in the PECIConfigSet() function.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain,
unsigned long *pulHigh, unsigned long *pulLow)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
ASSERT(pulHigh != 0);
ASSERT(pulLow != 0);
//
// Get the HTHRESH and LTHRESH fields in the domain control/status
// register.
//
ulTemp = HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4));
*pulHigh = ((ulTemp && PECI_M0D0C_HITHR_M) >> PECI_M0D0C_HITHR_S);
*pulLow = ((ulTemp && PECI_M0D0C_LOTHR_M) >> PECI_M0D0C_LOTHR_S);
}
//*****************************************************************************
//
//! Enables a domain within the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be enabled.
//!
//! This function enables the specified PECI domain for temperature monitoring
//! operations.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Enable the specified domain.
//
HWREG(ulBase + PECI_O_CTL) |= (1 << ulDomain);
}
//*****************************************************************************
//
//! Disables a domain within the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function disables the specified PECI domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Disable the specified domain.
//
HWREG(ulBase + PECI_O_CTL) &= ~(1 << ulDomain);
}
//*****************************************************************************
//
//! Reads the current temperature value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function returns the most recently read temperature value from the
//! specified domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIDomainValueGet(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Return the most recently polled temperature value
//
return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) &
PECI_M0D0_VALUE_M)));
}
//*****************************************************************************
//
//! Reads the maximum/error value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function returns the maximum temperature value for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIDomainMaxReadGet(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Return the most recently polled temperature value
//
return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) &
PECI_M0D0_MAXREAD_M) >> PECI_M0D0_MAXREAD_S));
}
//*****************************************************************************
//
//! Clears the current temperature value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function clears the current and maximum values for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Clear the temperature value.
//
HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_VALUE_M;
}
//*****************************************************************************
//
//! Clears the maximum/error value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function clears the current and maximum values for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainMaxReadClear(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Clear the maximum/error value.
//
HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_MAXREAD_M;
}
//*****************************************************************************
//
//! Registers an interrupt handler for the PECI module.
//!
//! \param ulBase specifies the PECI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! PECI interrupt occurs.
//!
//! This function registers the handler to be called when an PECI interrupt
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific PECI interrupts must be enabled via PECIIntEnable().
//! If necessary, it is the interrupt handler's responsibility to clear the
//! interrupt source via PECIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(pfnHandler != 0);
//
// Register the interrupt handler.
//
IntRegister(INT_PECI0, pfnHandler);
//
// Enable the PECI interrupt.
//
IntEnable(INT_PECI0);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the PECI module.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function unregisters the handler to be called when a PECI interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable the PECI interrupt.
//
IntDisable(INT_PECI0);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_PECI0);
}
//*****************************************************************************
//
//! Enables individual PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! \param ulIntMode is the mode for the PECI domain interrupts.
//!
//! This function enables the indicated PECI interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter can be any of the following values:
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//!
//! The \e ulIntMode parameter is used to configure the interrupt mode for
//! the corresponding \b PECI_DOMAIN_MnDm field, and can be any of the
//! following values: \b PECI_M0D0_MODE1, \b PECI_M0D0_MODE2,
//! \b PECI_M0D0_MODE3, \b PECI_M0D1_MODE1, \b PECI_M0D1_MODE2,
//! \b PECI_M0D1_MODE3. \b PECI_M1D0_MODE1, \b PECI_M1D0_MODE2,
//! \b PECI_M1D0_MODE3, \b PECI_M1D1_MODE1, \b PECI_M1D1_MODE2, or
//! \b PECI_M1D1_MODE3.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags,
unsigned long ulIntMode)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Get the current mask value.
//
ulTemp = HWREG(ulBase + PECI_O_IM);
//
// Clear the bit/bit-fields that are configured, based on the value
// in the flags parameter.
//
ulTemp &= ~ulIntFlags;
//
// Set/Enable the bit/bit-fields based on the value in the flags and mode
// parameter. The flags parameter alters the bits in the lower half
// of the mask, while the mode alters the bit fields in the upper
// half of the mask.
//
ulTemp |= (0x0000FFFF & ulIntFlags);
ulTemp |= (0xFFFF0000 & ulIntMode);
HWREG(ulBase + PECI_O_IM) = ulTemp;
}
//*****************************************************************************
//
//! Disables individual PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated PECI interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter can be any of the following values:
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable the specified interrupts.
//
HWREG(ulBase + PECI_O_IM) &= ~ulIntFlags;
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the PECI module base address.
//! \param bMasked is \b false if the raw interrupt status is required or
//! \b true if the masked interrupt status is required.
//!
//! This function returns the interrupt status for the PECI module. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! The interpretation of the PECI_DOMAIN_MnDm fields vary based on the mode
//! value programed using the PECIIntEnable() function for the field. Each
//! field may take on one of the following values:
//! \b PECI_MnDm_MODE1_HIGH, \b PECI_MnDm_MODE2_MID, \b PECI_MnDm_MODE2_HIGH,
//! \b PECI_MnDm_MODE3_LOW, \b PECI_MnDm_MODE3_MID, or \b PECI_MnDm_MODE3_HIGH.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//
//*****************************************************************************
unsigned long
PECIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + PECI_O_MIS));
}
else
{
return(HWREG(ulBase + PECI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified PECI interrupt sources so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep the interrupts from being recognized again immediately upon exit.
//! The \e ulIntFlags parameter can consist of any combination of the
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1 values.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + PECI_O_IC) = ulIntFlags;
}
//*****************************************************************************
//
//! Sends a PECI Advanced Command.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function sends a PECI Advanced Command. If the interface is not IDLE,
//! it waits for the interface to become IDLE then sends the command. The
//! function parameters are used to populate the message control fields before
//! activating the command.
//!
//! \return None.
//
//*****************************************************************************
void
PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Wait for the interface to be idle.
//
while(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF)
{
}
//
// Fill in the registers for the advanced command.
//
HWREG(ulBase + PECI_O_ACARG) = ulArg;
HWREG(ulBase + PECI_O_ACRDWR0) = ulData0;
HWREG(ulBase + PECI_O_ACRDWR1) = ulData1;
HWREG(ulBase + PECI_O_ACADDR) = (ucHidRe << 24) |
(ucSize << 16) |
(ucDomain << 8) |
(ucProcAdd << 0);
//
// Now, issue the command.
//
HWREG(ulBase + PECI_O_ACCMD) = ucCmd;
}
//*****************************************************************************
//
//! Sends a PECI Advanced Command (non blocking).
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function sends a PECI Advanced Command. If the interface is not IDLE,
//! it returns immediately. Otherwise, it sends the the command. The function
//! paramters are used to populate the message control fields before activating
//! the command.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIAdvCmdSendNonBlocking(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Check for the interface to be idle.
// If not, return immediately.
//
if(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF)
{
return(0);
}
//
// Send the command.
//
PECIAdvCmdSend(ulBase, ucCmd, ucHidRe, ucDomain, ucProcAdd, ulArg,
ucSize, ulData0, ulData1);
//
// Return, indicating that the command has been issued.
//
return(1);
}
//*****************************************************************************
//
//! Obtains status of previous PECI Advanced Command.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function gets the status of a previously issued PECI Advanced Command.
//! If the command has completed, and the data pointers are non-zero, the data
//! registers are read and saved.
//!
//! \return -1 if command has not yet been completed, otherwise, the return
//! code associated with the Advanced Command.
//
//*****************************************************************************
unsigned long
PECIAdvCmdStatusGet(unsigned long ulBase, unsigned long *pulData0,
unsigned long *pulData1)
{
unsigned long ulCode;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// If the command has completed, optionally read and save the data
// registers.
//
ulCode = HWREG(ulBase + PECI_O_ACCODE);
if(ulCode != 0xFFFFFFFF)
{
if(pulData0 != (void *)0)
{
*pulData0 = HWREG(ulBase + PECI_O_ACRDWR0);
}
if(pulData1 != (void *)0)
{
*pulData1 = HWREG(ulBase + PECI_O_ACRDWR1);
}
}
//
// Return the command code from the most recently completed command.
//
return(ulCode);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

226
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@ -0,0 +1,226 @@
//*****************************************************************************
//
// peci.h - Prototypes for Platform Environment Control Interface (PECI)
// driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PECI_H__
#define __PECI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to PECIConfigDomain, PECIEnableDomain,
// PECIDisableDomain, PECIReadDomainValue, PECIReadDomainMax, and
// PECIClearDomain as the ulDomain parameter.
//
//*****************************************************************************
#define PECI_DOMAIN_M0D0 0 // Microprocessor 0 / Domain 0
#define PECI_DOMAIN_M0D1 1 // Microprocessor 0 / Domain 1
#define PECI_DOMAIN_M1D0 2 // Microprocessor 1 / Domain 0
#define PECI_DOMAIN_M1D1 3 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable, PECIIntDisable, and PECIIntClear
// as the ulIntFlags parameter and returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_READ 0x00000001 // End of PECI Poll
#define PECI_ERR 0x00000002 // Error on PECI Poll
#define PECI_AC 0x00000004 // Advanced Command Complete
#define PECI_M0D0 0x00030000 // Microprocessor 0 / Domain 0
#define PECI_M0D1 0x000C0000 // Microprocessor 0 / Domain 1
#define PECI_M1D0 0x00300000 // Microprocessor 1 / Domain 0
#define PECI_M1D1 0x00C00000 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Additional values that can be returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_M0D0_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D0_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D0_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D0_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D0_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D0_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D1_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D1_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D1_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D1_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D0_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D0_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D0_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D0_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D1_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D1_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D1_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D1_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable as the ulIntMode parameter.
//
//*****************************************************************************
#define PECI_M0D0_MODE1 0x00010000 // Domain Interrupt Mode 1
#define PECI_M0D0_MODE2 0x00020000 // Domain Interrupt Mode 2
#define PECI_M0D0_MODE3 0x00030000 // Domain Interrupt Mode 3
#define PECI_M0D1_MODE1 0x00040000 // Domain Interrupt Mode 1
#define PECI_M0D1_MODE2 0x00080000 // Domain Interrupt Mode 2
#define PECI_M0D1_MODE3 0x000C0000 // Domain Interrupt Mode 3
#define PECI_M1D0_MODE1 0x00100000 // Domain Interrupt Mode 1
#define PECI_M1D0_MODE2 0x00200000 // Domain Interrupt Mode 2
#define PECI_M1D0_MODE3 0x00300000 // Domain Interrupt Mode 3
#define PECI_M1D1_MODE1 0x00400000 // Domain Interrupt Mode 1
#define PECI_M1D1_MODE2 0x00800000 // Domain Interrupt Mode 2
#define PECI_M1D1_MODE3 0x00C00000 // Domain Interrupt Mode 3
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long ulBaud, unsigned long ulPoll,
unsigned long ulOffset, unsigned long ulRetry);
extern void PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long *pulBaud, unsigned long *pulPoll,
unsigned long *pulOffset, unsigned long *pulRetry);
extern void PECIBypassEnable(unsigned long ulBase);
extern void PECIBypassDisable(unsigned long ulBase);
extern void PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain,
unsigned long ulHigh, unsigned long ulLow);
extern void PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain,
unsigned long *pulHigh, unsigned long *pulLow);
extern void PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain);
extern unsigned long PECIDomainValueGet(unsigned long ulBase,
unsigned long ulDomain);
extern unsigned long PECIDomainMaxReadGet(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainMaxReadClear(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void PECIIntUnregister(unsigned long ulBase);
extern void PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags,
unsigned long ulIntMode);
extern void PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long PECIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdSendNonBlocking(unsigned long ulBase,
unsigned char ucCmd,
unsigned char ucHidRe,
unsigned char ucDomain,
unsigned char ucProcAdd,
unsigned long ulArg,
unsigned char ucSize,
unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdStatusGet(unsigned long ulBase,
unsigned long *pulData0,
unsigned long *pulData1);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PECI_H__

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bsp/lm3s8962/Libraries/driverlib/pin_map.h
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bsp/lm3s8962/Libraries/driverlib/pwm.c
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4
bsp/lm3s8962/Libraries/driverlib/pwm.h
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@ -2,7 +2,7 @@
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

118
bsp/lm3s8962/Libraries/driverlib/qei.c
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@ -2,7 +2,7 @@
//
// qei.c - Driver for the Quadrature Encoder with Index.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -43,8 +43,8 @@
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the quadrature encoder module. It must be
//! configured before it is enabled.
//! This function enables operation of the quadrature encoder module. The
//! module must be configured before it is enabled.
//!
//! \sa QEIConfigure()
//!
@ -71,7 +71,7 @@ QEIEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the quadrature encoder module.
//! This function disables operation of the quadrature encoder module.
//!
//! \return None.
//
@ -99,22 +99,22 @@ QEIDisable(unsigned long ulBase)
//! for a description of this parameter.
//! \param ulMaxPosition specifies the maximum position value.
//!
//! This will configure the operation of the quadrature encoder. The
//! This function configures the operation of the quadrature encoder. The
//! \e ulConfig parameter provides the configuration of the encoder and is the
//! logical OR of several values:
//!
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges
//! on channel A or on both channels A and B should be counted by the
//! position integrator and velocity accumulator.
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the
//! position integrator should be reset when the index pulse is detected.
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if
//! quadrature signals are being provided on ChA and ChB, or if a direction
//! signal and a clock are being provided instead.
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
//! provided on ChA and ChB should be swapped before being processed.
//!
//! \e ulMaxPosition is the maximum value of the position integrator, and is
//! \e ulMaxPosition is the maximum value of the position integrator and is
//! the value used to reset the position capture when in index reset mode and
//! moving in the reverse (negative) direction.
//!
@ -150,11 +150,11 @@ QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current position of the encoder. Depending upon the
//! configuration of the encoder, and the incident of an index pulse, this
//! This function returns the current position of the encoder. Depending upon
//! the configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter will not be aligned with the index pulse yet).
//! counter is not yet aligned with the index pulse).
//!
//! \return The current position of the encoder.
//
@ -180,8 +180,8 @@ QEIPositionGet(unsigned long ulBase)
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPosition is the new position for the encoder.
//!
//! This sets the current position of the encoder; the encoder position will
//! then be measured relative to this value.
//! This function sets the current position of the encoder; the encoder
//! position is then measured relative to this value.
//!
//! \return None.
//
@ -206,9 +206,10 @@ QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current direction of rotation. In this case, current
//! means the most recently detected direction of the encoder; it may not be
//! presently moving but this is the direction it last moved before it stopped.
//! This function returns the current direction of rotation. In this case,
//! current means the most recently detected direction of the encoder; it may
//! not be presently moving but this is the direction it last moved before it
//! stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
@ -234,9 +235,9 @@ QEIDirectionGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the error indicator for the quadrature encoder. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//! This function returns the error indicator for the quadrature encoder. It
//! is an error for both of the signals of the quadrature input to change at
//! the same time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
@ -261,9 +262,9 @@ QEIErrorGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the velocity capture in the quadrature
//! encoder module. It must be configured before it is enabled. Velocity
//! capture will not occur if the quadrature encoder is not enabled.
//! This function enables operation of the velocity capture in the quadrature
//! encoder module. The module must be configured before velocity capture is
//! enabled.
//!
//! \sa QEIVelocityConfigure() and QEIEnable()
//!
@ -290,7 +291,7 @@ QEIVelocityEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the velocity capture in the quadrature
//! This function disables operation of the velocity capture in the quadrature
//! encoder module.
//!
//! \return None.
@ -322,8 +323,8 @@ QEIVelocityDisable(unsigned long ulBase)
//! \param ulPeriod specifies the number of clock ticks over which to measure
//! the velocity; must be non-zero.
//!
//! This will configure the operation of the velocity capture portion of the
//! quadrature encoder. The position increment signal is predivided as
//! This function configures the operation of the velocity capture portion of
//! the quadrature encoder. The position increment signal is predivided as
//! specified by \e ulPreDiv before being accumulated by the velocity capture.
//! The divided signal is accumulated over \e ulPeriod system clock before
//! being saved and resetting the accumulator.
@ -360,10 +361,10 @@ QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current speed of the encoder. The value returned is the
//! number of pulses detected in the specified time period; this number can be
//! multiplied by the number of time periods per second and divided by the
//! number of pulses per revolution to obtain the number of revolutions per
//! This function returns the current speed of the encoder. The value returned
//! is the number of pulses detected in the specified time period; this number
//! can be multiplied by the number of time periods per second and divided by
//! the number of pulses per revolution to obtain the number of revolutions per
//! second.
//!
//! \return Returns the number of pulses captured in the given time period.
@ -391,11 +392,11 @@ QEIVelocityGet(unsigned long ulBase)
//! \param pfnHandler is a pointer to the function to be called when the
//! quadrature encoder interrupt occurs.
//!
//! This sets the handler to be called when a quadrature encoder interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
//! It is the interrupt handler's responsibility to clear the interrupt source
//! via QEIIntClear().
//! This function registers the handler to be called when a quadrature encoder
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific quadrature encoder interrupts must be
//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility to
//! clear the interrupt source via QEIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -435,9 +436,9 @@ QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This function will clear the handler to be called when a quadrature encoder
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//! This function unregisters the handler to be called when a quadrature
//! encoder interrupt occurs. This function also masks off the interrupt in
//! the interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -480,9 +481,9 @@ QEIIntUnregister(unsigned long ulBase)
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Enables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function enables the indicated quadrature encoder interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -507,12 +508,12 @@ QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
//!
//! Disables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function disables the indicated quadrature encoder interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@ -539,9 +540,9 @@ QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the quadrature encoder module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//! This function returns the interrupt status for the quadrature encoder
//! module. Either the raw interrupt status or the status of interrupts that
//! are allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
@ -575,21 +576,22 @@ QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
//!
//! The specified quadrature encoder interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to keep
//! it from being called again immediately upon exit.
//! they no longer assert. This function must be called in the interrupt
//! handler to keep the interrupt from being triggered again immediately upon
//! exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//

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bsp/lm3s8962/Libraries/driverlib/qei.h
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@ -2,7 +2,7 @@
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

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bsp/lm3s8962/Libraries/driverlib/rvmdk/driverlib.lib
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bsp/lm3s8962/Libraries/driverlib/ssi.c
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@ -2,7 +2,7 @@
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -37,6 +37,83 @@
#include "driverlib/interrupt.h"
#include "driverlib/ssi.h"
//*****************************************************************************
//
// A mapping of timer base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulSSIIntMap[][2] =
{
{ SSI0_BASE, INT_SSI0 },
{ SSI1_BASE, INT_SSI1 },
{ SSI2_BASE, INT_SSI2 },
{ SSI3_BASE, INT_SSI3 },
};
//*****************************************************************************
//
//! \internal
//! Checks an SSI base address.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function determines if a SSI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
SSIBaseValid(unsigned long ulBase)
{
return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) ||
(ulBase == SSI2_BASE) || (ulBase == SSI3_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the SSI interrupt number.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! Given a SSI base address, returns the corresponding interrupt number.
//!
//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SSIIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps SSI base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) /
sizeof(g_ppulSSIIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulSSIIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulSSIIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Configures the synchronous serial interface.
@ -55,7 +132,7 @@
//! \e ulProtocol parameter can be one of the following values:
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
//! frame formats imply the following polarity and phase configurations:
//! frame formats encode the following polarity and phase configurations:
//!
//! <pre>
//! Polarity Phase Mode
@ -66,26 +143,27 @@
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if a slave, the SSI can be
//! configured to disable output on its serial output line. The \e ulMode
//! SSI module can operate as a master or slave; if it is a slave, the SSI can
//! be configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SSI_MODE_MASTER,
//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSSI >= 2 * bit rate (master mode)
//! - FSSI >= 12 * bit rate (slave modes)
//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz.
//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the
//! capability of the specific microcontroller
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The \e ulDataWidth parameter defines the width of the data transfers, and
//! The \e ulDataWidth parameter defines the width of the data transfers and
//! can be a value between 4 and 16, inclusive.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original SSIConfig() API and performs the same
//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
@ -108,7 +186,7 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
@ -170,7 +248,7 @@ SSIEnable(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
@ -195,7 +273,7 @@ SSIDisable(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
@ -211,11 +289,11 @@ SSIDisable(unsigned long ulBase)
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an SSI interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
//! it is the interrupt handler's responsibility to clear the interrupt source
//! via SSIIntClear().
//! This function registers the handler to be called when an SSI interrupt
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If
//! necessary, it is the interrupt handler's responsibility to clear the
//! interrupt source via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -231,12 +309,12 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
ulInt = SSIIntNumberGet(ulBase);
//
// Register the interrupt handler, returning an error if an error occurs.
@ -255,8 +333,8 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function will clear the handler to be called when a SSI
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! This function clears the handler to be called when an SSI interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -273,12 +351,12 @@ SSIIntUnregister(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
ulInt = SSIIntNumberGet(ulBase);
//
// Disable the interrupt.
@ -298,10 +376,11 @@ SSIIntUnregister(unsigned long ulBase)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SSI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor. The \e ulIntFlags parameter can be any of the
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
//! This function enables the indicated SSI interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor. The \e ulIntFlags
//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
//! \b SSI_RXOR values.
//!
//! \return None.
//
@ -312,7 +391,7 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Enable the specified interrupts.
@ -327,9 +406,9 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
//! values.
//! This function disables the indicated SSI interrupt sources. The
//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
//! \b SSI_RXTO, or \b SSI_RXOR values.
//!
//! \return None.
//
@ -340,7 +419,7 @@ SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Disable the specified interrupts.
@ -370,7 +449,7 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Return either the interrupt status or the raw interrupt status as
@ -393,20 +472,20 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SSI interrupt sources are cleared so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupts from being recognized again immediately upon exit. The
//! This function clears the specified SSI interrupt sources so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep the interrupts from being triggered again immediately upon exit. The
//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
//! \b SSI_RXOR values.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -417,7 +496,7 @@ SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested interrupt sources.
@ -449,7 +528,7 @@ SSIDataPut(unsigned long ulBase, unsigned long ulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
@ -495,7 +574,7 @@ SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
@ -540,7 +619,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Wait until there is data to be read.
@ -565,7 +644,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
//!
//! This function gets received data from the receive FIFO of the specified SSI
//! module and places that data into the location specified by the \e ulData
//! parameter. If there is no data in the FIFO, then this function returns a
//! parameter. If there is no data in the FIFO, then this function returns a
//! zero.
//!
//! This function replaces the original SSIDataNonBlockingGet() API and
@ -587,7 +666,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Check for data to read.
@ -610,7 +689,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified SSI DMA features are enabled. The SSI can be
//! This function enables the specified SSI DMA features. The SSI can be
//! configured to use DMA for transmit and/or receive data transfers.
//! The \e ulDMAFlags parameter is the logical OR of any of the following
//! values:
@ -630,10 +709,10 @@ SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Set the requested bits in the UART DMA control register.
// Set the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
}
@ -661,10 +740,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested bits in the UART DMA control register.
// Clear the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
}
@ -675,10 +754,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//!
//! \param ulBase is the base address of the SSI port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware. If \b false is returned, then the transmit FIFO
//! is empty and all bits of the last transmitted word have left the hardware
//! shift register.
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, then the
//! transmit FIFO is empty and all bits of the last transmitted word have left
//! the hardware shift register.
//!
//! \return Returns \b true if the SSI is transmitting or \b false if all
//! transmissions are complete.
@ -690,7 +769,7 @@ SSIBusy(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine if the SSI is busy.
@ -698,6 +777,74 @@ SSIBusy(unsigned long ulBase)
return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
}
//*****************************************************************************
//
//! Sets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulSource is the baud clock source for the SSI.
//!
//! This function allows the baud clock source for the SSI to be selected.
//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! Changing the baud clock source changes the data rate generated by the
//! SSI. Therefore, the data rate should be reconfigured after any change to
//! the SSI clock source.
//!
//! \note The ability to specify the SSI baud clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC));
//
// Set the SSI clock source.
//
HWREG(ulBase + SSI_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! This function returns the data clock source for the specified SSI. The
//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! \note The ability to specify the SSI data clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
SSIClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return the SSI clock source.
//
return(HWREG(ulBase + SSI_O_CC));
}
//*****************************************************************************
//
// Close the Doxygen group.

15
bsp/lm3s8962/Libraries/driverlib/ssi.h
View File

@ -2,7 +2,7 @@
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -71,6 +71,15 @@ extern "C"
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
@ -96,6 +105,8 @@ extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern tBoolean SSIBusy(unsigned long ulBase);
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
//*****************************************************************************
//

1373
bsp/lm3s8962/Libraries/driverlib/sysctl.c
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181
bsp/lm3s8962/Libraries/driverlib/sysctl.h
View File

@ -2,7 +2,7 @@
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -55,7 +55,10 @@ extern "C"
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
@ -103,6 +106,72 @@ extern "C"
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
//*****************************************************************************
//
@ -194,6 +263,7 @@ extern "C"
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
@ -393,16 +463,115 @@ extern "C"
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPIOSCCalibrate()
// API as the ulType parameter.
//
//*****************************************************************************
#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlMOSCConfigSet() API
// as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
//*****************************************************************************
//
// Prototypes for the APIs.
@ -412,6 +581,9 @@ extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
@ -437,8 +609,11 @@ extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);

241
bsp/lm3s8962/Libraries/driverlib/sysexc.c Normal file
View File

@ -0,0 +1,241 @@
//*****************************************************************************
//
// sysexc.c - Routines for the System Exception Module.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup sysexc_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_sysexc.h"
#include "inc/hw_types.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Registers an interrupt handler for the system exception interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the system
//! exception interrupt occurs.
//!
//! This function places the address of the system exception interrupt handler
//! into the interrupt vector table in SRAM. This function also enables the
//! global interrupt in the interrupt controller; specific system exception
//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_SYSEXC, pfnHandler);
//
// Enable the system exception interrupt.
//
IntEnable(INT_SYSEXC);
}
//*****************************************************************************
//
//! Unregisters the system exception interrupt handler.
//!
//! This function removes the system exception interrupt handler from the
//! vector table in SRAM. This function also masks off the system exception
//! interrupt in the interrupt controller so that the interrupt handler is no
//! longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntUnregister(void)
{
//
// Disable the system exception interrupt.
//
IntDisable(INT_SYSEXC);
//
// Unregister the system exception interrupt handler.
//
IntUnregister(INT_SYSEXC);
}
//*****************************************************************************
//
//! Enables individual system exception interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated system exception interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(SYSEXC_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual system exception interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated system exception interrupt sources.
//! Only sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(SYSEXC_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current system exception interrupt status.
//!
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This function returns the system exception interrupt status. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current system exception interrupt status, enumerated
//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC,
//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and
//! \b SYSEXC_INT_FP_IDC.
//
//*****************************************************************************
unsigned long
SysExcIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(SYSEXC_MIS));
}
else
{
return(HWREG(SYSEXC_RIS));
}
}
//*****************************************************************************
//
//! Clears system exception interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified system exception interrupt sources, so
//! that they no longer assert. This function must be called in the interrupt
//! handler to keep the interrupt from being recognized again immediately upon
//! exit.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntClear(unsigned long ulIntFlags)
{
//
// Clear the requested interrupt sources.
//
HWREG(SYSEXC_IC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

74
bsp/lm3s8962/Libraries/driverlib/sysexc.h Normal file
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@ -0,0 +1,74 @@
//*****************************************************************************
//
// sysexc.h - Prototypes for the System Exception Module routines.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSEXC_H__
#define __SYSEXC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
// SysExcIntClear as the ulIntFlags parameter, and returned from
// SysExcIntStatus.
//
//*****************************************************************************
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void SysExcIntRegister(void (*pfnHandler)(void));
extern void SysExcIntUnregister(void);
extern void SysExcIntEnable(unsigned long ulIntFlags);
extern void SysExcIntDisable(unsigned long ulIntFlags);
extern unsigned long SysExcIntStatus(tBoolean bMasked);
extern void SysExcIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSEXC_H__

47
bsp/lm3s8962/Libraries/driverlib/systick.c
View File

@ -2,7 +2,7 @@
//
// systick.c - Driver for the SysTick timer in NVIC.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -40,15 +40,15 @@
//
//! Enables the SysTick counter.
//!
//! This will start the SysTick counter. If an interrupt handler has been
//! registered, it will be called when the SysTick counter rolls over.
//! This function starts the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function will cause the SysTick counter to (re)commence
//! \note Calling this function causes the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force this. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the supplied period on the next
//! written to force the reload. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the supplied period on the next
//! clock.
//!
//! \return None.
@ -67,8 +67,8 @@ SysTickEnable(void)
//
//! Disables the SysTick counter.
//!
//! This will stop the SysTick counter. If an interrupt handler has been
//! registered, it will no longer be called until SysTick is restarted.
//! This function stops the SysTick counter. If an interrupt handler has been
//! registered, it is not called until SysTick is restarted.
//!
//! \return None.
//
@ -89,7 +89,8 @@ SysTickDisable(void)
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This sets the handler to be called when a SysTick interrupt occurs.
//! This function registers the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -115,7 +116,7 @@ SysTickIntRegister(void (*pfnHandler)(void))
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function will clear the handler to be called when a SysTick interrupt
//! This function unregisters the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -142,12 +143,12 @@ SysTickIntUnregister(void)
//
//! Enables the SysTick interrupt.
//!
//! This function will enable the SysTick interrupt, allowing it to be
//! This function enables the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler does not need to clear the SysTick
//! interrupt source as this is done automatically by NVIC when the interrupt
//! handler is called.
//! \note The SysTick interrupt handler is not required to clear the SysTick
//! interrupt source because it is cleared automatically by the NVIC when the
//! interrupt handler is called.
//!
//! \return None.
//
@ -165,7 +166,7 @@ SysTickIntEnable(void)
//
//! Disables the SysTick interrupt.
//!
//! This function will disable the SysTick interrupt, preventing it from being
//! This function disables the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
@ -185,16 +186,16 @@ SysTickIntDisable(void)
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter; must be between 1 and 16,777,216, inclusive.
//! counter and must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps; this
//! This function sets the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
//! the next clock after the SysTick is enabled.
//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
//! the next clock after SysTick is enabled.
//!
//! \return None.
//
@ -217,7 +218,7 @@ SysTickPeriodSet(unsigned long ulPeriod)
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps; this
//! This function returns the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
@ -236,8 +237,8 @@ SysTickPeriodGet(void)
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter; this will
//! be a value between the period - 1 and zero, inclusive.
//! This function returns the current value of the SysTick counter, which is
//! a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//

4
bsp/lm3s8962/Libraries/driverlib/systick.h
View File

@ -2,7 +2,7 @@
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

598
bsp/lm3s8962/Libraries/driverlib/timer.c
View File

@ -2,7 +2,7 @@
//
// timer.c - Driver for the timer module.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -37,6 +37,27 @@
#include "driverlib/interrupt.h"
#include "driverlib/timer.h"
//*****************************************************************************
//
// A mapping of timer base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulTimerIntMap[][2] =
{
{ TIMER0_BASE, INT_TIMER0A },
{ TIMER1_BASE, INT_TIMER1A },
{ TIMER2_BASE, INT_TIMER2A },
{ TIMER3_BASE, INT_TIMER3A },
{ TIMER4_BASE, INT_TIMER4A },
{ TIMER5_BASE, INT_TIMER5A },
{ WTIMER0_BASE, INT_WTIMER0A },
{ WTIMER1_BASE, INT_WTIMER1A },
{ WTIMER2_BASE, INT_WTIMER2A },
{ WTIMER3_BASE, INT_WTIMER3A },
{ WTIMER4_BASE, INT_WTIMER4A },
{ WTIMER5_BASE, INT_WTIMER5A },
};
//*****************************************************************************
//
//! \internal
@ -55,10 +76,57 @@ static tBoolean
TimerBaseValid(unsigned long ulBase)
{
return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
(ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE));
(ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) ||
(ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) ||
(ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) ||
(ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) ||
(ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the timer interrupt number.
//!
//! \param ulBase is the base address of the timer module.
//!
//! Given a timer base address, this function returns the corresponding
//! interrupt number.
//!
//! \return Returns a timer interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
TimerIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps timer base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulTimerIntMap) /
sizeof(g_ppulTimerIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulTimerIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulTimerIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Enables the timer(s).
@ -67,7 +135,7 @@ TimerBaseValid(unsigned long ulBase)
//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH.
//!
//! This will enable operation of the timer module. The timer must be
//! This function enables operation of the timer module. The timer must be
//! configured before it is enabled.
//!
//! \return None.
@ -97,7 +165,7 @@ TimerEnable(unsigned long ulBase, unsigned long ulTimer)
//! \param ulTimer specifies the timer(s) to disable; must be one of
//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
//!
//! This will disable operation of the timer module.
//! This function disables operation of the timer module.
//!
//! \return None.
//
@ -127,33 +195,43 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer)
//! \param ulConfig is the configuration for the timer.
//!
//! This function configures the operating mode of the timer(s). The timer
//! module is disabled before being configured, and is left in the disabled
//! state. The configuration is specified in \e ulConfig as one of the
//! following values:
//! module is disabled before being configured and is left in the disabled
//! state. There are two types of timers; a 16/32-bit variety and a 32/64-bit
//! variety. The 16/32-bit variety is comprised of two 16-bit timers that can
//! operate independently or be concatenated to form a 32-bit timer.
//! Similarly, the 32/64-bit variety is comprised of two 32-bit timers that can
//! operate independently or be concatenated to form a 64-bit timer.
//!
//! - \b TIMER_CFG_32_BIT_OS - 32-bit one-shot timer
//! - \b TIMER_CFG_32_BIT_OS_UP - 32-bit one-shot timer that counts up instead
//! of down (not available on all parts)
//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
//! - \b TIMER_CFG_32_BIT_PER_UP - 32-bit periodic timer that counts up instead
//! of down (not available on all parts)
//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
//! The configuration is specified in \e ulConfig as one of the following
//! values:
//!
//! When configured for a pair of 16-bit timers, each timer is separately
//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
//! instead of down (not available on all parts)
//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
//! instead of down (not available on all parts)
//! - \b TIMER_CFG_RTC - Full-width real time clock timer
//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
//!
//! When configured for a pair of half-width timers, each timer is separately
//! configured. The first timer is configured by setting \e ulConfig to
//! the result of a logical OR operation between one of the following values
//! and \e ulConfig:
//!
//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one-shot timer
//! - \b TIMER_CFG_A_ONE_SHOT_UP - 16-bit one-shot timer that counts up instead
//! of down (not available on all parts)
//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
//! - \b TIMER_CFG_A_PERIODIC_UP - 16-bit periodic timer that counts up instead
//! of down (not available on all parts)
//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
//! - \b TIMER_CFG_A_PWM - 16-bit PWM output
//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up
//! instead of down (not available on all parts)
//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer
//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up
//! instead of down (not available on all parts)
//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts
//! up instead of down (not available on all parts)
//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture
//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up
//! instead of down (not available on all parts)
//! - \b TIMER_CFG_A_PWM - Half-width PWM output
//!
//! Similarly, the second timer is configured by setting \e ulConfig to
//! the result of a logical OR operation between one of the corresponding
@ -169,13 +247,13 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
(ulConfig == TIMER_CFG_32_BIT_OS_UP) ||
(ulConfig == TIMER_CFG_32_BIT_PER) ||
(ulConfig == TIMER_CFG_32_BIT_PER_UP) ||
(ulConfig == TIMER_CFG_32_RTC) ||
((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
ASSERT((ulConfig == TIMER_CFG_ONE_SHOT) ||
(ulConfig == TIMER_CFG_ONE_SHOT_UP) ||
(ulConfig == TIMER_CFG_PERIODIC) ||
(ulConfig == TIMER_CFG_PERIODIC_UP) ||
(ulConfig == TIMER_CFG_RTC) ||
((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
@ -188,7 +266,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
//
@ -205,8 +285,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
// Set the configuration of the A and B timers. Note that the B timer
// configuration is ignored by the hardware in 32-bit modes.
//
HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
HWREG(ulBase + TIMER_O_TAMR) = (ulConfig & 255) | TIMER_TAMR_TAPWMIE;
HWREG(ulBase + TIMER_O_TBMR) =
((ulConfig >> 8) & 255) | TIMER_TBMR_TBPWMIE;
}
//*****************************************************************************
@ -218,9 +299,9 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
//! \b TIMER_B, or \b TIMER_BOTH.
//! \param bInvert specifies the output level.
//!
//! This function sets the PWM output level for the specified timer. If the
//! \e bInvert parameter is \b true, then the timer's output will be made
//! active low; otherwise, it will be made active high.
//! This function configures the PWM output level for the specified timer. If
//! the \e bInvert parameter is \b true, then the timer's output is made active
//! low; otherwise, it is made active high.
//!
//! \return None.
//
@ -247,15 +328,15 @@ TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
//*****************************************************************************
//
//! Enables or disables the trigger output.
//! Enables or disables the ADC trigger output.
//!
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH.
//! \param bEnable specifies the desired trigger state.
//! \param bEnable specifies the desired ADC trigger state.
//!
//! This function controls the trigger output for the specified timer. If the
//! \e bEnable parameter is \b true, then the timer's output trigger is
//! This function controls the ADC trigger output for the specified timer. If
//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is
//! enabled; otherwise it is disabled.
//!
//! \return None.
@ -274,6 +355,7 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
//
// Set the trigger output as requested.
// Set the ADC trigger output as requested.
//
ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
@ -292,8 +374,8 @@ TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
//! \b TIMER_EVENT_BOTH_EDGES.
//!
//! This function sets the signal edge(s) that will trigger the timer when in
//! capture mode.
//! This function configures the signal edge(s) that triggers the timer when
//! in capture mode.
//!
//! \return None.
//
@ -312,10 +394,9 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
//
// Set the event type.
//
ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
~(TIMER_CTL_TAEVENT_M |
TIMER_CTL_TBEVENT_M)) | ulEvent);
ulTimer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M;
HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) |
(ulEvent & ulTimer));
}
//*****************************************************************************
@ -328,8 +409,8 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
//! \param bStall specifies the response to a stall signal.
//!
//! This function controls the stall response for the specified timer. If the
//! \e bStall parameter is \b true, then the timer will stop counting if the
//! processor enters debug mode; otherwise the timer will keep running while in
//! \e bStall parameter is \b true, then the timer stops counting if the
//! processor enters debug mode; otherwise the timer keeps running while in
//! debug mode.
//!
//! \return None.
@ -337,7 +418,7 @@ TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
//*****************************************************************************
void
TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall)
tBoolean bStall)
{
//
// Check the arguments.
@ -369,7 +450,8 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
//! count to its timeout in order for this timer to start counting. Refer to
//! the part's data sheet for a description of the trigger chain.
//!
//! \note This functionality is not available on all parts.
//! \note This functionality is not available on all parts. This function
//! should not be used for Timer 0A or Wide Timer 0A.
//!
//! \return None.
//
@ -401,7 +483,7 @@ TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer,
}
//
// Set the wait on trigger mode for timer A.
// Set the wait on trigger mode for timer B.
//
if((ulTimer & TIMER_B) != 0)
{
@ -423,7 +505,7 @@ TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer,
//! \param ulBase is the base address of the timer module.
//!
//! This function causes the timer to start counting when in RTC mode. If not
//! configured for RTC mode, this will do nothing.
//! configured for RTC mode, this function does nothing.
//!
//! \return None.
//
@ -474,12 +556,19 @@ TimerRTCDisable(unsigned long ulBase)
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH.
//! \param ulValue is the timer prescale value; must be between 0 and 255,
//! inclusive.
//! \param ulValue is the timer prescale value which must be between 0 and 255
//! (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive) for
//! 32/64-bit timers.
//!
//! This function sets the value of the input clock prescaler. The prescaler
//! is only operational when in 16-bit mode and is used to extend the range of
//! the 16-bit timer modes.
//! This function configures the value of the input clock prescaler. The
//! prescaler is only operational when in half-width mode and is used to extend
//! the range of the half-width timer modes. The prescaler provides the least
//! significant bits when counting down in periodic and one-shot modes; in all
//! other modes, the prescaler provides the most significant bits.
//!
//! \note The availability of the prescaler varies with the Stellaris part and
//! timer mode in use. Please consult the datasheet for the part you are using
//! to determine whether this support is available.
//!
//! \return None.
//
@ -522,8 +611,14 @@ TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
//! \b TIMER_B.
//!
//! This function gets the value of the input clock prescaler. The prescaler
//! is only operational when in 16-bit mode and is used to extend the range of
//! the 16-bit timer modes.
//! is only operational when in half-width mode and is used to extend the range
//! of the half-width timer modes. The prescaler provides the least significant
//! bits when counting down in periodic and one-shot modes; in all other modes,
//! the prescaler provides the most significant bits.
//!
//! \note The availability of the prescaler varies with the Stellaris part and
//! timer mode in use. Please consult the datasheet for the part you are using
//! to determine whether this support is available.
//!
//! \return The value of the timer prescaler.
//
@ -552,14 +647,20 @@ TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH.
//! \param ulValue is the timer prescale match value; must be between 0 and
//! 255, inclusive.
//! \param ulValue is the timer prescale match value which must be between 0
//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535
//! (inclusive) for 32/64-bit timers.
//!
//! This function sets the value of the input clock prescaler match value.
//! When in a 16-bit mode that uses the counter match and the prescaler, the
//! prescale match effectively extends the range of the counter to 24-bits.
//! This function configures the value of the input clock prescaler match
//! value. When in a half-width mode that uses the counter match and the
//! prescaler, the prescale match effectively extends the range of the match.
//! The prescaler provides the least significant bits when counting down in
//! periodic and one-shot modes; in all other modes, the prescaler provides the
//! most significant bits.
//!
//! \note This functionality is not available on all parts.
//! \note The availability of the prescaler match varies with the Stellaris
//! part and timer mode in use. Please consult the datasheet for the part you
//! are using to determine whether this support is available.
//!
//! \return None.
//
@ -602,10 +703,15 @@ TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
//! \b TIMER_B.
//!
//! This function gets the value of the input clock prescaler match value.
//! When in a 16-bit mode that uses the counter match and prescaler, the
//! prescale match effectively extends the range of the counter to 24-bits.
//! When in a half-width mode that uses the counter match and prescaler, the
//! prescale match effectively extends the range of the match. The prescaler
//! provides the least significant bits when counting down in periodic and
//! one-shot modes; in all other modes, the prescaler provides the most
//! significant bits.
//!
//! \note This functionality is not available on all parts.
//! \note The availability of the prescaler match varies with the Stellaris
//! part and timer mode in use. Please consult the datasheet for the part you
//! are using to determine whether this support is available.
//!
//! \return The value of the timer prescale match.
//
@ -634,11 +740,15 @@ TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
//! timer is configured for 32-bit operation.
//! timer is configured for full-width operation.
//! \param ulValue is the load value.
//!
//! This function sets the timer load value; if the timer is running then the
//! value will be immediately loaded into the timer.
//! This function configures the timer load value; if the timer is running then
//! the value is immediately loaded into the timer.
//!
//! \note This function can be used for both full- and half-width modes of
//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
//! TimerLoadSet64() for full-width modes of 32/64-bit timers.
//!
//! \return None.
//
@ -678,11 +788,15 @@ TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
//! for 32-bit operation.
//! for full-width operation.
//!
//! This function gets the currently programmed interval load value for the
//! specified timer.
//!
//! \note This function can be used for both full- and half-width modes of
//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
//! TimerLoadGet64() for full-width modes of 32/64-bit timers.
//!
//! \return Returns the load value for the timer.
//
//*****************************************************************************
@ -702,6 +816,79 @@ TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
HWREG(ulBase + TIMER_O_TBILR));
}
//*****************************************************************************
//
//! Sets the timer load value for a 64-bit timer.
//!
//! \param ulBase is the base address of the timer module.
//! \param ullValue is the load value.
//!
//! This function configures the timer load value for a 64-bit timer; if the
//! timer is running, then the value is immediately loaded into the timer.
//!
//! \return None.
//
//*****************************************************************************
void
TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue)
{
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
//
// Set the timer load value. The upper 32-bits must be written before the
// lower 32-bits in order to adhere to the hardware interlocks on the
// 64-bit value.
//
HWREG(ulBase + TIMER_O_TBILR) = ullValue >> 32;
HWREG(ulBase + TIMER_O_TAILR) = ullValue & 0xffffffff;
}
//*****************************************************************************
//
//! Gets the timer load value for a 64-bit timer.
//!
//! \param ulBase is the base address of the timer module.
//!
//! This function gets the currently programmed interval load value for the
//! specified 64-bit timer.
//!
//! \return Returns the load value for the timer.
//
//*****************************************************************************
unsigned long long
TimerLoadGet64(unsigned long ulBase)
{
unsigned long ulHigh1, ulHigh2, ulLow;
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
//
// Read the 64-bit load value. A read of the low 32-bits is performed
// between two reads of the upper 32-bits; if the upper 32-bit values match
// then the 64-bit value is consistent. If they do not match, then the
// read is performed again until they do match (it should never execute the
// loop body more than twice).
//
do
{
ulHigh1 = HWREG(ulBase + TIMER_O_TBILR);
ulLow = HWREG(ulBase + TIMER_O_TAILR);
ulHigh2 = HWREG(ulBase + TIMER_O_TBILR);
}
while(ulHigh1 != ulHigh2);
//
// Return the load value.
//
return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow);
}
//*****************************************************************************
//
//! Gets the current timer value.
@ -709,10 +896,14 @@ TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
//! for 32-bit operation.
//! for full-width operation.
//!
//! This function reads the current value of the specified timer.
//!
//! \note This function can be used for both full- and half-width modes of
//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
//! TimerValueGet64() for full-width modes of 32/64-bit timers.
//!
//! \return Returns the current value of the timer.
//
//*****************************************************************************
@ -732,6 +923,48 @@ TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
HWREG(ulBase + TIMER_O_TBR));
}
//*****************************************************************************
//
//! Gets the current 64-bit timer value.
//!
//! \param ulBase is the base address of the timer module.
//!
//! This function reads the current value of the specified timer.
//!
//! \return Returns the current value of the timer.
//
//*****************************************************************************
unsigned long long
TimerValueGet64(unsigned long ulBase)
{
unsigned long ulHigh1, ulHigh2, ulLow;
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
//
// Read the 64-bit timer value. A read of the low 32-bits is performed
// between two reads of the upper 32-bits; if the upper 32-bit values match
// then the 64-bit value is consistent. If they do not match, then the
// read is performed again until they do match (it should never execute the
// loop body more than twice).
//
do
{
ulHigh1 = HWREG(ulBase + TIMER_O_TBR);
ulLow = HWREG(ulBase + TIMER_O_TAR);
ulHigh2 = HWREG(ulBase + TIMER_O_TBR);
}
while(ulHigh1 != ulHigh2);
//
// Return the timer value.
//
return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow);
}
//*****************************************************************************
//
//! Sets the timer match value.
@ -739,12 +972,18 @@ TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
//! timer is configured for 32-bit operation.
//! timer is configured for full-width operation.
//! \param ulValue is the match value.
//!
//! This function sets the match value for a timer. This is used in capture
//! count mode to determine when to interrupt the processor and in PWM mode to
//! determine the duty cycle of the output signal.
//! This function configures the match value for a timer. This value is used
//! in capture count mode to determine when to interrupt the processor and in
//! PWM mode to determine the duty cycle of the output signal. On some
//! Stellaris devices, match interrupts can also be generated in periodic and
//! one-shot modes.
//!
//! \note This function can be used for both full- and half-width modes of
//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
//! TimerMatchSet64() for full-width modes of 32/64-bit timers.
//!
//! \return None.
//
@ -784,10 +1023,14 @@ TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
//! \param ulBase is the base address of the timer module.
//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
//! for 32-bit operation.
//! for full-width operation.
//!
//! This function gets the match value for the specified timer.
//!
//! \note This function can be used for both full- and half-width modes of
//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
//! TimerMatchGet64() for full-width modes of 32/64-bit timers.
//!
//! \return Returns the match value for the timer.
//
//*****************************************************************************
@ -807,6 +1050,79 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
HWREG(ulBase + TIMER_O_TBMATCHR));
}
//*****************************************************************************
//
//! Sets the timer match value for a 64-bit timer.
//!
//! \param ulBase is the base address of the timer module.
//! \param ullValue is the match value.
//!
//! This function configures the match value for a timer. This value is used
//! in capture count mode to determine when to interrupt the processor and in
//! PWM mode to determine the duty cycle of the output signal.
//!
//! \return None.
//
//*****************************************************************************
void
TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue)
{
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
//
// Set the timer match value. The upper 32-bits must be written before the
// lower 32-bits in order to adhere to the hardware interlocks on the
// 64-bit value.
//
HWREG(ulBase + TIMER_O_TBMATCHR) = ullValue >> 32;
HWREG(ulBase + TIMER_O_TAMATCHR) = ullValue & 0xffffffff;
}
//*****************************************************************************
//
//! Gets the timer match value for a 64-bit timer.
//!
//! \param ulBase is the base address of the timer module.
//!
//! This function gets the match value for the specified timer.
//!
//! \return Returns the match value for the timer.
//
//*****************************************************************************
unsigned long long
TimerMatchGet64(unsigned long ulBase)
{
unsigned long ulHigh1, ulHigh2, ulLow;
//
// Check the arguments.
//
ASSERT(TimerBaseValid(ulBase));
//
// Read the 64-bit match value. A read of the low 32-bits is performed
// between two reads of the upper 32-bits; if the upper 32-bit values match
// then the 64-bit value is consistent. If they do not match, then the
// read is performed again until they do match (it should never execute the
// loop body more than twice).
//
do
{
ulHigh1 = HWREG(ulBase + TIMER_O_TBMATCHR);
ulLow = HWREG(ulBase + TIMER_O_TAMATCHR);
ulHigh2 = HWREG(ulBase + TIMER_O_TBMATCHR);
}
while(ulHigh1 != ulHigh2);
//
// Return the match value.
//
return(((unsigned long long)ulHigh1 << 32) | (unsigned long long)ulLow);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the timer interrupt.
@ -817,10 +1133,11 @@ TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
//! \param pfnHandler is a pointer to the function to be called when the timer
//! interrupt occurs.
//!
//! This sets the handler to be called when a timer interrupt occurs. This
//! will enable the global interrupt in the interrupt controller; specific
//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via TimerIntClear().
//! This function registers the handler to be called when a timer interrupt
//! occurs. In addition, this function enables the global interrupt in the
//! interrupt controller; specific timer interrupts must be enabled via
//! TimerIntEnable(). It is the interrupt handler's responsibility to clear the
//! interrupt source via TimerIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -842,9 +1159,7 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
//
// Get the interrupt number for this timer module.
//
ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
((ulBase == TIMER1_BASE) ? INT_TIMER1A :
((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
ulBase = TimerIntNumberGet(ulBase);
//
// Register an interrupt handler for timer A if requested.
@ -887,9 +1202,9 @@ TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
//! \b TIMER_B, or \b TIMER_BOTH.
//!
//! This function will clear the handler to be called when a timer interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//! This function unregisters the handler to be called when a timer interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -910,9 +1225,7 @@ TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
//
// Get the interrupt number for this timer module.
//
ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
((ulBase == TIMER1_BASE) ? INT_TIMER1A :
((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
ulBase = TimerIntNumberGet(ulBase);
//
// Unregister the interrupt handler for timer A if requested.
@ -954,9 +1267,9 @@ TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
//! \param ulBase is the base address of the timer module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated timer interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function enables the indicated timer interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter must be the logical OR of any combination of
//! the following:
@ -993,9 +1306,9 @@ TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase is the base address of the timer module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated timer interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function disables the indicated timer interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to TimerIntEnable().
@ -1025,9 +1338,9 @@ TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the timer module. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the timer module. Either
//! the raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! values described in TimerIntEnable().
@ -1057,20 +1370,20 @@ TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified timer interrupt sources are cleared, so that they no longer
//! assert. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to TimerIntEnable().
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -1089,15 +1402,76 @@ TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Synchronizes the counters in a set of timers.
//!
//! \param ulBase is the base address of the timer module. This parameter must
//! be the base address of Timer0 (in other words, \b TIMER0_BASE).
//! \param ulTimers is the set of timers to synchronize.
//!
//! This function synchronizes the counters in a specified set of timers.
//! When a timer is running in half-width mode, each half can be included or
//! excluded in the synchronization event. When a timer is running in
//! full-width mode, only the A timer can be synchronized (specifying the B
//! timer has no effect).
//!
//! The \e ulTimers parameter is the logical OR of any of the following
//! defines:
//!
//! - \b TIMER_0A_SYNC
//! - \b TIMER_0B_SYNC
//! - \b TIMER_1A_SYNC
//! - \b TIMER_1B_SYNC
//! - \b TIMER_2A_SYNC
//! - \b TIMER_2B_SYNC
//! - \b TIMER_3A_SYNC
//! - \b TIMER_3B_SYNC
//! - \b TIMER_4A_SYNC
//! - \b TIMER_4B_SYNC
//! - \b TIMER_5A_SYNC
//! - \b TIMER_5B_SYNC
//! - \b WTIMER_0A_SYNC
//! - \b WTIMER_0B_SYNC
//! - \b WTIMER_1A_SYNC
//! - \b WTIMER_1B_SYNC
//! - \b WTIMER_2A_SYNC
//! - \b WTIMER_2B_SYNC
//! - \b WTIMER_3A_SYNC
//! - \b WTIMER_3B_SYNC
//! - \b WTIMER_4A_SYNC
//! - \b WTIMER_4B_SYNC
//! - \b WTIMER_5A_SYNC
//! - \b WTIMER_5B_SYNC
//!
//! \note This functionality is not available on all parts.
//!
//! \return None.
//
//*****************************************************************************
void
TimerSynchronize(unsigned long ulBase, unsigned long ulTimers)
{
//
// Check the arguments.
//
ASSERT(ulBase == TIMER0_BASE);
//
// Synchronize the specified timers.
//
HWREG(ulBase + TIMER_O_SYNC) = ulTimers;
}
//*****************************************************************************
//
// Puts the timer into its reset state.
//
// \param ulBase is the base address of the timer module.
//
// The specified timer is disabled, and all its interrupts are disabled,
// cleared, and unregistered. Then the timer registers are set to their reset
// value.
// This function disables the specified timer, and all its interrupts are
// disabled, cleared, and unregistered. Then the timer registers are set to
// their reset value.
//
// \return None.
//
@ -1127,7 +1501,7 @@ TimerQuiesce(unsigned long ulBase)
HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
//
// Unregister the interrupt handler. This also disables interrupts to the
// Unregister the interrupt handler, which also disables interrupts to the
// core.
//
TimerIntUnregister(ulBase, TIMER_BOTH);

100
bsp/lm3s8962/Libraries/driverlib/timer.h
View File

@ -2,7 +2,7 @@
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -41,26 +41,32 @@ extern "C"
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_OS_UP 0x00000011 // 32-bit one-shot up-count timer
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
#define TIMER_CFG_32_BIT_PER_UP 0x00000012 // 32-bit periodic up-count timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000011 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000012 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00001100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00001200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
@ -97,6 +103,36 @@ extern "C"
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
//*****************************************************************************
//
// Prototypes for the APIs.
@ -129,12 +165,17 @@ extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerLoadGet64(unsigned long ulBase);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern unsigned long long TimerValueGet64(unsigned long ulBase);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerMatchGet64(unsigned long ulBase);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
@ -142,6 +183,7 @@ extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers);
//*****************************************************************************
//
@ -153,6 +195,20 @@ extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerQuiesce(unsigned long ulBase);
#endif
//*****************************************************************************
//
// These values for TimerConfigure have been deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer
#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer
#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.

582
bsp/lm3s8962/Libraries/driverlib/uart.c
View File

@ -2,7 +2,7 @@
//
// uart.c - Driver for the UART.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -49,6 +49,23 @@
(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
16 : 8)
//*****************************************************************************
//
// A mapping of UART base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulUARTIntMap[][2] =
{
{ UART0_BASE, INT_UART0 },
{ UART1_BASE, INT_UART1 },
{ UART2_BASE, INT_UART2 },
{ UART3_BASE, INT_UART3 },
{ UART4_BASE, INT_UART4 },
{ UART5_BASE, INT_UART5 },
{ UART6_BASE, INT_UART6 },
{ UART7_BASE, INT_UART7 },
};
//*****************************************************************************
//
//! \internal
@ -67,10 +84,55 @@ static tBoolean
UARTBaseValid(unsigned long ulBase)
{
return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
(ulBase == UART2_BASE) || (ulBase == UART3_BASE) ||
(ulBase == UART4_BASE) || (ulBase == UART5_BASE) ||
(ulBase == UART6_BASE) || (ulBase == UART7_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the UART interrupt number.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Given a UART base address, this function returns the corresponding
//! interrupt number.
//!
//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
UARTIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps UART base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) /
sizeof(g_ppulUARTIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulUARTIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulUARTIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Sets the type of parity.
@ -78,11 +140,12 @@ UARTBaseValid(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ulParity specifies the type of parity to use.
//!
//! Sets the type of parity to use for transmitting and expect when receiving.
//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
//! parity bit; it is always either one or zero based on the mode.
//! This function configures the type of parity to use for transmitting and
//! expect when receiving. The \e ulParity parameter must be one of
//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two
//! parameters allow direct control of the parity bit; it is always either one
//! or zero based on the mode.
//!
//! \return None.
//
@ -149,8 +212,8 @@ UARTParityModeGet(unsigned long ulBase)
//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//! This function configures the FIFO level at which transmit and receive
//! interrupts are generated.
//!
//! \return None.
//
@ -193,7 +256,7 @@ UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are xogenerated.
//! are generated.
//!
//! \return None.
//
@ -245,10 +308,15 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
//! select the parity mode (no parity bit, even parity bit, odd parity bit,
//! parity bit always one, and parity bit always zero, respectively).
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. The frequency of
//! the system clock is the value returned by SysCtlClockGet(), or it can be
//! explicitly hard coded if it is constant and known (to save the
//! code/execution overhead of a call to SysCtlClockGet()).
//!
//! For Stellaris parts that have the ability to specify the UART baud clock
//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
//! PIOSC. In this case, the peripheral clock should be specified as
//! 16,000,000 (the nominal rate of PIOSC).
//!
//! This function replaces the original UARTConfigSet() API and performs the
//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
@ -336,17 +404,22 @@ UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
//! \param pulBaud is a pointer to storage for the baud rate.
//! \param pulConfig is a pointer to storage for the data format.
//!
//! The baud rate and data format for the UART is determined, given an
//! explicitly provided peripheral clock (hence the ExpClk suffix). The
//! This function determines the baud rate and data format for the UART, given
//! an explicitly provided peripheral clock (hence the ExpClk suffix). The
//! returned baud rate is the actual baud rate; it may not be the exact baud
//! rate requested or an ``official'' baud rate. The data format returned in
//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
//! UARTConfigSetExpClk().
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. The frequency of
//! the system clock is the value returned by SysCtlClockGet(), or it can be
//! explicitly hard coded if it is constant and known (to save the
//! code/execution overhead of a call to SysCtlClockGet()).
//!
//! For Stellaris parts that have the ability to specify the UART baud clock
//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
//! PIOSC. In this case, the peripheral clock should be specified as
//! 16,000,000 (the nominal rate of PIOSC).
//!
//! This function replaces the original UARTConfigGet() API and performs the
//! same actions. A macro is provided in <tt>uart.h</tt> to map the original
@ -399,8 +472,8 @@ UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
//!
//! \param ulBase is the base address of the UART port.
//!
//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
//! FIFOs.
//! This function sets the UARTEN, TXE, and RXE bits and enables the transmit
//! and receive FIFOs.
//!
//! \return None.
//
@ -431,7 +504,7 @@ UARTEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
//! transmission of the current character, and flushes the transmit FIFO.
//!
//! \return None.
@ -495,7 +568,7 @@ UARTFIFOEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! This functions disables the transmit and receive FIFOs in the UART.
//! This function disables the transmit and receive FIFOs in the UART.
//!
//! \return None.
//
@ -521,10 +594,18 @@ UARTFIFODisable(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param bLowPower indicates if SIR Low Power Mode is to be used.
//!
//! Enables the SIREN control bit for IrDA mode on the UART. If the
//! \e bLowPower flag is set, then SIRLP bit will also be set.
//! This function enables the SIREN control bit for IrDA mode on the UART. If
//! the \e bLowPower flag is set, then SIRLP bit is also set. This
//! function only has an effect if the UART has not been enabled
//! by a call to UARTEnable(). The call UARTEnableSIR() must be made before
//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function
//! calls the UARTEnable() function. Another option is to call UARTDisable()
//! followed by UARTEnableSIR() and then enable the UART by calling
//! UARTEnable().
//!
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -556,9 +637,17 @@ UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
//! This function clears the SIREN (IrDA) and SIRLP (Low Power) bits. This
//! function only has an effect if the UART has not been enabled by a
//! call to UARTEnable(). The call UARTEnableSIR() must be made before
//! a call to UARTConfigSetExpClk() because the UARTConfigSetExpClk() function
//! calls the UARTEnable() function. Another option is to call UARTDisable()
//! followed by UARTEnableSIR() and then enable the UART by calling
//! UARTEnable().
//!
//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -579,17 +668,17 @@ UARTDisableSIR(unsigned long ulBase)
//*****************************************************************************
//
//! Enables ISO 7816 smart card mode on the specified UART.
//! Enables ISO7816 smart card mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
//! This call also sets 8 bit word length and even parity as required by ISO
//! 7816.
//! This function enables the SMART control bit for the ISO7816 smart card mode
//! on the UART. This call also sets 8-bit word length and even parity as
//! required by ISO7816.
//!
//! \note The availability of ISO 7816 smart card mode varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of SIR (IrDA) operation varies with the Stellaris
//! part in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
@ -603,13 +692,12 @@ UARTSmartCardEnable(unsigned long ulBase)
// Check the arguments.
//
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
//
// Set 8 bit word length, even parity, 2 stop bits (even though the STP2
// bit is ignored when in smartcard mode, this lets the caller read back
// the actual setting in use).
// Set 8-bit word length, even parity, 2 stop bits (note that although the
// STP2 bit is ignored when in smartcard mode, this code lets the caller
// read back the actual setting in use).
//
ulVal = HWREG(ulBase + UART_O_LCRH);
ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
@ -625,15 +713,16 @@ UARTSmartCardEnable(unsigned long ulBase)
//*****************************************************************************
//
//! Disables ISO 7816 smart card mode on the specified UART.
//! Disables ISO7816 smart card mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
//! This function clears the SMART (ISO7816 smart card) bit in the UART
//! control register.
//!
//! \note The availability of ISO 7816 smart card mode varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of ISO7816 smart card mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
@ -645,8 +734,7 @@ UARTSmartCardDisable(unsigned long ulBase)
// Check the arguments.
//
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
//
// Disable the SMART bit.
@ -662,16 +750,17 @@ UARTSmartCardDisable(unsigned long ulBase)
//! \param ulControl is a bit-mapped flag indicating which modem control bits
//! should be set.
//!
//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
//! This function configures the states of the DTR or RTS modem handshake
//! outputs from the UART.
//!
//! The \e ulControl parameter is the logical OR of any of the following:
//!
//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//! \note The availability of ISO7816 smart card mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
@ -704,7 +793,8 @@ UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
//! \param ulControl is a bit-mapped flag indicating which modem control bits
//! should be set.
//!
//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
//! This function clears the states of the DTR or RTS modem handshake outputs
//! from the UART.
//!
//! The \e ulControl parameter is the logical OR of any of the following:
//!
@ -744,15 +834,15 @@ UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current states of each of the two UART modem control signals,
//! DTR and RTS.
//! This function returns the current states of each of the two UART modem
//! control signals, DTR and RTS.
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//!
//! \return Returns the states of the handshake output signals. This will be a
//! logical logical OR combination of values \b UART_OUTPUT_RTS and
//! \return Returns the states of the handshake output signals. This value is
//! a logical OR combination of values \b UART_OUTPUT_RTS and
//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
//! associated signal is asserted.
//
@ -775,16 +865,16 @@ UARTModemControlGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current states of each of the four UART modem status signals,
//! RI, DCD, DSR and CTS.
//! This function returns the current states of each of the four UART modem
//! status signals, RI, DCD, DSR and CTS.
//!
//! \note The availability of hardware modem handshake signals varies with the
//! Stellaris part and UART in use. Please consult the datasheet for the part
//! you are using to determine whether this support is available.
//!
//! \return Returns the states of the handshake output signals. This will be a
//! logical logical OR combination of values \b UART_INPUT_RI, \b
//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
//! \return Returns the states of the handshake output signals. This value
//! is a logical OR combination of values \b UART_INPUT_RI,
//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
//! presence of each flag indicates that the associated signal is asserted.
//
//*****************************************************************************
@ -806,17 +896,18 @@ UARTModemStatusGet(unsigned long ulBase)
//! Sets the UART hardware flow control mode to be used.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulMode indicates the flow control modes to be used. This is a
//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
//! \param ulMode indicates the flow control modes to be used. This parameter
//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and
//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
//!
//! Sets the required hardware flow control modes. If \e ulMode contains
//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
//! the RTS output is controlled by the hardware and is asserted only when
//! there is space available in the receive FIFO. If no hardware flow control
//! is required, UART_FLOWCONTROL_NONE should be passed.
//! This function configures the required hardware flow control modes. If
//! \e ulMode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted
//! if the incoming CTS signal is asserted. If \e ulMode contains flag
//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
//! asserted only when there is space available in the receive FIFO. If no
//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
//! passed.
//!
//! \note The availability of hardware flow control varies with the Stellaris
//! part and UART in use. Please consult the datasheet for the part you are
@ -832,8 +923,7 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
// Check the arguments.
//
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
//
@ -850,17 +940,17 @@ UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Returns the current hardware flow control mode.
//! This function returns the current hardware flow control mode.
//!
//! \note The availability of hardware flow control varies with the Stellaris
//! part and UART in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return Returns the current flow control mode in use. This is a
//! \return Returns the current flow control mode in use. This value is a
//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
//! flow control is in use. If hardware flow control is disabled, \b
//! UART_FLOWCONTROL_NONE will be returned.
//! flow control is in use. If hardware flow control is disabled,
//! \b UART_FLOWCONTROL_NONE is returned.
//
//*****************************************************************************
unsigned long
@ -870,8 +960,7 @@ UARTFlowControlGet(unsigned long ulBase)
// Check the arguments.
//
ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
UART_FLOWCONTROL_RX));
@ -891,9 +980,9 @@ UARTFlowControlGet(unsigned long ulBase)
//! default, the transmit interrupt is asserted when the FIFO level falls past
//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
//! transmit interrupt will only be asserted once the transmitter is completely
//! idle - the transmit FIFO is empty and all bits, including any stop bits,
//! have cleared the transmitter.
//! transmit interrupt is asserted once the transmitter is completely idle -
//! the transmit FIFO is empty and all bits, including any stop bits, have
//! cleared the transmitter.
//!
//! \note The availability of end-of-transmission mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
@ -908,8 +997,7 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
(ulMode == UART_TXINT_MODE_FIFO));
@ -928,12 +1016,12 @@ UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
//! \param ulBase is the base address of the UART port.
//!
//! This function returns the current operating mode for the UART transmit
//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
//! transmit interrupt is currently set to be asserted once the transmitter is
//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit
//! interrupt is currently configured to be asserted once the transmitter is
//! completely idle - the transmit FIFO is empty and all bits, including any
//! stop bits, have cleared the transmitter. The return value will be \b
//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
//! level of the transmit FIFO.
//! stop bits, have cleared the transmitter. The return value is
//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based
//! on the level of the transmit FIFO.
//!
//! \note The availability of end-of-transmission mode varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
@ -948,8 +1036,7 @@ UARTTxIntModeGet(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
(ulBase == UART2_BASE));
ASSERT(UARTBaseValid(ulBase));
//
// Return the current transmit interrupt mode.
@ -1018,7 +1105,8 @@ UARTSpaceAvail(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port.
//! This function gets a character from the receive FIFO for the specified
//! port.
//!
//! This function replaces the original UARTCharNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
@ -1063,9 +1151,9 @@ UARTCharGetNonBlocking(unsigned long ulBase)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Gets a character from the receive FIFO for the specified port. If there
//! are no characters available, this function waits until a character is
//! received before returning.
//! This function gets a character from the receive FIFO for the specified
//! port. If there are no characters available, this function waits until a
//! character is received before returning.
//!
//! \return Returns the character read from the specified port, cast as a
//! \e long.
@ -1099,9 +1187,10 @@ UARTCharGet(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Writes the character \e ucData to the transmit FIFO for the specified port.
//! This function does not block, so if there is no space available, then a
//! \b false is returned, and the application must retry the function later.
//! This function writes the character \e ucData to the transmit FIFO for the
//! specified port. This function does not block, so if there is no space
//! available, then a \b false is returned and the application must retry the
//! function later.
//!
//! This function replaces the original UARTCharNonBlockingPut() API and
//! performs the same actions. A macro is provided in <tt>uart.h</tt> to map
@ -1151,9 +1240,9 @@ UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
//! \param ulBase is the base address of the UART port.
//! \param ucData is the character to be transmitted.
//!
//! Sends the character \e ucData to the transmit FIFO for the specified port.
//! If there is no space available in the transmit FIFO, this function waits
//! until there is space available before returning.
//! This function sends the character \e ucData to the transmit FIFO for the
//! specified port. If there is no space available in the transmit FIFO, this
//! function waits until there is space available before returning.
//!
//! \return None.
//
@ -1217,10 +1306,10 @@ UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
//!
//! \param ulBase is the base address of the UART port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware. If \b false is returned, the transmit FIFO is
//! empty and all bits of the last transmitted character, including all stop
//! bits, have left the hardware shift register.
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, the
//! transmit FIFO is empty and all bits of the last transmitted character,
//! including all stop bits, have left the hardware shift register.
//!
//! \return Returns \b true if the UART is transmitting or \b false if all
//! transmissions are complete.
@ -1249,8 +1338,8 @@ UARTBusy(unsigned long ulBase)
//! UART interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; specific UART
//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
//! function enables the global interrupt in the interrupt controller; specific
//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
@ -1272,8 +1361,7 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//
// Determine the interrupt number based on the UART port.
//
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
ulInt = UARTIntNumberGet(ulBase);
//
// Register the interrupt handler.
@ -1293,9 +1381,9 @@ UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//! \param ulBase is the base address of the UART port.
//!
//! This function does the actual unregistering of the interrupt handler. It
//! will clear the handler to be called when a UART interrupt occurs. This
//! will also mask off the interrupt in the interrupt controller so that the
//! interrupt handler no longer is called.
//! clears the handler to be called when a UART interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@ -1316,8 +1404,7 @@ UARTIntUnregister(unsigned long ulBase)
//
// Determine the interrupt number based on the UART port.
//
ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
ulInt = UARTIntNumberGet(ulBase);
//
// Disable the interrupt.
@ -1337,12 +1424,13 @@ UARTIntUnregister(unsigned long ulBase)
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function enables the indicated UART interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b UART_INT_9BIT - 9-bit Address Match interrupt
//! - \b UART_INT_OE - Overrun Error interrupt
//! - \b UART_INT_BE - Break Error interrupt
//! - \b UART_INT_PE - Parity Error interrupt
@ -1379,9 +1467,9 @@ UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase is the base address of the UART port.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated UART interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//! This function disables the indicated UART interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to UARTIntEnable().
@ -1411,9 +1499,9 @@ UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified UART. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the specified UART. Either
//! the raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in UARTIntEnable().
@ -1450,19 +1538,19 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
//!
//! The specified UART interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to UARTIntEnable().
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -1489,7 +1577,7 @@ UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified UART DMA features are enabled. The UART can be
//! configured to use DMA for transmit or receive, and to disable
//! configured to use DMA for transmit or receive and to disable
//! receive if an error occurs. The \e ulDMAFlags parameter is the
//! logical OR of any of the following values:
//!
@ -1558,8 +1646,8 @@ UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//! This function returns the current state of each of the 4 receiver error
//! sources. The returned errors are equivalent to the four error bits
//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
//! with the exception that the overrun error is set immediately the overrun
//! occurs rather than when a character is next read.
//! with the exception that the overrun error is set immediately when the
//! overrun occurs rather than when a character is next read.
//!
//! \return Returns a logical OR combination of the receiver error flags,
//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
@ -1603,12 +1691,240 @@ UARTRxErrorClear(unsigned long ulBase)
ASSERT(UARTBaseValid(ulBase));
//
// Any write to the Error Clear Register will clear all bits which are
// Any write to the Error Clear Register clears all bits which are
// currently set.
//
HWREG(ulBase + UART_O_ECR) = 0;
}
//*****************************************************************************
//
//! Sets the baud clock source for the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//! \param ulSource is the baud clock source for the UART.
//!
//! This function allows the baud clock source for the UART to be selected.
//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
//!
//! Changing the baud clock source changes the baud rate generated by the
//! UART. Therefore, the baud rate should be reconfigured after any change to
//! the baud clock source.
//!
//! \note The ability to specify the UART baud clock source varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
ASSERT((ulSource == UART_CLOCK_SYSTEM) || (ulSource == UART_CLOCK_PIOSC));
//
// Set the UART clock source.
//
HWREG(ulBase + UART_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the baud clock source for the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function returns the baud clock source for the specified UART. The
//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
//!
//! \note The ability to specify the UART baud clock source varies with the
//! Stellaris part in use. Please consult the datasheet for the part you are
//! using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
UARTClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Return the UART clock source.
//
return(HWREG(ulBase + UART_O_CC));
}
//*****************************************************************************
//
//! Enables 9-bit mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function enables the 9-bit operational mode of the UART.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Enable 9-bit mode.
//
HWREG(ulBase + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN;
}
//*****************************************************************************
//
//! Disables 9-bit mode on the specified UART.
//!
//! \param ulBase is the base address of the UART port.
//!
//! This function disables the 9-bit operational mode of the UART.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Disable 9-bit mode.
//
HWREG(ulBase + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN;
}
//*****************************************************************************
//
//! Sets the device address(es) for 9-bit mode.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucAddr is the device address.
//! \param ucMask is the device address mask.
//!
//! This function configures the device address or range of device addresses
//! that respond to requests on the 9-bit UART port. The received address is
//! masked with the mask and then compared against the given address, allowing
//! either a single address (if \b ucMask is 0xff) or a set of addresses to be
//! matched.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask)
{
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Set the address and mask.
//
HWREG(ulBase + UART_O_9BITADDR) = ucAddr << UART_9BITADDR_ADDR_S;
HWREG(ulBase + UART_O_9BITAMASK) = ucMask << UART_9BITAMASK_MASK_S;
}
//*****************************************************************************
//
//! Sends an address character from the specified port when operating in 9-bit
//! mode.
//!
//! \param ulBase is the base address of the UART port.
//! \param ucAddr is the address to be transmitted.
//!
//! This function waits until all data has been sent from the specified port
//! and then sends the given address as an address byte. It then waits until
//! the address byte has been transmitted before returning.
//!
//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(),
//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive
//! data characters in 9-bit mode.
//!
//! \note The availability of 9-bit mode varies with the Stellaris part in use.
//! Please consult the datasheet for the part you are using to determine
//! whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr)
{
unsigned long ulLCRH;
//
// Check the arguments.
//
ASSERT(UARTBaseValid(ulBase));
//
// Wait until the FIFO is empty and the UART is not busy.
//
while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY))
{
}
//
// Force the address/data bit to 1 to indicate this is an address byte.
//
ulLCRH = HWREG(ulBase + UART_O_LCRH);
HWREG(ulBase + UART_O_LCRH) = ((ulLCRH & ~UART_LCRH_EPS) | UART_LCRH_SPS |
UART_LCRH_PEN);
//
// Send the address.
//
HWREG(ulBase + UART_O_DR) = ucAddr;
//
// Wait until the address has been sent.
//
while(HWREG(ulBase + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY))
{
}
//
// Restore the address/data setting.
//
HWREG(ulBase + UART_O_LCRH) = ulLCRH;
}
//*****************************************************************************
//
// Close the Doxygen group.

21
bsp/lm3s8962/Libraries/driverlib/uart.h
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@ -2,7 +2,7 @@
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -42,6 +42,7 @@ extern "C"
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
@ -159,6 +160,15 @@ extern "C"
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// Values that can be passed to UARTClockSourceSet() or returned from
// UARTClockSourceGet().
//
//*****************************************************************************
#define UART_CLOCK_SYSTEM 0x00000000
#define UART_CLOCK_PIOSC 0x00000001
//*****************************************************************************
//
// API Function prototypes
@ -212,6 +222,13 @@ extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
extern void UART9BitEnable(unsigned long ulBase);
extern void UART9BitDisable(unsigned long ulBase);
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask);
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
//*****************************************************************************
//

813
bsp/lm3s8962/Libraries/driverlib/udma.c
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435
bsp/lm3s8962/Libraries/driverlib/udma.h
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@ -2,7 +2,7 @@
//
// udma.h - Prototypes and macros for the uDMA controller.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -36,6 +36,13 @@ extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup udma_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
@ -67,6 +74,104 @@ typedef struct
}
tDMAControlTable;
//*****************************************************************************
//
//! A helper macro for building scatter-gather task table entries.
//!
//! \param ulTransferCount is the count of items to transfer for this task.
//! \param ulItemSize is the bit size of the items to transfer for this task.
//! \param ulSrcIncrement is the bit size increment for source data.
//! \param pvSrcAddr is the starting address of the data to transfer.
//! \param ulDstIncrement is the bit size increment for destination data.
//! \param pvDstAddr is the starting address of the destination data.
//! \param ulArbSize is the arbitration size to use for the transfer task.
//! \param ulMode is the transfer mode for this task.
//!
//! This macro is intended to be used to help populate a table of uDMA tasks
//! for a scatter-gather transfer. This macro will calculate the values for
//! the fields of a task structure entry based on the input parameters.
//!
//! There are specific requirements for the values of each parameter. No
//! checking is done so it is up to the caller to ensure that correct values
//! are used for the parameters.
//!
//! The \e ulTransferCount parameter is the number of items that will be
//! transferred by this task. It must be in the range 1-1024.
//!
//! The \e ulItemSize parameter is the bit size of the transfer data. It must
//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
//!
//! The \e ulSrcIncrement parameter is the increment size for the source data.
//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
//!
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
//! data.
//!
//! The \e ulDstIncrement parameter is the increment size for the destination
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
//!
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
//! location where the data will be transferred.
//!
//! The \e ulArbSize parameter is the arbitration size for the transfer, and
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
//! powers of 2, from 1 to 1024.
//!
//! The \e ulMode parameter is the mode to use for this transfer task. It
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
//! that normally all tasks will be one of the scatter-gather modes while the
//! last task is a task list will be AUTO or BASIC.
//!
//! This macro is intended to be used to initialize individual entries of
//! a structure of tDMAControlTable type, like this:
//!
//! \verbatim
//! tDMAControlTable MyTaskList[] =
//! {
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
//! UDMA_SRC_INC_8, MySourceBuf,
//! UDMA_DST_INC_8, MyDestBuf,
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
//! uDMATaskStructEntry(Task2Count, ... ),
//! }
//! \endverbatim
//!
//! \return Nothing; this is not a function.
//
//*****************************************************************************
#define uDMATaskStructEntry(ulTransferCount, \
ulItemSize, \
ulSrcIncrement, \
pvSrcAddr, \
ulDstIncrement, \
pvDstAddr, \
ulArbSize, \
ulMode) \
{ \
(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
((ulSrcIncrement) >> 26)) - 1]))), \
(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
((ulDstIncrement) >> 30)) - 1]))), \
(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
(((ulTransferCount) - 1) << 4) | \
((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
@ -287,6 +392,301 @@ tDMAControlTable;
#define UDMA_DEF_I2S0TX_SEC_RESERVED \
0x20000000
//*****************************************************************************
//
// Values that can be passed to uDMAChannelMapConfigure() to select peripheral
// mapping for each channel. The channels named RESERVED may be assigned
// to a peripheral in future parts.
//
//*****************************************************************************
//
// Channel 0
//
#define UDMA_CH0_USB0EP1RX 0x00000000
#define UDMA_CH0_UART2RX 0x00010000
#define UDMA_CH0_RESERVED2 0x00020000
#define UDMA_CH0_TIMER4A 0x00030000
#define UDMA_CH0_RESERVED4 0x00040000
//
// Channel 1
//
#define UDMA_CH1_USB0EP1TX 0x00000001
#define UDMA_CH1_UART2TX 0x00010001
#define UDMA_CH1_RESERVED2 0x00020001
#define UDMA_CH1_TIMER4B 0x00030001
#define UDMA_CH1_RESERVED4 0x00040001
//
// Channel 2
//
#define UDMA_CH2_USB0EP2RX 0x00000002
#define UDMA_CH2_TIMER3A 0x00010002
#define UDMA_CH2_RESERVED2 0x00020002
#define UDMA_CH2_RESERVED3 0x00030002
#define UDMA_CH2_RESERVED4 0x00040002
//
// Channel 3
//
#define UDMA_CH3_USB0EP2TX 0x00000003
#define UDMA_CH3_TIMER3B 0x00010003
#define UDMA_CH3_RESERVED2 0x00020003
#define UDMA_CH3_LPC0_3 0x00030003
#define UDMA_CH3_RESERVED4 0x00040003
//
// Channel 4
//
#define UDMA_CH4_USB0EP3RX 0x00000004
#define UDMA_CH4_TIMER2A 0x00010004
#define UDMA_CH4_RESERVED2 0x00020004
#define UDMA_CH4_GPIOA 0x00030004
#define UDMA_CH4_RESERVED4 0x00040004
//
// Channel 5
//
#define UDMA_CH5_USB0EP3TX 0x00000005
#define UDMA_CH5_TIMER2B 0x00010005
#define UDMA_CH5_RESERVED2 0x00020005
#define UDMA_CH5_GPIOB 0x00030005
#define UDMA_CH5_RESERVED4 0x00040005
//
// Channel 6
//
#define UDMA_CH6_RESERVED0 0x00000006
#define UDMA_CH6_TIMER2A 0x00010006
#define UDMA_CH6_UART5RX 0x00020006
#define UDMA_CH6_GPIOC 0x00030006
#define UDMA_CH6_I2C0RX 0x00040006
//
// Channel 7
//
#define UDMA_CH7_RESERVED0 0x00000007
#define UDMA_CH7_TIMER2B 0x00010007
#define UDMA_CH7_UART5TX 0x00020007
#define UDMA_CH7_GPIOD 0x00030007
#define UDMA_CH7_I2C0TX 0x00040007
//
// Channel 8
//
#define UDMA_CH8_UART0RX 0x00000008
#define UDMA_CH8_UART1RX 0x00010008
#define UDMA_CH8_RESERVED2 0x00020008
#define UDMA_CH8_TIMER5A 0x00030008
#define UDMA_CH8_I2C1RX 0x00040008
//
// Channel 9
//
#define UDMA_CH9_UART0TX 0x00000009
#define UDMA_CH9_UART1TX 0x00010009
#define UDMA_CH9_RESERVED2 0x00020009
#define UDMA_CH9_TIMER5B 0x00030009
#define UDMA_CH9_I2C1TX 0x00040009
//
// Channel 10
//
#define UDMA_CH10_SSI0RX 0x0000000A
#define UDMA_CH10_SSI1RX 0x0001000A
#define UDMA_CH10_UART6RX 0x0002000A
#define UDMA_CH10_WTIMER0A 0x0003000A
#define UDMA_CH10_I2C2RX 0x0004000A
//
// Channel 11
//
#define UDMA_CH11_SSI0TX 0x0000000B
#define UDMA_CH11_SSI1TX 0x0001000B
#define UDMA_CH11_UART6TX 0x0002000B
#define UDMA_CH11_WTIMER0B 0x0003000B
#define UDMA_CH11_I2C2TX 0x0004000B
//
// Channel 12
//
#define UDMA_CH12_RESERVED0 0x0000000C
#define UDMA_CH12_UART2RX 0x0001000C
#define UDMA_CH12_SSI2RX 0x0002000C
#define UDMA_CH12_WTIMER1A 0x0003000C
#define UDMA_CH12_GPIOK 0x0004000C
//
// Channel 13
//
#define UDMA_CH13_RESERVED0 0x0000000D
#define UDMA_CH13_UART2TX 0x0001000D
#define UDMA_CH13_SSI2TX 0x0002000D
#define UDMA_CH13_WTIMER1B 0x0003000D
#define UDMA_CH13_GPIOL 0x0004000D
//
// Channel 14
//
#define UDMA_CH14_ADC0_0 0x0000000E
#define UDMA_CH14_TIMER2A 0x0001000E
#define UDMA_CH14_SSI3RX 0x0002000E
#define UDMA_CH14_GPIOE 0x0003000E
#define UDMA_CH14_GPIOM 0x0004000E
//
// Channel 15
//
#define UDMA_CH15_ADC0_1 0x0000000F
#define UDMA_CH15_TIMER2B 0x0001000F
#define UDMA_CH15_SSI3TX 0x0002000F
#define UDMA_CH15_GPIOF 0x0003000F
#define UDMA_CH15_GPION 0x0004000F
//
// Channel 16
//
#define UDMA_CH16_ADC0_2 0x00000010
#define UDMA_CH16_RESERVED1 0x00010010
#define UDMA_CH16_UART3RX 0x00020010
#define UDMA_CH16_WTIMER2A 0x00030010
#define UDMA_CH16_GPIOP 0x00040010
//
// Channel 17
//
#define UDMA_CH17_ADC0_3 0x00000011
#define UDMA_CH17_RESERVED1 0x00010011
#define UDMA_CH17_UART3TX 0x00020011
#define UDMA_CH17_WTIMER2B 0x00030011
#define UDMA_CH17_RESERVED4 0x00040011
//
// Channel 18
//
#define UDMA_CH18_TIMER0A 0x00000012
#define UDMA_CH18_TIMER1A 0x00010012
#define UDMA_CH18_UART4RX 0x00020012
#define UDMA_CH18_GPIOB 0x00030012
#define UDMA_CH18_I2C3RX 0x00040012
//
// Channel 19
//
#define UDMA_CH19_TIMER0B 0x00000013
#define UDMA_CH19_TIMER1B 0x00010013
#define UDMA_CH19_UART4TX 0x00020013
#define UDMA_CH19_GPIOG 0x00030013
#define UDMA_CH19_I2C3TX 0x00040013
//
// Channel 20
//
#define UDMA_CH20_TIMER1A 0x00000014
#define UDMA_CH20_RESERVED1 0x00010014
#define UDMA_CH20_UART7RX 0x00020014
#define UDMA_CH20_GPIOH 0x00030014
#define UDMA_CH20_I2C4RX 0x00040014
//
// Channel 21
//
#define UDMA_CH21_TIMER1B 0x00000015
#define UDMA_CH21_RESERVED1 0x00010015
#define UDMA_CH21_UART7TX 0x00020015
#define UDMA_CH21_GPIOJ 0x00030015
#define UDMA_CH21_I2C4TX 0x00040015
//
// Channel 22
//
#define UDMA_CH22_UART1RX 0x00000016
#define UDMA_CH22_RESERVED1 0x00010016
#define UDMA_CH22_RESERVED2 0x00020016
#define UDMA_CH22_LPC0_2 0x00030016
#define UDMA_CH22_I2C5RX 0x00040016
//
// Channel 23
//
#define UDMA_CH23_UART1TX 0x00000017
#define UDMA_CH23_RESERVED1 0x00010017
#define UDMA_CH23_RESERVED2 0x00020017
#define UDMA_CH23_LPC0_1 0x00030017
#define UDMA_CH23_I2C5TX 0x00040017
//
// Channel 24
//
#define UDMA_CH24_SSI1RX 0x00000018
#define UDMA_CH24_ADC1_0 0x00010018
#define UDMA_CH24_RESERVED2 0x00020018
#define UDMA_CH24_WTIMER3A 0x00030018
#define UDMA_CH24_GPIOQ 0x00040018
//
// Channel 25
//
#define UDMA_CH25_SSI1TX 0x00000019
#define UDMA_CH25_ADC1_1 0x00010019
#define UDMA_CH25_RESERVED2 0x00020019
#define UDMA_CH25_WTIMER3B 0x00030019
#define UDMA_CH25_RESERVED4 0x00040019
//
// Channel 26
//
#define UDMA_CH26_RESERVED0 0x0000001A
#define UDMA_CH26_ADC1_2 0x0001001A
#define UDMA_CH26_RESERVED2 0x0002001A
#define UDMA_CH26_WTIMER4A 0x0003001A
#define UDMA_CH26_RESERVED4 0x0004001A
//
// Channel 27
//
#define UDMA_CH27_RESERVED0 0x0000001B
#define UDMA_CH27_ADC1_3 0x0001001B
#define UDMA_CH27_RESERVED2 0x0002001B
#define UDMA_CH27_WTIMER4B 0x0003001B
#define UDMA_CH27_RESERVED4 0x0004001B
//
// Channel 28
//
#define UDMA_CH28_RESERVED0 0x0000001C
#define UDMA_CH28_RESERVED1 0x0001001C
#define UDMA_CH28_RESERVED2 0x0002001C
#define UDMA_CH28_WTIMER5A 0x0003001C
#define UDMA_CH28_RESERVED4 0x0004001C
//
// Channel 29
//
#define UDMA_CH29_RESERVED0 0x0000001D
#define UDMA_CH29_RESERVED1 0x0001001D
#define UDMA_CH29_RESERVED2 0x0002001D
#define UDMA_CH29_WTIMER5B 0x0003001D
#define UDMA_CH29_RESERVED4 0x0004001D
//
// Channel 30
//
#define UDMA_CH30_SW 0x0000001E
#define UDMA_CH30_RESERVED1 0x0001001E
#define UDMA_CH30_RESERVED2 0x0002001E
#define UDMA_CH30_RESERVED3 0x0003001E
#define UDMA_CH30_RESERVED4 0x0004001E
//
// Channel 31
//
#define UDMA_CH31_RESERVED0 0x0000001F
#define UDMA_CH31_RESERVED1 0x0001001F
#define UDMA_CH31_RESERVED2 0x0002001F
#define UDMA_CH31_LPC0_0 0x0003001F
#define UDMA_CH31_RESERVED4 0x0004001F
//*****************************************************************************
//
// API Function prototypes
@ -296,30 +696,37 @@ extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannel);
extern void uDMAChannelDisable(unsigned long ulChannel);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannel);
extern void uDMAChannelEnable(unsigned long ulChannelNum);
extern void uDMAChannelDisable(unsigned long ulChannelNum);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannel);
extern void uDMAChannelAttributeEnable(unsigned long ulChannel,
extern void *uDMAControlAlternateBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannelNum);
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannel,
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannel);
extern void uDMAChannelControlSet(unsigned long ulChannel,
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannel,
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannel);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannel);
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
unsigned ulTaskCount, void *pvTaskList,
unsigned long ulIsPeriphSG);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
extern void uDMAChannelAssign(unsigned long ulMapping);
//*****************************************************************************
//
@ -330,4 +737,4 @@ extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
}
#endif
#endif // __UDMA_H__
#endif // __UDMA_H__

685
bsp/lm3s8962/Libraries/driverlib/usb.c
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bsp/lm3s8962/Libraries/driverlib/usb.h
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@ -2,7 +2,7 @@
//
// usb.h - Prototypes for the USB Interface Driver.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -152,6 +152,7 @@ extern "C"
// USB_DEV_* values are used when the USB controller is in device mode.
//
//*****************************************************************************
#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts
#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received
#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond
#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
@ -163,6 +164,7 @@ extern "C"
// device
#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts
#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
// specified timeout period
#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
@ -474,6 +476,8 @@ extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags);
extern void USBHostPwrFaultDisable(unsigned long ulBase);
extern void USBHostPwrFaultEnable(unsigned long ulBase);
extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
extern void USBHostRequestINClear(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBHostRequestStatus(unsigned long ulBase);
extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
@ -497,8 +501,10 @@ extern void USBEndpointDMAChannel(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulChannel);
extern void USBHostMode(unsigned long ulBase);
extern void USBHostMode(unsigned long ulBase);
extern void USBDevMode(unsigned long ulBase);
extern void USBOTGMode(unsigned long ulBase);
extern void USBPHYPowerOff(unsigned long ulBase);
extern void USBPHYPowerOn(unsigned long ulBase);
//*****************************************************************************
//

137
bsp/lm3s8962/Libraries/driverlib/watchdog.c
View File

@ -2,7 +2,7 @@
//
// watchdog.c - Driver for the Watchdog Timer Module.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -43,9 +43,9 @@
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//! This function checks to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! \return Returns \b true if the watchdog timer is enabled and \b false
//! if it is not.
//
//*****************************************************************************
@ -69,10 +69,9 @@ WatchdogRunning(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//! This function enables the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//! \note This function has no effect if the watchdog timer has been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
@ -99,12 +98,11 @@ WatchdogEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//! This function enables the capability of the watchdog timer to issue a reset
//! to the processor after a second timeout condition.
//!
//! \note This function has no effect if the watchdog timer has been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
@ -130,11 +128,10 @@ WatchdogResetEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Disables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//! This function disables the capability of the watchdog timer to issue a
//! reset to the processor after a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//! \note This function has no effect if the watchdog timer has been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
@ -161,7 +158,8 @@ WatchdogResetDisable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//! This function locks out write access to the watchdog timer configuration
//! registers.
//!
//! \return None.
//
@ -187,7 +185,8 @@ WatchdogLock(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//! This function enables write access to the watchdog timer configuration
//! registers.
//!
//! \return None.
//
@ -212,7 +211,7 @@ WatchdogUnlock(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//! This function returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
@ -239,14 +238,13 @@ WatchdogLockState(unsigned long ulBase)
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value will be immediately loaded into the
//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
//! This function configures the value to load into the watchdog timer when the
//! count reaches zero for the first time; if the watchdog timer is running
//! when this function is called, then the value is immediately loaded into the
//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
//! interrupt is immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//! \note This function has no effect if the watchdog timer has been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
@ -322,21 +320,27 @@ WatchdogValueGet(unsigned long ulBase)
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//! Registers an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! function also enables the global interrupt in the interrupt controller; the
//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the
//! interrupt handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note For parts with a watchdog timer module that has the ability to
//! generate an NMI instead of a standard interrupt, this function registers
//! the standard watchdog interrupt handler. To register the NMI watchdog
//! handler, use IntRegister() to register the handler for the
//! \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
@ -366,13 +370,19 @@ WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! function clears the handler to be called when a watchdog timer interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note For parts with a watchdog timer module that has the ability to
//! generate an NMI instead of a standard interrupt, this function unregisters
//! the standard watchdog interrupt handler. To unregister the NMI watchdog
//! handler, use IntUnregister() to unregister the handler for the
//! \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
@ -401,10 +411,9 @@ WatchdogIntUnregister(unsigned long ulBase)
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the watchdog timer interrupt.
//! This function enables the watchdog timer interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//! \note This function has no effect if the watchdog timer has been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
//!
@ -433,9 +442,9 @@ WatchdogIntEnable(unsigned long ulBase)
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//! This function returns the interrupt status for the watchdog timer module.
//! Either the raw interrupt status or the status of interrupt that is allowed
//! to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, where a 1 indicates that the
//! watchdog interrupt is active, and a 0 indicates that it is not active.
@ -472,14 +481,14 @@ WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@ -498,6 +507,46 @@ WatchdogIntClear(unsigned long ulBase)
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
//*****************************************************************************
//
//! Sets the type of interrupt generated by the watchdog.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulType is the type of interrupt to generate.
//!
//! This function sets the type of interrupt that is generated if the watchdog
//! timer expires. \e ulType can be either \b WATCHDOG_INT_TYPE_INT to
//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
//! generate a non-maskable interrupt (NMI).
//!
//! When configured to generate an NMI, the watchdog interrupt must still be
//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
//! NMI handler with WatchdogIntClear().
//!
//! \note The ability to select an NMI interrupt varies with the Stellaris part
//! in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
ASSERT((ulType == WATCHDOG_INT_TYPE_INT) ||
(ulType == WATCHDOG_INT_TYPE_NMI));
//
// Set the interrupt type.
//
HWREG(ulBase + WDT_O_CTL) =
(HWREG(ulBase + WDT_O_CTL) & ~WDT_CTL_INTTYPE) | ulType;
}
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
@ -507,9 +556,9 @@ WatchdogIntClear(unsigned long ulBase)
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! resetting the system (if reset is enabled). The watchdog instead expires
//! after the appropriate number of processor cycles have been executed while
//! debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.

13
bsp/lm3s8962/Libraries/driverlib/watchdog.h
View File

@ -2,7 +2,7 @@
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@ -36,6 +36,14 @@ extern "C"
{
#endif
//*****************************************************************************
//
// The type of interrupt that can be generated by the watchdog.
//
//*****************************************************************************
#define WATCHDOG_INT_TYPE_INT 0x00000000
#define WATCHDOG_INT_TYPE_NMI 0x00000004
//*****************************************************************************
//
// Prototypes for the APIs.
@ -56,6 +64,7 @@ extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);

4
bsp/lm3s8962/Libraries/inc/asmdefs.h
View File

@ -2,7 +2,7 @@
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

26
bsp/lm3s8962/Libraries/inc/cr_project.xml
View File

@ -1,26 +0,0 @@
<!--
Configuration file for Code Red project inc
Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
Software License Agreement
Texas Instruments (TI) is supplying this software for use solely and
exclusively on TI's microcontroller products. The software is owned by
TI and/or its suppliers, and is protected under applicable copyright
laws. You may not combine this software with "viral" open-source
software in order to form a larger program.
THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 6459 of the Stellaris Firmware Development Package.
-->
<project>
<import src=".">
</import>
</project>

188
bsp/lm3s8962/Libraries/inc/hw_adc.h
View File

@ -2,7 +2,7 @@
//
// hw_adc.h - Macros used when accessing the ADC hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -37,6 +37,7 @@
#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
#define ADC_O_USTAT 0x00000018 // ADC Underflow Status
#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select
#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
@ -55,6 +56,8 @@
#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
// Comparator Select
#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended
// Input Multiplexer Select 0
#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
// Multiplexer Select 1
#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
@ -65,6 +68,8 @@
#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
// Comparator Select
#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended
// Input Multiplexer Select 1
#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
// Multiplexer Select 2
#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
@ -75,6 +80,8 @@
#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
// Comparator Select
#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended
// Input Multiplexer Select 2
#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
// Multiplexer Select 3
#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
@ -85,6 +92,8 @@
#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
// Comparator Select
#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended
// Input Multiplexer Select 3
#define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback
#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
// Initial Conditions
@ -104,6 +113,9 @@
#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties
#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration
#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration
//*****************************************************************************
//
@ -237,6 +249,24 @@
#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_TSSEL register.
//
//*****************************************************************************
#define ADC_TSSEL_PS3_M 0x03000000 // PWM Unit Select
#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0
#define ADC_TSSEL_PS3_1 0x01000000 // PWM Unit 1
#define ADC_TSSEL_PS2_M 0x00030000 // PWM Unit Select
#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0
#define ADC_TSSEL_PS2_1 0x00010000 // PWM Unit 1
#define ADC_TSSEL_PS1_M 0x00000300 // PWM Unit Select
#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0
#define ADC_TSSEL_PS1_1 0x00000100 // PWM Unit 1
#define ADC_TSSEL_PS0_M 0x00000003 // PWM Unit Select
#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0
#define ADC_TSSEL_PS0_1 0x00000001 // PWM Unit 1
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSPRI register.
@ -339,6 +369,19 @@
// The following are defines for the bit fields in the ADC_O_CTL register.
//
//*****************************************************************************
#define ADC_CTL_RES 0x00000010 // Sample Resolution
#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the
// voltage reference
#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is
// the voltage reference. The ADC
// conversion range is 0.0 V to the
// external reference value
#define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is
// the voltage reference. The ADC
// conversion range is 0.0 V to
// three times the external
// reference value
#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select
//*****************************************************************************
@ -406,7 +449,7 @@
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
//
//*****************************************************************************
#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
#define ADC_SSFIFO0_DATA_S 0
//*****************************************************************************
@ -472,6 +515,28 @@
#define ADC_SSDC0_S1DCSEL_S 4
#define ADC_SSDC0_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
//
//*****************************************************************************
#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
// Bit)
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
@ -513,7 +578,7 @@
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
//
//*****************************************************************************
#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
#define ADC_SSFIFO1_DATA_S 0
//*****************************************************************************
@ -559,6 +624,20 @@
#define ADC_SSDC1_S1DCSEL_S 4
#define ADC_SSDC1_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
//
//*****************************************************************************
#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
// Bit)
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
@ -600,7 +679,7 @@
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
//
//*****************************************************************************
#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
#define ADC_SSFIFO2_DATA_S 0
//*****************************************************************************
@ -646,6 +725,20 @@
#define ADC_SSDC2_S1DCSEL_S 4
#define ADC_SSDC2_S0DCSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
//
//*****************************************************************************
#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
// Bit)
#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
// Bit)
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
@ -669,7 +762,7 @@
// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
//
//*****************************************************************************
#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data
#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
#define ADC_SSFIFO3_DATA_S 0
//*****************************************************************************
@ -700,6 +793,14 @@
#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
// Select
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
//
//*****************************************************************************
#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
// Bit)
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_TMLB register.
@ -942,8 +1043,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
//
//*****************************************************************************
#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP0_COMP1_S 16
#define ADC_DCCMP0_COMP0_S 0
@ -952,8 +1053,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
//
//*****************************************************************************
#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP1_COMP1_S 16
#define ADC_DCCMP1_COMP0_S 0
@ -962,8 +1063,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
//
//*****************************************************************************
#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP2_COMP1_S 16
#define ADC_DCCMP2_COMP0_S 0
@ -972,8 +1073,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
//
//*****************************************************************************
#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP3_COMP1_S 16
#define ADC_DCCMP3_COMP0_S 0
@ -982,8 +1083,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
//
//*****************************************************************************
#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP4_COMP1_S 16
#define ADC_DCCMP4_COMP0_S 0
@ -992,8 +1093,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
//
//*****************************************************************************
#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP5_COMP1_S 16
#define ADC_DCCMP5_COMP0_S 0
@ -1002,8 +1103,8 @@
// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
//
//*****************************************************************************
#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP6_COMP1_S 16
#define ADC_DCCMP6_COMP0_S 0
@ -1012,11 +1113,54 @@
// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
//
//*****************************************************************************
#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1
#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0
#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
#define ADC_DCCMP7_COMP1_S 16
#define ADC_DCCMP7_COMP0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_PP register.
//
//*****************************************************************************
#define ADC_PP_TS 0x00800000 // Temperature Sensor
#define ADC_PP_RSL_M 0x007C0000 // Resolution
#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
#define ADC_PP_TYPE_SAR 0x00000000 // SAR
#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
#define ADC_PP_RSL_S 18
#define ADC_PP_DC_S 10
#define ADC_PP_CH_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_PC register.
//
//*****************************************************************************
#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
#define ADC_PC_SR_125K 0x00000001 // 125 ksps
#define ADC_PC_SR_250K 0x00000003 // 250 ksps
#define ADC_PC_SR_500K 0x00000005 // 500 ksps
#define ADC_PC_SR_1M 0x00000007 // 1 Msps
//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_CC register.
//
//*****************************************************************************
#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
// PLL bypass is in effect) or the
// 16 MHz clock derived from PLL /
// 25 (default)
#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
//*****************************************************************************
//
// The following are defines for the the interpretation of the data in the

4
bsp/lm3s8962/Libraries/inc/hw_can.h
View File

@ -2,7 +2,7 @@
//
// hw_can.h - Defines and macros used when accessing the CAN controllers.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

18
bsp/lm3s8962/Libraries/inc/hw_comp.h
View File

@ -2,7 +2,7 @@
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -44,6 +44,8 @@
#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
// Properties
//*****************************************************************************
//
@ -182,6 +184,18 @@
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_PP register.
//
//*****************************************************************************
#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
//*****************************************************************************
//
// The following definitions are deprecated.

206
bsp/lm3s8962/Libraries/inc/hw_eeprom.h Normal file
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@ -0,0 +1,206 @@
//*****************************************************************************
//
// hw_eeprom.h - Macros used when accessing the EEPROM controller.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EEPROM_H__
#define __HW_EEPROM_H__
//*****************************************************************************
//
// The following are defines for the EEPROM register offsets.
//
//*****************************************************************************
#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
// Status
#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
#define EEPROM_EEPROMPP 0x400AFFC0 // EEPROM
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESIZE register.
//
//*****************************************************************************
#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
#define EEPROM_EESIZE_WORDCNT_S 0
#define EEPROM_EESIZE_BLKCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
//
//*****************************************************************************
#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
#define EEPROM_EEBLOCK_BLOCK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEOFFSET
// register.
//
//*****************************************************************************
#define EEPROM_EEOFFSET_OFFSET_M \
0x0000000F // Current Address Offset
#define EEPROM_EEOFFSET_OFFSET_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWR register.
//
//*****************************************************************************
#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
#define EEPROM_EERDWR_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWRINC
// register.
//
//*****************************************************************************
#define EEPROM_EERDWRINC_VALUE_M \
0xFFFFFFFF // EEPROM Read or Write Data with
// Increment
#define EEPROM_EERDWRINC_VALUE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDONE register.
//
//*****************************************************************************
#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESUPP register.
//
//*****************************************************************************
#define EEPROM_EESUPP_START 0x00000001 // Start Erase
#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEUNLOCK
// register.
//
//*****************************************************************************
#define EEPROM_EEUNLOCK_UNLOCK_M \
0xFFFFFFFF // EEPROM Unlock
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPROT register.
//
//*****************************************************************************
#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
#define EEPROM_EEPROT_PROT_RWNPW \
0x00000000 // This setting is the default. If
// there is no password, the block
// is not protected and is readable
// and writable
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
// block is readable or writable
// only when unlocked
#define EEPROM_EEPROT_PROT_RONPW \
0x00000002 // If there is no password, the
// block is readable, not writable
#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
//
//*****************************************************************************
#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS0_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
//
//*****************************************************************************
#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS1_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
//
//*****************************************************************************
#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS2_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEINT register.
//
//*****************************************************************************
#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE register.
//
//*****************************************************************************
#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDBGME register.
//
//*****************************************************************************
#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
#define EEPROM_EEDBGME_KEY_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPROMPP
// register.
//
//*****************************************************************************
#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size
#define EEPROM_EEPROMPP_SIZE_S 0
#endif // __HW_EEPROM_H__

28
bsp/lm3s8962/Libraries/inc/hw_epi.h
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@ -2,7 +2,7 @@
//
// hw_epi.h - Macros for use in accessing the EPI registers.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -206,6 +206,18 @@
#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states
#define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states
#define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states
//*****************************************************************************
//
@ -219,6 +231,18 @@
#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states
#define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states
#define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states
//*****************************************************************************
//

13
bsp/lm3s8962/Libraries/inc/hw_ethernet.h
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@ -2,7 +2,7 @@
//
// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -45,6 +45,7 @@
#define MAC_O_THR 0x0000001C // Ethernet MAC Threshold
#define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control
#define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider
#define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address
#define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit
// Data
#define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive
@ -176,6 +177,14 @@
#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
#define MAC_MDV_DIV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MADD register.
//
//*****************************************************************************
#define MAC_MADD_PHYADR_M 0x0000001F // PHY Address
#define MAC_MADD_PHYADR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MTXD register.

636
bsp/lm3s8962/Libraries/inc/hw_fan.h Normal file
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@ -0,0 +1,636 @@
//*****************************************************************************
//
// hw_fan.h - Macros used when accessing the fan control hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_FAN_H__
#define __HW_FAN_H__
//*****************************************************************************
//
// The following are defines for the Fan Control register offsets.
//
//*****************************************************************************
#define FAN_O_STS 0x00000000 // FAN Status
#define FAN_O_CTL 0x00000004 // FAN Control
#define FAN_O_CH0 0x00000010 // FAN Channel Command
#define FAN_O_CMD0 0x00000014 // FAN Channel Command
#define FAN_O_CST0 0x00000018 // FAN Channel Status
#define FAN_O_CH1 0x00000020 // FAN Channel Setup
#define FAN_O_CMD1 0x00000024 // FAN Channel Command
#define FAN_O_CST1 0x00000028 // FAN Channel Status
#define FAN_O_CH2 0x00000030 // FAN Channel Setup
#define FAN_O_CMD2 0x00000034 // FAN Channel Command
#define FAN_O_CST2 0x00000038 // FAN Channel Status
#define FAN_O_CH3 0x00000040 // FAN Channel Setup
#define FAN_O_CMD3 0x00000044 // FAN Channel Command
#define FAN_O_CST3 0x00000048 // FAN Channel Status
#define FAN_O_CH4 0x00000050 // FAN Channel Setup
#define FAN_O_CMD4 0x00000054 // FAN Channel Command
#define FAN_O_CST4 0x00000058 // FAN Channel Status
#define FAN_O_CH5 0x00000060 // FAN Channel Setup
#define FAN_O_CMD5 0x00000064 // FAN Channel Command
#define FAN_O_CST5 0x00000068 // FAN Channel Status
#define FAN_O_CH6 0x00000070 // FAN Channel Setup
#define FAN_O_CMD6 0x00000074 // FAN Channel Command
#define FAN_O_CST6 0x00000078 // FAN Channel Status
#define FAN_O_CH7 0x00000080 // FAN Channel Setup
#define FAN_O_CMD7 0x00000084 // FAN Channel Command
#define FAN_O_CST7 0x00000088 // FAN Channel Status
#define FAN_O_IM 0x00000090 // FAN Interrupt Mask
#define FAN_O_RIS 0x00000094 // FAN Raw Interrupt Status
#define FAN_O_MIS 0x00000098 // FAN Masked Interrupt Status
#define FAN_O_IC 0x0000009C // FAN Interrupt Clear
#define FAN_O_PP 0x00000FC0 // FAN Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_STS register.
//
//*****************************************************************************
#define FAN_STS_FANCNT_M 0x000F0000 // Fan Count
#define FAN_STS_ST5_M 0x00000C00 // Fan 5 Status
#define FAN_STS_ST5_STALLED 0x00000000 // Stalled
#define FAN_STS_ST5_CHANGING 0x00000400 // Changing
#define FAN_STS_ST5_LOCKED 0x00000800 // Locked
#define FAN_STS_ST5_UNBALANCED 0x00000C00 // Unbalanced Spin
#define FAN_STS_ST4_M 0x00000300 // Fan 4 Status
#define FAN_STS_ST3_M 0x000000C0 // Fan 3 Status
#define FAN_STS_ST2_M 0x00000030 // Fan 2 Status
#define FAN_STS_ST1_M 0x0000000C // Fan 1 Status
#define FAN_STS_ST0_M 0x00000003 // Fan 0 Status
#define FAN_STS_FANCNT_S 16
#define FAN_STS_ST4_S 8
#define FAN_STS_ST3_S 6
#define FAN_STS_ST2_S 4
#define FAN_STS_ST1_S 2
#define FAN_STS_ST0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CTL register.
//
//*****************************************************************************
#define FAN_CTL_E5 0x00000020 // Fan 5 Enable
#define FAN_CTL_E4 0x00000010 // Fan 4 Enable
#define FAN_CTL_E3 0x00000008 // Fan 3 Enable
#define FAN_CTL_E2 0x00000004 // Fan 2 Enable
#define FAN_CTL_E1 0x00000002 // Fan 1 Enable
#define FAN_CTL_E0 0x00000001 // Fan 0 Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH0 register.
//
//*****************************************************************************
#define FAN_CH0_ASTART 0x00008000 // Auto Restart
#define FAN_CH0_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH0_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH0_STPER_M 0x00000700 // Start Period
#define FAN_CH0_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH0_START_NOFAST 0x00000000 // No fast start
#define FAN_CH0_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH0_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH0_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH0_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH0_AVG_0 0x00000000 // No averaging
#define FAN_CH0_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH0_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH0_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH0_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH0_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH0_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH0_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH0_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH0_MAN 0x00000001 // Control Type
#define FAN_CH0_HYST_S 11
#define FAN_CH0_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD0 register.
//
//*****************************************************************************
#define FAN_CMD0_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD0_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD0_DC_S 16
#define FAN_CMD0_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST0 register.
//
//*****************************************************************************
#define FAN_CST0_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST0_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST0_COUNT_S 16
#define FAN_CST0_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH1 register.
//
//*****************************************************************************
#define FAN_CH1_ASTART 0x00008000 // Auto Restart
#define FAN_CH1_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH1_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH1_STPER_M 0x00000700 // Start Period
#define FAN_CH1_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH1_START_NOFAST 0x00000000 // No fast start
#define FAN_CH1_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH1_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH1_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH1_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH1_AVG_0 0x00000000 // No averaging
#define FAN_CH1_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH1_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH1_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH1_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH1_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH1_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH1_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH1_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH1_MAN 0x00000001 // Control Type
#define FAN_CH1_HYST_S 11
#define FAN_CH1_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD1 register.
//
//*****************************************************************************
#define FAN_CMD1_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD1_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD1_DC_S 16
#define FAN_CMD1_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST1 register.
//
//*****************************************************************************
#define FAN_CST1_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST1_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST1_COUNT_S 16
#define FAN_CST1_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH2 register.
//
//*****************************************************************************
#define FAN_CH2_ASTART 0x00008000 // Auto Restart
#define FAN_CH2_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH2_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH2_STPER_M 0x00000700 // Start Period
#define FAN_CH2_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH2_START_NOFAST 0x00000000 // No fast start
#define FAN_CH2_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH2_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH2_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH2_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH2_AVG_0 0x00000000 // No averaging
#define FAN_CH2_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH2_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH2_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH2_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH2_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH2_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH2_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH2_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH2_MAN 0x00000001 // Control Type
#define FAN_CH2_HYST_S 11
#define FAN_CH2_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD2 register.
//
//*****************************************************************************
#define FAN_CMD2_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD2_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD2_DC_S 16
#define FAN_CMD2_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST2 register.
//
//*****************************************************************************
#define FAN_CST2_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST2_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST2_COUNT_S 16
#define FAN_CST2_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH3 register.
//
//*****************************************************************************
#define FAN_CH3_ASTART 0x00008000 // Auto Restart
#define FAN_CH3_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH3_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH3_STPER_M 0x00000700 // Start Period
#define FAN_CH3_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH3_START_NOFAST 0x00000000 // No fast start
#define FAN_CH3_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH3_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH3_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH3_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH3_AVG_0 0x00000000 // No averaging
#define FAN_CH3_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH3_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH3_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH3_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH3_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH3_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH3_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH3_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH3_MAN 0x00000001 // Control Type
#define FAN_CH3_HYST_S 11
#define FAN_CH3_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD3 register.
//
//*****************************************************************************
#define FAN_CMD3_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD3_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD3_DC_S 16
#define FAN_CMD3_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST3 register.
//
//*****************************************************************************
#define FAN_CST3_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST3_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST3_COUNT_S 16
#define FAN_CST3_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH4 register.
//
//*****************************************************************************
#define FAN_CH4_ASTART 0x00008000 // Auto Restart
#define FAN_CH4_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH4_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH4_STPER_M 0x00000700 // Start Period
#define FAN_CH4_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH4_START_NOFAST 0x00000000 // No fast start
#define FAN_CH4_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH4_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH4_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH4_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH4_AVG_0 0x00000000 // No averaging
#define FAN_CH4_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH4_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH4_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH4_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH4_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH4_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH4_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH4_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH4_MAN 0x00000001 // Control Type
#define FAN_CH4_HYST_S 11
#define FAN_CH4_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD4 register.
//
//*****************************************************************************
#define FAN_CMD4_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD4_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD4_DC_S 16
#define FAN_CMD4_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST4 register.
//
//*****************************************************************************
#define FAN_CST4_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST4_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST4_COUNT_S 16
#define FAN_CST4_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH5 register.
//
//*****************************************************************************
#define FAN_CH5_ASTART 0x00008000 // Auto Restart
#define FAN_CH5_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH5_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH5_STPER_M 0x00000700 // Start Period
#define FAN_CH5_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH5_START_NOFAST 0x00000000 // No fast start
#define FAN_CH5_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH5_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH5_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH5_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH5_AVG_0 0x00000000 // No averaging
#define FAN_CH5_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH5_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH5_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH5_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH5_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH5_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH5_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH5_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH5_MAN 0x00000001 // Control Type
#define FAN_CH5_HYST_S 11
#define FAN_CH5_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD5 register.
//
//*****************************************************************************
#define FAN_CMD5_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD5_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD5_DC_S 16
#define FAN_CMD5_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST5 register.
//
//*****************************************************************************
#define FAN_CST5_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST5_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST5_COUNT_S 16
#define FAN_CST5_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH6 register.
//
//*****************************************************************************
#define FAN_CH6_MAN 0x00000001 // Control Type
#define FAN_CH6_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH6_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH6_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH6_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH6_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH6_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH6_AVG_0 0x00000000 // No averaging
#define FAN_CH6_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH6_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH6_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH6_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH6_START_NOFAST 0x00000000 // No fast start
#define FAN_CH6_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH6_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH6_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH6_STPER_M 0x00000700 // Start Period
#define FAN_CH6_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH6_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH6_ASTART 0x00008000 // Auto Restart
#define FAN_CH6_STPER_S 8
#define FAN_CH6_HYST_S 11
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD6 register.
//
//*****************************************************************************
#define FAN_CMD6_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD6_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD6_RPM_S 0
#define FAN_CMD6_DC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST6 register.
//
//*****************************************************************************
#define FAN_CST6_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST6_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST6_RPM_S 0
#define FAN_CST6_COUNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH7 register.
//
//*****************************************************************************
#define FAN_CH7_MAN 0x00000001 // Control Type
#define FAN_CH7_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH7_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH7_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH7_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH7_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH7_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH7_AVG_0 0x00000000 // No averaging
#define FAN_CH7_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH7_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH7_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH7_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH7_START_NOFAST 0x00000000 // No fast start
#define FAN_CH7_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH7_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH7_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH7_STPER_M 0x00000700 // Start Period
#define FAN_CH7_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH7_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH7_ASTART 0x00008000 // Auto Restart
#define FAN_CH7_STPER_S 8
#define FAN_CH7_HYST_S 11
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD7 register.
//
//*****************************************************************************
#define FAN_CMD7_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD7_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD7_RPM_S 0
#define FAN_CMD7_DC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST7 register.
//
//*****************************************************************************
#define FAN_CST7_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST7_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST7_RPM_S 0
#define FAN_CST7_COUNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_IM register.
//
//*****************************************************************************
#define FAN_IM_C5INT1IM 0x00400000 // Channel 5 Interrupt 1 Mask
#define FAN_IM_C5INT0IM 0x00200000 // Channel 5 Interrupt 0 Mask
#define FAN_IM_C5STALLIM 0x00100000 // Channel 5 Stall Interrupt Mask
#define FAN_IM_C4INT1IM 0x00040000 // Channel 4 Interrupt 1 Mask
#define FAN_IM_C4INT0IM 0x00020000 // Channel 4 Interrupt 0 Mask
#define FAN_IM_C4STALLIM 0x00010000 // Channel 4 Stall Interrupt Mask
#define FAN_IM_C3INT1IM 0x00004000 // Channel 3 Interrupt 1 Mask
#define FAN_IM_C3INT0IM 0x00002000 // Channel 3 Interrupt 0 Mask
#define FAN_IM_C3STALLIM 0x00001000 // Channel 3 Stall Interrupt Mask
#define FAN_IM_C2INT1IM 0x00000400 // Channel 2 Interrupt 1 Mask
#define FAN_IM_C2INT0IM 0x00000200 // Channel 2 Interrupt 0 Mask
#define FAN_IM_C2STALLIM 0x00000100 // Channel 2 Stall Interrupt Mask
#define FAN_IM_C1INT1IM 0x00000040 // Channel 1 Interrupt 1 Mask
#define FAN_IM_C1INT0IM 0x00000020 // Channel 1 Interrupt 0 Mask
#define FAN_IM_C1STALLIM 0x00000010 // Channel 1 Stall Interrupt Mask
#define FAN_IM_C0INT1IM 0x00000004 // Channel 0 Interrupt 1 Mask
#define FAN_IM_C0INT0IM 0x00000002 // Channel 0 Interrupt 0 Mask
#define FAN_IM_C0STALLIM 0x00000001 // Channel 0 Stall Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_RIS register.
//
//*****************************************************************************
#define FAN_RIS_C5INT1RIS 0x00400000 // Channel 5 Raw Interrupt 1 Status
#define FAN_RIS_C5INT0RIS 0x00200000 // Channel 5 Raw Interrupt 0 Status
#define FAN_RIS_C5STALLRIS 0x00100000 // Channel 5 Raw Stall Interrupt
// Status
#define FAN_RIS_C4INT1RIS 0x00040000 // Channel 4 Raw Interrupt 1 Status
#define FAN_RIS_C4INT0RIS 0x00020000 // Channel 4 Raw Interrupt 0 Status
#define FAN_RIS_C4STALLRIS 0x00010000 // Channel 4 Raw Stall Interrupt
// Status
#define FAN_RIS_C3INT1RIS 0x00004000 // Channel 3 Raw Interrupt 1 Status
#define FAN_RIS_C3INT0RIS 0x00002000 // Channel 3 Raw Interrupt 0 Status
#define FAN_RIS_C3STALLRIS 0x00001000 // Channel 3 Raw Stall Interrupt
// Status
#define FAN_RIS_C2INT1RIS 0x00000400 // Channel 2 Raw Interrupt 1 Status
#define FAN_RIS_C2INT0RIS 0x00000200 // Channel 2 Raw Interrupt 0 Status
#define FAN_RIS_C2STALLRIS 0x00000100 // Channel 2 Raw Stall Interrupt
// Status
#define FAN_RIS_C1INT1RIS 0x00000040 // Channel 1 Raw Interrupt 1 Status
#define FAN_RIS_C1INT0RIS 0x00000020 // Channel 1 Raw Interrupt 0 Status
#define FAN_RIS_C1STALLRIS 0x00000010 // Channel 1 Raw Stall Interrupt
// Status
#define FAN_RIS_C0INT1RIS 0x00000004 // Channel 0 Raw Interrupt 1 Status
#define FAN_RIS_C0INT0RIS 0x00000002 // Channel 0 Raw Interrupt 0 Status
#define FAN_RIS_C0STALLRIS 0x00000001 // Channel 0 Raw Stall Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_MIS register.
//
//*****************************************************************************
#define FAN_MIS_C5INT1MIS 0x00400000 // Channel 5 Masked Interrupt 1
// Status
#define FAN_MIS_C5INT0MIS 0x00200000 // Channel 5 Masked Interrupt 0
// Status
#define FAN_MIS_C5STALLMIS 0x00100000 // Channel 5 Masked Stall Interrupt
// Status
#define FAN_MIS_C54NT1MIS 0x00040000 // Channel 4 Masked Interrupt 1
// Status
#define FAN_MIS_C4INT0MIS 0x00020000 // Channel 4 Masked Interrupt 0
// Status
#define FAN_MIS_C4STALLMIS 0x00010000 // Channel 4 Masked Stall Interrupt
// Status
#define FAN_MIS_C3INT1MIS 0x00004000 // Channel 3 Masked Interrupt 1
// Status
#define FAN_MIS_C3INT0MIS 0x00002000 // Channel 3 Masked Interrupt 0
// Status
#define FAN_MIS_C3STALLMIS 0x00001000 // Channel 3 Masked Stall Interrupt
// Status
#define FAN_MIS_C2INT1MIS 0x00000400 // Channel 2 Masked Interrupt 1
// Status
#define FAN_MIS_C2INT0MIS 0x00000200 // Channel 2 Masked Interrupt 0
// Status
#define FAN_MIS_C2STALLMIS 0x00000100 // Channel 2 Masked Stall Interrupt
// Status
#define FAN_MIS_C1INT1MIS 0x00000040 // Channel 1 Masked Interrupt 1
// Status
#define FAN_MIS_C1INT0MIS 0x00000020 // Channel 1 Masked Interrupt 0
// Status
#define FAN_MIS_C1STALLMIS 0x00000010 // Channel 1 Masked Stall Interrupt
// Status
#define FAN_MIS_C0INT1MIS 0x00000004 // Channel 0 Masked Interrupt 1
// Status
#define FAN_MIS_C0INT0MIS 0x00000002 // Channel 0 Masked Interrupt 0
// Status
#define FAN_MIS_C0STALLMIS 0x00000001 // Channel 0 Masked Stall Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_IC register.
//
//*****************************************************************************
#define FAN_IC_C5INT1IC 0x00400000 // Channel 5 Interrupt 1 Clear
#define FAN_IC_C5INT0IC 0x00200000 // Channel 5 Interrupt 0 Clear
#define FAN_IC_C5STALLIC 0x00100000 // Channel 5 Stall Interrupt Clear
#define FAN_IC_C4INT1IC 0x00040000 // Channel 4 Interrupt 1 Clear
#define FAN_IC_C4INT0IC 0x00020000 // Channel 4 Interrupt 0 Clear
#define FAN_IC_C4STALLIC 0x00010000 // Channel 4 Stall Interrupt Clear
#define FAN_IC_C3INT1IC 0x00004000 // Channel 3 Interrupt 1 Clear
#define FAN_IC_C53INT0IC 0x00002000 // Channel 3 Interrupt 0 Clear
#define FAN_IC_C3STALLIC 0x00001000 // Channel 3 Stall Interrupt Clear
#define FAN_IC_C2INT1IC 0x00000400 // Channel 2 Interrupt 1 Clear
#define FAN_IC_C2INT0IC 0x00000200 // Channel 2 Interrupt 0 Clear
#define FAN_IC_C2STALLIC 0x00000100 // Channel 2 Stall Interrupt Clear
#define FAN_IC_C1INT1IC 0x00000040 // Channel 1 Interrupt 1 Clear
#define FAN_IC_C1INT0IC 0x00000020 // Channel 1 Interrupt 0 Clear
#define FAN_IC_C1STALLIC 0x00000010 // Channel 1 Stall Interrupt Clear
#define FAN_IC_C0INT1IC 0x00000004 // Channel 0 Interrupt 1 Clear
#define FAN_IC_C0INT0IC 0x00000002 // Channel 0 Interrupt 0 Clear
#define FAN_IC_C0STALLIC 0x00000001 // Channel 0 Stall Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_PP register.
//
//*****************************************************************************
#define FAN_PP_CHAN_M 0x0000000F // Channel Count
#define FAN_PP_CHAN_S 0
#endif // __HW_FAN_H__

135
bsp/lm3s8962/Libraries/inc/hw_flash.h
View File

@ -2,7 +2,7 @@
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -42,8 +42,10 @@
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
#define FLASH_FCTL 0x400FD0F8 // Flash Control
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
// Enable
#define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program
@ -63,6 +65,14 @@
// Enable 2
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
// Enable 3
#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
// Enable 4
#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
// Enable 5
#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
// Enable 6
#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
// Enable 7
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
// Enable 0
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
@ -71,13 +81,21 @@
// Enable 2
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
// Enable 3
#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
// Enable 4
#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
// Enable 5
#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
// Enable 6
#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
// Enable 7
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
@ -104,6 +122,12 @@
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
// Status
#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
@ -112,6 +136,11 @@
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
@ -120,6 +149,16 @@
// The following are defines for the bit fields in the FLASH_FCMISC register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
// Clear
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
@ -155,6 +194,44 @@
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FSIZE register.
//
//*****************************************************************************
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_SSIZE register.
//
//*****************************************************************************
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
//
//*****************************************************************************
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
@ -162,27 +239,6 @@
//*****************************************************************************
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMVER register.
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
// DriverLib
#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
0x03000000 // Stellaris Boot Loader &
// DriverLib with AES and SAFERTOS
#define FLASH_RMVER_CONT_LM_AES2 \
0x05000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
#define FLASH_RMVER_VER_S 8
#define FLASH_RMVER_REV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USECRL register.
@ -323,6 +379,13 @@
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the FLASH register offsets.
//
//*****************************************************************************
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FMC
@ -360,6 +423,28 @@
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_RMVER
// register.
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
// DriverLib
#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
0x03000000 // Stellaris Boot Loader &
// DriverLib with AES and SAFERTOS
#define FLASH_RMVER_CONT_LM_AES2 \
0x05000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
#define FLASH_RMVER_VER_S 8
#define FLASH_RMVER_REV_S 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_USECRL

461
bsp/lm3s8962/Libraries/inc/hw_gpio.h
View File

@ -2,7 +2,7 @@
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -52,6 +52,9 @@
#define GPIO_O_CR 0x00000524 // GPIO Commit
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
//*****************************************************************************
//
@ -70,460 +73,10 @@
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port A.
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2
#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3
#define GPIO_PCTL_PA3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PA3
#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4
#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5
#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6
#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6
#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6
#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7
#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7
#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port B.
//
//*****************************************************************************
#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0
#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0
#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1
#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1
#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2
#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2
#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2
#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3
#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3
#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4
#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4
#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4
#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5
#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5
#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5
#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5
#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5
#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6
#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6
#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port C.
//
//*****************************************************************************
#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4
#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4
#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4
#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4
#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4
#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4
#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5
#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5
#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5
#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5
#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5
#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6
#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6
#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6
#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6
#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6
#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7
#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port D.
//
//*****************************************************************************
#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0
#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0
#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0
#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0
#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1
#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1
#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1
#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1
#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2
#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2
#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2
#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2
#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2
#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3
#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3
#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3
#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3
#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4
#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4
#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4
#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5
#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5
#define GPIO_PCTL_PD5_I2S0RXMCLK \
0x00800000 // I2S0RXMCLK on PD5
#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5
#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6
#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port E.
//
//*****************************************************************************
#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0
#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0
#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0
#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1
#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1
#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1
#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1
#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2
#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2
#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2
#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3
#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3
#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3
#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4
#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4
#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6
#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7
#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port F.
//
//*****************************************************************************
#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0
#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1
#define GPIO_PCTL_PF1_I2S0TXMCLK \
0x00000080 // I2S0TXMCLK on PF1
#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2
#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2
#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2
#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3
#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3
#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4
#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4
#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5
#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5
#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6
#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6
#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
#define GPIO_PCTL_PF6_I2S0TXMCLK \
0x09000000 // I2S0TXMCLK on PF6
#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7
#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port G.
//
//*****************************************************************************
#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0
#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0
#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0
#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1
#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1
#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1
#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2
#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2
#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3
#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3
#define GPIO_PCTL_PG3_I2S0RXMCLK \
0x00009000 // I2S0RXMCLK on PG3
#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4
#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4
#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4
#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4
#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5
#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5
#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5
#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6
#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7
#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port H.
//
//*****************************************************************************
#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0
#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0
#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0
#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1
#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1
#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2
#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3
#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4
#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5
#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6
#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7
#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_PCTL register for
// port J.
//
//*****************************************************************************
#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0
#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1
#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2
#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3
#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3
#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3
#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4
#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4
#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4
#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5
#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5
#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5
#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6
#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6
#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6
#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7
#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
//*****************************************************************************
//

34
bsp/lm3s8962/Libraries/inc/hw_hibernate.h
View File

@ -2,7 +2,7 @@
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -41,6 +41,7 @@
// Status
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
#define HIB_DATA 0x400FC030 // Hibernation Data
//*****************************************************************************
@ -81,6 +82,17 @@
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
#define HIB_CTL_OSCHYS 0x00040000 // 32
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
// Comparator
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
@ -96,6 +108,8 @@
// The following are defines for the bit fields in the HIB_IM register.
//
//*****************************************************************************
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
// Interrupt Mask
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Mask
@ -107,6 +121,8 @@
// The following are defines for the bit fields in the HIB_RIS register.
//
//*****************************************************************************
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
// Interrupt Status
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
// Status
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
@ -119,6 +135,8 @@
// The following are defines for the bit fields in the HIB_MIS register.
//
//*****************************************************************************
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Status
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Status
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
@ -133,6 +151,8 @@
// The following are defines for the bit fields in the HIB_IC register.
//
//*****************************************************************************
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Clear
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Clear
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
@ -150,6 +170,16 @@
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCSS register.
//
//*****************************************************************************
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
#define HIB_RTCSS_RTCSSM_S 16
#define HIB_RTCSS_RTCSSC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_DATA register.

62
bsp/lm3s8962/Libraries/inc/hw_i2c.h
View File

@ -2,7 +2,7 @@
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -47,7 +47,13 @@
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
#define I2C_O_SACKCTL 0x00000020 // I2C ACK Control
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
// Count
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
//*****************************************************************************
//
@ -71,6 +77,9 @@
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
@ -81,9 +90,12 @@
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_QCMD 0x00000020 // Quick Command
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
@ -142,6 +154,7 @@
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Interrupt Mask
//*****************************************************************************
@ -149,6 +162,8 @@
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status
//*****************************************************************************
@ -176,6 +191,8 @@
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
@ -183,8 +200,18 @@
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//*****************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
@ -194,6 +221,37 @@
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//*****************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//*****************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//*****************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//*****************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//*****************************************************************************
//
// The following definitions are deprecated.

4
bsp/lm3s8962/Libraries/inc/hw_i2s.h
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@ -2,7 +2,7 @@
//
// hw_i2s.h - Macros for use in accessing the I2S registers.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

77
bsp/lm3s8962/Libraries/inc/hw_ints.h
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@ -2,7 +2,7 @@
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -54,10 +54,10 @@
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_PWM0_FAULT 25 // PWM0 Fault
#define INT_PWM0_0 26 // PWM0 Generator 0
#define INT_PWM0_1 27 // PWM0 Generator 1
#define INT_PWM0_2 28 // PWM0 Generator 2
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0SS0 30 // ADC0 Sequence 0
#define INT_ADC0SS1 31 // ADC0 Sequence 1
@ -90,7 +90,7 @@
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
#define INT_USB0 60 // USB 0 Controller
#define INT_PWM3 61 // PWM Generator 3
#define INT_PWM0_3 61 // PWM0 Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_ADC1SS0 64 // ADC1 Sequence 0
@ -100,13 +100,69 @@
#define INT_I2S0 68 // I2S0
#define INT_EPI0 69 // EPI0
#define INT_GPIOJ 70 // GPIO Port J
#define INT_GPIOK 71 // GPIO Port K
#define INT_GPIOL 72 // GPIO Port L
#define INT_SSI2 73 // SSI2
#define INT_SSI3 74 // SSI3
#define INT_UART3 75 // UART3
#define INT_UART4 76 // UART4
#define INT_UART5 77 // UART5
#define INT_UART6 78 // UART6
#define INT_UART7 79 // UART7
#define INT_I2C2 84 // I2C2
#define INT_I2C3 85 // I2C3
#define INT_TIMER4A 86 // Timer 4A
#define INT_TIMER4B 87 // Timer 4B
#define INT_TIMER5A 108 // Timer 5A
#define INT_TIMER5B 109 // Timer 5B
#define INT_WTIMER0A 110 // Wide Timer 0A
#define INT_WTIMER0B 111 // Wide Timer 0B
#define INT_WTIMER1A 112 // Wide Timer 1A
#define INT_WTIMER1B 113 // Wide Timer 1B
#define INT_WTIMER2A 114 // Wide Timer 2A
#define INT_WTIMER2B 115 // Wide Timer 2B
#define INT_WTIMER3A 116 // Wide Timer 3A
#define INT_WTIMER3B 117 // Wide Timer 3B
#define INT_WTIMER4A 118 // Wide Timer 4A
#define INT_WTIMER4B 119 // Wide Timer 4B
#define INT_WTIMER5A 120 // Wide Timer 5A
#define INT_WTIMER5B 121 // Wide Timer 5B
#define INT_SYSEXC 122 // System Exception (imprecise)
#define INT_PECI0 123 // PECI 0
#define INT_LPC0 124 // LPC 0
#define INT_I2C4 125 // I2C4
#define INT_I2C5 126 // I2C5
#define INT_GPIOM 127 // GPIO Port M
#define INT_GPION 128 // GPIO Port N
#define INT_FAN0 130 // FAN 0
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
#define INT_GPIOP1 133 // GPIO Port P1
#define INT_GPIOP2 134 // GPIO Port P2
#define INT_GPIOP3 135 // GPIO Port P3
#define INT_GPIOP4 136 // GPIO Port P4
#define INT_GPIOP5 137 // GPIO Port P5
#define INT_GPIOP6 138 // GPIO Port P6
#define INT_GPIOP7 139 // GPIO Port P7
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1 141 // GPIO Port Q1
#define INT_GPIOQ2 142 // GPIO Port Q2
#define INT_GPIOQ3 143 // GPIO Port Q3
#define INT_GPIOQ4 144 // GPIO Port Q4
#define INT_GPIOQ5 145 // GPIO Port Q5
#define INT_GPIOQ6 146 // GPIO Port Q6
#define INT_GPIOQ7 147 // GPIO Port Q7
#define INT_PWM1_0 150 // PWM1 Generator 0
#define INT_PWM1_1 151 // PWM1 Generator 1
#define INT_PWM1_2 152 // PWM1 Generator 2
#define INT_PWM1_3 153 // PWM1 Generator 3
#define INT_PWM1_FAULT 154 // PWM1 Fault
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 71
#define NUM_INTERRUPTS 155
//*****************************************************************************
//
@ -130,11 +186,16 @@
//*****************************************************************************
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_PWM3 61 // PWM Generator 3
#endif

974
bsp/lm3s8962/Libraries/inc/hw_lpc.h Normal file
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@ -0,0 +1,974 @@
//*****************************************************************************
//
// hw_lpc.h - Macros used when accessing the LPC hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_LPC_H__
#define __HW_LPC_H__
//*****************************************************************************
//
// The following are defines for the LPC register addresses.
//
//*****************************************************************************
#define LPC_O_CTL 0x00000000 // LPC Control
#define LPC_O_STS 0x00000004 // LPC Status
#define LPC_O_IRQCTL 0x00000008 // LPC IRQ Control
#define LPC_O_IRQST 0x0000000C // LPC IRQ Status
#define LPC_O_CH0CTL 0x00000010 // LPC Channel 0 Control
#define LPC_O_CH0ST 0x00000014 // LPC Channel 0 Status
#define LPC_O_CH0ADR 0x00000018 // LPC Channel 0 Address
#define LPC_O_CH1CTL 0x00000020 // LPC Channel 1 Control
#define LPC_O_CH1ST 0x00000024 // LPC Channel 1 Status
#define LPC_O_CH1ADR 0x00000028 // LPC Channel 1 Address
#define LPC_O_CH2CTL 0x00000030 // LPC Channel 2 Control
#define LPC_O_CH2ST 0x00000034 // LPC Channel 2 Status
#define LPC_O_CH2ADR 0x00000038 // LPC Channel 2 Address
#define LPC_O_CH3CTL 0x00000040 // LPC Channel 3 Control
#define LPC_O_CH3ST 0x00000044 // LPC Channel 3 Status
#define LPC_O_CH3ADR 0x00000048 // LPC Channel 3 Address
#define LPC_O_CH4CTL 0x00000050 // LPC Channel 4 Control
#define LPC_O_CH4ST 0x00000054 // LPC Channel 4 Status
#define LPC_O_CH4ADR 0x00000058 // LPC Channel 4 Address
#define LPC_O_CH5CTL 0x00000060 // LPC Channel 5 Control
#define LPC_O_CH5ST 0x00000064 // LPC Channel 5 Status
#define LPC_O_CH5ADR 0x00000068 // LPC Channel 5 Address
#define LPC_O_CH6CTL 0x00000070 // LPC Channel 6 Control
#define LPC_O_CH6ST 0x00000074 // LPC Channel 6 Status
#define LPC_O_CH6ADR 0x00000078 // LPC Channel 6 Address
#define LPC_O_CH7CTL 0x00000080 // LPC Channel 7 / COMx Control
#define LPC_O_CH7ST 0x00000084 // LPC Channel 7 / COMx Status
#define LPC_O_CH7ADR 0x00000088 // LPC Channel 7 / COMx Address
#define LPC_O_STSADDR 0x000000A0 // LPC Status Block Address
#define LPC_O_IM 0x00000100 // LPC Interrupt Mask
#define LPC_O_RIS 0x00000104 // LPC Raw Interrupt Status
#define LPC_O_MIS 0x00000108 // LPC Masked Interrupt Status
#define LPC_O_IC 0x0000010C // LPC Interrupt Clear
#define LPC_O_DMACX 0x00000120 // LPC DMA and COMx Control
#define LPC_O_POOL 0x00000400 // LPC Register Pool
#define LPC_O_PP 0x00000FC0 // LPC Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CTL register.
//
//*****************************************************************************
#define LPC_CTL_SCICNT_M 0x00000C00 // LPC0SCI Pulse Length
#define LPC_CTL_SCICNT_0 0x00000000 // No pulse occurs on the LPC0SCI
// pin
#define LPC_CTL_SCICNT_2 0x00000400 // The pulse on the LPC0SCI pin is
// 2 LPC0CLK periods
#define LPC_CTL_SCICNT_4 0x00000800 // The pulse on the LPC0SCI pin is
// 4 LPC0CLK periods
#define LPC_CTL_SCICNT_8 0x00000C00 // The pulse on the LPC0SCI pin is
// 8 LPC0CLK periods
#define LPC_CTL_SCI 0x00000200 // Start SCI Pulse
#define LPC_CTL_WAKE 0x00000100 // Restart the LPC Bus
#define LPC_CTL_CE7 0x00000080 // Enable Channel 7
#define LPC_CTL_CE6 0x00000040 // Enable Channel 6
#define LPC_CTL_CE5 0x00000020 // Enable Channel 5
#define LPC_CTL_CE4 0x00000010 // Enable Channel 4
#define LPC_CTL_CE3 0x00000008 // Enable Channel 3
#define LPC_CTL_CE2 0x00000004 // Enable Channel 2
#define LPC_CTL_CE1 0x00000002 // Enable Channel 1
#define LPC_CTL_CE0 0x00000001 // Enable Channel 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_STS register.
//
//*****************************************************************************
#define LPC_STS_CHCNT_M 0x00700000 // Number of Channels
#define LPC_STS_POOLSZ_M 0x00070000 // Register Pool Size
#define LPC_STS_POOLSZ_256 0x00010000 // 256 bytes
#define LPC_STS_POOLSZ_512 0x00020000 // 512 bytes
#define LPC_STS_POOLSZ_768 0x00030000 // 768 bytes
#define LPC_STS_POOLSZ_1024 0x00040000 // 1024 bytes
#define LPC_STS_RST 0x00000400 // LPC is in Reset
#define LPC_STS_BUSY 0x00000200 // LPC is Busy
#define LPC_STS_SLEEP 0x00000100 // LPC is in Sleep Mode
#define LPC_STS_CA7 0x00000080 // Channel 7 Active
#define LPC_STS_CA6 0x00000040 // Channel 6 Active
#define LPC_STS_CA5 0x00000020 // Channel 5 Active
#define LPC_STS_CA4 0x00000010 // Channel 4 Active
#define LPC_STS_CA3 0x00000008 // Channel 3 Active
#define LPC_STS_CA2 0x00000004 // Channel 2 Active
#define LPC_STS_CA1 0x00000002 // Channel 1 Active
#define LPC_STS_CA0 0x00000001 // Channel 0 Active
#define LPC_STS_CHCNT_S 20
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IRQCTL register.
//
//*****************************************************************************
#define LPC_IRQCTL_I15 0x80000000 // Manual IRQ15 State
#define LPC_IRQCTL_I14 0x40000000 // Manual IRQ14 State
#define LPC_IRQCTL_I13 0x20000000 // Manual IRQ13 State
#define LPC_IRQCTL_I12 0x10000000 // Manual IRQ12 State
#define LPC_IRQCTL_I11 0x08000000 // Manual IRQ11 State
#define LPC_IRQCTL_I10 0x04000000 // Manual IRQ10 State
#define LPC_IRQCTL_I9 0x02000000 // Manual IRQ9 State
#define LPC_IRQCTL_I8 0x01000000 // Manual IRQ8 State
#define LPC_IRQCTL_I7 0x00800000 // Manual IRQ7 State
#define LPC_IRQCTL_I6 0x00400000 // Manual IRQ6 State
#define LPC_IRQCTL_I5 0x00200000 // Manual IRQ5 State
#define LPC_IRQCTL_I4 0x00100000 // Manual IRQ4 State
#define LPC_IRQCTL_I3 0x00080000 // Manual IRQ3 State
#define LPC_IRQCTL_I2 0x00040000 // Manual IRQ2 State
#define LPC_IRQCTL_I1 0x00020000 // Manual IRQ1 State
#define LPC_IRQCTL_AH 0x00010000 // Active High Control
#define LPC_IRQCTL_PULSE 0x00000004 // Pulse IRQ States
#define LPC_IRQCTL_ONCHG 0x00000002 // Initiate on Change
#define LPC_IRQCTL_SND 0x00000001 // Initiate Immediately
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IRQST register.
//
//*****************************************************************************
#define LPC_IRQST_I15 0x80000000 // Host IRQ15 State
#define LPC_IRQST_I14 0x40000000 // IRQ14 State
#define LPC_IRQST_I13 0x20000000 // IRQ13 State
#define LPC_IRQST_I12 0x10000000 // IRQ12 State
#define LPC_IRQST_I11 0x08000000 // IRQ11 State
#define LPC_IRQST_I10 0x04000000 // IRQ10 State
#define LPC_IRQST_I9 0x02000000 // IRQ9 State
#define LPC_IRQST_I8 0x01000000 // IRQ8 State
#define LPC_IRQST_I7 0x00800000 // IRQ7 State
#define LPC_IRQST_I6 0x00400000 // IRQ6 State
#define LPC_IRQST_I5 0x00200000 // IRQ5 State
#define LPC_IRQST_I4 0x00100000 // IRQ4 State
#define LPC_IRQST_I3 0x00080000 // IRQ3 State
#define LPC_IRQST_I2 0x00040000 // IRQ2 State
#define LPC_IRQST_I1 0x00020000 // IRQ1 State
#define LPC_IRQST_I0 0x00010000 // IRQ0 State
#define LPC_IRQST_SIRQ 0x00000004 // Pulse IRQ States
#define LPC_IRQST_CONT 0x00000001 // Initiate Immediately
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0CTL register.
//
//*****************************************************************************
#define LPC_CH0CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH0CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH0CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH0CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH0CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH0CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH0CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH0CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH0CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH0CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH0CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH0CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH0CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH0CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH0CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH0CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH0CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH0CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH0CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH0CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH0CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH0CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH0CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH0CTL_IRQSEL2_S 28
#define LPC_CH0CTL_IRQSEL1_S 24
#define LPC_CH0CTL_IRQSEL0_S 20
#define LPC_CH0CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0ST register.
//
//*****************************************************************************
#define LPC_CH0ST_USER_M 0x00001F00 // User Data
#define LPC_CH0ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH0ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH0ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH0ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH0ST_CMD 0x00000008 // Command or Data
#define LPC_CH0ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH0ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH0ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0ADR register.
//
//*****************************************************************************
#define LPC_CH0ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH0ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH0ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH0ADR_ADDRH_S 16
#define LPC_CH0ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1CTL register.
//
//*****************************************************************************
#define LPC_CH1CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH1CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH1CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH1CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH1CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH1CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH1CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH1CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH1CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH1CTL_IRQEN0_TRGI2 0x00020000 // Trigger 2
#define LPC_CH1CTL_IRQEN0_TRGI3 0x00030000 // Trigger 3
#define LPC_CH1CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH1CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH1CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH1CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH1CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH1CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH1CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH1CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH1CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH1CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH1CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH1CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH1CTL_IRQSEL2_S 28
#define LPC_CH1CTL_IRQSEL1_S 24
#define LPC_CH1CTL_IRQSEL0_S 20
#define LPC_CH1CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1ST register.
//
//*****************************************************************************
#define LPC_CH1ST_USER_M 0x00001F00 // User Data
#define LPC_CH1ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH1ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH1ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH1ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH1ST_CMD 0x00000008 // Command or Data
#define LPC_CH1ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH1ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH1ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1ADR register.
//
//*****************************************************************************
#define LPC_CH1ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH1ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH1ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH1ADR_ADDRH_S 16
#define LPC_CH1ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2CTL register.
//
//*****************************************************************************
#define LPC_CH2CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH2CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH2CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH2CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH2CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH2CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH2CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH2CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH2CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH2CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH2CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH2CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH2CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH2CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH2CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH2CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH2CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH2CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH2CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH2CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH2CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH2CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH2CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH2CTL_IRQSEL2_S 28
#define LPC_CH2CTL_IRQSEL1_S 24
#define LPC_CH2CTL_IRQSEL0_S 20
#define LPC_CH2CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2ST register.
//
//*****************************************************************************
#define LPC_CH2ST_USER_M 0x00001F00 // User Data
#define LPC_CH2ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH2ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH2ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH2ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH2ST_CMD 0x00000008 // Command or Data
#define LPC_CH2ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH2ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH2ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2ADR register.
//
//*****************************************************************************
#define LPC_CH2ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH2ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH2ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH2ADR_ADDRH_S 16
#define LPC_CH2ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3CTL register.
//
//*****************************************************************************
#define LPC_CH3CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH3CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH3CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH3CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH3CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH3CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH3CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH3CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH3CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH3CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH3CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH3CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH3CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH3CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH3CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH3CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH3CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH3CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH3CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH3CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH3CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH3CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH3CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH3CTL_IRQSEL2_S 28
#define LPC_CH3CTL_IRQSEL1_S 24
#define LPC_CH3CTL_IRQSEL0_S 20
#define LPC_CH3CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3ST register.
//
//*****************************************************************************
#define LPC_CH3ST_USER_M 0x00001F00 // User Data
#define LPC_CH3ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH3ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH3ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH3ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH3ST_CMD 0x00000008 // Command or Data
#define LPC_CH3ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH3ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH3ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3ADR register.
//
//*****************************************************************************
#define LPC_CH3ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH3ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH3ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH3ADR_ADDRH_S 16
#define LPC_CH3ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4CTL register.
//
//*****************************************************************************
#define LPC_CH4CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH4CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH4CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH4CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH4CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH4CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH4CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH4CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH4CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH4CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH4CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH4CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH4CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH4CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH4CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH4CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH4CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH4CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH4CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH4CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH4CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH4CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH4CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH4CTL_IRQSEL2_S 28
#define LPC_CH4CTL_IRQSEL1_S 24
#define LPC_CH4CTL_IRQSEL0_S 20
#define LPC_CH4CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4ST register.
//
//*****************************************************************************
#define LPC_CH4ST_USER_M 0x00001F00 // User Data
#define LPC_CH4ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH4ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH4ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH4ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH4ST_CMD 0x00000008 // Command or Data
#define LPC_CH4ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH4ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH4ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4ADR register.
//
//*****************************************************************************
#define LPC_CH4ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH4ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH4ADR_ADDRH_S 16
#define LPC_CH4ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5CTL register.
//
//*****************************************************************************
#define LPC_CH5CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH5CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH5CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH5CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH5CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH5CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH5CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH5CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH5CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH5CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH5CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH5CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH5CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH5CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH5CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH5CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH5CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH5CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH5CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH5CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH5CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH5CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH5CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH5CTL_IRQSEL2_S 28
#define LPC_CH5CTL_IRQSEL1_S 24
#define LPC_CH5CTL_IRQSEL0_S 20
#define LPC_CH5CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5ST register.
//
//*****************************************************************************
#define LPC_CH5ST_USER_M 0x00001F00 // User Data
#define LPC_CH5ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH5ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH5ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH5ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH5ST_CMD 0x00000008 // Command or Data
#define LPC_CH5ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH5ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH5ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5ADR register.
//
//*****************************************************************************
#define LPC_CH5ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH5ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH5ADR_ADDRH_S 16
#define LPC_CH5ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6CTL register.
//
//*****************************************************************************
#define LPC_CH6CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH6CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH6CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH6CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH6CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH6CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH6CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH6CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH6CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH6CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH6CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH6CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH6CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH6CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH6CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH6CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH6CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH6CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH6CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH6CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH6CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH6CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH6CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH6CTL_IRQSEL2_S 28
#define LPC_CH6CTL_IRQSEL1_S 24
#define LPC_CH6CTL_IRQSEL0_S 20
#define LPC_CH6CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6ST register.
//
//*****************************************************************************
#define LPC_CH6ST_USER_M 0x00001F00 // User Data
#define LPC_CH6ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH6ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH6ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH6ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH6ST_CMD 0x00000008 // Command or Data
#define LPC_CH6ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH6ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH6ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6ADR register.
//
//*****************************************************************************
#define LPC_CH6ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH6ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH6ADR_ADDRH_S 16
#define LPC_CH6ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7CTL register.
//
//*****************************************************************************
#define LPC_CH7CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH7CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH7CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH7CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH7CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH7CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH7CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH7CTL_IRQEN0_AUTO 0x00000000 // The automatic IRQ trigger is
// disabled
#define LPC_CH7CTL_IRQEN0_MST 0x00010000 // If TYPE is set, the IRQ selected
// by IRQSEL0 is triggered when the
// master wins arbitration (the
// HW1ST bit is set)
#define LPC_CH7CTL_IRQEN0_SLV 0x00020000 // If TYPE is set, the IRQ selected
// by IRQSEL0 is triggered when the
// slave wins arbitration (the
// SW1ST bit is set)
#define LPC_CH7CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH7CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH7CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH7CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH7CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH7CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH7CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH7CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH7CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH7CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH7CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH7CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH7CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH7CTL_IRQSEL2_S 28
#define LPC_CH7CTL_IRQSEL1_S 24
#define LPC_CH7CTL_IRQSEL0_S 20
#define LPC_CH7CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7ST register.
//
//*****************************************************************************
#define LPC_CH7ST_USER_M 0x00001F00 // User Data
#define LPC_CH7ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH7ST_HW1ST 0x00000040 // Host Wrote First
#define LPC_CH7ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH7ST_SW1ST 0x00000010 // Slave Wrote First
#define LPC_CH7ST_CMD 0x00000008 // Command or Data
#define LPC_CH7ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH7ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH7ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7ADR register.
//
//*****************************************************************************
#define LPC_CH7ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH7ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH7ADR_ADDRH_S 16
#define LPC_CH7ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_STSADDR register.
//
//*****************************************************************************
#define LPC_STSADDR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_STSADDR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_STSADDR_ENA 0x00000001 // Enable Status Block
#define LPC_STSADDR_ADDRH_S 16
#define LPC_STSADDR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IM register.
//
//*****************************************************************************
#define LPC_IM_RSTIM 0x80000000 // Reset State Interrupt Mask
#define LPC_IM_SLEEPIM 0x40000000 // Sleep State Interrupt Mask
#define LPC_IM_COMXIM 0x20000000 // COMx Interrupt Mask
#define LPC_IM_SIRQIM 0x10000000 // SERIRQ Frame Complete Interrupt
// Mask
#define LPC_IM_CH6IM3 0x08000000 // Channel 6 Interrupt Mask 3
#define LPC_IM_CH6IM2 0x04000000 // Channel 6 Interrupt Mask 2
#define LPC_IM_CH6IM1 0x02000000 // Channel 6 Interrupt Mask 1
#define LPC_IM_CH6IM0 0x01000000 // Channel 6 Interrupt Mask 0
#define LPC_IM_CH5IM3 0x00800000 // Channel 5 Interrupt Mask 3
#define LPC_IM_CH5IM2 0x00400000 // Channel 5 Interrupt Mask 2
#define LPC_IM_CH5IM1 0x00200000 // Channel 5 Interrupt Mask 1
#define LPC_IM_CH5IM0 0x00100000 // Channel 5 Interrupt Mask 0
#define LPC_IM_CH4IM3 0x00080000 // Channel 4 Interrupt Mask 3
#define LPC_IM_CH4IM2 0x00040000 // Channel 4 Interrupt Mask 2
#define LPC_IM_CH4IM1 0x00020000 // Channel 4 Interrupt Mask 1
#define LPC_IM_CH4IM0 0x00010000 // Channel 4 Interrupt Mask 0
#define LPC_IM_CH3IM3 0x00008000 // Channel 3 Interrupt Mask 3
#define LPC_IM_CH3IM2 0x00004000 // Channel 3 Interrupt Mask 2
#define LPC_IM_CH3IM1 0x00002000 // Channel 3 Interrupt Mask 1
#define LPC_IM_CH3IM0 0x00001000 // Channel 3 Interrupt Mask 0
#define LPC_IM_CH2IM3 0x00000800 // Channel 2 Interrupt Mask 3
#define LPC_IM_CH2IM2 0x00000400 // Channel 2 Interrupt Mask 2
#define LPC_IM_CH2IM1 0x00000200 // Channel 2 Interrupt Mask 1
#define LPC_IM_CH2IM0 0x00000100 // Channel 2 Interrupt Mask 0
#define LPC_IM_CH1IM3 0x00000080 // Channel 1 Interrupt Mask 3
#define LPC_IM_CH1IM2 0x00000040 // Channel 1 Interrupt Mask 2
#define LPC_IM_CH1IM1 0x00000020 // Channel 1 Interrupt Mask 1
#define LPC_IM_CH1IM0 0x00000010 // Channel 1 Interrupt Mask 0
#define LPC_IM_CH0IM3 0x00000008 // Channel 0 Interrupt Mask 3
#define LPC_IM_CH0IM2 0x00000004 // Channel 0 Interrupt Mask 2
#define LPC_IM_CH0IM1 0x00000002 // Channel 0 Interrupt Mask 1
#define LPC_IM_CH0IM0 0x00000001 // Channel 0 Interrupt Mask 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_RIS register.
//
//*****************************************************************************
#define LPC_RIS_RSTRIS 0x80000000 // Reset State Raw Interrupt Status
#define LPC_RIS_SLEEPRIS 0x40000000 // Sleep State Raw Interrupt Status
#define LPC_RIS_COMXRIS 0x20000000 // COMx Raw Interrupt Status
#define LPC_RIS_SIRQRIS 0x10000000 // SERIRQ Frame Complete Raw
// Interrupt Status
#define LPC_RIS_CH6RIS3 0x08000000 // Channel 6 Raw Interrupt Status 3
#define LPC_RIS_CH6RIS2 0x04000000 // Channel 6 Raw Interrupt Status 2
#define LPC_RIS_CH6RIS1 0x02000000 // Channel 6 Raw Interrupt Status 1
#define LPC_RIS_CH6RIS0 0x01000000 // Channel 6 Raw Interrupt Status 0
#define LPC_RIS_CH5RIS3 0x00800000 // Channel 5 Raw Interrupt Status 3
#define LPC_RIS_CH5RIS2 0x00400000 // Channel 5 Raw Interrupt Status 2
#define LPC_RIS_CH5RIS1 0x00200000 // Channel 5 Raw Interrupt Status 1
#define LPC_RIS_CH5RIS0 0x00100000 // Channel 5 Raw Interrupt Status 0
#define LPC_RIS_CH4RIS3 0x00080000 // Channel 4 Raw Interrupt Status 3
#define LPC_RIS_CH4RIS2 0x00040000 // Channel 4 Raw Interrupt Status 2
#define LPC_RIS_CH4RIS1 0x00020000 // Channel 4 Raw Interrupt Status 1
#define LPC_RIS_CH4RIS0 0x00010000 // Channel 4 Raw Interrupt Status 0
#define LPC_RIS_CH3RIS3 0x00008000 // Channel 3 Raw Interrupt Status 3
#define LPC_RIS_CH3RIS2 0x00004000 // Channel 3 Raw Interrupt Status 2
#define LPC_RIS_CH3RIS1 0x00002000 // Channel 3 Raw Interrupt Status 1
#define LPC_RIS_CH3RIS0 0x00001000 // Channel 3 Raw Interrupt Status 0
#define LPC_RIS_CH2RIS3 0x00000800 // Channel 2 Raw Interrupt Status 3
#define LPC_RIS_CH2RIS2 0x00000400 // Channel 2 Raw Interrupt Status 2
#define LPC_RIS_CH2RIS1 0x00000200 // Channel 2 Raw Interrupt Status 1
#define LPC_RIS_CH2RIS0 0x00000100 // Channel 2 Raw Interrupt Status 0
#define LPC_RIS_CH1RIS3 0x00000080 // Channel 1 Raw Interrupt Status 3
#define LPC_RIS_CH1RIS2 0x00000040 // Channel 1 Raw Interrupt Status 2
#define LPC_RIS_CH1RIS1 0x00000020 // Channel 1 Raw Interrupt Status 1
#define LPC_RIS_CH1RIS0 0x00000010 // Channel 1 Raw Interrupt Status 0
#define LPC_RIS_CH0RIS3 0x00000008 // Channel 0 Raw Interrupt Status 3
#define LPC_RIS_CH0RIS2 0x00000004 // Channel 0 Raw Interrupt Status 2
#define LPC_RIS_CH0RIS1 0x00000002 // Channel 0 Raw Interrupt Status 1
#define LPC_RIS_CH0RIS0 0x00000001 // Channel 0 Raw Interrupt Status 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_MIS register.
//
//*****************************************************************************
#define LPC_MIS_RSTMIS 0x80000000 // Reset State Masked Interrupt
// Status
#define LPC_MIS_SLEEPMIS 0x40000000 // Sleep State Masked Interrupt
// Status
#define LPC_MIS_COMXMIS 0x20000000 // COMx Masked Interrupt Status
#define LPC_MIS_SIRQMIS 0x10000000 // SERIRQ Frame Complete Masked
// Interrupt Status
#define LPC_MIS_CH6MIS3 0x08000000 // Channel 6 Masked Interrupt
// Status 3
#define LPC_MIS_CH6MIS2 0x04000000 // Channel 6 Masked Interrupt
// Status 2
#define LPC_MIS_CH6MIS1 0x02000000 // Channel 6 Masked Interrupt
// Status 1
#define LPC_MIS_CH6MIS0 0x01000000 // Channel 6 Masked Interrupt
// Status 0
#define LPC_MIS_CH5MIS3 0x00800000 // Channel 5 Masked Interrupt
// Status 3
#define LPC_MIS_CH5MIS2 0x00400000 // Channel 5 Masked Interrupt
// Status 2
#define LPC_MIS_CH5MIS1 0x00200000 // Channel 5 Masked Interrupt
// Status 1
#define LPC_MIS_CH5MIS0 0x00100000 // Channel 5 Masked Interrupt
// Status 0
#define LPC_MIS_CH4MIS3 0x00080000 // Channel 4 Masked Interrupt
// Status 3
#define LPC_MIS_CH4MIS2 0x00040000 // Channel 4 Masked Interrupt
// Status 2
#define LPC_MIS_CH4MIS1 0x00020000 // Channel 4 Masked Interrupt
// Status 1
#define LPC_MIS_CH4MIS0 0x00010000 // Channel 4 Masked Interrupt
// Status 0
#define LPC_MIS_CH3MIS3 0x00008000 // Channel 3 Masked Interrupt
// Status 3
#define LPC_MIS_CH3MIS2 0x00004000 // Channel 3 Masked Interrupt
// Status 2
#define LPC_MIS_CH3MIS1 0x00002000 // Channel 3 Masked Interrupt
// Status 1
#define LPC_MIS_CH3MIS0 0x00001000 // Channel 3 Masked Interrupt
// Status 0
#define LPC_MIS_CH2MIS3 0x00000800 // Channel 2 Masked Interrupt
// Status 3
#define LPC_MIS_CH2MIS2 0x00000400 // Channel 2 Masked Interrupt
// Status 2
#define LPC_MIS_CH2MIS1 0x00000200 // Channel 2 Masked Interrupt
// Status 1
#define LPC_MIS_CH2MIS0 0x00000100 // Channel 2 Masked Interrupt
// Status 0
#define LPC_MIS_CH1MIS3 0x00000080 // Channel 1 Masked Interrupt
// Status 3
#define LPC_MIS_CH1MIS2 0x00000040 // Channel 1 Masked Interrupt
// Status 2
#define LPC_MIS_CH1MIS1 0x00000020 // Channel 1 Masked Interrupt
// Status 1
#define LPC_MIS_CH1MIS0 0x00000010 // Channel 1 Masked Interrupt
// Status 0
#define LPC_MIS_CH0MIS3 0x00000008 // Channel 0 Masked Interrupt
// Status 3
#define LPC_MIS_CH0MIS2 0x00000004 // Channel 0 Masked Interrupt
// Status 2
#define LPC_MIS_CH0MIS1 0x00000002 // Channel 0 Masked Interrupt
// Status 1
#define LPC_MIS_CH0MIS0 0x00000001 // Channel 0 Masked Interrupt
// Status 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IC register.
//
//*****************************************************************************
#define LPC_IC_RSTIC 0x80000000 // Reset State Interrupt Clear
#define LPC_IC_SLEEPIC 0x40000000 // Sleep State Interrupt Clear
#define LPC_IC_COMXIC 0x20000000 // COMx Interrupt Clear
#define LPC_IC_SIRQRIC 0x10000000 // SERIRQ Frame Complete Interrupt
// Clear
#define LPC_IC_CH6IC3 0x08000000 // Channel 6 Interrupt Clear 3
#define LPC_IC_CH6IC2 0x04000000 // Channel 6 Interrupt Clear 2
#define LPC_IC_CH6IC1 0x02000000 // Channel 6 Interrupt Clear 1
#define LPC_IC_CH6IC0 0x01000000 // Channel 6 Interrupt Clear 0
#define LPC_IC_CH5IC3 0x00800000 // Channel 5 Interrupt Clear 3
#define LPC_IC_CH5IC2 0x00400000 // Channel 5 Interrupt Clear 2
#define LPC_IC_CH5IC1 0x00200000 // Channel 5 Interrupt Clear 1
#define LPC_IC_CH5IC0 0x00100000 // Channel 5 Interrupt Clear 0
#define LPC_IC_CH4IC3 0x00080000 // Channel 4 Interrupt Clear 3
#define LPC_IC_CH4IC2 0x00040000 // Channel 4 Interrupt Clear 2
#define LPC_IC_CH4IC1 0x00020000 // Channel 4 Interrupt Clear 1
#define LPC_IC_CH4IC0 0x00010000 // Channel 4 Interrupt Clear 0
#define LPC_IC_CH3IC3 0x00008000 // Channel 3 Interrupt Clear 3
#define LPC_IC_CH3IC2 0x00004000 // Channel 3 Interrupt Clear 2
#define LPC_IC_CH3IC1 0x00002000 // Channel 3 Interrupt Clear 1
#define LPC_IC_CH3IC0 0x00001000 // Channel 3 Interrupt Clear 0
#define LPC_IC_CH2IC3 0x00000800 // Channel 2 Interrupt Clear 3
#define LPC_IC_CH2IC2 0x00000400 // Channel 2 Interrupt Clear 2
#define LPC_IC_CH2IC1 0x00000200 // Channel 2 Interrupt Clear 1
#define LPC_IC_CH2IC0 0x00000100 // Channel 2 Interrupt Clear 0
#define LPC_IC_CH1IC3 0x00000080 // Channel 1 Interrupt Clear 3
#define LPC_IC_CH1IC2 0x00000040 // Channel 1 Interrupt Clear 2
#define LPC_IC_CH1IC1 0x00000020 // Channel 1 Interrupt Clear 1
#define LPC_IC_CH1IC0 0x00000010 // Channel 1 Interrupt Clear 0
#define LPC_IC_CH0IC3 0x00000008 // Channel 0 Interrupt Clear 3
#define LPC_IC_CH0IC2 0x00000004 // Channel 0 Interrupt Clear 2
#define LPC_IC_CH0IC1 0x00000002 // Channel 0 Interrupt Clear 1
#define LPC_IC_CH0IC0 0x00000001 // Channel 0 Interrupt Clear 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_DMACX register.
//
//*****************************************************************************
#define LPC_DMACX_CXRES 0x02000000 // Raw Event State for COMx
#define LPC_DMACX_CXTXRES 0x01000000 // Raw Event State for COMx TX
#define LPC_DMACX_CXRXRES 0x00800000 // Raw Event State for COMx RX
#define LPC_DMACX_CXEM 0x00200000 // Event Mask for COMx
#define LPC_DMACX_CXTXEM 0x00100000 // Event Mask for COMx TX
#define LPC_DMACX_CXRXEM 0x00080000 // Event Mask for COMx RX
#define LPC_DMACX_CXACT_M 0x00060000 // COMx Action
#define LPC_DMACX_CXACT_FRMHNML 0x00000000 // Treat as normal FRMH model and
// let be full (and so marked as
// full)
#define LPC_DMACX_CXACT_FRMHIGN 0x00020000 // Ignore FRMH bytes and continue
// to mark FRMH as empty
#define LPC_DMACX_CXACT_FRMHDMA 0x00040000 // COMx DMA on FRMH byte (e.g. to
// memory)
#define LPC_DMACX_CXACT_UARTDMA 0x00060000 // COMx DMA model with UART
#define LPC_DMACX_COMX 0x00010000 // COMx Handling
#define LPC_DMACX_C3W 0x00000080 // Write Control for Channel 3
#define LPC_DMACX_C3R 0x00000040 // Read Control for Channel 3
#define LPC_DMACX_C2W 0x00000020 // Write Control for Channel 2
#define LPC_DMACX_C2R 0x00000010 // Read Control for Channel 2
#define LPC_DMACX_C1W 0x00000008 // Write Control for Channel 1
#define LPC_DMACX_C1R 0x00000004 // Read Control for Channel 1
#define LPC_DMACX_C0W 0x00000002 // Write Control for Channel 0
#define LPC_DMACX_C0R 0x00000001 // Read Control for Channel 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_POOL register.
//
//*****************************************************************************
#define LPC_POOL_BYTE3_M 0xFF000000 // Byte 3
#define LPC_POOL_BYTE2_M 0x00FF0000 // Byte 2
#define LPC_POOL_BYTE1_M 0x0000FF00 // Byte 1
#define LPC_POOL_BYTE0_M 0x000000FF // Byte 0
#define LPC_POOL_BYTE3_S 24
#define LPC_POOL_BYTE2_S 16
#define LPC_POOL_BYTE1_S 8
#define LPC_POOL_BYTE0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_PP register.
//
//*****************************************************************************
#define LPC_PP_COMX 0x00000010 // COMx Support Available
#define LPC_PP_CHANCNT_M 0x0000000F // Number of Channels (Excluding
// COMx)
#define LPC_PP_CHANCNT_S 0
#endif // __HW_LPC_H__

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bsp/lm3s8962/Libraries/inc/hw_memmap.h
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@ -2,7 +2,7 @@
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -41,24 +41,40 @@
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define SSI2_BASE 0x4000A000 // SSI2
#define SSI3_BASE 0x4000B000 // SSI3
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define UART3_BASE 0x4000F000 // UART3
#define UART4_BASE 0x40010000 // UART4
#define UART5_BASE 0x40011000 // UART5
#define UART6_BASE 0x40012000 // UART6
#define UART7_BASE 0x40013000 // UART7
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM_BASE 0x40028000 // PWM
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define TIMER4_BASE 0x40034000 // Timer4
#define TIMER5_BASE 0x40035000 // Timer5
#define WTIMER0_BASE 0x40036000 // Wide Timer0
#define WTIMER1_BASE 0x40037000 // Wide Timer1
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
@ -68,6 +84,10 @@
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
#define USB0_BASE 0x40050000 // USB 0 Controller
#define I2S0_BASE 0x40054000 // I2S0
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
@ -79,7 +99,23 @@
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
#define EEPROM_BASE 0x400AF000 // EEPROM memory
#define PECI0_BASE 0x400B0000 // Platform Environment Control
// Interface (PECI)
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
#define EPI0_BASE 0x400D0000 // EPI0
#define SYSEXC_BASE 0x400F9000 // System Exception Module
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
@ -107,6 +143,7 @@
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define ADC_BASE 0x40038000 // ADC

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bsp/lm3s8962/Libraries/inc/hw_nvic.h
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bsp/lm3s8962/Libraries/inc/hw_peci.h Normal file
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@ -0,0 +1,375 @@
//*****************************************************************************
//
// hw_peci.h - Macros used when accessing the PECI hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_PECI_H__
#define __HW_PECI_H__
//*****************************************************************************
//
// The following are defines for the PECI register addresses.
//
//*****************************************************************************
#define PECI_O_CTL 0x00000000 // PECI Control
#define PECI_O_DIV 0x00000004 // PECI Poll-Rate Divider
#define PECI_O_CMP 0x00000008 // PECI Comparator
#define PECI_O_M0D0C 0x00000010 // PECI Microprocessor 0 / Domain 0
// Control
#define PECI_O_M0D1C 0x00000014 // PECI Microprocessor 0 / Domain 1
// Control
#define PECI_O_M1D0C 0x00000018 // PECI Microprocessor 1 / Domain 0
// Control
#define PECI_O_M1D1C 0x0000001C // PECI Microprocessor 1 / Domain 1
// Control
#define PECI_O_M0D0 0x00000040 // PECI Microprocessor 0 / Domain 0
// Value
#define PECI_O_M0D1 0x00000044 // PECI Microprocessor 0 / Domain 1
// Value
#define PECI_O_M1D0 0x00000048 // PECI Microprocessor 1 / Domain 0
// Value
#define PECI_O_M1D1 0x0000004C // PECI Microprocessor 1 / Domain 1
// Value
#define PECI_O_IM 0x00000080 // PECI Interrupt Mask
#define PECI_O_RIS 0x00000084 // PECI Raw Interrupt Status
#define PECI_O_MIS 0x00000088 // PECI Masked Interrupt Status
#define PECI_O_IC 0x0000008C // PECI Interrupt Clear
#define PECI_O_ACADDR 0x00000100 // PECI Advanced Command Address
#define PECI_O_ACARG 0x00000104 // PECI Advanced Command Argument
#define PECI_O_ACRDWR0 0x00000108 // PECI Advanced Command Data 0
#define PECI_O_ACRDWR1 0x0000010C // PECI Advanced Command Data 1
#define PECI_O_ACCMD 0x00000110 // PECI Advanced Command
#define PECI_O_ACCODE 0x00000114 // PECI Advanced Command Completion
// Code
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_CTL register.
//
//*****************************************************************************
#define PECI_CTL_OFFSET_M 0xFFFF0000 // Offset Value
#define PECI_CTL_CRETRY_M 0x00007000 // Number of Controller Retries
#define PECI_CTL_BYERR 0x00000800 // Number of Retries
#define PECI_CTL_RXINV 0x00000400 // Invert PECI RX Input
#define PECI_CTL_M1D1EN 0x00000008 // Enable Microprocessor 1 and
// Domain 1
#define PECI_CTL_M1D0EN 0x00000004 // Enable Microprocessor 1 and
// Domain 0
#define PECI_CTL_M0D1EN 0x00000002 // Enable Microprocessor 0 and
// Domain 1
#define PECI_CTL_M0D0EN 0x00000001 // Enable Microprocessor 0 and
// Domain 0
#define PECI_CTL_OFFSET_S 16
#define PECI_CTL_CRETRY_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_DIV register.
//
//*****************************************************************************
#define PECI_DIV_BAUD_M 0xFFFF0000 // Initial Baud Rate
#define PECI_DIV_POLL_M 0x0000FFFF // Counter for Inter-Poll Delay
#define PECI_DIV_BAUD_S 16
#define PECI_DIV_POLL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_CMP register.
//
//*****************************************************************************
#define PECI_CMP_VREF_M 0x00000007 // Resistor Ladder Voltage Ref
#define PECI_CMP_VREF_0_5000V 0x00000000 // 0.5000
#define PECI_CMP_VREF_0_5125V 0x00000001 // 0.5125
#define PECI_CMP_VREF_0_5250V 0x00000002 // 0.5250
#define PECI_CMP_VREF_0_5375V 0x00000003 // 0.5375
#define PECI_CMP_VREF_0_5500V 0x00000004 // 0.5500
#define PECI_CMP_VREF_0_5625V 0x00000005 // 0.5625
#define PECI_CMP_VREF_0_6000V 0x00000006 // 0.6000
#define PECI_CMP_VREF_0_6625V 0x00000007 // 0.6625
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D0C register.
//
//*****************************************************************************
#define PECI_M0D0C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M0D0C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M0D0C_HITHR_S 16
#define PECI_M0D0C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D1C register.
//
//*****************************************************************************
#define PECI_M0D1C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M0D1C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M0D1C_HITHR_S 16
#define PECI_M0D1C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D0C register.
//
//*****************************************************************************
#define PECI_M1D0C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M1D0C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M1D0C_HITHR_S 16
#define PECI_M1D0C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D1C register.
//
//*****************************************************************************
#define PECI_M1D1C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M1D1C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M1D1C_HITHR_S 16
#define PECI_M1D1C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D0 register.
//
//*****************************************************************************
#define PECI_M0D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M0D0_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M0D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M0D0_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M0D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M0D0_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M0D0_VALUE_TO 0x000081FD // Timeout error
#define PECI_M0D0_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D1 register.
//
//*****************************************************************************
#define PECI_M0D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M0D1_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M0D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M0D1_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M0D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M0D1_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M0D1_VALUE_TO 0x000081FD // Timeout error
#define PECI_M0D1_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D0 register.
//
//*****************************************************************************
#define PECI_M1D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M1D0_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M1D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M1D0_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M1D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M1D0_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M1D0_VALUE_TO 0x000081FD // Timeout error
#define PECI_M1D0_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D1 register.
//
//*****************************************************************************
#define PECI_M1D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M1D1_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M1D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M1D1_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M1D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M1D1_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M1D1_VALUE_TO 0x000081FD // Timeout error
#define PECI_M1D1_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_IM register.
//
//*****************************************************************************
#define PECI_IM_M1D1IM_M 0x00C00000 // Microprocessor 1 and Domain 1
// Interrupt Mask
#define PECI_IM_M1D1IM_HIGH 0x00400000 // Interrupt when value is above
// high threshold
#define PECI_IM_M1D1IM_CROSSUP 0x00800000 // Interrupt when crossing above
// either threshold
#define PECI_IM_M1D1IM_CROSSANY 0x00C00000 // Interrupt when crossing either
// threshold in either direction
#define PECI_IM_M1D0IM_M 0x00300000 // Microprocessor 1 and Domain 0
// Interrupt Mask
#define PECI_IM_M0D1IM_M 0x000C0000 // Microprocessor 0 and Domain 1
// Interrupt Mask
#define PECI_IM_M0D0IM_M 0x00030000 // Microprocessor 0 and Domain 0
// Interrupt Mask
#define PECI_IM_ACIM 0x00000004 // Advanced Command Interrupt Mask
#define PECI_IM_ERRIM 0x00000002 // Error Detected Interrupt Mask
#define PECI_IM_POLLIM 0x00000001 // Poll Completed Interrupt Mask
#define PECI_IM_M1D0IM_S 20
#define PECI_IM_M0D1IM_S 18
#define PECI_IM_M0D0IM_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_RIS register.
//
//*****************************************************************************
#define PECI_RIS_M1D1RIS_M 0x00C00000 // Microprocessor 1 and Domain 1
// Raw Interrupt Status
#define PECI_RIS_M1D0RIS_M 0x00300000 // Microprocessor 1 and Domain 0
// Raw Interrupt Status
#define PECI_RIS_M0D1RIS_M 0x000C0000 // Microprocessor 0 and Domain 1
// Raw Interrupt Status
#define PECI_RIS_M0D0RIS_M 0x00030000 // Microprocessor 0 and Domain 0
// Raw Interrupt Status
#define PECI_RIS_ACRIS 0x00000004 // Advanced Command Raw Interrupt
// Status
#define PECI_RIS_ERRRIS 0x00000002 // Error Detected Raw Interrupt
// Status
#define PECI_RIS_POLLRIS 0x00000001 // Poll Completed Raw Interrupt
// Status
#define PECI_RIS_M1D1RIS_S 22
#define PECI_RIS_M1D0RIS_S 20
#define PECI_RIS_M0D1RIS_S 18
#define PECI_RIS_M0D0RIS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_MIS register.
//
//*****************************************************************************
#define PECI_MIS_M1D1MIS_M 0x00C00000 // Microprocessor 1 and Domain 1
// Masked Interrupt Status
#define PECI_MIS_M1D0MIS_M 0x00300000 // Microprocessor 1 and Domain 0
// Masked Interrupt Status
#define PECI_MIS_M0D1MIS_M 0x000C0000 // Microprocessor 0 and Domain 1
// Masked Interrupt Status
#define PECI_MIS_M0D0MIS_M 0x00030000 // Microprocessor 0 and Domain 0
// Masked Interrupt Status
#define PECI_MIS_ACMIS 0x00000004 // Advanced Command Masked
// Interrupt Status
#define PECI_MIS_ERRMIS 0x00000002 // Error Detected Masked Interrupt
// Status
#define PECI_MIS_POLLMIS 0x00000001 // Poll Completed Masked Interrupt
// Status
#define PECI_MIS_M1D1MIS_S 22
#define PECI_MIS_M1D0MIS_S 20
#define PECI_MIS_M0D1MIS_S 18
#define PECI_MIS_M0D0MIS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_IC register.
//
//*****************************************************************************
#define PECI_IC_M1D1IC_M 0x00C00000 // Microprocessor 1 and Domain 1
// Interrupt Clear
#define PECI_IC_M1D0IC_M 0x00300000 // Microprocessor 1 and Domain 0
// Interrupt Clear
#define PECI_IC_M0D1IC_M 0x000C0000 // Microprocessor 0 and Domain 1
// Interrupt Clear
#define PECI_IC_M0D0IC_M 0x00030000 // Microprocessor 0 and Domain 0
// Interrupt Clear
#define PECI_IC_ACIC 0x00000004 // Advanced Command Interrupt Clear
#define PECI_IC_ERRIC 0x00000002 // Error Detected Interrupt Clear
#define PECI_IC_POLLIC 0x00000001 // Poll Completed Interrupt Clear
#define PECI_IC_M1D1IC_S 22
#define PECI_IC_M1D0IC_S 20
#define PECI_IC_M0D1IC_S 18
#define PECI_IC_M0D0IC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACADDR register.
//
//*****************************************************************************
#define PECI_ACADDR_HIDRE_M 0xFF000000 // HostID and Retry
#define PECI_ACADDR_SIZE_M 0x00FF0000 // Size Override
#define PECI_ACADDR_DOMAIN_M 0x0000FF00 // Domain Select
#define PECI_ACADDR_PROCADD_M 0x000000FF // Processor Address
#define PECI_ACADDR_HIDRE_S 24
#define PECI_ACADDR_SIZE_S 16
#define PECI_ACADDR_DOMAIN_S 8
#define PECI_ACADDR_PROCADD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACARG register.
//
//*****************************************************************************
#define PECI_ACARG_ARG3_M 0xFF000000 // Argument 3
#define PECI_ACARG_ARG2_M 0x00FF0000 // Argument 2
#define PECI_ACARG_ARG1_M 0x0000FF00 // Argument 1
#define PECI_ACARG_ARG0_M 0x000000FF // Argument 0
#define PECI_ACARG_ARG3_S 24
#define PECI_ACARG_ARG2_S 16
#define PECI_ACARG_ARG1_S 8
#define PECI_ACARG_ARG0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACRDWR0 register.
//
//*****************************************************************************
#define PECI_ACRDWR0_D3_M 0xFF000000 // Data 3
#define PECI_ACRDWR0_D2_M 0x00FF0000 // Data 2
#define PECI_ACRDWR0_D1_M 0x0000FF00 // Data 1
#define PECI_ACRDWR0_D0_M 0x000000FF // Data 0
#define PECI_ACRDWR0_D3_S 24
#define PECI_ACRDWR0_D2_S 16
#define PECI_ACRDWR0_D1_S 8
#define PECI_ACRDWR0_D0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACRDWR1 register.
//
//*****************************************************************************
#define PECI_ACRDWR1_D3_M 0xFF000000 // Data 3
#define PECI_ACRDWR1_D2_M 0x00FF0000 // Data 2
#define PECI_ACRDWR1_D1_M 0x0000FF00 // Data 1
#define PECI_ACRDWR1_D0_M 0x000000FF // Data 0
#define PECI_ACRDWR1_D3_S 24
#define PECI_ACRDWR1_D2_S 16
#define PECI_ACRDWR1_D1_S 8
#define PECI_ACRDWR1_D0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACCMD register.
//
//*****************************************************************************
#define PECI_ACCMD_CMD_M 0x000000FF // Base Command
#define PECI_ACCMD_CMD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACCODE register.
//
//*****************************************************************************
#define PECI_ACCODE_CODE_M 0xFFFFFFFF // Signed Completion Code
#endif // __HW_PECI_H__

33
bsp/lm3s8962/Libraries/inc/hw_pwm.h
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@ -2,7 +2,7 @@
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -125,6 +125,8 @@
#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
#define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration
//*****************************************************************************
//
@ -594,6 +596,33 @@
#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_PP register.
//
//*****************************************************************************
#define PWM_PP_GCNT_M 0x0000000F // Generators
#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs
#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
#define PWM_PP_EFAULT 0x00000200 // Extended Fault
#define PWM_PP_ONE 0x00000400 // One-Shot Mode
#define PWM_PP_GCNT_S 0
#define PWM_PP_FCNT_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_PC register.
//
//*****************************************************************************
#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor
#define PWM_PC_PWMDIV_2 0x00000000 // /2
#define PWM_PC_PWMDIV_4 0x00000001 // /4
#define PWM_PC_PWMDIV_8 0x00000002 // /8
#define PWM_PC_PWMDIV_16 0x00000003 // /16
#define PWM_PC_PWMDIV_32 0x00000004 // /32
#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default)
#define PWM_PC_USEOPWMDIV 0x00000100 // Enable PWM Clock Divisor
//*****************************************************************************
//
// The following are defines for the PWM Generator standard offsets.

4
bsp/lm3s8962/Libraries/inc/hw_qei.h
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@ -2,7 +2,7 @@
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************

16
bsp/lm3s8962/Libraries/inc/hw_ssi.h
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@ -2,7 +2,7 @@
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -40,6 +40,7 @@
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
//*****************************************************************************
//
@ -167,6 +168,17 @@
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
// PLL bypass is in effect) or the
// PLL output (default)
#define SSI_CC_CS_PIOSC 0x00000001 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.

2018
bsp/lm3s8962/Libraries/inc/hw_sysctl.h
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89
bsp/lm3s8962/Libraries/inc/hw_sysexc.h Normal file
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@ -0,0 +1,89 @@
//*****************************************************************************
//
// hw_sysexc.h - Macros used when accessing the system exception module.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SYSEXC_H__
#define __HW_SYSEXC_H__
//*****************************************************************************
//
// The following are defines for the System Exception Module register
// addresses.
//
//*****************************************************************************
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
// Status
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
#define SYSEXC_MIS 0x400F9008 // System Exception Raw Interrupt
// Status
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_RIS register.
//
//*****************************************************************************
#define SYSEXC_RIS_IXCRIS 0x00000020 // Inexact Exception Flag
#define SYSEXC_RIS_OFCRIS 0x00000010 // Overflow Exception Flag
#define SYSEXC_RIS_UFCRIS 0x00000008 // Underflow Exception Flag
#define SYSEXC_RIS_IOCRIS 0x00000004 // Invalid Operation Flag
#define SYSEXC_RIS_DZCRIS 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_RIS_IDCRIS 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IM register.
//
//*****************************************************************************
#define SYSEXC_IM_IXCIM 0x00000020 // Inexact Exception Flag
#define SYSEXC_IM_OFCIM 0x00000010 // Overflow Exception Flag
#define SYSEXC_IM_UFCIM 0x00000008 // Underflow Exception Flag
#define SYSEXC_IM_IOCIM 0x00000004 // Invalid Operation Flag
#define SYSEXC_IM_DZCIM 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_IM_IDCIM 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_MIS register.
//
//*****************************************************************************
#define SYSEXC_MIS_IXCMIS 0x00000020 // Inexact Exception Flag
#define SYSEXC_MIS_OFCMIS 0x00000010 // Overflow Exception Flag
#define SYSEXC_MIS_UFCMIS 0x00000008 // Underflow Exception Flag
#define SYSEXC_MIS_IOCMIS 0x00000004 // Invalid Operation Flag
#define SYSEXC_MIS_DZCMIS 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_MIS_IDCMIS 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IC register.
//
//*****************************************************************************
#define SYSEXC_IC_IXCIC 0x00000020 // Inexact Exception Flag
#define SYSEXC_IC_OFCIC 0x00000010 // Overflow Exception Flag
#define SYSEXC_IC_UFCIC 0x00000008 // Underflow Exception Flag
#define SYSEXC_IC_IOCIC 0x00000004 // Invalid Operation Flag
#define SYSEXC_IC_DZCIC 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_IC_IDCIC 0x00000001 // Input Denormal Exception Flag
#endif // __HW_SYSEXC_H__

276
bsp/lm3s8962/Libraries/inc/hw_timer.h
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@ -2,7 +2,7 @@
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -34,6 +34,7 @@
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
@ -50,6 +51,12 @@
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
//*****************************************************************************
//
@ -69,6 +76,13 @@
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
@ -87,6 +101,13 @@
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
@ -125,11 +146,175 @@
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
// 5
#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
// 4
#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
// 3
#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
// 2
#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
// 1
#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
// 0
#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 0 is triggered
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
// 5
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
// 4
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
// 3
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
// 2
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
// 1
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
// 0
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 0 is triggered
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Mask
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
// Interrupt Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
@ -153,6 +338,8 @@
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Raw Interrupt Status
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
// Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
@ -176,6 +363,8 @@
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Masked Interrupt Status
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
@ -199,6 +388,8 @@
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Clear
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
// Interrupt Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
@ -222,21 +413,27 @@
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
#define TIMER_TAILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
#define TIMER_TBILR_S 0
//*****************************************************************************
//
@ -244,10 +441,12 @@
// register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
#define TIMER_TAMATCHR_TAMR_S 0
//*****************************************************************************
//
@ -255,7 +454,9 @@
// register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
#define TIMER_TBMATCHR_TBMR_S 0
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
@ -263,7 +464,9 @@
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
#define TIMER_TAPR_TAPSRH_S 8
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
@ -271,7 +474,9 @@
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
#define TIMER_TBPR_TBPSRH_S 8
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
@ -279,7 +484,10 @@
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
#define TIMER_TAPMR_TAPSMRH_S 8
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
@ -287,7 +495,10 @@
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
#define TIMER_TBPMR_TBPSMRH_S 8
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
@ -295,36 +506,97 @@
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
#define TIMER_TAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
#define TIMER_TBR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
#define TIMER_TAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
// 32 bits each with a 16-bit
// prescale counter
//*****************************************************************************
//

28
bsp/lm3s8962/Libraries/inc/hw_types.h
View File

@ -2,7 +2,7 @@
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -115,6 +115,18 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
#endif
#ifndef CLASS_IS_FIRESTORM
#define CLASS_IS_FIRESTORM \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
#endif
#ifndef CLASS_IS_BLIZZARD
#define CLASS_IS_BLIZZARD \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
@ -163,6 +175,18 @@ typedef unsigned char tBoolean;
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_C3
#define REVISION_IS_C3 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
#endif
#ifndef REVISION_IS_C5
#define REVISION_IS_C5 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
#endif
//*****************************************************************************
//
// Deprecated silicon class and revision detection macros.

62
bsp/lm3s8962/Libraries/inc/hw_uart.h
View File

@ -2,7 +2,7 @@
//
// hw_uart.h - Macros and defines used when accessing the UART hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -49,6 +49,10 @@
#define UART_O_LCTL 0x00000090 // UART LIN Control
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
#define UART_O_LTIM 0x00000098 // UART LIN Timer
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
//*****************************************************************************
//
@ -185,6 +189,7 @@
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
@ -215,6 +220,7 @@
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
@ -249,6 +255,8 @@
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
@ -277,10 +285,11 @@
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
@ -335,6 +344,45 @@
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITADDR
// register.
//
//*****************************************************************************
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITAMASK
// register.
//
//*****************************************************************************
#define UART_9BITAMASK_RANGE_M 0x0000FF00 // Self Address Range for 9-Bit
// Mode
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_RANGE_S 8
#define UART_9BITAMASK_MASK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//*****************************************************************************
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//*****************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
#define UART_CC_CS_PIOSC 0x00000001 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
@ -418,6 +466,10 @@
// register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
UART_RSR_FE)

132
bsp/lm3s8962/Libraries/inc/hw_udma.h
View File

@ -2,7 +2,7 @@
//
// hw_udma.h - Macros for use in accessing the UDMA registers.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -52,7 +52,12 @@
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
//*****************************************************************************
//
@ -201,11 +206,109 @@
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHALT register.
// The following are defines for the bit fields in the UDMA_CHASGN register.
//
//*****************************************************************************
#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
// Select
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
// assignment
#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
// assignment
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHIS register.
//
//*****************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
//
//*****************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
//
//*****************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
//
//*****************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
//
//*****************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_S 0
//*****************************************************************************
//
@ -298,6 +401,14 @@
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Micro Direct Memory Access
// register addresses.
//
//*****************************************************************************
#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UDMA_ENASET
@ -306,6 +417,15 @@
//*****************************************************************************
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UDMA_CHALT
// register.
//
//*****************************************************************************
#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
// Select
#endif
#endif // __HW_UDMA_H__

23
bsp/lm3s8962/Libraries/inc/hw_usb.h
View File

@ -2,7 +2,7 @@
//
// hw_usb.h - Macros for use in accessing the USB registers.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -629,6 +629,7 @@
#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
// Status and Clear
#define USB_O_DMASEL 0x00000450 // USB DMA Select
#define USB_O_PP 0x00000FC0 // USB Peripheral Properties
//*****************************************************************************
//
@ -4569,11 +4570,29 @@
#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
#define USB_DMASEL_DMACTX_S 20
#define USB_DMASEL_DMACRX_S 16
#define USB_DMASEL_DMABTX_S 12
#define USB_DMASEL_DMABRX_S 8
#define USB_DMASEL_DMAATX_S 4
#define USB_DMASEL_DMAARX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_O_PP register.
//
//*****************************************************************************
#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
#define USB_PP_USB_M 0x000000C0 // USB Capability
#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
#define USB_PP_USB_OTG 0x000000C0 // OTG
#define USB_PP_PHY 0x00000010 // PHY Present
#define USB_PP_TYPE_M 0x0000000F // Controller Type
#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
// controller
#define USB_PP_ECNT_S 8
//*****************************************************************************
//
// The following definitions are deprecated.

5
bsp/lm3s8962/Libraries/inc/hw_watchdog.h
View File

@ -2,7 +2,7 @@
//
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Firmware Development Package.
// This is part of revision 8264 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
@ -61,6 +61,7 @@
//
//*****************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable

BIN
bsp/lm3s8962/Libraries/inc/inc.sgxx
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Binary file not shown.

5034
bsp/lm3s8962/Libraries/inc/lm3s8962.h
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File diff suppressed because it is too large Load Diff

7
bsp/lm3s8962/project.Uv2
View File

@ -22,19 +22,24 @@ File 3,1,<Libraries\driverlib\adc.c><adc.c>
File 3,1,<Libraries\driverlib\can.c><can.c>
File 3,1,<Libraries\driverlib\comp.c><comp.c>
File 3,1,<Libraries\driverlib\cpu.c><cpu.c>
File 3,1,<Libraries\driverlib\eeprom.c><eeprom.c>
File 3,1,<Libraries\driverlib\epi.c><epi.c>
File 3,1,<Libraries\driverlib\ethernet.c><ethernet.c>
File 3,1,<Libraries\driverlib\fan.c><fan.c>
File 3,1,<Libraries\driverlib\flash.c><flash.c>
File 3,1,<Libraries\driverlib\gpio.c><gpio.c>
File 3,1,<Libraries\driverlib\hibernate.c><hibernate.c>
File 3,1,<Libraries\driverlib\i2c.c><i2c.c>
File 3,1,<Libraries\driverlib\i2s.c><i2s.c>
File 3,1,<Libraries\driverlib\interrupt.c><interrupt.c>
File 3,1,<Libraries\driverlib\lpc.c><lpc.c>
File 3,1,<Libraries\driverlib\mpu.c><mpu.c>
File 3,1,<Libraries\driverlib\peci.c><peci.c>
File 3,1,<Libraries\driverlib\pwm.c><pwm.c>
File 3,1,<Libraries\driverlib\qei.c><qei.c>
File 3,1,<Libraries\driverlib\ssi.c><ssi.c>
File 3,1,<Libraries\driverlib\sysctl.c><sysctl.c>
File 3,1,<Libraries\driverlib\sysexc.c><sysexc.c>
File 3,1,<Libraries\driverlib\systick.c><systick.c>
File 3,1,<Libraries\driverlib\timer.c><timer.c>
File 3,1,<Libraries\driverlib\uart.c><uart.c>
@ -177,7 +182,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s'
RV_STAVEC ()
ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
ADSCMISC ()
ADSCDEFN ()
ADSCDEFN (PART_LM3S8962)
ADSCUDEF ()
ADSCINCD (..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\include;drivers;..\..\components\dfs;.;Libraries;applications;..\..\components\net\lwip\src\arch\include;..\..\libcpu\arm\cortex-m3;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\finsh;..\..\components\net\lwip\src\include\netif;..\..\components\dfs\include)
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }

3
bsp/lm3s8962/rtconfig.py
View File

@ -3,6 +3,9 @@ ARCH='arm'
CPU='cortex-m3'
CROSS_TOOL = 'keil'
#device options
PART_TYPE = 'PART_LM3S8962'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'

7
bsp/lm4f232/Libraries/SConscript
View File

@ -6,6 +6,10 @@ from building import *
cwd = GetCurrentDir()
src = Glob('driverlib/*.c')
# cortex-m3 no FPU.
if rtconfig.PART_TYPE.startswith('PART_LM4F') != True:
SrcRemove(src, 'fpu.c')
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/gcc/start_gcc.s']
@ -16,6 +20,7 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
CPPDEFINES = [rtconfig.PART_TYPE]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')

35
bsp/lm4f232/Libraries/driverlib/Makefile
View File

@ -1,35 +0,0 @@
#******************************************************************************
#
# Makefile - Rules for building the driver library.
#
# Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
# Software License Agreement
#
# Texas Instruments (TI) is supplying this software for use solely and
# exclusively on TI's microcontroller products. The software is owned by
# TI and/or its suppliers, and is protected under applicable copyright
# laws. You may not combine this software with "viral" open-source
# software in order to form a larger program.
#
# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
# DAMAGES, FOR ANY REASON WHATSOEVER.
#
# This is part of revision 8049 of the Stellaris Peripheral Driver Library.
#
#******************************************************************************
all:
@make -f Makefile.driverlib-cm3
@make -f Makefile.driverlib-cm4f
clean:
@make -f Makefile.driverlib-cm3 clean
@make -f Makefile.driverlib-cm4f clean
realclean:
@make -f Makefile.driverlib-cm3 realclean
@make -f Makefile.driverlib-cm4f realclean

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