diff --git a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_dac12.h b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_dac12.h index 4bdc22fcb9..f467ec038c 100644 --- a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_dac12.h +++ b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_dac12.h @@ -1,418 +1,418 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_DAC12_H_ -#define _FSL_DAC12_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup dac12 - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief DAC12 driver version 2.1.0. */ -#define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief Define "write 1 to clear" flags. */ -#define DAC12_CR_W1C_FLAGS_MASK (DAC_CR_OVFF_MASK | DAC_CR_UDFF_MASK) -/*! @brief Define all the flag bits in DACx_CR register. */ -#define DAC12_CR_ALL_FLAGS_MASK (DAC12_CR_W1C_FLAGS_MASK | DAC_CR_WMF_MASK | DAC_CR_NEMPTF_MASK | DAC_CR_FULLF_MASK) - -/*! - * @brief DAC12 flags. - */ -enum _dac12_status_flags -{ - kDAC12_OverflowFlag = DAC_CR_OVFF_MASK, /*!< FIFO overflow status flag, which indicates that more data has been - written into FIFO than it can hold. */ - kDAC12_UnderflowFlag = DAC_CR_UDFF_MASK, /*!< FIFO underflow status flag, which means that there is a new trigger - after the FIFO is nearly empty. */ - kDAC12_WatermarkFlag = DAC_CR_WMF_MASK, /*!< FIFO wartermark status flag, which indicates the remaining FIFO data is - less than the watermark setting. */ - kDAC12_NearlyEmptyFlag = DAC_CR_NEMPTF_MASK, /*!< FIFO nearly empty flag, which means there is only one data - remaining in FIFO. */ - kDAC12_FullFlag = DAC_CR_FULLF_MASK /*!< FIFO full status flag, which means that the FIFO read pointer equals the - write pointer, as the write pointer increase. */ -}; - -/*! - * @brief DAC12 interrupts. - */ -enum _dac12_interrupt_enable -{ - kDAC12_UnderOrOverflowInterruptEnable = DAC_CR_UVIE_MASK, /*!< Underflow and overflow interrupt enable. */ - kDAC12_WatermarkInterruptEnable = DAC_CR_WTMIE_MASK, /*!< Watermark interrupt enable. */ - kDAC12_NearlyEmptyInterruptEnable = DAC_CR_EMPTIE_MASK, /*!< Nearly empty interrupt enable. */ - kDAC12_FullInterruptEnable = DAC_CR_FULLIE_MASK /*!< Full interrupt enable. */ -}; - -/*! - * @brief DAC12 FIFO size information provided by hardware. - */ -typedef enum _dac12_fifo_size_info -{ - kDAC12_FIFOSize2 = 0U, /*!< FIFO depth is 2. */ - kDAC12_FIFOSize4 = 1U, /*!< FIFO depth is 4. */ - kDAC12_FIFOSize8 = 2U, /*!< FIFO depth is 8. */ - kDAC12_FIFOSize16 = 3U, /*!< FIFO depth is 16. */ - kDAC12_FIFOSize32 = 4U, /*!< FIFO depth is 32. */ - kDAC12_FIFOSize64 = 5U, /*!< FIFO depth is 64. */ - kDAC12_FIFOSize128 = 6U, /*!< FIFO depth is 128. */ - kDAC12_FIFOSize256 = 7U, /*!< FIFO depth is 256. */ -} dac12_fifo_size_info_t; - -/*! - * @brief DAC12 FIFO work mode. - */ -typedef enum _dac12_fifo_work_mode -{ - kDAC12_FIFODisabled = 0U, /*!< FIFO disabled and only one level buffer is enabled. Any data written from this buffer - goes to conversion. */ - kDAC12_FIFOWorkAsNormalMode = 1U, /*!< Data will first read from FIFO to buffer then go to conversion. */ - kDAC12_FIFOWorkAsSwingMode = 2U /*!< In Swing mode, the FIFO must be set up to be full. In Swing back mode, a - trigger changes the read pointer to make it swing between the FIFO Full and - Nearly Empty state. That is, the trigger increases the read pointer till FIFO - is nearly empty and decreases the read pointer till the FIFO is full. */ -} dac12_fifo_work_mode_t; - -/*! - * @brief DAC12 reference voltage source. - */ -typedef enum _dac12_reference_voltage_source -{ - kDAC12_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ - kDAC12_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ -} dac12_reference_voltage_source_t; - -/*! - * @brief DAC12 FIFO trigger mode. - */ -typedef enum _dac12_fifo_trigger_mode -{ - kDAC12_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ - kDAC12_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ -} dac12_fifo_trigger_mode_t; - -/*! - * @brief DAC internal reference current source. - * - * Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by - * on-chip PMC's "reference part". If no current reference be selected, analog module can’t working normally ,even when - * other register can still be assigned, DAC would waste current but no function. - * To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected. - */ -typedef enum _dac12_reference_current_source -{ - kDAC12_ReferenceCurrentSourceDisabled = 0U, /*!< None of reference current source is enabled. */ - kDAC12_ReferenceCurrentSourceAlt0 = 1U, /*!< Use the internal reference current generated by the module itself. */ - kDAC12_ReferenceCurrentSourceAlt1 = 2U, /*!< Use the ZTC(Zero Temperature Coefficient) reference current generated - by on-chip power management module. */ - kDAC12_ReferenceCurrentSourceAlt2 = 3U, /*!< Use the PTAT(Proportional To Absolution Temperature) reference current - generated by power management module. */ -} dac12_reference_current_source_t; - -/*! - * @brief DAC analog buffer speed mode for conversion. - */ -typedef enum _dac12_speed_mode -{ - kDAC12_SpeedLowMode = 0U, /*!< Low speed mode. */ - kDAC12_SpeedMiddleMode = 1U, /*!< Middle speed mode. */ - kDAC12_SpeedHighMode = 2U, /*!< High speed mode. */ -} dac12_speed_mode_t; - -/*! - * @brief DAC12 hardware information. - */ -typedef struct _dac12_hardware_info -{ - dac12_fifo_size_info_t fifoSizeInfo; /*!< The number of words in this device's DAC buffer. */ -} dac12_hardware_info_t; - -/*! - * @brief DAC12 module configuration. - * - * Actually, the most fields are for FIFO buffer. - */ -typedef struct -{ - uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ - dac12_fifo_work_mode_t fifoWorkMode; /*!< FIFI's work mode about pointers. */ - dac12_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ - dac12_fifo_trigger_mode_t fifoTriggerMode; /*! Select the trigger mode for FIFO. */ - - /* Analog part configuration. */ - dac12_reference_current_source_t referenceCurrentSource; /*!< Select the reference current source. */ - dac12_speed_mode_t speedMode; /*!< Select the speed mode for conversion. */ - bool enableAnalogBuffer; /*!< Enable analog buffer for high drive. */ -#if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) - uint32_t currentReferenceInternalTrimValue; /*!< Internal reference current trim value. 3-bit value is available.*/ -#endif /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */ -} dac12_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and de-initialization - * @{ - */ - -/*! - * @brief Get hardware information about this module. - * - * @param base DAC12 peripheral base address. - * @param info Pointer to info structure, see to #dac12_hardware_info_t. - */ -void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info); - -/*! - * @brief Initialize the DAC12 module. - * - * @param base DAC12 peripheral base address. - * @param config Pointer to configuration structure, see to #dac12_config_t. - */ -void DAC12_Init(DAC_Type *base, const dac12_config_t *config); - -/*! - * @brief Initializes the DAC12 user configuration structure. - * - * This function initializes the user configuration structure to a default value. The default values are: - * @code - * config->fifoWatermarkLevel = 0U; - * config->fifoWorkMode = kDAC12_FIFODisabled; - * config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1; - * config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode; - * config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0; - * config->speedMode = kDAC12_SpeedLowMode; - * config->speedMode = false; - * config->currentReferenceInternalTrimValue = 0x4; - * @endcode - * @param config Pointer to the configuration structure. See "dac12_config_t". - */ -void DAC12_GetDefaultConfig(dac12_config_t *config); - -/*! - * @brief De-initialize the DAC12 module. - * - * @param base DAC12 peripheral base address. - */ -void DAC12_Deinit(DAC_Type *base); - -/*! - * @brief Enable the DAC12's converter or not. - * - * @param base DAC12 peripheral base address. - * @param enable Enable the DAC12's converter or not. - */ -static inline void DAC12_Enable(DAC_Type *base, bool enable) -{ - if (enable) - { - base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DACEN_MASK; - } - else - { - base->CR &= ~DAC_CR_DACEN_MASK; - } -} - -/*! - * @brief Reset all internal logic and registers. - * - * @param base DAC12 peripheral base address. - */ -static inline void DAC12_ResetConfig(DAC_Type *base) -{ - base->CR = DAC_CR_SWRST_MASK; -} - -/*! - * @brief Reset the FIFO pointers. - * - * FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers - * to the same address to reset the FIFO as empty. - * - * @param base DAC12 peripheral base address. - */ -static inline void DAC12_ResetFIFO(DAC_Type *base) -{ - /* FIFO pointers should only be reset when the module is disabled. */ - base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_FIFORST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base DAC12 peripheral base address. - * @return Mask of current status flags. See to #_dac12_status_flags. - */ -static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base) -{ - return (DAC12_CR_ALL_FLAGS_MASK & base->CR); -} - -/*! - * @brief Clear status flags. - * - * Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to - * target chip's reference manual document. - * - * @param base DAC12 peripheral base address. - * @param flags Mask of status flags to be cleared. See to #_dac12_status_flags. - */ -static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags) -{ - base->CR |= (flags & DAC12_CR_W1C_FLAGS_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base DAC12 peripheral base address. - * @param mask Mask value of interrupts to be enabled. See to #_dac12_interrupt_enable. - */ -static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask) -{ - base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base DAC12 peripheral base address. - * @param mask Mask value of interrupts to be disabled. See to #_dac12_interrupt_enable. - */ -static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask) -{ - base->CR &= ~mask; -} - -/* @} */ - -/*! - * @name DMA control - * @{ - */ - -/*! - * @brief Enable DMA or not. - * - * When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented - * on this module at the same time. - */ -static inline void DAC12_EnableDMA(DAC_Type *base, bool enable) -{ - if (enable) - { - base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DMAEN_MASK; - } - else - { - base->CR &= ~DAC_CR_DMAEN_MASK; - } -} - -/* @} */ - -/*! - * @name Functional feature - * @{ - */ - -/*! - * @brief Set data into the entry of FIFO buffer. - * - * When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog - * output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion - * without trigger support. - * When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored - * into the FIFO buffer. - * - * @param base DAC12 peripheral base address. - * @param value Setting value into FIFO buffer. - */ -static inline void DAC12_SetData(DAC_Type *base, uint32_t value) -{ - /* The module is connected internally to a 32-bit interface. - * For the 8-bit or 16-bit, the write might be ignored. */ - base->DATA = DAC_DATA_DATA0(value); -} - -/*! - * @brief Do trigger the FIFO by software. - * - * When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the - * data in the entry pointed by read pointer would be converted as new output. - * - * @param base DAC12 peripheral base address. - */ -static inline void DAC12_DoSoftwareTrigger(DAC_Type *base) -{ - base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_SWTRG_MASK; -} - -/*! - * @brief Get the current read pointer of FIFO. - * - * @param base DAC12 peripheral base address. - * @return Read pointer index of FIFO buffer. - */ -static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base) -{ - return (DAC_PTR_DACRFP_MASK & base->PTR) >> DAC_PTR_DACRFP_SHIFT; -} - -/*! - * @brief Get the current write pointer of FIFO. - * - * @param base DAC12 peripheral base address. - * @return Write pointer index of FIFO buffer - */ -static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base) -{ - return (DAC_PTR_DACWFP_MASK & base->PTR) >> DAC_PTR_DACWFP_SHIFT; -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_DAC12_H_ */ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DAC12_H_ +#define _FSL_DAC12_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac12 + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DAC12 driver version 2.1.0. */ +#define FSL_DAC12_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Define "write 1 to clear" flags. */ +#define DAC12_CR_W1C_FLAGS_MASK (DAC_CR_OVFF_MASK | DAC_CR_UDFF_MASK) +/*! @brief Define all the flag bits in DACx_CR register. */ +#define DAC12_CR_ALL_FLAGS_MASK (DAC12_CR_W1C_FLAGS_MASK | DAC_CR_WMF_MASK | DAC_CR_NEMPTF_MASK | DAC_CR_FULLF_MASK) + +/*! + * @brief DAC12 flags. + */ +enum _dac12_status_flags +{ + kDAC12_OverflowFlag = DAC_CR_OVFF_MASK, /*!< FIFO overflow status flag, which indicates that more data has been + written into FIFO than it can hold. */ + kDAC12_UnderflowFlag = DAC_CR_UDFF_MASK, /*!< FIFO underflow status flag, which means that there is a new trigger + after the FIFO is nearly empty. */ + kDAC12_WatermarkFlag = DAC_CR_WMF_MASK, /*!< FIFO wartermark status flag, which indicates the remaining FIFO data is + less than the watermark setting. */ + kDAC12_NearlyEmptyFlag = DAC_CR_NEMPTF_MASK, /*!< FIFO nearly empty flag, which means there is only one data + remaining in FIFO. */ + kDAC12_FullFlag = DAC_CR_FULLF_MASK /*!< FIFO full status flag, which means that the FIFO read pointer equals the + write pointer, as the write pointer increase. */ +}; + +/*! + * @brief DAC12 interrupts. + */ +enum _dac12_interrupt_enable +{ + kDAC12_UnderOrOverflowInterruptEnable = DAC_CR_UVIE_MASK, /*!< Underflow and overflow interrupt enable. */ + kDAC12_WatermarkInterruptEnable = DAC_CR_WTMIE_MASK, /*!< Watermark interrupt enable. */ + kDAC12_NearlyEmptyInterruptEnable = DAC_CR_EMPTIE_MASK, /*!< Nearly empty interrupt enable. */ + kDAC12_FullInterruptEnable = DAC_CR_FULLIE_MASK /*!< Full interrupt enable. */ +}; + +/*! + * @brief DAC12 FIFO size information provided by hardware. + */ +typedef enum _dac12_fifo_size_info +{ + kDAC12_FIFOSize2 = 0U, /*!< FIFO depth is 2. */ + kDAC12_FIFOSize4 = 1U, /*!< FIFO depth is 4. */ + kDAC12_FIFOSize8 = 2U, /*!< FIFO depth is 8. */ + kDAC12_FIFOSize16 = 3U, /*!< FIFO depth is 16. */ + kDAC12_FIFOSize32 = 4U, /*!< FIFO depth is 32. */ + kDAC12_FIFOSize64 = 5U, /*!< FIFO depth is 64. */ + kDAC12_FIFOSize128 = 6U, /*!< FIFO depth is 128. */ + kDAC12_FIFOSize256 = 7U, /*!< FIFO depth is 256. */ +} dac12_fifo_size_info_t; + +/*! + * @brief DAC12 FIFO work mode. + */ +typedef enum _dac12_fifo_work_mode +{ + kDAC12_FIFODisabled = 0U, /*!< FIFO disabled and only one level buffer is enabled. Any data written from this buffer + goes to conversion. */ + kDAC12_FIFOWorkAsNormalMode = 1U, /*!< Data will first read from FIFO to buffer then go to conversion. */ + kDAC12_FIFOWorkAsSwingMode = 2U /*!< In Swing mode, the FIFO must be set up to be full. In Swing back mode, a + trigger changes the read pointer to make it swing between the FIFO Full and + Nearly Empty state. That is, the trigger increases the read pointer till FIFO + is nearly empty and decreases the read pointer till the FIFO is full. */ +} dac12_fifo_work_mode_t; + +/*! + * @brief DAC12 reference voltage source. + */ +typedef enum _dac12_reference_voltage_source +{ + kDAC12_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ + kDAC12_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ +} dac12_reference_voltage_source_t; + +/*! + * @brief DAC12 FIFO trigger mode. + */ +typedef enum _dac12_fifo_trigger_mode +{ + kDAC12_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ + kDAC12_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ +} dac12_fifo_trigger_mode_t; + +/*! + * @brief DAC internal reference current source. + * + * Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by + * on-chip PMC's "reference part". If no current reference be selected, analog module can’t working normally ,even when + * other register can still be assigned, DAC would waste current but no function. + * To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected. + */ +typedef enum _dac12_reference_current_source +{ + kDAC12_ReferenceCurrentSourceDisabled = 0U, /*!< None of reference current source is enabled. */ + kDAC12_ReferenceCurrentSourceAlt0 = 1U, /*!< Use the internal reference current generated by the module itself. */ + kDAC12_ReferenceCurrentSourceAlt1 = 2U, /*!< Use the ZTC(Zero Temperature Coefficient) reference current generated + by on-chip power management module. */ + kDAC12_ReferenceCurrentSourceAlt2 = 3U, /*!< Use the PTAT(Proportional To Absolution Temperature) reference current + generated by power management module. */ +} dac12_reference_current_source_t; + +/*! + * @brief DAC analog buffer speed mode for conversion. + */ +typedef enum _dac12_speed_mode +{ + kDAC12_SpeedLowMode = 0U, /*!< Low speed mode. */ + kDAC12_SpeedMiddleMode = 1U, /*!< Middle speed mode. */ + kDAC12_SpeedHighMode = 2U, /*!< High speed mode. */ +} dac12_speed_mode_t; + +/*! + * @brief DAC12 hardware information. + */ +typedef struct _dac12_hardware_info +{ + dac12_fifo_size_info_t fifoSizeInfo; /*!< The number of words in this device's DAC buffer. */ +} dac12_hardware_info_t; + +/*! + * @brief DAC12 module configuration. + * + * Actually, the most fields are for FIFO buffer. + */ +typedef struct +{ + uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ + dac12_fifo_work_mode_t fifoWorkMode; /*!< FIFI's work mode about pointers. */ + dac12_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + dac12_fifo_trigger_mode_t fifoTriggerMode; /*! Select the trigger mode for FIFO. */ + + /* Analog part configuration. */ + dac12_reference_current_source_t referenceCurrentSource; /*!< Select the reference current source. */ + dac12_speed_mode_t speedMode; /*!< Select the speed mode for conversion. */ + bool enableAnalogBuffer; /*!< Enable analog buffer for high drive. */ +#if !(defined(FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) && FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER) + uint32_t currentReferenceInternalTrimValue; /*!< Internal reference current trim value. 3-bit value is available.*/ +#endif /* FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER */ +} dac12_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief Get hardware information about this module. + * + * @param base DAC12 peripheral base address. + * @param info Pointer to info structure, see to #dac12_hardware_info_t. + */ +void DAC12_GetHardwareInfo(DAC_Type *base, dac12_hardware_info_t *info); + +/*! + * @brief Initialize the DAC12 module. + * + * @param base DAC12 peripheral base address. + * @param config Pointer to configuration structure, see to #dac12_config_t. + */ +void DAC12_Init(DAC_Type *base, const dac12_config_t *config); + +/*! + * @brief Initializes the DAC12 user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->fifoWatermarkLevel = 0U; + * config->fifoWorkMode = kDAC12_FIFODisabled; + * config->referenceVoltageSource = kDAC12_ReferenceVoltageSourceAlt1; + * config->fifoTriggerMode = kDAC12_FIFOTriggerByHardwareMode; + * config->referenceCurrentSource = kDAC12_ReferenceCurrentSourceAlt0; + * config->speedMode = kDAC12_SpeedLowMode; + * config->speedMode = false; + * config->currentReferenceInternalTrimValue = 0x4; + * @endcode + * @param config Pointer to the configuration structure. See "dac12_config_t". + */ +void DAC12_GetDefaultConfig(dac12_config_t *config); + +/*! + * @brief De-initialize the DAC12 module. + * + * @param base DAC12 peripheral base address. + */ +void DAC12_Deinit(DAC_Type *base); + +/*! + * @brief Enable the DAC12's converter or not. + * + * @param base DAC12 peripheral base address. + * @param enable Enable the DAC12's converter or not. + */ +static inline void DAC12_Enable(DAC_Type *base, bool enable) +{ + if (enable) + { + base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DACEN_MASK; + } + else + { + base->CR &= ~DAC_CR_DACEN_MASK; + } +} + +/*! + * @brief Reset all internal logic and registers. + * + * @param base DAC12 peripheral base address. + */ +static inline void DAC12_ResetConfig(DAC_Type *base) +{ + base->CR = DAC_CR_SWRST_MASK; +} + +/*! + * @brief Reset the FIFO pointers. + * + * FIFO pointers should only be reset when the DAC12 is disabled. This function can be used to configure both pointers + * to the same address to reset the FIFO as empty. + * + * @param base DAC12 peripheral base address. + */ +static inline void DAC12_ResetFIFO(DAC_Type *base) +{ + /* FIFO pointers should only be reset when the module is disabled. */ + base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_FIFORST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base DAC12 peripheral base address. + * @return Mask of current status flags. See to #_dac12_status_flags. + */ +static inline uint32_t DAC12_GetStatusFlags(DAC_Type *base) +{ + return (DAC12_CR_ALL_FLAGS_MASK & base->CR); +} + +/*! + * @brief Clear status flags. + * + * Note: Not all the flags can be cleared by this API. Several flags need special condition to clear them according to + * target chip's reference manual document. + * + * @param base DAC12 peripheral base address. + * @param flags Mask of status flags to be cleared. See to #_dac12_status_flags. + */ +static inline void DAC12_ClearStatusFlags(DAC_Type *base, uint32_t flags) +{ + base->CR |= (flags & DAC12_CR_W1C_FLAGS_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base DAC12 peripheral base address. + * @param mask Mask value of interrupts to be enabled. See to #_dac12_interrupt_enable. + */ +static inline void DAC12_EnableInterrupts(DAC_Type *base, uint32_t mask) +{ + base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base DAC12 peripheral base address. + * @param mask Mask value of interrupts to be disabled. See to #_dac12_interrupt_enable. + */ +static inline void DAC12_DisableInterrupts(DAC_Type *base, uint32_t mask) +{ + base->CR &= ~mask; +} + +/* @} */ + +/*! + * @name DMA control + * @{ + */ + +/*! + * @brief Enable DMA or not. + * + * When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented + * on this module at the same time. + */ +static inline void DAC12_EnableDMA(DAC_Type *base, bool enable) +{ + if (enable) + { + base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_DMAEN_MASK; + } + else + { + base->CR &= ~DAC_CR_DMAEN_MASK; + } +} + +/* @} */ + +/*! + * @name Functional feature + * @{ + */ + +/*! + * @brief Set data into the entry of FIFO buffer. + * + * When the DAC FIFO is disabled, and the one entry buffer is enabled, the DAC converts the data in the buffer to analog + * output voltage. Any write to the DATA register will replace the data in the buffer and push data to analog conversion + * without trigger support. + * When the DAC FIFO is enabled. Writing data would increase the write pointer of FIFO. Also, the data would be restored + * into the FIFO buffer. + * + * @param base DAC12 peripheral base address. + * @param value Setting value into FIFO buffer. + */ +static inline void DAC12_SetData(DAC_Type *base, uint32_t value) +{ + /* The module is connected internally to a 32-bit interface. + * For the 8-bit or 16-bit, the write might be ignored. */ + base->DATA = DAC_DATA_DATA0(value); +} + +/*! + * @brief Do trigger the FIFO by software. + * + * When the DAC FIFO is enabled, and software trigger is used. Doing trigger would increase the read pointer, and the + * data in the entry pointed by read pointer would be converted as new output. + * + * @param base DAC12 peripheral base address. + */ +static inline void DAC12_DoSoftwareTrigger(DAC_Type *base) +{ + base->CR = (base->CR & ~DAC12_CR_W1C_FLAGS_MASK) | DAC_CR_SWTRG_MASK; +} + +/*! + * @brief Get the current read pointer of FIFO. + * + * @param base DAC12 peripheral base address. + * @return Read pointer index of FIFO buffer. + */ +static inline uint32_t DAC12_GetFIFOReadPointer(DAC_Type *base) +{ + return (DAC_PTR_DACRFP_MASK & base->PTR) >> DAC_PTR_DACRFP_SHIFT; +} + +/*! + * @brief Get the current write pointer of FIFO. + * + * @param base DAC12 peripheral base address. + * @return Write pointer index of FIFO buffer + */ +static inline uint32_t DAC12_GetFIFOWritePointer(DAC_Type *base) +{ + return (DAC_PTR_DACWFP_MASK & base->PTR) >> DAC_PTR_DACWFP_SHIFT; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_DAC12_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_lpadc.h b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_lpadc.h index 386102a5a6..d3e5a9ec30 100644 --- a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_lpadc.h +++ b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_lpadc.h @@ -1,964 +1,964 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_LPADC_H_ -#define _FSL_LPADC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpadc - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPADC driver version 2.5.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) -/*@}*/ - -/*! - * @brief Define the MACRO function to get command status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) - -/*! - * @brief Define the MACRO function to get trigger status from status value. - * - * The statusVal is the return value from LPADC_GetStatusFlags(). - */ -#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result - FIFO 0 than it can hold. */ - kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 0 is greater than the setting watermark level. */ - kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result - FIFO 1 than it can hold. */ - kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result - FIFO 1 is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF0 flag is asserted. */ - kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY0 flag is asserted. */ - kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF1 flag is asserted. */ - kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY1 flag is asserted. */ -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) - kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception - interrupt. */ - kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt - when trigger 0 completion. */ - kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt - when trigger 1 completion. */ - kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt - when trigger 2 completion. */ - kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt - when trigger 3 completion. */ - kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt - when trigger 4 completion. */ - kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt - when trigger 5 completion. */ - kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt - when trigger 6 completion. */ - kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt - when trigger 7 completion. */ - kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt - when trigger 8 completion. */ - kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt - when trigger 9 completion. */ - kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt - when trigger 10 completion. */ - kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt - when trigger 11 completion. */ - kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt - when trigger 12 completion. */ - kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt - when trigger 13 completion. */ - kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt - when trigger 14 completion. */ - kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt - when trigger 15 completion. */ -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ -}; -#else -/*! - * @brief Define hardware flags of the module. - */ -enum _lpadc_status_flags -{ - kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO - than it can hold. */ - kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO - is greater than the setting watermark level. */ -}; - -/*! - * @brief Define interrupt switchers of the module. - */ -enum _lpadc_interrupt_enable -{ - kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt - requests when FOF flag is asserted. */ - kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt - requests when RDY flag is asserted. */ -}; -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. - */ -enum _lpadc_trigger_status_flags -{ - kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ - kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ - kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ - kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ - kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ - kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ - kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ - kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ - kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ - kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ - kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ - kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ - kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ - kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ - kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ - kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ - - kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and - trigger 0 has enabled completion interrupts. */ - kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and - trigger 1 has enabled completion interrupts. */ - kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and - trigger 2 has enabled completion interrupts. */ - kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and - trigger 3 has enabled completion interrupts. */ - kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and - trigger 4 has enabled completion interrupts. */ - kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and - trigger 5 has enabled completion interrupts. */ - kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and - trigger 6 has enabled completion interrupts. */ - kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and - trigger 7 has enabled completion interrupts. */ - kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and - trigger 8 has enabled completion interrupts. */ - kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and - trigger 9 has enabled completion interrupts. */ - kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and - trigger 10 has enabled completion interrupts. */ - kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and - trigger 11 has enabled completion interrupts. */ - kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and - trigger 12 has enabled completion interrupts. */ - kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and - trigger 13 has enabled completion interrupts. */ - kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and - trigger 14 has enabled completion interrupts. */ - kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and - trigger 15 has enabled completion interrupts. */ -}; -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/*! - * @brief Define enumeration of sample scale mode. - * - * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum - * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the - * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows - * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. - */ -typedef enum _lpadc_sample_scale_mode -{ - kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ - kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ -} lpadc_sample_scale_mode_t; - -/*! - * @brief Define enumeration of channel sample mode. - * - * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. - */ -typedef enum _lpadc_sample_channel_mode -{ - kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ - kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ -#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE - kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ - kLPADC_SampleChannelDualSingleEndBothSide = - 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ -#endif -} lpadc_sample_channel_mode_t; - -/*! - * @brief Define enumeration of hardware average selection. - * - * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to - * capture temporary results while the averaging iterations are executed. - */ -typedef enum _lpadc_hardware_average_mode -{ - kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ - kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_hardware_average_mode_t; - -/*! - * @brief Define enumeration of sample time selection. - * - * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher - * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption - * when command looping and sequencing is configured and high conversion rates are not required. - */ -typedef enum _lpadc_sample_time_mode -{ - kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ - kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ -} lpadc_sample_time_mode_t; - -/*! - * @brief Define enumeration of hardware compare mode. - * - * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting - * guides operation of the automatic compare function to optionally only store when the compare operation is true. - * When compare is enabled, the conversion result is compared to the compare values. - */ -typedef enum _lpadc_hardware_compare_mode -{ - kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ - kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ - kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ -} lpadc_hardware_compare_mode_t; - -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE -/*! - * @brief Define enumeration of conversion resolution mode. - * - * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #lpadc_sample_channel_mode_t - */ -typedef enum _lpadc_conversion_resolution_mode -{ - kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential - 13-bit conversion with 2’s complement output. */ - kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit - conversion with 2’s complement output. */ -} lpadc_conversion_resolution_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS -/*! - * @brief Define enumeration of conversion averages mode. - * - * Configure the converion average number for auto-calibration. - */ -typedef enum _lpadc_conversion_average_mode -{ - kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ - kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ - kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ - kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ - kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ - kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ - kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ - kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ -} lpadc_conversion_average_mode_t; -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - -/*! - * @brief Define enumeration of reference voltage source. - * - * For detail information, need to check the SoC's specification. - */ -typedef enum _lpadc_reference_voltage_mode -{ - kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ - kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ - kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ -} lpadc_reference_voltage_source_t; - -/*! - * @brief Define enumeration of power configuration. - * - * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be - * possible. Refer to the device data sheet for power and performance capabilities for each setting. - */ -typedef enum _lpadc_power_level_mode -{ - kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ - kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ - kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ - kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ -} lpadc_power_level_mode_t; - -/*! - * @brief Define enumeration of trigger priority policy. - * - * This selection controls how higher priority triggers are handled. - */ -typedef enum _lpadc_trigger_priority_policy -{ - kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command - processing, the current conversion is aborted and the new - command specified by the trigger is started. */ - kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, - the current conversion is completed (including averaging iterations - and compare function if enabled) and stored to the result FIFO - before the higher priority trigger/command is initiated. */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY - kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command - processing, the current command will be completed (averaging, - looping, compare) before servicing the higher priority trigger. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ -} lpadc_trigger_priority_policy_t; - -/*! - * @brief LPADC global configuration. - * - * This structure would used to keep the settings for initialization. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN - bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock - selection logic at the chip level and is optionally used for the ADC clock source. */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ -#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG - bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". - If voltage reference option1 input is above 1.8V, it should be "false". */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ - bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When - enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the - ADC will wait for the current averaging iteration/FIFO storage to complete before - acknowledging stop or wait mode entry. */ -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS - lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ - bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without - startup delays(at the cost of higher DC current consumption). */ - uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered - while the ADC is active and there is a counted delay defined by this field after an - initial trigger transitions the ADC from its Idle state to allow time for the analog - circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must - result in a longer delay than the analog startup time. */ - lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for - conversions.*/ - lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to - lpadc_trigger_priority_policy_t. */ - bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during - command execution sequencing between LOOP iterations, between commands in a sequence, and - between conversions when command is executing in "Compare Until True" configuration. */ - uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay - is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing - function is enabled. The available value range is in 9-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - /* for FIFO0. */ - uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ - /* for FIFO1. */ - uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords - stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag - would be asserted to indicate stored data has reached the programmable threshold. */ -#else - /* for FIFO. */ - uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored - in the ADC Result FIFO is greater than the value in this field, the ready flag would be - asserted to indicate stored data has reached the programmable threshold. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ -} lpadc_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion command. - */ -typedef struct -{ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE - lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ - lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ - uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ - uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. - 1-15 is available, 0 is to terminate the chain after this command. */ - bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number - of times the selected channel is converted consecutively; when enabled, the - "loopCount" field defines how many consecutive channels are converted as part - of the command execution. */ - uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next - command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ - lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ - lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ - - lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ - uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ - uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ -#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG - bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be - automatically executed; when enabled, the active trigger must be asserted again before - executing this command. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ -} lpadc_conv_command_config_t; - -/*! - * @brief Define structure to keep the configuration for conversion trigger. - */ -typedef struct -{ - uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated - trigger event. */ - uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. - When this field is clear, then no delay is incurred. When this field is set to a non-zero - value, the duration for the delay is 2^delayPower ADCK cycles. The available value range - is 4-bit. */ - uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same - priority level setting, the lower order trigger event has the higher priority. The lower - value for this field is for the higher priority, the available value range is 1-bit. */ -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ - uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the - input trigger source or not. THe software trigger is always available. */ -} lpadc_conv_trigger_config_t; - -/*! - * @brief Define the structure to keep the conversion result. - */ -typedef struct -{ - uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ - uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ - uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ - uint16_t convValue; /*!< Data result. */ -} lpadc_conv_result_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -/*! - * @name Initialization & de-initialization. - * @{ - */ - -/*! - * @brief Initializes the LPADC module. - * - * @param base LPADC peripheral base address. - * @param config Pointer to configuration structure. See "lpadc_config_t". - */ -void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for initial configuration. - * - * This function initializes the converter configuration structure with an available settings. The default values are: - * @code - * config->enableInDozeMode = true; - * config->enableAnalogPreliminary = false; - * config->powerUpDelay = 0x80; - * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; - * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; - * config->enableConvPause = false; - * config->convPauseDelay = 0U; - * config->FIFOWatermark = 0U; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConfig(lpadc_config_t *config); - -/*! - * @brief De-initializes the LPADC module. - * - * @param base LPADC peripheral base address. - */ -void LPADC_Deinit(ADC_Type *base); - -/*! - * @brief Switch on/off the LPADC module. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the module. - */ -static inline void LPADC_Enable(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_ADCEN_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_ADCEN_MASK; - } -} - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Do reset the conversion FIFO0. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO0(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; -} - -/*! - * @brief Do reset the conversion FIFO1. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO1(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; -} -#else -/*! - * @brief Do reset the conversion FIFO. - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetFIFO(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RSTFIFO_MASK; -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Do reset the module's configuration. - * - * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). - * - * @param base LPADC peripheral base address. - */ -static inline void LPADC_DoResetConfig(ADC_Type *base) -{ - base->CTRL |= ADC_CTRL_RST_MASK; - base->CTRL &= ~ADC_CTRL_RST_MASK; -} - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get status flags. - * - * @param base LPADC peripheral base address. - * @return status flags' mask. See to #_lpadc_status_flags. - */ -static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) -{ - return base->STAT; -} - -/*! - * @brief Clear status flags. - * - * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. - */ -static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->STAT = mask; -} - -#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) -/*! - * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high - * priority trigger exception. - * - * @param base LPADC peripheral base address. - * @return The OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) -{ - return base->TSTAT; -} - -/*! - * @brief Clear trigger status flags. - * - * @param base LPADC peripheral base address. - * @param mask The mask of trigger status flags to be cleared, should be the - * OR'ed value of @ref _lpadc_trigger_status_flags. - */ -static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) -{ - base->TSTAT = mask; -} -#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE |= mask; -} - -/*! - * @brief Disable interrupts. - * - * @param base LPADC peripheral base address. - * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. - */ -static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) -{ - base->IE &= ~mask; -} - -/*! - * @name DMA Control - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Switch on/off the DMA trigger for FIFO0 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE0_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE0_MASK; - } -} - -/*! - * @brief Switch on/off the DMA trigger for FIFO1 watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE1_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE1_MASK; - } -} -#else -/*! - * @brief Switch on/off the DMA trigger for FIFO watermark event. - * - * @param base LPADC peripheral base address. - * @param enable Switcher to the event. - */ -static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) -{ - if (enable) - { - base->DE |= ADC_DE_FWMDE_MASK; - } - else - { - base->DE &= ~ADC_DE_FWMDE_MASK; - } -} -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - /* @} */ - -/*! - * @name Trigger and conversion with FIFO. - * @{ - */ - -#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) -/*! - * @brief Get the count of result kept in conversion FIFOn. - * - * @param base LPADC peripheral base address. - * @param index Result FIFO index. - * @return The count of result kept in conversion FIFOn. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * brief Get the result in conversion FIFOn. - * - * param base LPADC peripheral base address. - * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. - * param index Result FIFO index. - * - * return Status whether FIFOn entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); -#else -/*! - * @brief Get the count of result kept in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @return The count of result kept in conversion FIFO. - */ -static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) -{ - return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; -} - -/*! - * @brief Get the result in conversion FIFO. - * - * @param base LPADC peripheral base address. - * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. - * - * @return Status whether FIFO entry is valid. - */ -bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); -#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ - -/*! - * @brief Configure the conversion trigger source. - * - * Each programmable trigger can launch the conversion command in command buffer. - * - * @param base LPADC peripheral base address. - * @param triggerId ID for each trigger. Typically, the available value range is from 0. - * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. - */ -void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for trigger's configuration. - * - * This function initializes the trigger's configuration structure with an available settings. The default values are: - * @code - * config->commandIdSource = 0U; - * config->loopCountIndex = 0U; - * config->triggerIdSource = 0U; - * config->enableHardwareTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); - -/*! - * @brief Do software trigger to conversion command. - * - * @param base LPADC peripheral base address. - * @param triggerIdMask Mask value for software trigger indexes, which count from zero. - */ -static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) -{ - /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ - base->SWTRIG = triggerIdMask; -} - -/*! - * @brief Configure conversion command. - * - * @param base LPADC peripheral base address. - * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. - * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. - */ -void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); - -/*! - * @brief Gets an available pre-defined settings for conversion command's configuration. - * - * This function initializes the conversion command's configuration structure with an available settings. The default - * values are: - * @code - * config->sampleScaleMode = kLPADC_SampleFullScale; - * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; - * config->channelNumber = 0U; - * config->chainedNextCmdNumber = 0U; - * config->enableAutoChannelIncrement = false; - * config->loopCount = 0U; - * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; - * config->sampleTimeMode = kLPADC_SampleTimeADCK3; - * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; - * config->hardwareCompareValueHigh = 0U; - * config->hardwareCompareValueLow = 0U; - * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; - * config->enableWaitTrigger = false; - * @endcode - * @param config Pointer to configuration structure. - */ -void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); - -#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS -/*! - * @brief Enable the calibration function. - * - * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes - * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value - * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- - * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the - * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -void LPADC_EnableCalibration(ADC_Type *base, bool enable); -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * To minimize the offset during normal operation, software should read the conversion result from - * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. - * - * @param base LPADC peripheral base address. - * @param value Setting offset value. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) -{ - base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; -} - -/*! - * @brief Do auto calibration. - * - * Calibration function should be executed before using converter in application. It used the software trigger and a - * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API - * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) - * -LPADC_SetConvTriggerConfig(...) - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ -#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS -#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM -/*! - * @brief Set proper offset value to trim ADC. - * - * Set the offset trim value for offset calibration manually. - * - * @param base LPADC peripheral base address. - * @param valueA Setting offset value A. - * @param valueB Setting offset value B. - * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. - */ -static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) -{ - base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); -} -#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ - -/*! - * @brief Enable the offset calibration function. - * - * @param base LPADC peripheral base address. - * @param enable switcher to the calibration function. - */ -static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) -{ - if (enable) - { - base->CTRL |= ADC_CTRL_CALOFS_MASK; - } - else - { - base->CTRL &= ~ADC_CTRL_CALOFS_MASK; - } -} - -/*! - * @brief Do offset calibration. - * - * @param base LPADC peripheral base address. - */ -void LPADC_DoOffsetCalibration(ADC_Type *base); - -#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ -/*! - * brief Do auto calibration. - * - * param base LPADC peripheral base address. - */ -void LPADC_DoAutoCalibration(ADC_Type *base); -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ -#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! - * @} - */ -#endif /* _FSL_LPADC_H_ */ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPADC_H_ +#define _FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPADC driver version 2.5.1. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) +/*@}*/ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) + kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception + interrupt. */ + kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt + when trigger 0 completion. */ + kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt + when trigger 1 completion. */ + kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt + when trigger 2 completion. */ + kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt + when trigger 3 completion. */ + kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt + when trigger 4 completion. */ + kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt + when trigger 5 completion. */ + kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt + when trigger 6 completion. */ + kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt + when trigger 7 completion. */ + kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt + when trigger 8 completion. */ + kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt + when trigger 9 completion. */ + kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt + when trigger 10 completion. */ + kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt + when trigger 11 completion. */ + kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt + when trigger 12 completion. */ + kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt + when trigger 13 completion. */ + kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt + when trigger 14 completion. */ + kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt + when trigger 15 completion. */ +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +}; +#else +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO + than it can hold. */ + kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO + is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF flag is asserted. */ + kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY flag is asserted. */ +}; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ + kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ + kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ +#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ + kLPADC_SampleChannelDualSingleEndBothSide = + 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ +#endif +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #lpadc_sample_channel_mode_t + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2’s complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2’s complement output. */ +} lpadc_conversion_resolution_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_conversion_average_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started. */ + kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, + the current conversion is completed (including averaging iterations + and compare function if enabled) and stored to the result FIFO + before the higher priority trigger/command is initiated. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY + kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ +} lpadc_trigger_priority_policy_t; + +/*! + * @brief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->TSTAT = mask; +} +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + /* @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +/*! + * @brief Configure conversion command. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_semc.h b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_semc.h index 68fb9291d3..e6efec0d8e 100644 --- a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_semc.h +++ b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/drivers/fsl_semc.h @@ -1,924 +1,924 @@ -/* - * Copyright 2017-2022 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_SEMC_H_ -#define _FSL_SEMC_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup semc - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief SEMC driver version. */ -#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) -/*@}*/ - -/*! @brief SEMC status, _semc_status. */ -enum -{ - kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */ - kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */ - kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */ - kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */ - kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */ - kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */ - kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */ - kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */ - kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */ - /*! Invalid column address bit width. */ - kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), - kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */ - kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */ -}; - -/*! @brief SEMC memory device type. */ -typedef enum _semc_mem_type -{ - kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ - kSEMC_MemType_SRAM, /*!< SRAM */ - kSEMC_MemType_NOR, /*!< NOR */ - kSEMC_MemType_NAND, /*!< NAND */ - kSEMC_MemType_8080 /*!< 8080. */ -} semc_mem_type_t; - -/*! @brief SEMC WAIT/RDY polarity. */ -typedef enum _semc_waitready_polarity -{ - kSEMC_LowActive = 0, /*!< Low active. */ - kSEMC_HighActive, /*!< High active. */ -} semc_waitready_polarity_t; - -/*! @brief SEMC SDRAM Chip selection . */ -typedef enum _semc_sdram_cs -{ - kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ - kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ - kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ - kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ -} semc_sdram_cs_t; - -/*! @brief SEMC SRAM Chip selection . */ -typedef enum _semc_sram_cs -{ -#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U) - kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ - kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */ - kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */ - kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */ -#else - kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ -#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */ -} semc_sram_cs_t; - -/*! @brief SEMC NAND device type. */ -typedef enum _semc_nand_access_type -{ - kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */ - kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */ -} semc_nand_access_type_t; - -/*! @brief SEMC interrupts . */ -typedef enum _semc_interrupt_enable -{ - kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ - kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ - kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ - kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ -} semc_interrupt_enable_t; - -/*! @brief SEMC IP command data size in bytes. */ -typedef enum _semc_ipcmd_datasize -{ - kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ - kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ - kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ - kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ -} semc_ipcmd_datasize_t; - -/*! @brief SEMC auto-refresh timing. */ -typedef enum _semc_refresh_time -{ - kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ - kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ - kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ -} semc_refresh_time_t; - -/*! @brief CAS latency */ -typedef enum _semc_caslatency -{ - kSEMC_LatencyOne = 1, /*!< Latency 1. */ - kSEMC_LatencyTwo, /*!< Latency 2. */ - kSEMC_LatencyThree, /*!< Latency 3. */ -} semc_caslatency_t; - -/*! @brief SEMC sdram column address bit number. */ -typedef enum _semc_sdram_column_bit_num -{ - kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_SdramColunm_11bit, /*!< 11 bit. */ - kSEMC_SdramColunm_10bit, /*!< 10 bit. */ - kSEMC_SdramColunm_9bit, /*!< 9 bit. */ -#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) - kSEMC_SdramColunm_8bit, /*!< 8 bit. */ -#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */ -} semc_sdram_column_bit_num_t; - -/*! @brief SEMC sdram burst length. */ -typedef enum _semc_sdram_burst_len -{ -/*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during - long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */ -#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U) - kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ -#else - kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ - kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ - kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ -#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */ -} sem_sdram_burst_len_t; - -/*! @brief SEMC nand column address bit number. */ -typedef enum _semc_nand_column_bit_num -{ - kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ - kSEMC_NandColum_15bit, /*!< 15 bit. */ - kSEMC_NandColum_14bit, /*!< 14 bit. */ - kSEMC_NandColum_13bit, /*!< 13 bit. */ - kSEMC_NandColum_12bit, /*!< 12 bit. */ - kSEMC_NandColum_11bit, /*!< 11 bit. */ - kSEMC_NandColum_10bit, /*!< 10 bit. */ - kSEMC_NandColum_9bit, /*!< 9 bit. */ -} semc_nand_column_bit_num_t; - -/*! @brief SEMC nand burst length. */ -typedef enum _semc_nand_burst_len -{ - kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ - kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ - kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ - kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ - kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ - kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ -} sem_nand_burst_len_t; - -/*! @brief SEMC nor/sram column address bit number. */ -typedef enum _semc_norsram_column_bit_num -{ - kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_NorColum_11bit, /*!< 11 bit. */ - kSEMC_NorColum_10bit, /*!< 10 bit. */ - kSEMC_NorColum_9bit, /*!< 9 bit. */ - kSEMC_NorColum_8bit, /*!< 8 bit. */ - kSEMC_NorColum_7bit, /*!< 7 bit. */ - kSEMC_NorColum_6bit, /*!< 6 bit. */ - kSEMC_NorColum_5bit, /*!< 5 bit. */ - kSEMC_NorColum_4bit, /*!< 4 bit. */ - kSEMC_NorColum_3bit, /*!< 3 bit. */ - kSEMC_NorColum_2bit /*!< 2 bit. */ -} semc_norsram_column_bit_num_t; - -/*! @brief SEMC nor/sram burst length. */ -typedef enum _semc_norsram_burst_len -{ - kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ - kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ - kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ - kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ - kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ - kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ -} sem_norsram_burst_len_t; - -/*! @brief SEMC dbi column address bit number. */ -typedef enum _semc_dbi_column_bit_num -{ - kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ - kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ - kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ - kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ - kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ - kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ - kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ - kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ - kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ - kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ - kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ -} semc_dbi_column_bit_num_t; - -/*! @brief SEMC dbi burst length. */ -typedef enum _semc_dbi_burst_len -{ - kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ - kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ - kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ - kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ - kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ - kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ - kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ -} sem_dbi_burst_len_t; - -/*! @brief SEMC IOMUXC. */ -typedef enum _semc_iomux_pin -{ - kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ - kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ - kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ - kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ - kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ - kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ -} semc_iomux_pin; - -/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ -typedef enum _semc_iomux_nora27_pin -{ - kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ - kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ - kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ -} semc_iomux_nora27_pin; - -/*! @brief SEMC port size. */ -typedef enum _semc_port_size -{ - kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ - kSEMC_PortSize16Bit, /*!< 16-Bit port size. */ -#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U) - kSEMC_PortSize32Bit /*!< 32-Bit port size. */ -#endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */ -} smec_port_size_t; - -/*! @brief SEMC address mode. */ -typedef enum _semc_addr_mode -{ - kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ - kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ - kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ -} semc_addr_mode_t; - -/*! @brief SEMC DQS read strobe mode. */ -typedef enum _semc_dqs_mode -{ - kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ - kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ -} semc_dqs_mode_t; - -/*! @brief SEMC ADV signal active polarity. */ -typedef enum _semc_adv_polarity -{ - kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ - kSEMC_AdvActiveHigh, /*!< Adv active high. */ -} semc_adv_polarity_t; - -/*! @brief SEMC sync mode. */ -typedef enum _semc_sync_mode -{ - kSEMC_AsyncMode = 0, /*!< Async mode. */ - kSEMC_SyncMode, /*!< Sync mode. */ -} semc_sync_mode_t; - -/*! @brief SEMC ADV signal level control. */ -typedef enum _semc_adv_level_control -{ - kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */ - kSEMC_AdvLow, /*!< Adv is low during address hold state. */ -} semc_adv_level_control_t; - -/*! @brief SEMC RDY signal active polarity. */ -typedef enum _semc_rdy_polarity -{ - kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ - kSEMC_RdyActivehigh, /*!< Adv active low. */ -} semc_rdy_polarity_t; - -/*! @brief SEMC IP command for NAND: address mode. */ -typedef enum _semc_ipcmd_nand_addrmode -{ - kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ - kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ - kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ - kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ - kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ - kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ -} semc_ipcmd_nand_addrmode_t; - -/*! @brief SEMC IP command for NAND： command mode. */ -typedef enum _semc_ipcmd_nand_cmdmode -{ - kSEMC_NANDCM_Command = 0x2U, /*!< command. */ - kSEMC_NANDCM_CommandHold, /*!< Command hold. */ - kSEMC_NANDCM_CommandAddress, /*!< Command address. */ - kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ - kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ - kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ - kSEMC_NANDCM_CommandRead, /*!< Command read. */ - kSEMC_NANDCM_CommandWrite, /*!< Command write. */ - kSEMC_NANDCM_Read, /*!< Read. */ - kSEMC_NANDCM_Write /*!< Write. */ -} semc_ipcmd_nand_cmdmode_t; - -/*! @brief SEMC NAND address option. */ -typedef enum _semc_nand_address_option -{ - kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ - kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ - kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ - kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ - kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ - kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ -} semc_nand_address_option_t; - -/*! @brief SEMC IP command for NOR. */ -typedef enum _semc_ipcmd_nor_dbi -{ - kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ - kSEMC_NORDBICM_Write /*!< NOR write. */ -} semc_ipcmd_nor_dbi_t; - -/*! @brief SEMC IP command for SRAM. */ -typedef enum _semc_ipcmd_sram -{ - kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ - kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ - kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ - kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ -} semc_ipcmd_sram_t; - -/*! @brief SEMC IP command for SDARM. */ -typedef enum _semc_ipcmd_sdram -{ - kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ - kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ - kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ - kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ - kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ - kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ - kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ - kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ -} semc_ipcmd_sdram_t; - -/*! @brief SEMC SDRAM configuration structure. - * - * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes - * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. - * Take refer to BR0~BR3 register in RM for details. - * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, - * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, - * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. - * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are - * similar to prescalePeriod_N16Cycle. - * - */ -typedef struct _semc_sdram_config -{ - semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - smec_port_size_t portSize; /*!< Port size. */ - sem_sdram_burst_len_t burstLen; /*!< Burst length. */ - semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_caslatency_t casLatency; /*!< CAS latency. */ - uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ - uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ - uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ - uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ - uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ - uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ - uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ - uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ - uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ - uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ - uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ - uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ - uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ - uint8_t refreshBurstLen; /*!< Refresh burst length. */ -#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) - uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than - read data. */ -#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ -} semc_sdram_config_t; - -/*! @brief SEMC NAND device timing configuration structure. */ -typedef struct _semc_nand_timing_config -{ - uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ - uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ - uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ - uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ - uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ - uint8_t tReLow_Ns; /*!< RE low time: tRP. */ - uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ - uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ - uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ - uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ - uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ - uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ -} semc_nand_timing_config_t; - -/*! @brief SEMC NAND configuration structure. */ -typedef struct _semc_nand_config -{ - semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ - uint32_t axiAddress; /*!< The base address for AXI nand. */ - uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ - uint32_t ipgAddress; /*!< The base address for IPG nand . */ - uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ - semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ - bool edoModeEnabled; /*!< EDO mode enabled. */ - semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ - sem_nand_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ -} semc_nand_config_t; - -/*! @brief SEMC NOR configuration structure. */ -typedef struct _semc_nor_config -{ - semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ - semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - uint8_t addrPortWidth; /*!< The address port width. */ - semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ - semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ - semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ - semc_addr_mode_t addrMode; /*!< Address mode. */ - sem_norsram_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ - uint8_t tCeSetup_Ns; /*!< The CE setup time. */ - uint8_t tCeHold_Ns; /*!< The CE hold time. */ - uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ - uint8_t tAddrSetup_Ns; /*!< The address setup time. */ - uint8_t tAddrHold_Ns; /*!< The address hold time. */ - uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ - uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ - uint8_t tReLow_Ns; /*!< RE low time for async mode. */ - uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ - uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ -#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) - uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ -#endif -#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) - uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ -#endif -#if defined(FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) - uint8_t latencyCount; /*!< Latency count for sync mode. */ -#endif -#if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) - uint8_t readCycle; /*!< Read cycle time for sync mode. */ -#endif -#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) - uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than - read data. */ -#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ -} semc_nor_config_t; - -/*! @brief SEMC SRAM configuration structure. */ -typedef struct _semc_sram_config -{ - semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ - semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ - uint32_t address; /*!< The base address. */ - uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ - uint8_t addrPortWidth; /*!< The address port width. */ - semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ - semc_addr_mode_t addrMode; /*!< Address mode. */ - sem_norsram_burst_len_t burstLen; /*!< Burst length. */ - smec_port_size_t portSize; /*!< Port size. */ -#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK) - semc_sync_mode_t syncMode; /*!< Sync mode. */ -#endif /* SEMC_SRAMCR4_SYNCEN_MASK */ -#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK) - bool waitEnable; /*!< Wait enable. */ -#endif /* SEMC_SRAMCR0_WAITEN_MASK */ -#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK) - uint8_t waitSample; /*!< Wait sample. */ -#endif /* SEMC_SRAMCR0_WAITSP_MASK */ -#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK) - semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */ -#endif /* SEMC_SRAMCR4_ADVH_MASK */ - uint8_t tCeSetup_Ns; /*!< The CE setup time. */ - uint8_t tCeHold_Ns; /*!< The CE hold time. */ - uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ -#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) - uint8_t readHoldTime_Ns; /*!< read hold time. */ -#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */ - uint8_t tAddrSetup_Ns; /*!< The address setup time. */ - uint8_t tAddrHold_Ns; /*!< The address hold time. */ - uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ - uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ - uint8_t tReLow_Ns; /*!< RE low time for async mode. */ - uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ - uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ - uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ -#if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) - uint8_t tWriteSetup_Ns; /*!INTEN |= mask; -} - -/*! - * @brief Disables the SEMC interrupt. - * - * This function disables the SEMC interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. - * For example, to disable the IP command done and error interrupt, do the following. - * @code - * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); - * @endcode - * - * @param base SEMC peripheral base address. - * @param mask SEMC interrupts to disable. This is a logical OR of the - * enumeration :: semc_interrupt_enable_t. - */ -static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) -{ - base->INTEN &= ~mask; -} - -/*! - * @brief Gets the SEMC status. - * - * This function gets the SEMC interrupts event status. - * User can use the a logical OR of enumeration member as a mask. - * See @ref semc_interrupt_enable_t. - * - * @param base SEMC peripheral base address. - * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. - */ -static inline bool SEMC_GetStatusFlag(SEMC_Type *base) -{ - return (base->INTR != 0x00U) ? true : false; -} - -/*! - * @brief Clears the SEMC status flag state. - * - * The following status register flags can be cleared SEMC interrupt status. - * - * @param base SEMC base pointer - * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. - */ -static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) -{ - base->INTR |= mask; -} - -/* @} */ - -/*! - * @name SEMC Memory Access Operation - * @{ - */ - -/*! - * @brief Check if SEMC is in idle. - * - * @param base SEMC peripheral base address. - * @return True SEMC is in idle, false is not in idle. - */ -static inline bool SEMC_IsInIdle(SEMC_Type *base) -{ - return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false; -} - -/*! - * @brief SEMC IP command access. - * - * @param base SEMC peripheral base address. - * @param memType SEMC memory type. refer to "semc_mem_type_t" - * @param address SEMC device address. - * @param command SEMC IP command. - * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. - * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". - * For SRAM device, take refer to "semc_ipcmd_sram_t". - * For SDRAM device, take refer to "semc_ipcmd_sdram_t". - * @param write Data for write access. - * @param read Data pointer for read data out. - */ -status_t SEMC_SendIPCommand( - SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read); - -/*! - * @brief Build SEMC IP command for NAND. - * - * This function build SEMC NAND IP command. The command is build of user command code, - * SEMC address mode and SEMC command mode. - * - * @param userCommand NAND device normal command. - * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". - * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". - */ -static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, - semc_ipcmd_nand_addrmode_t addrMode, - semc_ipcmd_nand_cmdmode_t cmdMode) -{ - return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU); -} - -/*! - * @brief Check if the NAND device is ready. - * - * @param base SEMC peripheral base address. - * @return True NAND is ready, false NAND is not ready. - */ -static inline bool SEMC_IsNandReady(SEMC_Type *base) -{ - return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false; -} - -/*! - * @brief SEMC NAND device memory write through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NAND device address. - * @param data Data for write access. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NAND device memory read through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NAND device address. - * @param data Data pointer for data read out. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NOR device memory write through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NOR device address. - * @param data Data for write access. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/*! - * @brief SEMC NOR device memory read through IP command. - * - * @param base SEMC peripheral base address. - * @param address SEMC NOR device address. - * @param data Data pointer for data read out. - * @param size_bytes Data length. - */ -status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_SEMC_H_*/ +/* + * Copyright 2017-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) +/*@}*/ + +/*! @brief SEMC status, _semc_status. */ +enum +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */ + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */ + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */ + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */ + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */ + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */ + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */ + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */ + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */ + /*! Invalid column address bit width. */ + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */ + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */ +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type +{ + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity +{ + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs +{ + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC SRAM Chip selection . */ +typedef enum _semc_sram_cs +{ +#if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U) + kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ + kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */ + kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */ + kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */ +#else + kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ +#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */ +} semc_sram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type +{ + kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */ + kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */ +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable +{ + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize +{ + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time +{ + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency +{ + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num +{ + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +#if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) + kSEMC_SdramColunm_8bit, /*!< 8 bit. */ +#endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len +{ +/*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during + long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */ +#if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U) + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ +#else + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +#endif /* FSL_FEATURE_SEMC_ERRATA_050577 */ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num +{ + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len +{ + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num +{ + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len +{ + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num +{ + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len +{ + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin +{ + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin +{ + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size +{ + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit, /*!< 16-Bit port size. */ +#if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U) + kSEMC_PortSize32Bit /*!< 32-Bit port size. */ +#endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode +{ + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode +{ + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity +{ + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActiveHigh, /*!< Adv active high. */ +} semc_adv_polarity_t; + +/*! @brief SEMC sync mode. */ +typedef enum _semc_sync_mode +{ + kSEMC_AsyncMode = 0, /*!< Async mode. */ + kSEMC_SyncMode, /*!< Sync mode. */ +} semc_sync_mode_t; + +/*! @brief SEMC ADV signal level control. */ +typedef enum _semc_adv_level_control +{ + kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */ + kSEMC_AdvLow, /*!< Adv is low during address hold state. */ +} semc_adv_level_control_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity +{ + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode +{ + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode +{ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option +{ + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi +{ + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram +{ + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram +{ + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) + uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than + read data. */ +#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ +} semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) + uint8_t latencyCount; /*!< Latency count for sync mode. */ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) + uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than + read data. */ +#endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ +#if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK) + semc_sync_mode_t syncMode; /*!< Sync mode. */ +#endif /* SEMC_SRAMCR4_SYNCEN_MASK */ +#if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK) + bool waitEnable; /*!< Wait enable. */ +#endif /* SEMC_SRAMCR0_WAITEN_MASK */ +#if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK) + uint8_t waitSample; /*!< Wait sample. */ +#endif /* SEMC_SRAMCR0_WAITSP_MASK */ +#if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK) + semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */ +#endif /* SEMC_SRAMCR4_ADVH_MASK */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ +#if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) + uint8_t readHoldTime_Ns; /*!< read hold time. */ +#endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return (base->INTR != 0x00U) ? true : false; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param memType SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/utilities/debug_console/fsl_debug_console_conf.h b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/utilities/debug_console/fsl_debug_console_conf.h index 179fe8e116..fd235b1e54 100644 --- a/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/utilities/debug_console/fsl_debug_console_conf.h +++ b/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/utilities/debug_console/fsl_debug_console_conf.h @@ -1,160 +1,160 @@ -/* - * Copyright 2017 - 2020 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ -#define _FSL_DEBUG_CONSOLE_CONF_H_ - -#include "fsl_common.h" - -/****************Debug console configuration********************/ - -/*! @brief If Non-blocking mode is needed, please define it at project setting, - * otherwise blocking mode is the default transfer mode. - * Warning: If you want to use non-blocking transfer,please make sure the corresponding - * IO interrupt is enable, otherwise there is no output. - * And non-blocking is combine with buffer, no matter bare-metal or rtos. - * Below shows how to configure in your project if you want to use non-blocking mode. - * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". - * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". - * For ARMGCC, open CmakeLists.txt and add the following lines, - * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. - * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. - * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C - * Complier->Preprocessor". - * - */ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically - * when - * non-blocking transfer is using, - * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. - * If it is configured too small, log maybe missed , because the log will not be - * buffered if the buffer is full, and the print will return immediately with -1. - * And this value should be multiple of 4 to meet memory alignment. - * - */ -#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN -#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) -#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ - -/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when - * non-blocking transfer is using, - * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. - * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. - * And this value should be multiple of 4 to meet memory alignment. - * - */ -#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN -#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) -#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ - -/*!@ brief Whether enable the reliable TX function - * If the macro is zero, the reliable TX function of the debug console is disabled. - * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. - */ -#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE -#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) -#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ - -#else -#define DEBUG_CONSOLE_TRANSFER_BLOCKING -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/*!@ brief Whether enable the RX function - * If the macro is zero, the receive function of the debug console is disabled. - */ -#ifndef DEBUG_CONSOLE_RX_ENABLE -#define DEBUG_CONSOLE_RX_ENABLE (1U) -#endif /* DEBUG_CONSOLE_RX_ENABLE */ - -/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log - * length can not bigger than this value. - * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if - * the buffer is too big and current task stack size not big enough. - */ -#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN -#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) -#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ - -/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log - * length can not bigger than this value. - * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. - */ -#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN -#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) -#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ - -/*! @brief Debug console synchronization - * User should not change these macro for synchronization mode, but add the - * corresponding synchronization mechanism per different software environment. - * Such as, if another RTOS is used, - * add: - * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 - * in this configuration file and implement the synchronization in fsl.log.c. - */ -/*! @brief synchronization for baremetal software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 -/*! @brief synchronization for freertos software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 - -/*! @brief RTOS synchronization mechanism disable - * If not defined, default is enable, to avoid multitask log print mess. - * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c - * If synchronization is disabled, log maybe messed on terminal. - */ -#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#ifdef SDK_OS_FREE_RTOS -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* SDK_OS_FREE_RTOS */ -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ - -/*! @brief echo function support - * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO - * at your project setting. - */ -#ifndef DEBUG_CONSOLE_ENABLE_ECHO -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 -#else -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 -#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ - -/*********************************************************************/ - -/***************Debug console other configuration*********************/ -/*! @brief Definition to printf the float number. */ -#ifndef PRINTF_FLOAT_ENABLE -#define PRINTF_FLOAT_ENABLE 0U -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! @brief Definition to scanf the float number. */ -#ifndef SCANF_FLOAT_ENABLE -#define SCANF_FLOAT_ENABLE 0U -#endif /* SCANF_FLOAT_ENABLE */ - -/*! @brief Definition to support advanced format specifier for printf. */ -#ifndef PRINTF_ADVANCED_ENABLE -#define PRINTF_ADVANCED_ENABLE 0U -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Definition to support advanced format specifier for scanf. */ -#ifndef SCANF_ADVANCED_ENABLE -#define SCANF_ADVANCED_ENABLE 0U -#endif /* SCANF_ADVANCED_ENABLE */ - -/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ -#ifndef BOARD_USE_VIRTUALCOM -#define BOARD_USE_VIRTUALCOM 0U -#endif -/*******************************************************************/ - -#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +#include "fsl_common.h" + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef SDK_OS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* SDK_OS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */