forked from springcute/rt-thread
add NRZ feature on K60
This commit is contained in:
parent
a927b48049
commit
421d980b07
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@ -0,0 +1,43 @@
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HEADERS += \
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../rtconfig.h \
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../drivers/led.h \
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../drivers/drv_uart.h \
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../drivers/board.h \
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../../../components/drivers/include/rtdevice.h \
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../../../components/drivers/include/drivers/serial.h \
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../../../include/rtthread.h \
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../../../include/rtservice.h \
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../../../include/rtm.h \
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../../../include/rthw.h \
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../../../include/rtdef.h \
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../../../include/rtdebug.h \
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../../../src/module.h \
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../../../../../../../../Keil/ARM/INC/Freescale/Kinetis/MK60F12.H
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SOURCES += \
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../applications/startup.c \
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../applications/application.c \
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../drivers/system_MK60F12.c \
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../drivers/led.c \
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../drivers/drv_uart.c \
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../drivers/board.c \
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../../../components/drivers/serial/serial.c \
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../../../src/timer.c \
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../../../src/thread.c \
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../../../src/slab.c \
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../../../src/scheduler.c \
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../../../src/object.c \
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../../../src/module.c \
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../../../src/mempool.c \
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../../../src/memheap.c \
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../../../src/mem.c \
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../../../src/kservice.c \
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../../../src/irq.c \
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../../../src/ipc.c \
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../../../src/idle.c \
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../../../src/device.c \
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../../../src/clock.c
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OTHER_FILES += \
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../drivers/startup_MK60F12.s \
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../../../src/SConscript
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@ -39,52 +39,83 @@ static struct k60_serial_device _k60_node =
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static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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unsigned int reg_C1 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2,reg_BRFA=0;
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unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2,reg_BRFA=0;
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unsigned int cal_SBR = 0;
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UART_Type *uart_reg;
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/* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz */
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/* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
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* calculate baud_rate
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*/
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uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
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//calc SBR
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/* calc SBR */
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cal_SBR = 60000000 / (16 * cfg->baud_rate);
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//calc baud_rate
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/* calc baud_rate */
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reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
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reg_BDL = cal_SBR & 0x00FF;
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//fractional divider
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/* fractional divider */
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reg_BRFA = ((60000*32000)/(cfg->baud_rate * 16)) - (cal_SBR * 32);
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reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
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//calc bit_order
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/*
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* set bit order
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*/
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if (cfg->bit_order == BIT_ORDER_LSB)
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reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
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else if (cfg->bit_order == BIT_ORDER_MSB)
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reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
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//calc data_bits
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/*
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* set data_bits
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*/
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if (cfg->data_bits == DATA_BITS_8)
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reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
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else if (cfg->data_bits == DATA_BITS_9)
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reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
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//clac parity
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/*
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* set parity
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*/
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if (cfg->parity == PARITY_NONE)
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reg_C1 &= ~(UART_C1_PE_MASK<<UART_C1_PE_SHIFT);
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{
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reg_C1 &= ~(UART_C1_PE_MASK);
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}
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else
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{
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reg_C1 &= ~(UART_C1_PE_MASK<<UART_C1_PE_SHIFT);
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/* first ,set parity enable bit */
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reg_C1 |= (UART_C1_PE_MASK);
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/* second ,determine parity odd or even*/
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if (cfg->parity == PARITY_ODD)
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reg_C1 |= UART_C1_PT_MASK<<UART_C1_PT_SHIFT;
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reg_C1 |= UART_C1_PT_MASK;
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if (cfg->parity == PARITY_EVEN)
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reg_C1 &= ~(UART_C1_PT_MASK<<UART_C1_PT_SHIFT);
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reg_C1 &= ~(UART_C1_PT_MASK);
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}
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/*
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* set stop bit
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* not supported on Tower? need ur help!
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*/
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/*
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* set NZR mode
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* not tested
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*/
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if(cfg->invert != NRZ_NORMAL)
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{
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/* not in normal mode ,set inverted polarity */
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reg_C3 |= UART_C3_TXINV_MASK;
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}
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switch( (int)uart_reg)
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{
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/* Tower board use UART5 for communication
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* if you're using other board
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* set clock and pin map for UARTx
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*/
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case UART5_BASE:
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//set UART5 clock
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