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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1817 bbd45198-f89e-11dd-88c7-29a3b14d5316

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fengzi.rtt@gmail.com 2011-11-29 08:06:46 +00:00
parent 819fd97ff8
commit 1b3411abde
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21
bsp/lm4f232/Libraries/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
# The set of source files associated with this SConscript file.
cwd = GetCurrentDir()
src = Glob('driverlib/*.c')
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/gcc/start_gcc.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup/arm/start_rvds.S']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['startup/iar/start_iar.S']
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

35
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#******************************************************************************
#
# Makefile - Rules for building the driver library.
#
# Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
# Software License Agreement
#
# Texas Instruments (TI) is supplying this software for use solely and
# exclusively on TI's microcontroller products. The software is owned by
# TI and/or its suppliers, and is protected under applicable copyright
# laws. You may not combine this software with "viral" open-source
# software in order to form a larger program.
#
# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
# DAMAGES, FOR ANY REASON WHATSOEVER.
#
# This is part of revision 8049 of the Stellaris Peripheral Driver Library.
#
#******************************************************************************
all:
@make -f Makefile.driverlib-cm3
@make -f Makefile.driverlib-cm4f
clean:
@make -f Makefile.driverlib-cm3 clean
@make -f Makefile.driverlib-cm4f clean
realclean:
@make -f Makefile.driverlib-cm3 realclean
@make -f Makefile.driverlib-cm4f realclean

106
bsp/lm4f232/Libraries/driverlib/Makefile.driverlib-cm4f Normal file
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#******************************************************************************
#
# Makefile.driverlib-cm4f - Rules for building the driver library.
#
# Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
# Software License Agreement
#
# Texas Instruments (TI) is supplying this software for use solely and
# exclusively on TI's microcontroller products. The software is owned by
# TI and/or its suppliers, and is protected under applicable copyright
# laws. You may not combine this software with "viral" open-source
# software in order to form a larger program.
#
# THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
# NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
# NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
# CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
# DAMAGES, FOR ANY REASON WHATSOEVER.
#
# This is part of revision 8049 of the Stellaris Peripheral Driver Library.
#
#******************************************************************************
#
# Defines the directory suffix that this project uses.
#
SUFFIX=-cm4f
#
# Set the processor variant.
#
VARIANT=cm4f
#
# The base directory for StellarisWare.
#
ROOT=..
#
# Include the common make definitions.
#
include ${ROOT}/makedefs
#
# Where to find header files that do not live in the source directory.
#
IPATH=..
#
# The default rule, which causes the driver library to be built.
#
all: ${COMPILER}-cm4f
all: ${COMPILER}-cm4f/libdriver-cm4f.a
#
# The rule to clean out all the build products.
#
clean:
@rm -rf ${COMPILER}-cm4f ${wildcard *~}
#
# The rule to create the target directory.
#
${COMPILER}-cm4f:
@mkdir -p ${COMPILER}-cm4f
#
# Rules for building the driver library.
#
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/adc.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/can.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/comp.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/cpu.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/eeprom.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/epi.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ethernet.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fan.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/flash.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/fpu.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/gpio.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/hibernate.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2c.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/i2s.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/interrupt.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/lpc.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/mpu.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/peci.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/pwm.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/qei.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/ssi.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysctl.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/sysexc.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/systick.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/timer.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/uart.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/udma.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/usb.o
${COMPILER}-cm4f/libdriver-cm4f.a: ${COMPILER}-cm4f/watchdog.o
#
# Include the automatically generated dependency files.
#
ifneq (${MAKECMDGOALS},clean)
-include ${wildcard ${COMPILER}-cm4f/*.d} __dummy__
endif

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bsp/lm4f232/Libraries/driverlib/adc.h Normal file
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//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ulConfig parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
// Values that can be used to modify the sequence number passed to
// ADCProcessorTrigger in order to get cross-module synchronous processor
// triggers.
//
//*****************************************************************************
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
//*****************************************************************************
//
// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
// returned from ADCPhaseDelayGet.
//
//*****************************************************************************
#define ADC_PHASE_0 0x00000000 // 0 degrees
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
#define ADC_PHASE_45 0x00000002 // 45 degrees
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
#define ADC_PHASE_90 0x00000004 // 90 degrees
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
#define ADC_PHASE_135 0x00000006 // 135 degrees
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
#define ADC_PHASE_180 0x00000008 // 180 degrees
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
#define ADC_PHASE_225 0x0000000A // 225 degrees
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
#define ADC_PHASE_270 0x0000000C // 270 degrees
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
#define ADC_PHASE_315 0x0000000E // 315 degrees
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
//*****************************************************************************
//
// Values that can be passed to ADCReferenceSet as the ulRef parameter.
//
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
//*****************************************************************************
//
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
//
//*****************************************************************************
#define ADC_RES_10BIT 0x00000000 // 10-bit resolution
#define ADC_RES_12BIT 0x00000010 // 12-bit resolution
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
extern unsigned long ADCIntStatus(unsigned long ulBase,
unsigned long ulSequenceNum,
tBoolean bMasked);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
extern void ADCSequenceEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulTrigger,
unsigned long ulPriority);
extern void ADCSequenceStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern long ADCSequenceOverflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceOverflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceUnderflow(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
unsigned long ulSequenceNum);
extern long ADCSequenceDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer);
extern void ADCProcessorTrigger(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulFactor);
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long ulStep,
unsigned long ulConfig);
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
unsigned long ulSequenceNum,
unsigned long *pulBuffer,
unsigned long ulCount);
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
unsigned long ulFactor);
extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
unsigned long ulLowRef,
unsigned long ulHighRef);
extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
tBoolean bTrigger, tBoolean bInterrupt);
extern void ADCComparatorIntDisable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern void ADCComparatorIntEnable(unsigned long ulBase,
unsigned long ulSequenceNum);
extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
extern void ADCComparatorIntClear(unsigned long ulBase,
unsigned long ulStatus);
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
extern unsigned long ADCReferenceGet(unsigned long ulBase);
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
extern unsigned long ADCResolutionGet(unsigned long ulBase);
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CAN_H__
#define __CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
// These are the flags used by the tCANMsgObject.ulFlags value when calling the
// CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
//
//! This definition is used with the tCANMsgObject ulFlags value and indicates
//! that transmit interrupts should be enabled, or are enabled.
//
#define MSG_OBJ_TX_INT_ENABLE 0x00000001
//
//! This indicates that receive interrupts should be enabled, or are
//! enabled.
//
#define MSG_OBJ_RX_INT_ENABLE 0x00000002
//
//! This indicates that a message object will use or is using an extended
//! identifier.
//
#define MSG_OBJ_EXTENDED_ID 0x00000004
//
//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.
//
#define MSG_OBJ_USE_ID_FILTER 0x00000008
//
//! This indicates that new data was available in the message object.
//
#define MSG_OBJ_NEW_DATA 0x00000080
//
//! This indicates that data was lost since this message object was last
//! read.
//
#define MSG_OBJ_DATA_LOST 0x00000100
//
//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object is a remote frame.
//
#define MSG_OBJ_REMOTE_FRAME 0x00000040
//
//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.
//
#define MSG_OBJ_FIFO 0x00000200
//
//! This indicates that a message object has no flags set.
//
#define MSG_OBJ_NO_FLAGS 0x00000000
//*****************************************************************************
//
//! This define is used with the flag values to allow checking only status
//! flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
unsigned long ulMsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
unsigned long ulMsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
unsigned long ulFlags;
//
//! This value is the number of bytes of data in the message object.
//
unsigned long ulMsgLen;
//
//! This is a pointer to the message object's data.
//
unsigned char *pucMsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned long ulSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned long ulPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned long ulSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned long ulQuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
// These definitions are used to specify interrupt sources to CANIntEnable()
// and CANIntDisable().
//
//*****************************************************************************
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
#define CAN_INT_ERROR 0x00000008
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
#define CAN_INT_STATUS 0x00000004
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts will be generated
//! by the CAN controller.
//
#define CAN_INT_MASTER 0x00000002
//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
// The following enumeration contains all error or status indicators that can
// be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
//
//! CAN controller has entered a Bus Off state.
//
#define CAN_STATUS_BUS_OFF 0x00000080
//
//! CAN controller error level has reached warning level.
//
#define CAN_STATUS_EWARN 0x00000040
//
//! CAN controller error level has reached error passive level.
//
#define CAN_STATUS_EPASS 0x00000020
//
//! A message was received successfully since the last read of this status.
//
#define CAN_STATUS_RXOK 0x00000010
//
//! A message was transmitted successfully since the last read of this
//! status.
//
#define CAN_STATUS_TXOK 0x00000008
//
//! This is the mask for the last error code field.
//
#define CAN_STATUS_LEC_MSK 0x00000007
//
//! There was no error.
//
#define CAN_STATUS_LEC_NONE 0x00000000
//
//! A bit stuffing error has occurred.
//
#define CAN_STATUS_LEC_STUFF 0x00000001
//
//! A formatting error has occurred.
//
#define CAN_STATUS_LEC_FORM 0x00000002
//
//! An acknowledge error has occurred.
//
#define CAN_STATUS_LEC_ACK 0x00000003
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT1 0x00000004
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT0 0x00000005
//
//! A CRC error has occurred.
//
#define CAN_STATUS_LEC_CRC 0x00000006
//
//! This is the mask for the CAN Last Error Code (LEC).
//
#define CAN_STATUS_LEC_MASK 0x00000007
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern void CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms);
extern unsigned long CANBitRateSet(unsigned long ulBase,
unsigned long ulSourceClock,
unsigned long ulBitRate);
extern void CANDisable(unsigned long ulBase);
extern void CANEnable(unsigned long ulBase);
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
unsigned long *pulTxCount);
extern void CANInit(unsigned long ulBase);
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern unsigned long CANIntStatus(unsigned long ulBase,
tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(unsigned long ulBase);
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt);
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
extern tBoolean CANRetryGet(unsigned long ulBase);
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry);
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Several CAN APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#define CANSetBitTiming(a, b) CANBitTimingSet(a, b)
#define CANGetBitTiming(a, b) CANBitTimingGet(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // __CAN_H__

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//*****************************************************************************
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup comp_api
//! @{
//
//*****************************************************************************
#include "inc/hw_comp.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/comp.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
//! Configures a comparator.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function configures a comparator. The \e ulConfig parameter is the
//! result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
//!
//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
//! high.
//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
//! or high.
//!
//! The \b COMP_INT_xxx term can take on the following values:
//!
//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
//! high.
//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
//! low.
//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
//! low.
//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
//! high.
//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
//! low or high.
//!
//! The \b COMP_ASRCP_xxx term can take on the following values:
//!
//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
//! voltage.
//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
//! the same as \b COMP_ASRCP_PIN for the comparator 0).
//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
//! reference voltage.
//!
//! The \b COMP_OUTPUT_xxx term can take on the following values:
//!
//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
//! to a device pin.
//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
//! a device pin.
//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as
//! \b COMP_OUTPUT_NORMAL.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Configure this comparator.
//
HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;
}
//*****************************************************************************
//
//! Sets the internal reference voltage.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulRef is the desired reference voltage.
//!
//! This function sets the internal reference voltage value. The voltage is
//! specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
//
// Set the voltage reference voltage as requested.
//
HWREG(ulBase + COMP_O_ACREFCTL) = ulRef;
}
//*****************************************************************************
//
//! Gets the current comparator output value.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function retrieves the current value of the comparator output.
//!
//! \return Returns \b true if the comparator output is high and \b false if
//! the comparator output is low.
//
//*****************************************************************************
tBoolean
ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return the appropriate value based on the comparator's present output
// value.
//
if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL)
{
return(true);
}
else
{
return(false);
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This sets the handler to be called when the comparator interrupt occurs
//! and enables the interrupt in the interrupt controller. It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_COMP0 + ulComp, pfnHandler);
//
// Enable the interrupt in the interrupt controller.
//
IntEnable(INT_COMP0 + ulComp);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function clears the handler to be called when a comparator interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
//
// Disable the interrupt in the interrupt controller.
//
IntDisable(INT_COMP0 + ulComp);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_COMP0 + ulComp);
}
//*****************************************************************************
//
//! Enables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Enable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
}
//*****************************************************************************
//
//! Disables the comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the comparator. Either the raw or
//! the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
//! asserted.
//
//*****************************************************************************
tBoolean
ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false);
}
else
{
return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false);
}
}
//*****************************************************************************
//
//! Clears a comparator interrupt.
//!
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! fucntion must be called in the interrupt handler to keep the handler from
//! being called again immediately upon exit. Note that for a level-triggered
//! interrupt, the interrupt cannot be cleared until it stops asserting.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)
{
//
// Check the arguments.
//
ASSERT(ulBase == COMP_BASE);
ASSERT(ulComp < 3);
//
// Clear the interrupt.
//
HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __COMP_H__
#define __COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ulConfig
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
// the values may be selected and combined together with values from the other
// groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#ifndef DEPRECATED
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
#endif
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
unsigned long ulConfig);
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(unsigned long ulBase,
unsigned long ulComp);
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
tBoolean bMasked);
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __COMP_H__

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//*****************************************************************************
//
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#include "driverlib/cpu.h"
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUcpsid(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
mrs r0, PRIMASK;
cpsid i;
bx lr
}
#endif
#if defined(ccs)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function returning the state of PRIMASK (indicating whether
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUprimask(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
mrs r0, PRIMASK;
bx lr
}
#endif
#if defined(ccs)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUcpsie(void)
{
unsigned long ulRet;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
mrs r0, PRIMASK;
cpsie i;
bx lr
}
#endif
#if defined(ccs)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the WFI instruction.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
void __attribute__((naked))
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n");
}
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
wfi;
bx lr
}
#endif
#if defined(ccs)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" wfi\n");
}
#endif
//*****************************************************************************
//
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
void __attribute__((naked))
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n");
}
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
msr BASEPRI, r0;
bx lr
}
#endif
#if defined(ccs)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n");
}
#endif
//*****************************************************************************
//
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(codered) || defined(gcc) || defined(sourcerygxx)
unsigned long __attribute__((naked))
CPUbasepriGet(void)
{
unsigned long ulRet;
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(rvmdk) || defined(__ARMCC_VERSION)
__asm unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
mrs r0, BASEPRI;
bx lr
}
#endif
#if defined(ccs)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif

60
bsp/lm4f232/Libraries/driverlib/cpu.h Normal file
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@ -0,0 +1,60 @@
//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern unsigned long CPUprimask(void);
extern void CPUwfi(void);
extern unsigned long CPUbasepriGet(void);
extern void CPUbasepriSet(unsigned long ulNewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

71
bsp/lm4f232/Libraries/driverlib/cr_driverlib-cm4f.xml Normal file
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@ -0,0 +1,71 @@
<!--
Configuration file for Code Red project libdriver-cm4f
Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
Software License Agreement
Texas Instruments (TI) is supplying this software for use solely and
exclusively on TI's microcontroller products. The software is owned by
TI and/or its suppliers, and is protected under applicable copyright
laws. You may not combine this software with "viral" open-source
software in order to form a larger program.
THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 8049 of the Stellaris Peripheral Driver Library.
-->
<project chip="LM3S101"
target="driver-cm4f"
type="Static library"
vendor="LMI">
<import src=".">
<exclude>{(Makefile|Makefile\..*|ccs-.*|codered-.*|ewarm-.*|gcc-.*|rvmdk-.*|sourcerygxx-.*)}</exclude>
<exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|sgxx|Uv2|uvopt|uvproj|xml|ld|cmd)}</exclude>
</import>
<requires>
<value>inc</value>
</requires>
<setting id="assembler.def">
<value>codered</value>
</setting>
<setting id="compiler.def"
buildType="Debug"
mode="replace">
<value>DEBUG</value>
</setting>
<setting id="compiler.def"
buildType="Release"
mode="replace">
<value>NDEBUG</value>
</setting>
<setting id="compiler.def">
<value>__CODE_RED</value>
<value>__NEWLIB__</value>
<value>codered</value>
</setting>
<setting id="compiler.opt"
buildType="Debug">
<value>-Os</value>
</setting>
<setting id="compiler.opt"
buildType="Release">
<value>-Os</value>
</setting>
<setting id="compiler.flags"
buildType="Debug">
<value>-Os</value>
</setting>
<setting id="compiler.flags"
buildType="Release">
<value>-Os</value>
</setting>
<setting id="compiler.inc">
<value>${workspace_loc:/}</value>
</setting>
</project>

53
bsp/lm4f232/Libraries/driverlib/debug.h Normal file
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@ -0,0 +1,53 @@
//*****************************************************************************
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) { \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
}
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

857
bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.ewp Normal file
View File

@ -0,0 +1,857 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>1</fileVersion>
<configuration>
<name>Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>General</name>
<archiveVersion>3</archiveVersion>
<data>
<version>14</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>ExePath</name>
<state>ewarm-cm4f\Exe</state>
</option>
<option>
<name>ObjPath</name>
<state>ewarm-cm4f\Obj</state>
</option>
<option>
<name>ListPath</name>
<state>ewarm-cm4f\List</state>
</option>
<option>
<name>Variant</name>
<version>19</version>
<state>39</state>
</option>
<option>
<name>GEndianMode</name>
<state>0</state>
</option>
<option>
<name>Input variant</name>
<version>1</version>
<state>0</state>
</option>
<option>
<name>Input description</name>
<state>Full formatting.</state>
</option>
<option>
<name>Output variant</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>Output description</name>
<state>Full formatting.</state>
</option>
<option>
<name>GOutputBinary</name>
<state>1</state>
</option>
<option>
<name>FPU</name>
<version>2</version>
<state>5</state>
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelect</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>GRuntimeLibSelectSlave</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>RTDescription</name>
<state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
</option>
<option>
<name>RTConfigPath</name>
<state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>
</option>
<option>
<name>OGProductVersion</name>
<state>5.11.0.50579</state>
</option>
<option>
<name>OGLastSavedByProductVersion</name>
<state>5.11.0.50579</state>
</option>
<option>
<name>GeneralMisraRules</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>GeneralEnableMisra</name>
<state>0</state>
</option>
<option>
<name>GeneralMisraVerbose</name>
<state>0</state>
</option>
<option>
<name>OGChipSelectEditMenu</name>
<state>LM4F110B2QR TexasInstruments LM4F110B2QR</state>
</option>
<option>
<name>GenLowLevelInterface</name>
<state>1</state>
</option>
<option>
<name>GEndianModeBE</name>
<state>1</state>
</option>
<option>
<name>OGBufferedTerminalOutput</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>ICCARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>19</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCDefines</name>
<state>ewarm</state>
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
</option>
<option>
<name>CCListCFile</name>
<state>0</state>
</option>
<option>
<name>CCListCMnemonics</name>
<state>0</state>
</option>
<option>
<name>CCListCMessages</name>
<state>0</state>
</option>
<option>
<name>CCListAssFile</name>
<state>0</state>
</option>
<option>
<name>CCListAssSource</name>
<state>0</state>
</option>
<option>
<name>CCEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>CCDiagSuppress</name>
<state>Pa050</state>
</option>
<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
</option>
<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
<option>
<name>CCAllowList</name>
<version>1</version>
<state>1111111</state>
</option>
<option>
<name>CCDebugInfo</name>
<state>1</state>
</option>
<option>
<name>IEndianMode</name>
<state>1</state>
</option>
<option>
<name>IProcessor</name>
<state>1</state>
</option>
<option>
<name>IExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>IExtraOptions</name>
<state></state>
</option>
<option>
<name>CCLangConformance</name>
<state>0</state>
</option>
<option>
<name>CCSignedPlainChar</name>
<state>1</state>
</option>
<option>
<name>CCRequirePrototypes</name>
<state>0</state>
</option>
<option>
<name>CCMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>CCDiagWarnAreErr</name>
<state>0</state>
</option>
<option>
<name>CCCompilerRuntimeInfo</name>
<state>0</state>
</option>
<option>
<name>IFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>CCLangSelect</name>
<state>0</state>
</option>
<option>
<name>CCLibConfigHeader</name>
<state>1</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CompilerMisraRules</name>
<version>0</version>
<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
</option>
<option>
<name>CompilerMisraOverride</name>
<state>0</state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
</option>
<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCStdIncludePath</name>
<state>$TOOLKIT_DIR$\INC\</state>
</option>
<option>
<name>CCCodeSection</name>
<state>.text</state>
</option>
<option>
<name>IInterwork2</name>
<state>0</state>
</option>
<option>
<name>IProcessorMode2</name>
<state>1</state>
</option>
<option>
<name>CCOptLevel</name>
<state>3</state>
</option>
<option>
<name>CCOptStrategy</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCOptLevelSlave</name>
<state>3</state>
</option>
</data>
</settings>
<settings>
<name>AARM</name>
<archiveVersion>2</archiveVersion>
<data>
<version>7</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>AObjPrefix</name>
<state>1</state>
</option>
<option>
<name>AEndian</name>
<state>1</state>
</option>
<option>
<name>ACaseSensitivity</name>
<state>1</state>
</option>
<option>
<name>MacroChars</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>AWarnEnable</name>
<state>0</state>
</option>
<option>
<name>AWarnWhat</name>
<state>0</state>
</option>
<option>
<name>AWarnOne</name>
<state></state>
</option>
<option>
<name>AWarnRange1</name>
<state></state>
</option>
<option>
<name>AWarnRange2</name>
<state></state>
</option>
<option>
<name>ADebug</name>
<state>1</state>
</option>
<option>
<name>AltRegisterNames</name>
<state>0</state>
</option>
<option>
<name>ADefines</name>
<state>ewarm</state>
</option>
<option>
<name>AList</name>
<state>0</state>
</option>
<option>
<name>AListHeader</name>
<state>1</state>
</option>
<option>
<name>AListing</name>
<state>1</state>
</option>
<option>
<name>Includes</name>
<state>0</state>
</option>
<option>
<name>MacDefs</name>
<state>0</state>
</option>
<option>
<name>MacExps</name>
<state>1</state>
</option>
<option>
<name>MacExec</name>
<state>0</state>
</option>
<option>
<name>OnlyAssed</name>
<state>0</state>
</option>
<option>
<name>MultiLine</name>
<state>0</state>
</option>
<option>
<name>PageLengthCheck</name>
<state>0</state>
</option>
<option>
<name>PageLength</name>
<state>80</state>
</option>
<option>
<name>TabSpacing</name>
<state>8</state>
</option>
<option>
<name>AXRef</name>
<state>0</state>
</option>
<option>
<name>AXRefDefines</name>
<state>0</state>
</option>
<option>
<name>AXRefInternal</name>
<state>0</state>
</option>
<option>
<name>AXRefDual</name>
<state>0</state>
</option>
<option>
<name>AProcessor</name>
<state>1</state>
</option>
<option>
<name>AFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>AOutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>AMultibyteSupport</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsCheck</name>
<state>0</state>
</option>
<option>
<name>ALimitErrorsEdit</name>
<state>100</state>
</option>
<option>
<name>AIgnoreStdInclude</name>
<state>0</state>
</option>
<option>
<name>AStdIncludes</name>
<state>$TOOLKIT_DIR$\INC\</state>
</option>
<option>
<name>AUserIncludes</name>
<state></state>
</option>
<option>
<name>AExtraOptionsCheckV2</name>
<state>0</state>
</option>
<option>
<name>AExtraOptionsV2</name>
<state></state>
</option>
</data>
</settings>
<settings>
<name>OBJCOPY</name>
<archiveVersion>0</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OOCOutputFormat</name>
<version>1</version>
<state>0</state>
</option>
<option>
<name>OCOutputOverride</name>
<state>0</state>
</option>
<option>
<name>OOCOutputFile</name>
<state>driverlib-cm4f.srec</state>
</option>
<option>
<name>OOCCommandLineProducer</name>
<state>1</state>
</option>
<option>
<name>OOCObjCopyEnable</name>
<state>0</state>
</option>
</data>
</settings>
<settings>
<name>CUSTOM</name>
<archiveVersion>3</archiveVersion>
<data>
<extensions></extensions>
<cmdline></cmdline>
</data>
</settings>
<settings>
<name>BICOMP</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
<settings>
<name>BUILDACTION</name>
<archiveVersion>1</archiveVersion>
<data>
<prebuild></prebuild>
<postbuild></postbuild>
</data>
</settings>
<settings>
<name>ILINK</name>
<archiveVersion>0</archiveVersion>
<data>
<version>5</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IlinkLibIOConfig</name>
<state>1</state>
</option>
<option>
<name>XLinkMisraHandler</name>
<state>0</state>
</option>
<option>
<name>IlinkInputFileSlave</name>
<state>0</state>
</option>
<option>
<name>IlinkOutputFile</name>
<state>driverlib-cm4f.out</state>
</option>
<option>
<name>IlinkDebugInfoEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkKeepSymbols</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryFile</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySymbol</name>
<state></state>
</option>
<option>
<name>IlinkRawBinarySegment</name>
<state></state>
</option>
<option>
<name>IlinkRawBinaryAlign</name>
<state></state>
</option>
<option>
<name>IlinkDefines</name>
<state></state>
</option>
<option>
<name>IlinkConfigDefines</name>
<state></state>
</option>
<option>
<name>IlinkMapFile</name>
<state>0</state>
</option>
<option>
<name>IlinkLogFile</name>
<state>0</state>
</option>
<option>
<name>IlinkLogInitialization</name>
<state>0</state>
</option>
<option>
<name>IlinkLogModule</name>
<state>0</state>
</option>
<option>
<name>IlinkLogSection</name>
<state>0</state>
</option>
<option>
<name>IlinkLogVeneer</name>
<state>0</state>
</option>
<option>
<name>IlinkIcfOverride</name>
<state>0</state>
</option>
<option>
<name>IlinkIcfFile</name>
<state>lnk0t.icf</state>
</option>
<option>
<name>IlinkIcfFileSlave</name>
<state></state>
</option>
<option>
<name>IlinkEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>IlinkSuppressDiags</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsRem</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsWarn</name>
<state></state>
</option>
<option>
<name>IlinkTreatAsErr</name>
<state></state>
</option>
<option>
<name>IlinkWarningsAreErrors</name>
<state>0</state>
</option>
<option>
<name>IlinkUseExtraOptions</name>
<state>0</state>
</option>
<option>
<name>IlinkExtraOptions</name>
<state></state>
</option>
<option>
<name>IlinkLowLevelInterfaceSlave</name>
<state>1</state>
</option>
<option>
<name>IlinkAutoLibEnable</name>
<state>1</state>
</option>
<option>
<name>IlinkAdditionalLibs</name>
<state></state>
</option>
<option>
<name>IlinkOverrideProgramEntryLabel</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabelSelect</name>
<state>0</state>
</option>
<option>
<name>IlinkProgramEntryLabel</name>
<state></state>
</option>
<option>
<name>IlinkNXPLPCChecksum</name>
<state>0</state>
</option>
<option>
<name>DoFill</name>
<state>0</state>
</option>
<option>
<name>FillerByte</name>
<state>0xFF</state>
</option>
<option>
<name>FillerStart</name>
<state>0x0</state>
</option>
<option>
<name>FillerEnd</name>
<state>0x0</state>
</option>
<option>
<name>CrcSize</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CrcAlign</name>
<state>1</state>
</option>
<option>
<name>CrcAlgo</name>
<state>1</state>
</option>
<option>
<name>CrcPoly</name>
<state>0x11021</state>
</option>
<option>
<name>CrcCompl</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcBitOrder</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CrcInitialValue</name>
<state>0x0</state>
</option>
<option>
<name>DoCrc</name>
<state>0</state>
</option>
<option>
<name>IlinkBE8Slave</name>
<state>1</state>
</option>
<option>
<name>IlinkBufferedTerminalOutput</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>IARCHIVE</name>
<archiveVersion>0</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>IarchiveInputs</name>
<state></state>
</option>
<option>
<name>IarchiveOverride</name>
<state>0</state>
</option>
<option>
<name>IarchiveOutput</name>
<state>$PROJ_DIR$\ewarm-cm4f\Exe\driverlib-cm4f.a</state>
</option>
</data>
</settings>
<settings>
<name>BILINK</name>
<archiveVersion>0</archiveVersion>
<data/>
</settings>
</configuration>
<group>
<name>Source</name>
<file>
<name>$PROJ_DIR$\adc.c</name>
</file>
<file>
<name>$PROJ_DIR$\can.c</name>
</file>
<file>
<name>$PROJ_DIR$\comp.c</name>
</file>
<file>
<name>$PROJ_DIR$\cpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\eeprom.c</name>
</file>
<file>
<name>$PROJ_DIR$\epi.c</name>
</file>
<file>
<name>$PROJ_DIR$\ethernet.c</name>
</file>
<file>
<name>$PROJ_DIR$\fan.c</name>
</file>
<file>
<name>$PROJ_DIR$\flash.c</name>
</file>
<file>
<name>$PROJ_DIR$\fpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\hibernate.c</name>
</file>
<file>
<name>$PROJ_DIR$\i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\i2s.c</name>
</file>
<file>
<name>$PROJ_DIR$\interrupt.c</name>
</file>
<file>
<name>$PROJ_DIR$\lpc.c</name>
</file>
<file>
<name>$PROJ_DIR$\mpu.c</name>
</file>
<file>
<name>$PROJ_DIR$\peci.c</name>
</file>
<file>
<name>$PROJ_DIR$\pwm.c</name>
</file>
<file>
<name>$PROJ_DIR$\qei.c</name>
</file>
<file>
<name>$PROJ_DIR$\ssi.c</name>
</file>
<file>
<name>$PROJ_DIR$\sysctl.c</name>
</file>
<file>
<name>$PROJ_DIR$\sysexc.c</name>
</file>
<file>
<name>$PROJ_DIR$\systick.c</name>
</file>
<file>
<name>$PROJ_DIR$\timer.c</name>
</file>
<file>
<name>$PROJ_DIR$\uart.c</name>
</file>
<file>
<name>$PROJ_DIR$\udma.c</name>
</file>
<file>
<name>$PROJ_DIR$\usb.c</name>
</file>
<file>
<name>$PROJ_DIR$\watchdog.c</name>
</file>
</group>
</project>

BIN
bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.sgxx Normal file
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bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.uvopt Normal file
View File

@ -0,0 +1,636 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>driverlib-cm4f</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>8000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\rvmdk-cm4f\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Data Sheet</Title>
<Path>DATASHTS\Luminary\LM4F110B2QR.PDF</Path>
</Book>
</Books>
<DllOpt>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-MPU</SimDllArguments>
<SimDlgDllName>DCM.DLL</SimDlgDllName>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
<TargetDlgDllName>TCM.DLL</TargetDlgDllName>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOpt>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\lmidk-agdi.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>lmidk-agdi</Key>
<Name>-O4622 -S3 -FO29</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
<Group>
<GroupName>Source</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\adc.c</PathWithFileName>
<FilenameWithoutPath>adc.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\can.c</PathWithFileName>
<FilenameWithoutPath>can.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\comp.c</PathWithFileName>
<FilenameWithoutPath>comp.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\cpu.c</PathWithFileName>
<FilenameWithoutPath>cpu.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\eeprom.c</PathWithFileName>
<FilenameWithoutPath>eeprom.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\epi.c</PathWithFileName>
<FilenameWithoutPath>epi.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\ethernet.c</PathWithFileName>
<FilenameWithoutPath>ethernet.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\fan.c</PathWithFileName>
<FilenameWithoutPath>fan.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\flash.c</PathWithFileName>
<FilenameWithoutPath>flash.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\fpu.c</PathWithFileName>
<FilenameWithoutPath>fpu.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>11</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\gpio.c</PathWithFileName>
<FilenameWithoutPath>gpio.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\hibernate.c</PathWithFileName>
<FilenameWithoutPath>hibernate.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\i2c.c</PathWithFileName>
<FilenameWithoutPath>i2c.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>14</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\i2s.c</PathWithFileName>
<FilenameWithoutPath>i2s.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\interrupt.c</PathWithFileName>
<FilenameWithoutPath>interrupt.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\lpc.c</PathWithFileName>
<FilenameWithoutPath>lpc.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\mpu.c</PathWithFileName>
<FilenameWithoutPath>mpu.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\peci.c</PathWithFileName>
<FilenameWithoutPath>peci.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>19</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\pwm.c</PathWithFileName>
<FilenameWithoutPath>pwm.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>20</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\qei.c</PathWithFileName>
<FilenameWithoutPath>qei.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>21</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\ssi.c</PathWithFileName>
<FilenameWithoutPath>ssi.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>22</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\sysctl.c</PathWithFileName>
<FilenameWithoutPath>sysctl.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>23</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\sysexc.c</PathWithFileName>
<FilenameWithoutPath>sysexc.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>24</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\systick.c</PathWithFileName>
<FilenameWithoutPath>systick.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>25</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\timer.c</PathWithFileName>
<FilenameWithoutPath>timer.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>26</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\uart.c</PathWithFileName>
<FilenameWithoutPath>uart.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>27</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\udma.c</PathWithFileName>
<FilenameWithoutPath>udma.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>28</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\usb.c</PathWithFileName>
<FilenameWithoutPath>usb.c</FilenameWithoutPath>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>29</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\watchdog.c</PathWithFileName>
<FilenameWithoutPath>watchdog.c</FilenameWithoutPath>
</File>
</Group>
<Group>
<GroupName>Documentation</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>30</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>1</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\readme.txt</PathWithFileName>
<FilenameWithoutPath>readme.txt</FilenameWithoutPath>
<WindowPosition>
<length>44</length>
<flags>0</flags>
<showCmd>1</showCmd>
<MinPosition>
<xPos>-1</xPos>
<yPos>-1</yPos>
</MinPosition>
<MaxPosition>
<xPos>-1</xPos>
<yPos>-1</yPos>
</MaxPosition>
<NormalPosition>
<Top>0</Top>
<Left>0</Left>
<Right>729</Right>
<Bottom>300</Bottom>
</NormalPosition>
</WindowPosition>
</File>
</Group>
<MDIGroups>
<Orientation>1</Orientation>
<ActiveMDIGroup>0</ActiveMDIGroup>
<MDIGroup>
<Size>100</Size>
<ActiveTab>0</ActiveTab>
<Documents>
<Doc>
<Name>.\readme.txt</Name>
<ColumnNumber>0</ColumnNumber>
<TopLine>1</TopLine>
<CurrentLine>1</CurrentLine>
</Doc>
</Documents>
</MDIGroup>
</MDIGroups>
</ProjectOpt>

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bsp/lm4f232/Libraries/driverlib/driverlib-cm4f.uvproj Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>driverlib-cm4f</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LM4F110B2QR</Device>
<Vendor>Texas Instruments</Vendor>
<Cpu>IRAM(0x20000000-0x20002FFF) IROM(0-0x7FFF) CLOCK(8000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\Luminary\Startup.s" ("Luminary Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM4F_32 -FS00 -FL08000)</FlashDriverDll>
<DeviceId>5919</DeviceId>
<RegisterFile>LM4Fxxxx.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\Luminary\LM4F110B2QR.SFR</SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Luminary\</RegisterFilePath>
<DBRegisterFilePath>Luminary\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\rvmdk-cm4f\</OutputDirectory>
<OutputName>driverlib-cm4f</OutputName>
<CreateExecutable>0</CreateExecutable>
<CreateLib>1</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\rvmdk-cm4f\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>1</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>0</UseTarget>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>3</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
<Driver>BIN\lmidk-agdi.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4097</DriverSelection>
</Flash1>
<Flash2>BIN\lmidk-agdi.dll</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>0</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>0</AdsLLst>
<AdsLmap>0</AdsLmap>
<AdsLcgr>0</AdsLcgr>
<AdsLsym>0</AdsLsym>
<AdsLszi>0</AdsLszi>
<AdsLtoi>0</AdsLtoi>
<AdsLsun>0</AdsLsun>
<AdsLven>0</AdsLven>
<AdsLsxf>0</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x3000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x8000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x3000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>0</interw>
<Optim>3</Optim>
<oTime>1</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<VariousControls>
<MiscControls></MiscControls>
<Define>rvmdk</Define>
<Undefine></Undefine>
<IncludePath>..;</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source</GroupName>
<Files>
<File>
<FileName>adc.c</FileName>
<FileType>1</FileType>
<FilePath>.\adc.c</FilePath>
</File>
<File>
<FileName>can.c</FileName>
<FileType>1</FileType>
<FilePath>.\can.c</FilePath>
</File>
<File>
<FileName>comp.c</FileName>
<FileType>1</FileType>
<FilePath>.\comp.c</FilePath>
</File>
<File>
<FileName>cpu.c</FileName>
<FileType>1</FileType>
<FilePath>.\cpu.c</FilePath>
</File>
<File>
<FileName>eeprom.c</FileName>
<FileType>1</FileType>
<FilePath>.\eeprom.c</FilePath>
</File>
<File>
<FileName>epi.c</FileName>
<FileType>1</FileType>
<FilePath>.\epi.c</FilePath>
</File>
<File>
<FileName>ethernet.c</FileName>
<FileType>1</FileType>
<FilePath>.\ethernet.c</FilePath>
</File>
<File>
<FileName>fan.c</FileName>
<FileType>1</FileType>
<FilePath>.\fan.c</FilePath>
</File>
<File>
<FileName>flash.c</FileName>
<FileType>1</FileType>
<FilePath>.\flash.c</FilePath>
</File>
<File>
<FileName>fpu.c</FileName>
<FileType>1</FileType>
<FilePath>.\fpu.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>.\gpio.c</FilePath>
</File>
<File>
<FileName>hibernate.c</FileName>
<FileType>1</FileType>
<FilePath>.\hibernate.c</FilePath>
</File>
<File>
<FileName>i2c.c</FileName>
<FileType>1</FileType>
<FilePath>.\i2c.c</FilePath>
</File>
<File>
<FileName>i2s.c</FileName>
<FileType>1</FileType>
<FilePath>.\i2s.c</FilePath>
</File>
<File>
<FileName>interrupt.c</FileName>
<FileType>1</FileType>
<FilePath>.\interrupt.c</FilePath>
</File>
<File>
<FileName>lpc.c</FileName>
<FileType>1</FileType>
<FilePath>.\lpc.c</FilePath>
</File>
<File>
<FileName>mpu.c</FileName>
<FileType>1</FileType>
<FilePath>.\mpu.c</FilePath>
</File>
<File>
<FileName>peci.c</FileName>
<FileType>1</FileType>
<FilePath>.\peci.c</FilePath>
</File>
<File>
<FileName>pwm.c</FileName>
<FileType>1</FileType>
<FilePath>.\pwm.c</FilePath>
</File>
<File>
<FileName>qei.c</FileName>
<FileType>1</FileType>
<FilePath>.\qei.c</FilePath>
</File>
<File>
<FileName>ssi.c</FileName>
<FileType>1</FileType>
<FilePath>.\ssi.c</FilePath>
</File>
<File>
<FileName>sysctl.c</FileName>
<FileType>1</FileType>
<FilePath>.\sysctl.c</FilePath>
</File>
<File>
<FileName>sysexc.c</FileName>
<FileType>1</FileType>
<FilePath>.\sysexc.c</FilePath>
</File>
<File>
<FileName>systick.c</FileName>
<FileType>1</FileType>
<FilePath>.\systick.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>.\timer.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>.\uart.c</FilePath>
</File>
<File>
<FileName>udma.c</FileName>
<FileType>1</FileType>
<FilePath>.\udma.c</FilePath>
</File>
<File>
<FileName>usb.c</FileName>
<FileType>1</FileType>
<FilePath>.\usb.c</FilePath>
</File>
<File>
<FileName>watchdog.c</FileName>
<FileType>1</FileType>
<FilePath>.\watchdog.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Documentation</GroupName>
<Files>
<File>
<FileName>readme.txt</FileName>
<FileType>5</FileType>
<FilePath>.\readme.txt</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
</Project>

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bsp/lm4f232/Libraries/driverlib/eeprom.c Normal file
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//*****************************************************************************
//
// eeprom.h - Prototypes for the EEPROM driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __EEPROM_H__
#define __EEPROM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup eeprom_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Values returned by EEPROMInit.
//
//*****************************************************************************
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! no previous write operations were interrupted by a reset event and that the
//! EEPROM peripheral is ready for use.
//
#define EEPROM_INIT_OK 0
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! a previous data or protection write operation was interrupted by a reset
//! event. The EEPROM peripheral has recovered its state but the last write
//! operation may have been lost. The application must check the validity of
//! data it has written and retry any writes as required.
//
#define EEPROM_INIT_RETRY 1
//
//! This value may be returned from a call to EEPROMInit(). It indicates that a
//! previous data or protection write operation was interrupted by a reset
//! event and that the EEPROM peripheral was unable to clean up after the
//! problem. This situation may be resolved with another reset or may be fatal
//! depending upon the cause of the problem. For example, if the voltage to
//! the part is unstable, retrying once the voltage has stabilized may clear
//! the error.
//
#define EEPROM_INIT_ERROR 2
//*****************************************************************************
//
// Error indicators returned by various EEPROM API calls. These will be ORed
// together into the final return code.
//
//*****************************************************************************
//
//! This return code bit indicates that the EEPROM programming state machine
//! failed to write a value due to the voltage level dropping below that
//! required for EEPROM programming. The operation may be retried once the
//! voltage stabilizes.
//
#define EEPROM_RC_INVPL 0x00000100
//
//! This return code bit indicates that an attempt was made to read from
//! the EEPROM while a write operation was in progress.
//
#define EEPROM_RC_WRBUSY 0x00000020
//
//! This return code bit indicates that an attempt was made to write a
//! value but the destination permissions disallow write operations. This
//! may be due to the destination block being locked, access protection set
//! to prohibit writes or an attempt to write a password when one is already
//! written.
//
#define EEPROM_RC_NOPERM 0x00000010
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently copying to or from the internal copy buffer to make room for
//! a newly written value. It is provided as a status indicator and does not
//! indicate an error.
//
#define EEPROM_RC_WKCOPY 0x00000008
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently erasing the internal copy buffer. It is provided as a
//! status indicator and does not indicate an error.
//
#define EEPROM_RC_WKERASE 0x00000004
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently working. No new write operations should be attempted until
//! this bit is clear.
//
#define EEPROM_RC_WORKING 0x00000001
//*****************************************************************************
//
// Values that can be passed to EEPROMBlockProtectSet() in the ulProtect
// parameter, and returned by EEPROMBlockProtectGet().
//
//*****************************************************************************
//
//! This bit may be ORed with the protection option passed to
//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It
//! restricts EEPROM access to threads running in supervisor mode and prevents
//! access to an EEPROM block when the CPU is in user mode.
//
#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read/write access when no password is set or when a password is set and
//! the block is unlocked, and read-only access when a password is set but
//! the block is locked.
//
#define EEPROM_PROT_RW_LRO_URW 0x00000000
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer neither
//! read nor write access unless it is protected by a password and unlocked.
//
#define EEPROM_PROT_NA_LNA_URW 0x00000001
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read-only access when no password is set or when a password is set and the
//! block is unlocked. When a password is set and the block is locked, neither
//! read nor write access is permitted.
//
#define EEPROM_PROT_RO_LNA_URO 0x00000002
//*****************************************************************************
//
//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
//! signaled.
//
//*****************************************************************************
#define EEPROM_INT_PROGRAM 0x00000004
//*****************************************************************************
//
//! Returns the EEPROM block number containing a given offset address.
//!
//! \param ulAddr is the linear, byte address of the EEPROM location whose
//! block number is to be returned. This is a zero-based offset from the start
//! of the EEPROM storage.
//!
//! This macro may be used to translate an EEPROM address offset into a
//! block number suitable for use in any of the driver's block protection
//! functions. The address provided is expressed as a byte offset from the
//! base of the EEPROM.
//!
//! \return Returns the zero-based block number which contains the passed
//! address.
//
//*****************************************************************************
#define EEPROMBlockFromAddr(ulAddr) ((ulAddr) >> 6)
//*****************************************************************************
//
//! Returns the offset address of the first word in an EEPROM block.
//!
//! \param ulBlock is the index of the EEPROM block whose first word address
//! is to be returned.
//!
//! This macro may be used to determine the address of the first word in a
//! given EEPROM block. The address returned is expressed as a byte offset
//! from the base of EEPROM storage.
//!
//! \return Returns the address of the first word in the given EEPROM block.
//
//*****************************************************************************
#define EEPROMAddrFromBlock(ulBlock) ((ulBlock) << 6)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long EEPROMInit(void);
extern unsigned long EEPROMSizeGet(void);
extern unsigned long EEPROMBlockCountGet(void);
extern void EEPROMRead(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgram(unsigned long *pulData,
unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgramNonBlocking(unsigned long ulData,
unsigned long ulAddress);
extern unsigned long EEPROMStatusGet(void);
extern unsigned long EEPROMMassErase(void);
extern unsigned long EEPROMBlockProtectGet(unsigned long ulBlock);
extern unsigned long EEPROMBlockProtectSet(unsigned long ulBlock,
unsigned long ulProtect);
extern unsigned long EEPROMBlockPasswordSet(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern unsigned long EEPROMBlockLock(unsigned long ulBlock);
extern unsigned long EEPROMBlockUnlock(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern void EEPROMBlockHide(unsigned long ulBlock);
extern void EEPROMIntEnable(unsigned long ulIntFlags);
extern void EEPROMIntDisable(unsigned long ulIntFlags);
extern unsigned long EEPROMIntStatus(tBoolean bMasked);
extern void EEPROMIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EEPROM_H__

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//*****************************************************************************
//
// epi.h - Prototypes and macros for the EPI module.
//
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __EPI_H__
#define __EPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EPIModeSet()
//
//*****************************************************************************
#define EPI_MODE_GENERAL 0x00000010
#define EPI_MODE_SDRAM 0x00000011
#define EPI_MODE_HB8 0x00000012
#define EPI_MODE_HB16 0x00000013
#define EPI_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
//
//*****************************************************************************
#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000
#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000
#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000
#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000
#define EPI_SDRAM_LOW_POWER 0x00000200
#define EPI_SDRAM_FULL_POWER 0x00000000
#define EPI_SDRAM_SIZE_64MBIT 0x00000000
#define EPI_SDRAM_SIZE_128MBIT 0x00000001
#define EPI_SDRAM_SIZE_256MBIT 0x00000002
#define EPI_SDRAM_SIZE_512MBIT 0x00000003
//*****************************************************************************
//
// Values that can be passed to EPIConfigGPModeSet()
//
//*****************************************************************************
#define EPI_GPMODE_CLKPIN 0x80000000
#define EPI_GPMODE_CLKGATE 0x40000000
#define EPI_GPMODE_RDYEN 0x10000000
#define EPI_GPMODE_FRAMEPIN 0x08000000
#define EPI_GPMODE_FRAME50 0x04000000
#define EPI_GPMODE_READWRITE 0x00200000
#define EPI_GPMODE_WRITE2CYCLE 0x00080000
#define EPI_GPMODE_READ2CYCLE 0x00040000
#define EPI_GPMODE_ASIZE_NONE 0x00000000
#define EPI_GPMODE_ASIZE_4 0x00000010
#define EPI_GPMODE_ASIZE_12 0x00000020
#define EPI_GPMODE_ASIZE_20 0x00000030
#define EPI_GPMODE_DSIZE_8 0x00000000
#define EPI_GPMODE_DSIZE_16 0x00000001
#define EPI_GPMODE_DSIZE_24 0x00000002
#define EPI_GPMODE_DSIZE_32 0x00000003
#define EPI_GPMODE_WORD_ACCESS 0x00000100
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB8ModeSet()
//
//*****************************************************************************
#define EPI_HB8_USE_TXEMPTY 0x00800000
#define EPI_HB8_USE_RXFULL 0x00400000
#define EPI_HB8_WRHIGH 0x00200000
#define EPI_HB8_RDHIGH 0x00100000
#define EPI_HB8_WRWAIT_0 0x00000000
#define EPI_HB8_WRWAIT_1 0x00000040
#define EPI_HB8_WRWAIT_2 0x00000080
#define EPI_HB8_WRWAIT_3 0x000000C0
#define EPI_HB8_RDWAIT_0 0x00000000
#define EPI_HB8_RDWAIT_1 0x00000010
#define EPI_HB8_RDWAIT_2 0x00000020
#define EPI_HB8_RDWAIT_3 0x00000030
#define EPI_HB8_MODE_ADMUX 0x00000000
#define EPI_HB8_MODE_ADDEMUX 0x00000001
#define EPI_HB8_MODE_SRAM 0x00000002
#define EPI_HB8_MODE_FIFO 0x00000003
#define EPI_HB8_WORD_ACCESS 0x00000100
#define EPI_HB8_CSCFG_ALE 0x00000000
#define EPI_HB8_CSCFG_CS 0x00000200
#define EPI_HB8_CSCFG_DUAL_CS 0x00000400
#define EPI_HB8_CSCFG_ALE_DUAL_CS 0x00000600
#define EPI_HB8_CSBAUD_DUAL 0x00000800
#define EPI_HB8_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB16ModeSet()
//
//*****************************************************************************
#define EPI_HB16_USE_TXEMPTY 0x00800000
#define EPI_HB16_USE_RXFULL 0x00400000
#define EPI_HB16_WRHIGH 0x00200000
#define EPI_HB16_RDHIGH 0x00100000
#define EPI_HB16_WRWAIT_0 0x00000000
#define EPI_HB16_WRWAIT_1 0x00000040
#define EPI_HB16_WRWAIT_2 0x00000080
#define EPI_HB16_WRWAIT_3 0x000000C0
#define EPI_HB16_RDWAIT_0 0x00000000
#define EPI_HB16_RDWAIT_1 0x00000010
#define EPI_HB16_RDWAIT_2 0x00000020
#define EPI_HB16_RDWAIT_3 0x00000030
#define EPI_HB16_MODE_ADMUX 0x00000000
#define EPI_HB16_MODE_ADDEMUX 0x00000001
#define EPI_HB16_MODE_SRAM 0x00000002
#define EPI_HB16_MODE_FIFO 0x00000003
#define EPI_HB16_BSEL 0x00000004
#define EPI_HB16_WORD_ACCESS 0x00000100
#define EPI_HB16_CSCFG_ALE 0x00000000
#define EPI_HB16_CSCFG_CS 0x00000200
#define EPI_HB16_CSCFG_DUAL_CS 0x00000400
#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600
#define EPI_HB16_CSBAUD_DUAL 0x00000800
#define EPI_HB16_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
//
//*****************************************************************************
#define EPI_ADDR_PER_SIZE_256B 0x00000000
#define EPI_ADDR_PER_SIZE_64KB 0x00000040
#define EPI_ADDR_PER_SIZE_16MB 0x00000080
#define EPI_ADDR_PER_SIZE_256MB 0x000000C0
#define EPI_ADDR_PER_BASE_NONE 0x00000000
#define EPI_ADDR_PER_BASE_A 0x00000010
#define EPI_ADDR_PER_BASE_C 0x00000020
#define EPI_ADDR_RAM_SIZE_256B 0x00000000
#define EPI_ADDR_RAM_SIZE_64KB 0x00000004
#define EPI_ADDR_RAM_SIZE_16MB 0x00000008
#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C
#define EPI_ADDR_RAM_BASE_NONE 0x00000000
#define EPI_ADDR_RAM_BASE_6 0x00000001
#define EPI_ADDR_RAM_BASE_8 0x00000002
//*****************************************************************************
//
// Values that can be passed to EPINonBlockingReadConfigure()
//
//*****************************************************************************
#define EPI_NBCONFIG_SIZE_8 1
#define EPI_NBCONFIG_SIZE_16 2
#define EPI_NBCONFIG_SIZE_32 3
//*****************************************************************************
//
// Values that can be passed to EPIFIFOConfig()
//
//*****************************************************************************
#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000
#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000
#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000
#define EPI_FIFO_CONFIG_TX_1_4 0x00000020
#define EPI_FIFO_CONFIG_TX_1_2 0x00000030
#define EPI_FIFO_CONFIG_TX_3_4 0x00000040
#define EPI_FIFO_CONFIG_RX_1_8 0x00000001
#define EPI_FIFO_CONFIG_RX_1_4 0x00000002
#define EPI_FIFO_CONFIG_RX_1_2 0x00000003
#define EPI_FIFO_CONFIG_RX_3_4 0x00000004
#define EPI_FIFO_CONFIG_RX_7_8 0x00000005
#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
//*****************************************************************************
//
// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
// as flags from EPIIntStatus()
//
//*****************************************************************************
#define EPI_INT_TXREQ 0x00000004
#define EPI_INT_RXREQ 0x00000002
#define EPI_INT_ERR 0x00000001
//*****************************************************************************
//
// Values that can be passed to EPIIntErrorClear(), or returned as flags from
// EPIIntErrorStatus()
//
//*****************************************************************************
#define EPI_INT_ERR_WTFULL 0x00000004
#define EPI_INT_ERR_RSTALL 0x00000002
#define EPI_INT_ERR_TIMEOUT 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
extern void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
extern void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulRefresh);
extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulFrameCount,
unsigned long ulMaxWait);
extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
extern void EPINonBlockingReadConfigure(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulDataSize,
unsigned long ulAddress);
extern void EPINonBlockingReadStart(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulCount);
extern void EPINonBlockingReadStop(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long EPINonBlockingReadCount(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
extern unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
unsigned long ulCount,
unsigned long *pulBuf);
extern unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
unsigned long ulCount,
unsigned short *pusBuf);
extern unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
unsigned long ulCount,
unsigned char *pucBuf);
extern void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long EPIWriteFIFOCountGet(unsigned long ulBase);
extern void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long EPIIntErrorStatus(unsigned long ulBase);
extern void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
extern void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void EPIIntUnregister(unsigned long ulBase);
//*****************************************************************************
//
// Several EPI APIs and labels have been renamed, with the original definition
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#define EPI_MODE_NONE EPI_MODE_GENERAL
#define EPI_NONMODE_CLKPIN EPI_GPMODE_CLKPIN
#define EPI_NONMODE_CLKSTOP EPI_GPMODE_CLKGATE
#define EPI_NONMODE_CLKENA EPI_GPMODE_RDYEN
#define EPI_NONMODE_FRAMEPIN EPI_GPMODE_FRAMEPIN
#define EPI_NONMODE_FRAME50 EPI_GPMODE_FRAME50
#define EPI_NONMODE_READWRITE EPI_GPMODE_READWRITE
#define EPI_NONMODE_WRITE2CYCLE EPI_GPMODE_WRITE2CYCLE
#define EPI_NONMODE_READ2CYCLE EPI_GPMODE_READ2CYCLE
#define EPI_NONMODE_ASIZE_NONE EPI_GPMODE_ASIZE_NONE
#define EPI_NONMODE_ASIZE_4 EPI_GPMODE_ASIZE_4
#define EPI_NONMODE_ASIZE_12 EPI_GPMODE_ASIZE_12
#define EPI_NONMODE_ASIZE_20 EPI_GPMODE_ASIZE_20
#define EPI_NONMODE_DSIZE_8 EPI_GPMODE_DSIZE_8
#define EPI_NONMODE_DSIZE_16 EPI_GPMODE_DSIZE_16
#define EPI_NONMODE_DSIZE_24 EPI_GPMODE_DSIZE_24
#define EPI_NONMODE_DSIZE_32 EPI_GPMODE_DSIZE_32
#define EPI_NONMODE_WORD_ACCESS EPI_GPMODE_WORD_ACCESS
#define EPINonBlockingWriteCount(a) EPIWriteFIFOCountGet(a)
#define EPIConfigNoModeSet(a, b, c, d) EPIConfigGPModeSet((a), (b), (c), (d))
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EPI_H__

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//*****************************************************************************
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __ETHERNET_H__
#define __ETHERNET_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to EthernetConfigSet as the ulConfig value, and
// returned from EthernetConfigGet.
//
//*****************************************************************************
#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
//*****************************************************************************
//
// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
// EthernetIntClear as the ulIntFlags parameter, and returned from
// EthernetIntStatus.
//
//*****************************************************************************
#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
#define ETH_INT_MDIO 0x020 // Management Transaction
#define ETH_INT_RXER 0x010 // RX Error
#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
#define ETH_INT_TX 0x004 // TX Complete
#define ETH_INT_TXER 0x002 // TX Error
#define ETH_INT_RX 0x001 // RX Complete
//*****************************************************************************
//
// Helper Macros for Ethernet Processing
//
//*****************************************************************************
//
// htonl/ntohl - big endian/little endian byte swapping macros for
// 32-bit (long) values
//
//*****************************************************************************
#ifndef htonl
#define htonl(a) \
((((a) >> 24) & 0x000000ff) | \
(((a) >> 8) & 0x0000ff00) | \
(((a) << 8) & 0x00ff0000) | \
(((a) << 24) & 0xff000000))
#endif
#ifndef ntohl
#define ntohl(a) htonl((a))
#endif
//*****************************************************************************
//
// htons/ntohs - big endian/little endian byte swapping macros for
// 16-bit (short) values
//
//*****************************************************************************
#ifndef htons
#define htons(a) \
((((a) >> 8) & 0x00ff) | \
(((a) << 8) & 0xff00))
#endif
#ifndef ntohs
#define ntohs(a) htons((a))
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long EthernetConfigGet(unsigned long ulBase);
extern void EthernetMACAddrSet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetMACAddrGet(unsigned long ulBase,
unsigned char *pucMACAddr);
extern void EthernetEnable(unsigned long ulBase);
extern void EthernetDisable(unsigned long ulBase);
extern tBoolean EthernetPacketAvail(unsigned long ulBase);
extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
unsigned char *pucBuf,
long lBufLen);
extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
long lBufLen);
extern void EthernetIntRegister(unsigned long ulBase,
void (*pfnHandler)(void));
extern void EthernetIntUnregister(unsigned long ulBase);
extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
extern void EthernetPHYPowerOff(unsigned long ulBase);
extern void EthernetPHYPowerOn(unsigned long ulBase);
//*****************************************************************************
//
// Several Ethernet APIs have been renamed, with the original function name
// being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define EthernetInit(a) \
EthernetInitExpClk(a, SysCtlClockGet())
#define EthernetPacketNonBlockingGet(a, b, c) \
EthernetPacketGetNonBlocking(a, b, c)
#define EthernetPacketNonBlockingPut(a, b, c) \
EthernetPacketPutNonBlocking(a, b, c)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ETHERNET_H__

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//*****************************************************************************
//
// fan.c - Driver for the FAN controller.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_fan.h"
#include "inc/hw_ints.h"
#include "driverlib/fan.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
//! \addtogroup fan_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables a FAN channel for operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to enable.
//!
//! This function enables the specified FAN channel for operation.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelEnable(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Enable the requested channel
//
HWREG(ulBase + FAN_O_CTL) |= 1 << ulChannel;
}
//*****************************************************************************
//
//! Disables a FAN channel for operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to disable.
//!
//! This function disables the specified FAN channel for operation.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelDisable(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Disable the requested channel
//
HWREG(ulBase + FAN_O_CTL) &= ~(1 << ulChannel);
}
//*****************************************************************************
//
//! Gets the status of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for status.
//!
//! This function queries and returns the status of the specified channel.
//! The returned value is one of:
//!
//! - \b FAN_STATUS_STALLED if the cooling fan is stalled
//! - \b FAN_STATUS_CHANGING if the fan is changing to the commanded speed
//! - \b FAN_STATUS_LOCKED if the fan is locked at the commanded speed
//! - \b FAN_STATUS_NOATTAIN if the fan cannot achieve the commanded speed
//!
//! \return Returns the status of the specified FAN channel.
//
//*****************************************************************************
unsigned long
FanChannelStatus(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read and return the status for the specified fan channel
//
return((HWREG(ulBase + FAN_O_STS) >> (ulChannel * 2)) & FAN_STS_ST0_M);
}
//*****************************************************************************
//
//! Configures a FAN channel for manual operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to configure.
//! \param ulConfig is the logical OR of manual configuration flags.
//!
//! This function configures a specific FAN channel to operate in manual
//! mode. The \e ulConfig parameter is the logical OR of several choices of
//! configuration flags as follows:
//!
//! One of the following to select the number of tachometer pulses used for
//! speed averaging:
//!
//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging
//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging
//!
//! One of the following to select the tachometer pulses per revolution:
//!
//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution
//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution
//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution
//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Program the fan channel for manual mode with parameters.
//
HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = FAN_CH0_MAN | ulConfig;
}
//*****************************************************************************
//
//! Configures a FAN channel for automatic operation.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to configure.
//! \param ulConfig is the logical OR of configuration flags.
//!
//! This function configures a specific FAN channel to operate in automatic
//! mode. The \e ulConfig parameter is the logical OR of several choices of
//! configuration flags as follows:
//!
//! One of the following to select the automatic restart mode:
//!
//! - \b FAN_CONFIG_RESTART to enable automatic restart after stall
//! - \b FAN_CONFIG_NORESTART to disable automatic restart after stall
//!
//! One of the following to select the acceleration rate when changing speed:
//!
//! - \b FAN_CONFIG_ACCEL_FAST to select fast acceleration
//! - \b FAN_CONFIG_ACCEL_SLOW to select slow acceleration
//!
//! One of the following to select the number of tachometer pulses to use
//! for the hysteresis count:
//! \b FAN_CONFIG_HYST_1, \b FAN_CONFIG_HYST_2, \b FAN_CONFIG_HYST_4,
//! \b FAN_CONFIG_HYST_8, \b FAN_CONFIG_HYST_16, \b FAN_CONFIG_HYST_32,
//! \b FAN_CONFIG_HYST_64, or \b FAN_CONFIG_HYST_128
//!
//! One of the following to select the start period as the number of tachometer
//! pulses. The start period is the amount of time that a starting PWM duty
//! cycle is used after the FAN channel is commended to a certain speed:
//! \b FAN_CONFIG_START_2, \b FAN_CONFIG_START_4, \b FAN_CONFIG_START_8,
//! \b FAN_CONFIG_START_16, \b FAN_CONFIG_START_32, \b FAN_CONFIG_START_64,
//! \b FAN_CONFIG_START_128, or \b FAN_CONFIG_START_256
//!
//! One of the following to specify the duty cycle that is used when the FAN
//! channel is starting, during the starting period (above):
//!
//! - \b FAN_CONFIG_START_DUTY_OFF to disable the use of startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_50 to select 50% startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_75 to select 75% startup duty cycle
//! - \b FAN_CONFIG_START_DUTY_100 to select 100% startup duty cycle
//!
//! One of the following to select the number of tachometer pulses used for
//! speed averaging:
//!
//! - \b FAN_CONFIG_AVG_NONE to disable fan speed averaging
//! - \b FAN_CONFIG_AVG_2 to select 2 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_4 to select 4 pulses for speed averaging
//! - \b FAN_CONFIG_AVG_8 to select 8 pulses for speed averaging
//!
//! One of the following to select the tachometer pulses per revolution:
//!
//! - \b FAN_CONFIG_TACH_1 to select 1 pulse per revolution
//! - \b FAN_CONFIG_TACH_2 to select 2 pulses per revolution
//! - \b FAN_CONFIG_TACH_4 to select 4 pulses per revolution
//! - \b FAN_CONFIG_TACH_8 to select 8 pulses per revolution
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Program the fan channel for automatic mode with parameters.
//
HWREG(ulBase + FAN_O_CH0 + (ulChannel * 0x10)) = ~FAN_CH0_MAN & ulConfig;
}
//*****************************************************************************
//
//! Sets the duty cycle of a FAN channel when in manual mode.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to program the duty cycle.
//! \param ulDuty is the duty cycle in clocks from 0-511.
//!
//! This function sets the duty cycle of a FAN channel if the channel is
//! configured for manual mode. The duty cycle is specified in clocks from
//! 0-511 out of a 512 clock PWM period.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDuty)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
ASSERT(ulDuty < 512);
//
// Program the specified duty cycle for the specified channel
//
HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) =
(ulDuty << FAN_CMD0_DC_S) & FAN_CMD0_DC_M;
}
//*****************************************************************************
//
//! Reads the duty cycle of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for duty cycle.
//!
//! This function gets the duty cycle of a FAN channel. If the channel is in
//! manual mode, then this is the value that was programmed. If the FAN
//! channel is configured for automatic mode, then this is the value that is
//! calculated by the Fan Control peripheral.
//!
//! \return Returns the FAN channel duty cycle as a number of clocks from
//! 0-511, out of a 512 clock PWM period.
//
//*****************************************************************************
unsigned long
FanChannelDutyGet(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulDuty;
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read the duty cycle field from the command register and shift to
// lower bits for return value.
//
ulDuty = HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) & FAN_CMD0_DC_M;
ulDuty >>= FAN_CMD0_DC_S;
//
// Return the duty cycle for the specified channel.
//
return(ulDuty);
}
//*****************************************************************************
//
//! Sets the RPM of a FAN channel when in automatic mode.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to program the RPM.
//! \param ulRPM is the RPM as a value from 0-8191.
//!
//! This function sets the RPM of the fan channel if the fan channel is
//! configured for automatic mode. If configured for manual mode, then this
//! function has no effect.
//!
//! \return None.
//
//*****************************************************************************
void
FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulRPM)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
ASSERT(ulRPM < 8192);
//
// Program the specified RPM for the specified channel
//
HWREG(ulBase + FAN_O_CMD0 + (ulChannel * 0x10)) = ulRPM;
}
//*****************************************************************************
//
//! Reads the RPM of a FAN channel.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulChannel is the FAN channel to query for RPM.
//!
//! This function gets the RPM of a FAN channel.
//!
//! \return Returns the FAN channel RPM as a number from 0-4095.
//
//*****************************************************************************
unsigned long
FanChannelRPMGet(unsigned long ulBase, unsigned long ulChannel)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(ulChannel <= 5);
//
// Read and return the RPM for the specified channel.
//
return(HWREG(ulBase + FAN_O_CST0 + (ulChannel * 0x10)) & FAN_CST0_RPM_M);
}
//*****************************************************************************
//
//! Enables FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be enabled.
//!
//! This enables one or more interrupts from the FAN module. The \e ulFlags
//! parameter is the logical OR of all the possible interrupts that can be
//! enabled. For each channel, the following interrupt flags are available:
//!
//! - \b FAN_CHn_INT_STALL means that a stall was detected (in either mode).
//! - \b FAN_CHn_INT_AUTO_SPEED_ERROR means that in automatic mode, the cooling
//! fan cannot attain the commanded speed.
//! - \b FAN_CHn_INT_AUTO_SPEED_OK means that in automatic mode, the cooling
//! fan has attained the commanded speed.
//!
//! In the above flag names, the \b CHn placeholder should be replaced with
//! the actual channel number, 0-5 (for example, CH1).
//!
//! The interrupt flags have a different meaning if the FAN channel is
//! configured for manual mode. The following alternate set of flag names is
//! available for convenience to use in manual mode:
//!
//! - \b FAN_CHn_INT_MANUAL_SPEED_UPDATE means that in manual mode the speed
//! was calculated.
//! - \b FAN_CHn_INT_MANUAL_SPEED_CHANGE means that in manual mode, the speed
//! changed.
//!
//! Note that even though the names are different for manual mode, the values
//! are the same. For example \b _AUTO_SPEED_ERROR is the same value as
//! \b _MANUAL_SPEED_UPDATE. The different names are provided just to make it
//! easier to associate a meaning with each interrupt flag.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntEnable(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Enable the requested interrupt sources.
//
HWREG(ulBase + FAN_O_IM) |= ulFlags;
}
//*****************************************************************************
//
//! Disables FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be disabled.
//!
//! This function disables one or more interrupts from the FAN module. The
//! \e ulFlags parameter is the logical OR of all the possible interrupts that
//! can be enabled. For a list of possible interrupt flags, refer to the
//! documentation for the function FanIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
FanIntDisable(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Disable the requested interrupt sources.
//
HWREG(ulBase + FAN_O_IM) &= ~ulFlags;
}
//*****************************************************************************
//
//! Gets the FAN module interrupt status.
//!
//! \param ulBase is the base address of the FAN module.
//! \param bMasked is set \b true to get the masked interrupt status, or
//! \b false to get the raw interrupt status.
//!
//! This function returns the interrupt status of the FAN module. It can
//! return either the raw or masked interrupt status.
//!
//! \return Returns the masked or raw FAN interrupt status, as a bit field
//! of multiple FAN interrupt flags. For a list of all the possible interrupt
//! flags, refer to the documentation for the function FanIntEnable().
//
//*****************************************************************************
unsigned long
FanIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + FAN_O_MIS));
}
else
{
return(HWREG(ulBase + FAN_O_RIS));
}
}
//*****************************************************************************
//
//! Clears pending FAN module interrupts.
//!
//! \param ulBase is the base address of the FAN module.
//! \param ulFlags is the logical OR of all the interrupts to be cleared.
//!
//! This clears one or more interrupts from the FAN module. The \e ulFlags
//! parameter is the logical OR of all the possible interrupts that can be
//! cleared. For a list of possible interrupt flags, refer to the
//! documentation for the function FanIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
FanIntClear(unsigned long ulBase, unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Clear the requested pending interrupts
//
HWREG(ulBase + FAN_O_IC) = ulFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for the FAN module.
//!
//! \param ulBase is the base address of the FAN module.
//! \param pfnHandler is a pointer to the function to be called when the
//! interrupt is activated.
//!
//! This function sets and enables the handler to be called when the FAN module
//! generates an interrupt. Specific FAN interrupts must still be enabled
//! with the FanIntEnable() function.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
ASSERT(pfnHandler);
//
// Register the interrupt handler.
//
IntRegister(INT_FAN0, pfnHandler);
//
// Enable the FAN peripheral interrupt.
//
IntEnable(INT_FAN0);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the FAN module.
//!
//! \param ulBase is the base address of the FAN module.
//!
//! This function disables and clears the handler to be called when the
//! FAN module interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FanIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Disable the FAN peripheral interrupt.
//
IntDisable(INT_FAN0);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FAN0);
}
//*****************************************************************************
//
//! Gets the number of supported FAN channels.
//!
//! \param ulBase is the base address of the FAN module.
//!
//! This function gets the number of FAN channels that are supported by the
//! Fan Control peripheral.
//!
//! \return Returns the number of FAN channels.
//
//*****************************************************************************
unsigned long
FanChannelsGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == FAN0_BASE);
//
// Read and return the fan channel count
//
return(HWREG(ulBase + FAN_O_PP) & FAN_PP_CHAN_M);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// fan.h - Prototypes and macros for the Fan controller.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FAN_H__
#define __FAN_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Fan status values that can be returned from the FanChannelStatus() function.
//
//*****************************************************************************
#define FAN_STATUS_STALLED 0
#define FAN_STATUS_CHANGING 1
#define FAN_STATUS_LOCKED 2
#define FAN_STATUS_NOATTAIN 3
//*****************************************************************************
//
// Configuration flags to be used with FanChannelConfigManual() and
// FanChannelConfigAuto().
//
//*****************************************************************************
#define FAN_CONFIG_RESTART (1 << 15)
#define FAN_CONFIG_NORESTART (0 << 15)
#define FAN_CONFIG_ACCEL_FAST (1 << 14)
#define FAN_CONFIG_ACCEL_SLOW (0 << 14)
#define FAN_CONFIG_HYST_1 (0 << 11)
#define FAN_CONFIG_HYST_2 (1 << 11)
#define FAN_CONFIG_HYST_4 (2 << 11)
#define FAN_CONFIG_HYST_8 (3 << 11)
#define FAN_CONFIG_HYST_16 (4 << 11)
#define FAN_CONFIG_HYST_32 (5 << 11)
#define FAN_CONFIG_HYST_64 (6 << 11)
#define FAN_CONFIG_HYST_128 (7 << 11)
#define FAN_CONFIG_START_2 (0 << 8)
#define FAN_CONFIG_START_4 (1 << 8)
#define FAN_CONFIG_START_8 (2 << 8)
#define FAN_CONFIG_START_16 (3 << 8)
#define FAN_CONFIG_START_32 (4 << 8)
#define FAN_CONFIG_START_64 (5 << 8)
#define FAN_CONFIG_START_128 (6 << 8)
#define FAN_CONFIG_START_256 (7 << 8)
#define FAN_CONFIG_START_DUTY_OFF (0 << 6)
#define FAN_CONFIG_START_DUTY_50 (1 << 6)
#define FAN_CONFIG_START_DUTY_75 (2 << 6)
#define FAN_CONFIG_START_DUTY_100 (3 << 6)
#define FAN_CONFIG_AVG_NONE (0 << 4)
#define FAN_CONFIG_AVG_2 (1 << 4)
#define FAN_CONFIG_AVG_4 (2 << 4)
#define FAN_CONFIG_AVG_8 (3 << 4)
#define FAN_CONFIG_TACH_1 (0 << 2)
#define FAN_CONFIG_TACH_2 (1 << 2)
#define FAN_CONFIG_TACH_4 (2 << 2)
#define FAN_CONFIG_TACH_8 (3 << 2)
//*****************************************************************************
//
// Interrupt configuration/status flags to be used with the following
// functions: FanIntEnable(), FanIntDisable(), FanIntStatus(), FanIntClear().
//
//*****************************************************************************
#define FAN_CH5_INT_AUTO_SPEED_OK (1 << 22)
#define FAN_CH5_INT_MANUAL_SPEED_CHANGE (1 << 22)
#define FAN_CH5_INT_AUTO_SPEED_ERROR (1 << 21)
#define FAN_CH5_INT_MANUAL_SPEED_UPDATE (1 << 21)
#define FAN_CH5_INT_STALL (1 << 20)
#define FAN_CH4_INT_AUTO_SPEED_OK (1 << 18)
#define FAN_CH4_INT_MANUAL_SPEED_CHANGE (1 << 18)
#define FAN_CH4_INT_AUTO_SPEED_ERROR (1 << 17)
#define FAN_CH4_INT_MANUAL_SPEED_UPDATE (1 << 17)
#define FAN_CH4_INT_STALL (1 << 16)
#define FAN_CH3_INT_AUTO_SPEED_OK (1 << 14)
#define FAN_CH3_INT_MANUAL_SPEED_CHANGE (1 << 14)
#define FAN_CH3_INT_AUTO_SPEED_ERROR (1 << 13)
#define FAN_CH3_INT_MANUAL_SPEED_UPDATE (1 << 13)
#define FAN_CH3_INT_STALL (1 << 12)
#define FAN_CH2_INT_AUTO_SPEED_OK (1 << 10)
#define FAN_CH2_INT_MANUAL_SPEED_CHANGE (1 << 10)
#define FAN_CH2_INT_AUTO_SPEED_ERROR (1 << 9)
#define FAN_CH2_INT_MANUAL_SPEED_UPDATE (1 << 9)
#define FAN_CH2_INT_STALL (1 << 8)
#define FAN_CH1_INT_AUTO_SPEED_OK (1 << 6)
#define FAN_CH1_INT_MANUAL_SPEED_CHANGE (1 << 6)
#define FAN_CH1_INT_AUTO_SPEED_ERROR (1 << 5)
#define FAN_CH1_INT_MANUAL_SPEED_UPDATE (1 << 5)
#define FAN_CH1_INT_STALL (1 << 4)
#define FAN_CH0_INT_AUTO_SPEED_OK (1 << 2)
#define FAN_CH0_INT_MANUAL_SPEED_CHANGE (1 << 2)
#define FAN_CH0_INT_AUTO_SPEED_ERROR (1 << 1)
#define FAN_CH0_INT_MANUAL_SPEED_UPDATE (1 << 1)
#define FAN_CH0_INT_STALL (1 << 0)
#define FAN_CHx_INT_AUTO_SPEED_OK(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_MANUAL_SPEED_CHANGE(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_AUTO_SPEED_ERROR(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_MANUAL_SPEED_UPDATE(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_STALL(x) (1 << ((x) * 4))
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void FanChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void FanChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern unsigned long FanChannelStatus(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDuty);
extern unsigned long FanChannelDutyGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulRPM);
extern unsigned long FanChannelRPMGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanIntEnable(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntDisable(unsigned long ulBase, unsigned long ulFlags);
extern unsigned long FanIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void FanIntClear(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void FanIntUnregister(unsigned long ulBase);
extern unsigned long FanChannelsGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FAN_H__

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bsp/lm4f232/Libraries/driverlib/flash.c Normal file
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@ -0,0 +1,913 @@
//*****************************************************************************
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "inc/hw_flash.h"
#include "inc/hw_ints.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/flash.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Program Enable (FMPPE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPPERegs[] =
{
FLASH_FMPPE,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3
};
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Read Enable (FMPRE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPRERegs[] =
{
FLASH_FMPRE,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3
};
//*****************************************************************************
//
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//!
//! \return Returns the number of processor clocks per micro-second.
//
//*****************************************************************************
unsigned long
FlashUsecGet(void)
{
//
// Return the number of clocks per micro-second.
//
return(HWREG(FLASH_USECRL) + 1);
}
//*****************************************************************************
//
//! Sets the number of processor clocks per micro-second.
//!
//! \param ulClocks is the number of processor clocks per micro-second.
//!
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//!
//! \return None.
//
//*****************************************************************************
void
FlashUsecSet(unsigned long ulClocks)
{
//
// Set the number of clocks per micro-second.
//
HWREG(FLASH_USECRL) = ulClocks - 1;
}
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block is filled with 0xFF bytes. Read-only and execute-only blocks
//! cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC);
//
// Erase the block.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
//
// Wait until the block has been erased.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times will result in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words.
//
HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
{
}
}
}
else
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_FMA) = ulAddress;
HWREG(FLASH_FMD) = *pulData;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Calculate the Flash Bank from Base Address, and mask off the Bank
// from ulAddress for subsequent reference.
//
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
//
// Read the appropriate flash protection registers for the specified
// flash bank.
//
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG protect options, and are
// not available for the FLASH protection scheme. When Querying Block
// Protection, assume these bits are 1.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
}
//
// Check the appropriate protection bits for the block of memory that
// is specified by the address.
//
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fetch interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (that is, it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
//*****************************************************************************
//
//! Sets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be protected.
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (that is, read-only to read/write) will
//! result in a failure (and be prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
//! protection was specified.
//
//*****************************************************************************
long
FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
unsigned long ulProtectRE, ulProtectPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
(eProtect == FlashExecuteOnly));
//
// Convert the address into a block number.
//
ulAddress /= FLASH_PROTECT_SIZE;
//
// ulAddress contains a "raw" block number. Derive the Flash Bank from
// the "raw" block number, and convert ulAddress to a "relative"
// block number.
//
ulBank = ((ulAddress / 32) % 4);
ulAddress %= 32;
//
// Get the current protection for the specified flash bank.
//
ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG protect options, and are
// not available for the FLASH protection scheme. When setting protection,
// check to see if block 30 or 31 and protection is FlashExecuteOnly. If
// so, return an error condition.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
{
return(-1);
}
}
//
// Set the protection based on the requested proection.
//
switch(eProtect)
{
//
// Make this block execute only.
//
case FlashExecuteOnly:
{
//
// Turn off the read and program bits for this block.
//
ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read only.
//
case FlashReadOnly:
{
//
// The block can not be made read only if it is execute only.
//
if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0)
{
return(-1);
}
//
// Make this block read only.
//
ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
//
// We're done handling this protection.
//
break;
}
//
// Make this block read/write.
//
case FlashReadWrite:
default:
{
//
// The block can not be made read/write if it is not already
// read/write.
//
if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0) ||
(((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
FLASH_FMP_BLOCK_0))
{
return(-1);
}
//
// The block is already read/write, so there is nothing to do.
//
return(0);
}
}
//
// For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
// bits of the FMPPE register are used for JTAG options, and are not
// available for the FLASH protection scheme. When setting block
// protection, ensure that these bits are not altered.
//
if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
{
ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
}
//
// Set the new protection for the specified flash bank.
//
HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashProtectSave(void)
{
unsigned long ulTemp, ulLimit;
//
// If running on a Sandstorm-class device, only trigger a save of the first
// two protection registers (FMPRE and FMPPE). Otherwise, save the
// entire bank of flash protection registers.
//
ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
{
//
// Tell the flash controller to write the flash protection register.
//
HWREG(FLASH_FMA) = ulTemp;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the user registers.
//!
//! \param pulUser0 is a pointer to the location to store USER Register 0.
//! \param pulUser1 is a pointer to the location to store USER Register 1.
//!
//! This function will read the contents of user registers (0 and 1), and
//! store them in the specified locations.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
{
//
// Verify that the pointers are valid.
//
ASSERT(pulUser0 != 0);
ASSERT(pulUser1 != 0);
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Get and store the current value of the user registers.
//
*pulUser0 = HWREG(FLASH_USERREG0);
*pulUser1 = HWREG(FLASH_USERREG1);
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Sets the user registers.
//!
//! \param ulUser0 is the value to store in USER Register 0.
//! \param ulUser1 is the value to store in USER Register 1.
//!
//! This function will set the contents of the user registers (0 and 1) to
//! the specified values.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
{
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Save the new values into the user registers.
//
HWREG(FLASH_USERREG0) = ulUser0;
HWREG(FLASH_USERREG1) = ulUser1;
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Saves the user registers.
//!
//! This function will make the currently programmed user register settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change this setting.
//!
//! This function will not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
//*****************************************************************************
long
FlashUserSave(void)
{
//
// Verify that hardware supports user registers.
//
if(CLASS_IS_SANDSTORM)
{
return(-1);
}
//
// Setting the MSB of FMA will trigger a permanent save of a USER
// register. Bit 0 will indicate User 0 (0) or User 1 (1).
//
HWREG(FLASH_FMA) = 0x80000000;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Tell the flash controller to write the USER1 Register.
//
HWREG(FLASH_FMA) = 0x80000001;
HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
//
// Wait until the write has completed.
//
while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
{
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt is automatically
//! enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_FCIM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_FCIM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
//
//*****************************************************************************
unsigned long
FlashIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_FCMISC));
}
else
{
return(HWREG(FLASH_FCRIS));
}
}
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_FCMISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long FlashUsecGet(void);
extern void FlashUsecSet(unsigned long ulClocks);
extern long FlashErase(unsigned long ulAddress);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
extern long FlashProtectSet(unsigned long ulAddress,
tFlashProtection eProtect);
extern long FlashProtectSave(void);
extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
extern long FlashUserSave(void);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Deprecated function names. These definitions ensure backwards compatibility
// but new code should avoid using deprecated function names since these will
// be removed at some point in the future.
//
//*****************************************************************************
#ifndef DEPRECATED
#define FlashIntGetStatus FlashIntStatus
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

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//*****************************************************************************
//
// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
// processor.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup fpu_api
//! @{
//
//*****************************************************************************
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "fpu.h"
//*****************************************************************************
//
//! Enables the floating-point unit.
//!
//! This function enables the floating-point unit, allowing the floating-point
//! instructions to be executed. This function must be called prior to
//! performing any hardware floating-point operations; failure to do so results
//! in a NOCP usage fault.
//!
//! \return None.
//
//*****************************************************************************
void
FPUEnable(void)
{
//
// Enable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
}
//*****************************************************************************
//
//! Disables the floating-point unit.
//!
//! This function disables the floating-point unit, preventing floating-point
//! instructions from executing (generating a NOCP usage fault instead).
//!
//! \return None.
//
//*****************************************************************************
void
FPUDisable(void)
{
//
// Disable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS);
}
//*****************************************************************************
//
//! Enables the stacking of floating-point registers.
//!
//! This function enables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When enabled, space is reserved on the stack for
//! the floating-point context and the floating-point state is saved into this
//! stack space. Upon return from the interrupt, the floating-point context is
//! restored.
//!
//! If the floating-point registers are not stacked, floating-point
//! instructions cannot be safely executed in an interrupt handler because the
//! values of s0-s15 are not likely to be preserved for the interrupted code.
//! On the other hand, stacking the floating-point registers increases the
//! stacking operation from 8 words to 26 words, also increasing the interrupt
//! response latency.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingEnable(void)
{
//
// Enable automatic state preservation for the floating-point unit, and
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN;
}
//*****************************************************************************
//
//! Enables the lazy stacking of floating-point registers.
//!
//! This function enables the lazy stacking of floating-point registers s0-s15
//! when an interrupt is handled. When lazy stacking is enabled, space is
//! reserved on the stack for the floating-point context, but the
//! floating-point state is not saved. If a floating-point instruction is
//! executed from within the interrupt context, the floating-point context is
//! first saved into the space reserved on the stack. On completion of the
//! interrupt handler, the floating-point context is only restored if it was
//! saved (as the result of executing a floating-point instruction).
//!
//! This provides a compromise between fast interrupt response (because the
//! floating-point state is not saved on interrupt entry) and the ability to
//! use floating-point in interrupt handlers (because the floating-point state
//! is saved if floating-point instructions are used).
//!
//! \return None.
//
//*****************************************************************************
void
FPULazyStackingEnable(void)
{
//
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN;
}
//*****************************************************************************
//
//! Disables the stacking of floating-point registers.
//!
//! This function disables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When floating-point context stacking is disabled,
//! floating-point operations performed in an interrupt handler destroy the
//! floating-point context of the main thread of execution.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingDisable(void)
{
//
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN);
}
//*****************************************************************************
//
//! Selects the format of half-precision floating-point values.
//!
//! \param ulMode is the format for half-precision floating-point values; which
//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
//!
//! This function selects between the IEEE half-precision floating-point
//! representation and the Cortex-M processor alternative representation. The
//! alternative representation has a larger range but does not have a way to
//! encode infinity (positive or negative) or NaN (quiet or signaling). The
//! default setting is the IEEE format.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUHalfPrecisionModeSet(unsigned long ulMode)
{
//
// Set the half-precision floating-point format.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode;
}
//*****************************************************************************
//
//! Selects the NaN mode.
//!
//! \param ulMode is the mode for NaN results; which is either
//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
//!
//! This function selects the handling of NaN results during floating-point
//! computations. NaNs can either propagate (the default), or they can return
//! the default NaN.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUNaNModeSet(unsigned long ulMode)
{
//
// Set the NaN mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode;
}
//*****************************************************************************
//
//! Selects the flush-to-zero mode.
//!
//! \param ulMode is the flush-to-zero mode; which is either
//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
//!
//! This function enables or disables the flush-to-zero mode of the
//! floating-point unit. When disabled (the default), the floating-point unit
//! is fully IEEE compliant. When enabled, values close to zero are treated as
//! zero, greatly improving the execution speed at the expense of some accuracy
//! (as well as IEEE compliance).
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUFlushToZeroModeSet(unsigned long ulMode)
{
//
// Set the flush-to-zero mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode;
}
//*****************************************************************************
//
//! Selects the rounding mode for floating-point results.
//!
//! \param ulMode is the rounding mode.
//!
//! This function selects the rounding mode for floating-point results. After
//! a floating-point operation, the result is rounded toward the specified
//! value. The default mode is \b FPU_ROUND_NEAREST.
//!
//! The following rounding modes are available (as specified by \e ulMode):
//!
//! - \b FPU_ROUND_NEAREST - round toward the nearest value
//! - \b FPU_ROUND_POS_INF - round toward positive infinity
//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
//! - \b FPU_ROUND_ZERO - round toward zero
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPURoundingModeSet(unsigned long ulMode)
{
//
// Set the rounding mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// fpu.h - Prototypes for the floatint point manipulation routines.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FPU_H__
#define __FPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void FPUEnable(void);
extern void FPUDisable(void);
extern void FPUStackingEnable(void);
extern void FPULazyStackingEnable(void);
extern void FPUStackingDisable(void);
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
extern void FPUNaNModeSet(unsigned long ulMode);
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
extern void FPURoundingModeSet(unsigned long ulMode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FPU_H__

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//*****************************************************************************
//
// gpio.h - Defines and Macros for GPIO API.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
//
//*****************************************************************************
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
//*****************************************************************************
//
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
//
//*****************************************************************************
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulStrength,
unsigned long ulPadType);
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
unsigned long *pulStrength,
unsigned long *pulPadType);
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPortIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOPortIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern void GPIOPinConfigure(unsigned long ulPinConfig);
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
unsigned char ucPins);
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
//****************************************************************************
//
// The definitions for GPIOPinConfigure previously resided in this file but
// have been moved to pin_map.h and made part-specific (in other words, only
// those definitions that are valid based on the selected part, as defined by
// PART_<partnum>, will be made available). For backwards compatibility,
// pin_map.h is included here so that the expected definitions will still be
// available (though part-specific now, so some that were previously available
// but inappropriate for the given part will not be available).
//
//*****************************************************************************
#ifndef DEPRECATED
#include "pin_map.h"
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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//*****************************************************************************
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __HIBERNATE_H__
#define __HIBERNATE_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x00000010
#define HIBERNATE_WAKE_RTC 0x00000008
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
#define HIBERNATE_INT_PIN_WAKE 0x00000008
#define HIBERNATE_INT_LOW_BAT 0x00000004
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
//*****************************************************************************
//
// Macros defining oscillator configuration options for the
// HibernateClockConfig() function.
//
//*****************************************************************************
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
#define HIBERNATE_OSC_DISABLE 0x00010000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HibernateEnableExpClk(unsigned long ulHibClk);
extern void HibernateDisable(void);
extern void HibernateClockSelect(unsigned long ulClockInput);
extern void HibernateRTCEnable(void);
extern void HibernateRTCDisable(void);
extern void HibernateWakeSet(unsigned long ulWakeFlags);
extern unsigned long HibernateWakeGet(void);
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
extern unsigned long HibernateLowBatGet(void);
extern void HibernateRTCSet(unsigned long ulRTCValue);
extern unsigned long HibernateRTCGet(void);
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch0Get(void);
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
extern unsigned long HibernateRTCMatch1Get(void);
extern void HibernateRTCTrimSet(unsigned long ulTrim);
extern unsigned long HibernateRTCTrimGet(void);
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
extern void HibernateRequest(void);
extern void HibernateIntEnable(unsigned long ulIntFlags);
extern void HibernateIntDisable(unsigned long ulIntFlags);
extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned long HibernateIsActive(void);
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCSSMatch0Get(void);
extern unsigned long HibernateRTCSSGet(void);
extern void HibernateClockConfig(unsigned long ulConfig);
extern void HibernateBatCheckStart(void);
extern unsigned long HibernateBatCheckDone(void);
//*****************************************************************************
//
// Several Hibernate module APIs have been renamed, with the original function
// name being deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define HibernateEnable(a) \
HibernateEnableExpClk(a, SysCtlClockGet())
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HIBERNATE_H__

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//*****************************************************************************
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2C_H__
#define __I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
extern void I2CIntUnregister(unsigned long ulBase);
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
extern tBoolean I2CMasterBusy(unsigned long ulBase);
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CMasterDisable(unsigned long ulBase);
extern void I2CMasterEnable(unsigned long ulBase);
extern unsigned long I2CMasterErr(unsigned long ulBase);
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
tBoolean bFast);
extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterIntEnableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern void I2CMasterIntClearEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2CSlaveIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
//*****************************************************************************
//
// Several I2C APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define I2CMasterInit(a, b) \
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2C_H__

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//*****************************************************************************
//
// i2s.h - Prototypes and macros for the I2S controller.
//
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __I2S_H__
#define __I2S_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet()
//
//*****************************************************************************
#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP
#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP
#define I2S_CONFIG_FORMAT_LEFT_JUST \
0x00000000 // !JST, !DLY, !SCP, !LRP
#define I2S_CONFIG_FORMAT_RIGHT_JUST \
0x20000000 // JST, !DLY, !SCP, !LRP
#define I2S_CONFIG_SCLK_INVERT 0x08000000
#define I2S_CONFIG_MODE_MASK 0x03000000
#define I2S_CONFIG_MODE_DUAL 0x00000000
#define I2S_CONFIG_MODE_COMPACT_16 \
0x01000000
#define I2S_CONFIG_MODE_COMPACT_8 \
0x03000000
#define I2S_CONFIG_MODE_MONO 0x02000000
#define I2S_CONFIG_EMPTY_MASK 0x00800000
#define I2S_CONFIG_EMPTY_ZERO 0x00000000
#define I2S_CONFIG_EMPTY_REPEAT 0x00800000
#define I2S_CONFIG_CLK_MASK 0x00400000
#define I2S_CONFIG_CLK_MASTER 0x00400000
#define I2S_CONFIG_CLK_SLAVE 0x00000000
#define I2S_CONFIG_SAMPLE_SIZE_MASK \
0x0000FC00
#define I2S_CONFIG_SAMPLE_SIZE_32 \
0x00007C00
#define I2S_CONFIG_SAMPLE_SIZE_24 \
0x00005C00
#define I2S_CONFIG_SAMPLE_SIZE_20 \
0x00004C00
#define I2S_CONFIG_SAMPLE_SIZE_16 \
0x00003C00
#define I2S_CONFIG_SAMPLE_SIZE_8 \
0x00001C00
#define I2S_CONFIG_WIRE_SIZE_MASK \
0x000003F0
#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0
#define I2S_CONFIG_WIRE_SIZE_24 0x00000170
#define I2S_CONFIG_WIRE_SIZE_20 0x00000130
#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0
#define I2S_CONFIG_WIRE_SIZE_8 0x00000070
//*****************************************************************************
//
// Values that can be passed to I2SMasterClockSelect()
//
//*****************************************************************************
#define I2S_TX_MCLK_EXT 0x00000010
#define I2S_TX_MCLK_INT 0x00000000
#define I2S_RX_MCLK_EXT 0x00000020
#define I2S_RX_MCLK_INT 0x00000000
//*****************************************************************************
//
// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and
// I2SIntClear()
//
//*****************************************************************************
#define I2S_INT_RXERR 0x00000020
#define I2S_INT_RXREQ 0x00000010
#define I2S_INT_TXERR 0x00000002
#define I2S_INT_TXREQ 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void I2STxEnable(unsigned long ulBase);
extern void I2STxDisable(unsigned long ulBase);
extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData);
extern long I2STxDataPutNonBlocking(unsigned long ulBase,
unsigned long ulData);
extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase);
extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase);
extern void I2SRxEnable(unsigned long ulBase);
extern void I2SRxDisable(unsigned long ulBase);
extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData);
extern long I2SRxDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase);
extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase);
extern void I2STxRxEnable(unsigned long ulBase);
extern void I2STxRxDisable(unsigned long ulBase);
extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock);
extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __I2S_H__

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//*****************************************************************************
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/cpu.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
};
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// The processor vector table.
//
// This contains a list of the handlers for the various interrupt sources in
// the system. The layout of this list is defined by the hardware; assertion
// of an interrupt causes the processor to start executing directly at the
// address given in the corresponding location in this list.
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#elif defined(sourcerygxx)
static __attribute__((section(".cs3.region-head.ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#elif defined(ccs) || defined(DOXYGEN)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
return(CPUcpsie());
}
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
return(CPUcpsid());
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function is called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! \return None.
//
//*****************************************************************************
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long ulIdx, ulValue;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Make sure that the RAM vector table is correctly aligned.
//
ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
//
// See if the RAM vector table has been initialized.
//
if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
{
//
// Copy the vector table from the beginning of FLASH to the RAM vector
// table.
//
ulValue = HWREG(NVIC_VTABLE);
for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
{
g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
ulValue);
}
//
// Point NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
//
// Save the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = pfnHandler;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source is
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
IntUnregister(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Reset the interrupt handler.
//
g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
}
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the Stellaris family, three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
//! hardware priority mechanism on a future part. This arrangement allows
//! priorities to migrate to different NVIC implementations without changing
//! the gross prioritization of the interrupts.
//!
//! \return None.
//
//*****************************************************************************
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Pends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendSet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to pend.
//
if(ulInterrupt == FAULT_NMI)
{
//
// Pend the NMI interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
}
else if(ulInterrupt == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
}
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Unpends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendClear(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to unpend.
//
if(ulInterrupt == FAULT_PENDSV)
{
//
// Unpend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that is masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater is blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityMaskSet(unsigned long ulPriorityMask)
{
CPUbasepriSet(ulPriorityMask);
}
//*****************************************************************************
//
//! Gets the priority masking level
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater is blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
unsigned long
IntPriorityMaskGet(void)
{
return(CPUbasepriGet());
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
extern void IntPendSet(unsigned long ulInterrupt);
extern void IntPendClear(unsigned long ulInterrupt);
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
extern unsigned long IntPriorityMaskGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

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//*****************************************************************************
//
// lpc.h - Prototypes for the Low Pin Count (LPC) driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __LPC_H__
#define __LPC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to LPCConfigSet as the ulConfig value, and
// returned from LPCConfigGet.
//
//*****************************************************************************
#define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus
//*****************************************************************************
//
// Values that can be returned from LPCStatus.
//
//*****************************************************************************
#define LPC_STATUS_RST 0x00000400 // LPC is in Reset
#define LPC_STATUS_BUSY 0x00000200 // LPC is Busy
#define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode
#define LPC_STATUS_CA7 0x00000080 // Channel 7 Active
#define LPC_STATUS_CA6 0x00000040 // Channel 6 Active
#define LPC_STATUS_CA5 0x00000020 // Channel 5 Active
#define LPC_STATUS_CA4 0x00000010 // Channel 4 Active
#define LPC_STATUS_CA3 0x00000008 // Channel 3 Active
#define LPC_STATUS_CA2 0x00000004 // Channel 2 Active
#define LPC_STATUS_CA1 0x00000002 // Channel 1 Active
#define LPC_STATUS_CA0 0x00000001 // Channel 0 Active
//*****************************************************************************
//
// Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ
// parameter and returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ15 0x80000000 // Serial IRQ15
#define LPC_IRQ14 0x40000000 // Serial IRQ14
#define LPC_IRQ13 0x20000000 // Serial IRQ13
#define LPC_IRQ12 0x10000000 // Serial IRQ12
#define LPC_IRQ11 0x08000000 // Serial IRQ11
#define LPC_IRQ10 0x04000000 // Serial IRQ10
#define LPC_IRQ9 0x02000000 // Serial IRQ9
#define LPC_IRQ8 0x01000000 // Serial IRQ8
#define LPC_IRQ7 0x00800000 // Serial IRQ7
#define LPC_IRQ6 0x00400000 // Serial IRQ6
#define LPC_IRQ5 0x00200000 // Serial IRQ5
#define LPC_IRQ4 0x00100000 // Serial IRQ4
#define LPC_IRQ3 0x00080000 // Serial IRQ3
#define LPC_IRQ2 0x00040000 // Serial IRQ2
#define LPC_IRQ1 0x00020000 // Serial IRQ1
#define LPC_IRQ0 0x00010000 // Serial IRQ0
//*****************************************************************************
//
// Addition values that can be returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress
#define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode
//*****************************************************************************
//
// Values that can be passed as the ulChannel parameter in LPCChannel...
// API calls.
//
//*****************************************************************************
#define LPC_CHAN_CH0 0 // LPC Channel 0
#define LPC_CHAN_CH1 1 // LPC Channel 1
#define LPC_CHAN_CH2 2 // LPC Channel 2
#define LPC_CHAN_CH3 3 // LPC Channel 3
#define LPC_CHAN_CH4 4 // LPC Channel 4
#define LPC_CHAN_CH5 5 // LPC Channel 5
#define LPC_CHAN_CH6 6 // LPC Channel 6
#define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx)
#define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx)
//*****************************************************************************
//
// Values that can be passed as part of the ulConfig parameter in the
// LPCChannelConfig... functions.
//
//*****************************************************************************
#define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled
#define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0
#define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1
#define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2
#define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3
#define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4
#define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5
#define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6
#define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7
#define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8
#define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9
#define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10
#define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11
#define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12
#define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13
#define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14
#define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15
#define LPC_CHAN_COMxIRQ_DISABLE \
0x00000000 // LCP Channel COMx IRQ Disabled
#define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled
#define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled
#define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0
#define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1
#define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2
#define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3
#define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4
#define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5
#define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6
#define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7
#define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8
#define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9
#define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10
#define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11
#define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12
#define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13
#define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14
#define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15
#define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled
#define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0
#define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1
#define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2
#define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3
#define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4
#define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5
#define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6
#define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7
#define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8
#define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9
#define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10
#define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11
#define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12
#define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13
#define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14
#define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15
#define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled
#define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1
#define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2
#define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3
#define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration
// enabled.
#define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration
// disabled.
#define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size
// is 4 Bytes.
//*****************************************************************************
//
// Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode
// parameter or returned from LPCChannelConfigGet in the pulCOMxMode
// parameter.
//
//*****************************************************************************
#define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model.
#define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data.
#define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to
// memory
#define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to
// UART1
//*****************************************************************************
//
// Additinal values that can be returned from LPCChannelConfigGet in the
// pulCOMxMode parameter.
//
//*****************************************************************************
#define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled.
//*****************************************************************************
//
// Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear
// as the ulIntFlags parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits
// Reset State.
#define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits
// Sleep State.
#define LPC_INT_COMx 0x20000000 // COMx has read/written
// data.
#define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed
#define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read.
#define LPC_INT_CH6_EP_FROM_DATA \
(2 << 24) // From-Host has been written as
// data.
#define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as
// command.
#define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST)
#define LPC_INT_CH6_MB_HOST_WRITE \
(2 << 24) // Host Wrote Last Byte.
#define LPC_INT_CH6_MB_HOST_READ \
(4 << 24) // Host Read Last Byte
#define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read.
#define LPC_INT_CH5_EP_FROM_DATA \
(2 << 20) // From-Host has been written as
// data.
#define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as
// command.
#define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST)
#define LPC_INT_CH5_MB_HOST_WRITE \
(2 << 20) // Host Wrote Last Byte.
#define LPC_INT_CH5_MB_HOST_READ \
(4 << 20) // Host Read Last Byte
#define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read.
#define LPC_INT_CH4_EP_FROM_DATA \
(2 << 16) // From-Host has been written as
// data.
#define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as
// command.
#define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST)
#define LPC_INT_CH4_MB_HOST_WRITE \
(2 << 16) // Host Wrote Last Byte.
#define LPC_INT_CH4_MB_HOST_READ \
(4 << 16) // Host Read Last Byte
#define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read.
#define LPC_INT_CH3_EP_FROM_DATA \
(2 << 12) // From-Host has been written as
// data.
#define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as
// command.
#define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST)
#define LPC_INT_CH3_MB_HOST_WRITE \
(2 << 12) // Host Wrote Last Byte.
#define LPC_INT_CH3_MB_HOST_READ \
(4 << 12) // Host Read Last Byte
#define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read.
#define LPC_INT_CH2_EP_FROM_DATA \
(2 << 8) // From-Host has been written as
// data.
#define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as
// command.
#define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST)
#define LPC_INT_CH2_MB_HOST_WRITE \
(2 << 8) // Host Wrote Last Byte.
#define LPC_INT_CH2_MB_HOST_READ \
(4 << 8) // Host Read Last Byte
#define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read.
#define LPC_INT_CH1_EP_FROM_DATA \
(2 << 4) // From-Host has been written as
// data.
#define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as
// command.
#define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST)
#define LPC_INT_CH1_MB_HOST_WRITE \
(2 << 4) // Host Wrote Last Byte.
#define LPC_INT_CH1_MB_HOST_READ \
(4 << 4) // Host Read Last Byte
#define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read.
#define LPC_INT_CH0_EP_FROM_DATA \
(2 << 0) // From-Host has been written as
// data.
#define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as
// command.
#define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST)
#define LPC_INT_CH0_MB_HOST_WRITE \
(2 << 0) // Host Wrote Last Byte.
#define LPC_INT_CH0_MB_HOST_READ \
(4 << 0) // Host Read Last Byte
#define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST).
//*****************************************************************************
//
// Values that can be passed to LPCCOMxInt... functions as the ulIntFlags
// parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx
#define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX
#define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX
#define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx
#define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX
#define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX
//*****************************************************************************
//
// Values that can be passed to the LPCChannelDMAConfigSet function as part
// of the ulConfig or ulMask parameter, or can be returned from the
// LPCChannelConfigGet function.
//
//*****************************************************************************
#define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host"
// data buffer is full.
//*****************************************************************************
//
// Values that can be passed to the LPCChannelStatusSet and
// LPCChannelStatusClear function, and returned by the LPCChannelStatusGet
// function.
//
//*****************************************************************************
#define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0
#define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1
#define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2
#define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3
#define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4
//*****************************************************************************
//
// Additinoal values that can be returned by the LPCChannelStatusGet function.
//
//*****************************************************************************
#define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH_ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH_ST_CMD 0x00000008 // Command or Data
#define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long LPCConfigGet(unsigned long ulBase);
extern unsigned long LPCStatusGet(unsigned long ulBase,
unsigned long *pulCount,
unsigned long *pulPoolSize);
extern void LPCStatusBlockAddressSet(unsigned long ulBase,
unsigned long ulAddress,
tBoolean bEnabled);
extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase);
extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount);
extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse,
tBoolean bIRQOnChange);
extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ);
extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ);
extern unsigned long LPCIRQGet(unsigned long ulBase);
extern void LPCIRQSend(unsigned long ulBase);
extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void LPCIntUnregister(unsigned long ulBase);
extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelConfigEPSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigMBSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigCOMxSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset,
unsigned long ulCOMxMode);
extern unsigned long LPCChannelConfigGet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long *pulAddress,
unsigned long *pulOffset,
unsigned long *pulCOMxMode);
extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long LPCChannelStatusGet(unsigned long ulBase,
unsigned long ulChannel);
extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelStatusClear(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelDMAConfigSet(unsigned long ulBase,
unsigned long ulConfig,
unsigned long ulMask);
extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase);
extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned char ucData);
extern unsigned short LPCHalfWordRead(unsigned long ulBase,
unsigned long ulOffset);
extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned short usData);
extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned long ulData);
extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __LPC_H__

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bsp/lm4f232/Libraries/driverlib/mpu.c Normal file
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//*****************************************************************************
//
// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup mpu_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/mpu.h"
//*****************************************************************************
//
//! Enables and configures the MPU for use.
//!
//! \param ulMPUConfig is the logical OR of the possible configurations.
//!
//! This function enables the Cortex-M3 memory protection unit. It also
//! configures the default behavior when in privileged mode and while handling
//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
//! be set by calling MPURegionSet() or else by enabling the default region for
//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
//! MPUEnable(). Once the MPU is enabled, a memory management fault are
//! generated for any memory access violations.
//!
//! The \e ulMPUConfig parameter should be the logical OR of any of the
//! following:
//!
//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
//! privileged mode and when no other regions are defined. If this option
//! is not enabled, then there must be at least one valid region already
//! defined when the MPU is enabled.
//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
//! exception handler. If this option is not enabled, then the MPU is
//! disabled while in one of these exception handlers and the default
//! memory map is applied.
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
//! no default memory map is provided in privileged mode, and the MPU will
//! not be enabled in the fault handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUEnable(unsigned long ulMPUConfig)
{
//
// Check the arguments.
//
ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
MPU_CONFIG_HARDFLT_NMI)));
//
// Set the MPU control bits according to the flags passed by the user,
// and also set the enable bit.
//
HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the MPU for use.
//!
//! This function disables the Cortex-M3 memory protection unit. When the
//! MPU is disabled, the default memory map is used and memory management
//! faults are not generated.
//!
//! \return None.
//
//*****************************************************************************
void
MPUDisable(void)
{
//
// Turn off the MPU enable bit.
//
HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Gets the count of regions supported by the MPU.
//!
//! This function is used to get the number of regions that are supported by
//! the MPU. This is the total number that are supported, including regions
//! that are already programmed.
//!
//! \return The number of memory protection regions that are available
//! for programming using MPURegionSet().
//
//*****************************************************************************
unsigned long
MPURegionCountGet(void)
{
//
// Read the DREGION field of the MPU type register, and mask off
// the bits of interest to get the count of regions.
//
return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
>> NVIC_MPU_TYPE_DREGION_S);
}
//*****************************************************************************
//
//! Enables a specific region.
//!
//! \param ulRegion is the region number to enable.
//!
//! This function is used to enable a memory protection region. The region
//! should already be set up with the MPURegionSet() function. Once enabled,
//! the memory protection rules of the region are applied and access violations
//! will cause a memory management fault.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionEnable(unsigned long ulRegion)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
//
// Select the region to modify.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Modify the enable bit in the region attributes.
//
HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
}
//*****************************************************************************
//
//! Disables a specific region.
//!
//! \param ulRegion is the region number to disable.
//!
//! This function is used to disable a previously enabled memory protection
//! region. The region will remain configured if it is not overwritten with
//! another call to MPURegionSet(), and can be enabled again by calling
//! MPURegionEnable().
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionDisable(unsigned long ulRegion)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
//
// Select the region to modify.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Modify the enable bit in the region attributes.
//
HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
}
//*****************************************************************************
//
//! Sets up the access rules for a specific region.
//!
//! \param ulRegion is the region number to set up.
//! \param ulAddr is the base address of the region. It must be aligned
//! according to the size of the region specified in ulFlags.
//! \param ulFlags is a set of flags to define the attributes of the region.
//!
//! This function sets up the protection rules for a region. The region has
//! a base address and a set of attributes including the size, which must
//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
//! according to the size.
//!
//! The \e ulFlags parameter is the logical OR of all of the attributes
//! of the region. It is a combination of choices for region size,
//! execute permission, read/write permissions, disabled sub-regions,
//! and a flag to determine if the region is enabled.
//!
//! The size flag determines the size of a region, and must be one of the
//! following:
//!
//! - \b MPU_RGN_SIZE_32B
//! - \b MPU_RGN_SIZE_64B
//! - \b MPU_RGN_SIZE_128B
//! - \b MPU_RGN_SIZE_256B
//! - \b MPU_RGN_SIZE_512B
//! - \b MPU_RGN_SIZE_1K
//! - \b MPU_RGN_SIZE_2K
//! - \b MPU_RGN_SIZE_4K
//! - \b MPU_RGN_SIZE_8K
//! - \b MPU_RGN_SIZE_16K
//! - \b MPU_RGN_SIZE_32K
//! - \b MPU_RGN_SIZE_64K
//! - \b MPU_RGN_SIZE_128K
//! - \b MPU_RGN_SIZE_256K
//! - \b MPU_RGN_SIZE_512K
//! - \b MPU_RGN_SIZE_1M
//! - \b MPU_RGN_SIZE_2M
//! - \b MPU_RGN_SIZE_4M
//! - \b MPU_RGN_SIZE_8M
//! - \b MPU_RGN_SIZE_16M
//! - \b MPU_RGN_SIZE_32M
//! - \b MPU_RGN_SIZE_64M
//! - \b MPU_RGN_SIZE_128M
//! - \b MPU_RGN_SIZE_256M
//! - \b MPU_RGN_SIZE_512M
//! - \b MPU_RGN_SIZE_1G
//! - \b MPU_RGN_SIZE_2G
//! - \b MPU_RGN_SIZE_4G
//!
//! The execute permission flag must be one of the following:
//!
//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
//!
//! The read/write access permissions are applied separately for the
//! privileged and user modes. The read/write access flags must be one
//! of the following:
//!
//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
//!
//! The region is automatically divided into 8 equally-sized sub-regions by
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
//! or larger. Any of these 8 sub-regions can be disabled. This allows
//! for creation of ``holes'' in a region which can be left open, or overlaid
//! by another region with different attributes. Any of the 8 sub-regions
//! can be disabled with a logical OR of any of the following flags:
//!
//! - \b MPU_SUB_RGN_DISABLE_0
//! - \b MPU_SUB_RGN_DISABLE_1
//! - \b MPU_SUB_RGN_DISABLE_2
//! - \b MPU_SUB_RGN_DISABLE_3
//! - \b MPU_SUB_RGN_DISABLE_4
//! - \b MPU_SUB_RGN_DISABLE_5
//! - \b MPU_SUB_RGN_DISABLE_6
//! - \b MPU_SUB_RGN_DISABLE_7
//!
//! Finally, the region can be initially enabled or disabled with one of
//! the following flags:
//!
//! - \b MPU_RGN_ENABLE
//! - \b MPU_RGN_DISABLE
//!
//! As an example, to set a region with the following attributes: size of
//! 32 KB, execution enabled, read-only for both privileged and user, one
//! sub-region disabled, and initially enabled; the \e ulFlags parameter would
//! have the following value:
//!
//! <code>
//! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
//! </code>
//!
//! \note This function will write to multiple registers and is not protected
//! from interrupts. It is possible that an interrupt which accesses a
//! region may occur while that region is in the process of being changed.
//! The safest way to handle this is to disable a region before changing it.
//! Refer to the discussion of this in the API Detailed Description section.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
unsigned long ulFlags)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))
== ulAddr);
//
// Program the base address, use the region field to select the
// region at the same time.
//
HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID;
//
// Program the region attributes. Set the TEX field and the S, C,
// and B bits to fixed values that are suitable for all Stellaris
// memory.
//
HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M |
NVIC_MPU_ATTR_CACHEABLE)) |
NVIC_MPU_ATTR_SHAREABLE |
NVIC_MPU_ATTR_BUFFRABLE;
}
//*****************************************************************************
//
//! Gets the current settings for a specific region.
//!
//! \param ulRegion is the region number to get.
//! \param pulAddr points to storage for the base address of the region.
//! \param pulFlags points to the attribute flags for the region.
//!
//! This function retrieves the configuration of a specific region. The
//! meanings and format of the parameters is the same as that of the
//! MPURegionSet() function.
//!
//! This function can be used to save the configuration of a region for later
//! use with the MPURegionSet() function. The region's enable state is
//! preserved in the attributes that are saved.
//!
//! \return None.
//
//*****************************************************************************
void
MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
unsigned long *pulFlags)
{
//
// Check the arguments.
//
ASSERT(ulRegion < 8);
ASSERT(pulAddr);
ASSERT(pulFlags);
//
// Select the region to get.
//
HWREG(NVIC_MPU_NUMBER) = ulRegion;
//
// Read and store the base address for the region.
//
*pulAddr = HWREG(NVIC_MPU_BASE);
//
// Read and store the region attributes.
//
*pulFlags = HWREG(NVIC_MPU_ATTR);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the memory management fault.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! memory management fault occurs.
//!
//! This sets and enables the handler to be called when the MPU generates
//! a memory management fault due to a protection region access violation.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUIntRegister(void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(pfnHandler);
//
// Register the interrupt handler.
//
IntRegister(FAULT_MPU, pfnHandler);
//
// Enable the memory management fault.
//
IntEnable(FAULT_MPU);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the memory management fault.
//!
//! This function will disable and clear the handler to be called when a
//! memory management fault occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
MPUIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(FAULT_MPU);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_MPU);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __MPU_H__
#define __MPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Flags that can be passed to MPUEnable.
//
//*****************************************************************************
#define MPU_CONFIG_PRIV_DEFAULT 4
#define MPU_CONFIG_HARDFLT_NMI 2
#define MPU_CONFIG_NONE 0
//*****************************************************************************
//
// Flags for the region size to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_SIZE_32B (4 << 1)
#define MPU_RGN_SIZE_64B (5 << 1)
#define MPU_RGN_SIZE_128B (6 << 1)
#define MPU_RGN_SIZE_256B (7 << 1)
#define MPU_RGN_SIZE_512B (8 << 1)
#define MPU_RGN_SIZE_1K (9 << 1)
#define MPU_RGN_SIZE_2K (10 << 1)
#define MPU_RGN_SIZE_4K (11 << 1)
#define MPU_RGN_SIZE_8K (12 << 1)
#define MPU_RGN_SIZE_16K (13 << 1)
#define MPU_RGN_SIZE_32K (14 << 1)
#define MPU_RGN_SIZE_64K (15 << 1)
#define MPU_RGN_SIZE_128K (16 << 1)
#define MPU_RGN_SIZE_256K (17 << 1)
#define MPU_RGN_SIZE_512K (18 << 1)
#define MPU_RGN_SIZE_1M (19 << 1)
#define MPU_RGN_SIZE_2M (20 << 1)
#define MPU_RGN_SIZE_4M (21 << 1)
#define MPU_RGN_SIZE_8M (22 << 1)
#define MPU_RGN_SIZE_16M (23 << 1)
#define MPU_RGN_SIZE_32M (24 << 1)
#define MPU_RGN_SIZE_64M (25 << 1)
#define MPU_RGN_SIZE_128M (26 << 1)
#define MPU_RGN_SIZE_256M (27 << 1)
#define MPU_RGN_SIZE_512M (28 << 1)
#define MPU_RGN_SIZE_1G (29 << 1)
#define MPU_RGN_SIZE_2G (30 << 1)
#define MPU_RGN_SIZE_4G (31 << 1)
//*****************************************************************************
//
// Flags for the permissions to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_PERM_EXEC 0x00000000
#define MPU_RGN_PERM_NOEXEC 0x10000000
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
//*****************************************************************************
//
// Flags for the sub-region to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_SUB_RGN_DISABLE_0 0x00000100
#define MPU_SUB_RGN_DISABLE_1 0x00000200
#define MPU_SUB_RGN_DISABLE_2 0x00000400
#define MPU_SUB_RGN_DISABLE_3 0x00000800
#define MPU_SUB_RGN_DISABLE_4 0x00001000
#define MPU_SUB_RGN_DISABLE_5 0x00002000
#define MPU_SUB_RGN_DISABLE_6 0x00004000
#define MPU_SUB_RGN_DISABLE_7 0x00008000
//*****************************************************************************
//
// Flags to enable or disable a region, to be passed to MPURegionSet.
//
//*****************************************************************************
#define MPU_RGN_ENABLE 1
#define MPU_RGN_DISABLE 0
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void MPUEnable(unsigned long ulMPUConfig);
extern void MPUDisable(void);
extern unsigned long MPURegionCountGet(void);
extern void MPURegionEnable(unsigned long ulRegion);
extern void MPURegionDisable(unsigned long ulRegion);
extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
unsigned long ulFlags);
extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
unsigned long *pulFlags);
extern void MPUIntRegister(void (*pfnHandler)(void));
extern void MPUIntUnregister(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __MPU_H__

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//*****************************************************************************
//
// peci.c - Driver for the Platform Environment Control Interface (PECI)
// module.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup peci_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_peci.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/peci.h"
//*****************************************************************************
//
// The following defines provide characteristics of the PECI module that are
// important to the driver but which can not be gleaned from the register
// definitions.
//
//*****************************************************************************
#define PECI_MAX_BAUD 2000000 // Maximum baud rate
#define PECI_MIN_BAUD 2000 // Minimum baud rate
#define PECI_MIN_RATIO 8 // Minimum baud rate divider
#define PECI_MAX_RATIO 65535 // Maximum baud rate divider
#define PECI_POLL_PRESCALE 4096 // Polling timer prescaler
#define PECI_MIN_POLL 2 // Minimum polling interval (ms)
#define PECI_MAX_POLL 1000 // Maximum polling interval (ms)
//*****************************************************************************
//
//! \internal
//! Checks a PECI domain.
//!
//! \param ulDomain is the PECI domain identifier.
//!
//! This function determines if a domain identifier is valid.
//!
//! \return Returns \b true if the domain identifier is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
PECIDomainValid(unsigned long ulDomain)
{
return((ulDomain == PECI_DOMAIN_M0D0) ||
(ulDomain == PECI_DOMAIN_M0D1) ||
(ulDomain == PECI_DOMAIN_M1D0) ||
(ulDomain == PECI_DOMAIN_M1D1));
}
#endif
//*****************************************************************************
//
//! Sets the configuration of the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulPECIClk is the rate of the clock supplied to the PECI module.
//! \param ulBaud is the bit rate that should be used for the PECI transfers.
//! \param ulPoll is the polling rate, in ms, that should be used for the
//! time between PECI polls.
//! \param ulOffset is the offset to be applied to all temperature values to
//! convert from relative to absolute.
//! \param ulRetry is the number of retry attempts for a PECI transaction.
//!
//! This function initializes operation of the PECI block. It programs the bit
//! rate, polling rate and retry counts for PECI transactions. It also
//! programs the offset value to be used to translate relative temperature
//! values from PECI transactions to absolute values. At the end of this
//! function, no host/domain combinations are enabled. Each desired
//! host/domain combination can be configured/enabled with a call to
//! PECIDomainEnable().
//!
//! The peripheral clock is the same as the processor clock. This is the value
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! The \e ulBaud parameter defines the bit rate for the PECI transactions.
//! This value is used to calculate a divisor value based on the specified
//! \e ulPECIClk. If the exact baud rate cannot be achieved (due to rounding),
//! the baud rate is programmed to the nearest value that is less than the
//! specified value.
//!
//! The \e ulPoll parameter defines the polling rate, in milliseconds, used
//! for PECI transactions. For generation of the polling rate, the \e
//! ulPECIClk is pre-divided by \b 4096. A value of 0 disables the polling
//! feature. If the exact polling rate cannot be achieved (due to rounding),
//! the polling rate is programmed to the nearest value that is greater than
//! the specified value.
//!
//! The \e ulRetry parameter defines the number of PECI transactions that are
//! attempted before indicating an error condition.
//!
//! \return None.
//
//*****************************************************************************
void
PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long ulBaud, unsigned long ulPoll,
unsigned long ulOffset, unsigned long ulRetry)
{
unsigned long ulTemp, ulDiv;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(ulPECIClk != 0);
ASSERT((ulBaud != 0) && (ulBaud <= PECI_MAX_BAUD) &&
(ulBaud >= PECI_MIN_BAUD) &&
((ulBaud * 4 * PECI_MIN_RATIO) < ulPECIClk));
ASSERT((ulPoll == 0) ||
((ulPoll >= PECI_MIN_POLL) && (ulPoll <= PECI_MAX_POLL)));
//
// Generate value for the PECI Control Register.
//
ulTemp = ((ulOffset << PECI_CTL_OFFSET_S) & PECI_CTL_OFFSET_M);
ulTemp |= ((ulRetry << PECI_CTL_CRETRY_S) & PECI_CTL_CRETRY_M);
HWREG(ulBase + PECI_O_CTL) = ulTemp;
//
// Compute the divisor for the PECI baud rate clock.
// Round up, to ensure programmed baud rate is <= specified rate.
// Ensure that proper ratio is maintained for clock:baud.
//
ulDiv = (ulPECIClk + (4 * ulBaud) - 1) / (4 * ulBaud);
ulDiv = (ulDiv < PECI_MIN_RATIO) ? PECI_MIN_RATIO : ulDiv;
ulDiv = (ulDiv > PECI_MAX_RATIO) ? PECI_MAX_RATIO : ulDiv;
ulTemp = ((ulDiv << PECI_DIV_BAUD_S) & PECI_DIV_BAUD_M);
//
// Compute the divisor for the PECI polling rate.
// Round up, to ensure programmed polling rate is >= specified rate.
//
ulDiv = ((ulPoll == 0) ? 0 : ((((ulPECIClk * ulPoll) / 1000) +
(PECI_POLL_PRESCALE - 1)) /
PECI_POLL_PRESCALE));
ulTemp |= ((ulDiv << PECI_DIV_POLL_S) & PECI_DIV_POLL_M);;
HWREG(ulBase + PECI_O_DIV) = ulTemp;
}
//*****************************************************************************
//
//! Gets the current configuration of the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulPECIClk is the rate of the clock supplied to the PECI module.
//! \param pulBaud is a pointer to storage for the bit rate.
//! \param pulPoll is a pointer to storage for the polling rate.
//! \param pulOffset is a pointer to stoarage for the offset.
//! \param pulRetry is a pointer to storage for the retry count.
//!
//! The baud rate and poll rate for the PECI module are determined, given an
//! explicitly provided peripheral clock. The returned rates are the actual
//! rates being used; they may not be the same as the requested rates, due to
//! rounding in the calculations.
//!
//! The peripheral clock is the same as the processor clock. This is the value
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! \return None.
//
//*****************************************************************************
void
PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long *pulBaud, unsigned long *pulPoll,
unsigned long *pulOffset, unsigned long *pulRetry)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(ulPECIClk != 0);
ASSERT(*pulBaud != 0);
ASSERT(*pulPoll != 0);
ASSERT(*pulOffset != 0);
ASSERT(*pulRetry != 0);
//
// Retrieve the Offset and Retry values
//
ulTemp = HWREG(ulBase + PECI_O_CTL);
*pulOffset = ((ulTemp & PECI_CTL_OFFSET_M) >> PECI_CTL_OFFSET_S);
*pulRetry = ((ulTemp & PECI_CTL_CRETRY_M) >> PECI_CTL_CRETRY_S);
//
// Calculate the baud rate.
//
ulTemp = HWREG(ulBase + PECI_O_DIV);
*pulBaud = ulPECIClk / ((ulTemp & PECI_DIV_BAUD_M) >> PECI_DIV_BAUD_S);
//
// Compute the divisor for the PECI polling rate.
// Round up, to ensure programmed polling rate is >= specified rate.
//
*pulPoll = ((((ulTemp & PECI_DIV_POLL_M) >> PECI_DIV_POLL_S) * 1000) /
(ulPECIClk / PECI_POLL_PRESCALE));
}
//*****************************************************************************
//
//! Enables bypassing of negotiation errors.
//!
//! \param ulBase is the base address of the PECI module.
//!
//! This function enables bypassing of negotiation errors that might occur
//! during a PECI transaction. When enabled, negotiation errors are ignored.
//!
//! \return None.
//
//*****************************************************************************
void
PECIBypassEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Enable bypass.
//
HWREG(ulBase + PECI_O_CTL) |= PECI_CTL_BYERR;
}
//*****************************************************************************
//
//! Disables bypassing of negotiation errors.
//!
//! \param ulBase is the base address of the PECI module.
//!
//! This function disables bypassing of negotiation errors that might occur
//! during a PECI transaction. When disabled, negotiation errors are reported
//! and the remainder of the transaction is aborted.
//!
//! \return None.
//
//*****************************************************************************
void
PECIBypassDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable bypass.
//
HWREG(ulBase + PECI_O_CTL) &= ~PECI_CTL_BYERR;
}
//*****************************************************************************
//
//! Sets the configuration of the specified PECI domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be configured.
//! \param ulHigh is the high temperature threshold value.
//! \param ulLow is the low temperature threshold value.
//!
//! This function configures the specified PECI domain for temperature
//! monitoring operations. The values for \e ulHigh and \e ulLow can be
//! specified as a value relative to the maximum temperature allowed, or it
//! can be specified as an absolute temperature (if an offset was programmed
//! in the PECIConfigSet() function.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain,
unsigned long ulHigh, unsigned long ulLow)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
ASSERT(ulHigh <= 0xFFFF);
ASSERT(ulLow <= 0xFFFF);
ASSERT(ulHigh > ulLow);
//
// Set the HTHRESH and LTHRESH fields in the domain control/status
// register.
//
HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4)) =
(((ulHigh << PECI_M0D0C_HITHR_S) & PECI_M0D0C_HITHR_M) |
((ulLow << PECI_M0D0C_LOTHR_S) & PECI_M0D0C_LOTHR_M));
}
//*****************************************************************************
//
//! Gets the configuration of the specified PECI domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be configured.
//! \param pulHigh is a pointer to storage for the high threshold.
//! \param pulLow is a pointer to storage for the low threshold.
//!
//! This function configures the specified PECI domain for temperature
//! monitoring operations. The values for \e ulHigh and \e ulLow can be
//! specified as a value relative to the maximum temperature allowed, or it
//! can be specified as an absolute temperature (if an offset was programmed
//! in the PECIConfigSet() function.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain,
unsigned long *pulHigh, unsigned long *pulLow)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
ASSERT(pulHigh != 0);
ASSERT(pulLow != 0);
//
// Get the HTHRESH and LTHRESH fields in the domain control/status
// register.
//
ulTemp = HWREG(ulBase + PECI_O_M0D0C + (ulDomain * 4));
*pulHigh = ((ulTemp && PECI_M0D0C_HITHR_M) >> PECI_M0D0C_HITHR_S);
*pulLow = ((ulTemp && PECI_M0D0C_LOTHR_M) >> PECI_M0D0C_LOTHR_S);
}
//*****************************************************************************
//
//! Enables a domain within the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be enabled.
//!
//! This function enables the specified PECI domain for temperature monitoring
//! operations.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Enable the specified domain.
//
HWREG(ulBase + PECI_O_CTL) |= (1 << ulDomain);
}
//*****************************************************************************
//
//! Disables a domain within the PECI module.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function disables the specified PECI domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Disable the specified domain.
//
HWREG(ulBase + PECI_O_CTL) &= ~(1 << ulDomain);
}
//*****************************************************************************
//
//! Reads the current temperature value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function returns the most recently read temperature value from the
//! specified domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIDomainValueGet(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Return the most recently polled temperature value
//
return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) &
PECI_M0D0_VALUE_M)));
}
//*****************************************************************************
//
//! Reads the maximum/error value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function returns the maximum temperature value for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIDomainMaxReadGet(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Return the most recently polled temperature value
//
return(((HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4)) &
PECI_M0D0_MAXREAD_M) >> PECI_M0D0_MAXREAD_S));
}
//*****************************************************************************
//
//! Clears the current temperature value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function clears the current and maximum values for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Clear the temperature value.
//
HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_VALUE_M;
}
//*****************************************************************************
//
//! Clears the maximum/error value for the specified domain.
//!
//! \param ulBase is the base address of the PECI module.
//! \param ulDomain is the PECI domain that should be disabled.
//!
//! This function clears the current and maximum values for the specified
//! domain.
//!
//! The \e ulDomain parameter can be one of the following values:
//! \b PECI_DOMAIN_M0D0, \b PECI_DOMAIN_M0D1, \b PECI_DOMAIN_M1D0, or
//! \b PECI_DOMAIN_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIDomainMaxReadClear(unsigned long ulBase, unsigned long ulDomain)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(PECIDomainValid(ulDomain));
//
// Clear the maximum/error value.
//
HWREG(ulBase + PECI_O_M0D0 + (ulDomain * 4) ) &= ~PECI_M0D0_MAXREAD_M;
}
//*****************************************************************************
//
//! Registers an interrupt handler for the PECI module.
//!
//! \param ulBase specifies the PECI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! PECI interrupt occurs.
//!
//! This sets the handler to be called when an PECI interrupt occurs. This
//! will enable the global interrupt in the interrupt controller; specific
//! PECI interrupts must be enabled via PECIIntEnable(). If necessary, it is
//! the interrupt handler's responsibility to clear the interrupt source via
//! PECIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
ASSERT(pfnHandler != 0);
//
// Register the interrupt handler.
//
IntRegister(INT_PECI0, pfnHandler);
//
// Enable the PECI interrupt.
//
IntEnable(INT_PECI0);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the PECI module.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function will clear the handler to be called when a PECI interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable the PECI interrupt.
//
IntDisable(INT_PECI0);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_PECI0);
}
//*****************************************************************************
//
//! Enables individual PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! \param ulIntMode is the mode for the PECI domain interrupts.
//!
//! Enables the indicated PECI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e ulIntFlags parameter can be any of the following values:
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//!
//! The \e ulIntMode parameter is used to configure the interrupt mode for
//! the corresponding \b PECI_DOMAIN_MnDm field, and can be any of the
//! following values: \b PECI_M0D0_MODE1, \b PECI_M0D0_MODE2,
//! \b PECI_M0D0_MODE3, \b PECI_M0D1_MODE1, \b PECI_M0D1_MODE2,
//! \b PECI_M0D1_MODE3. \b PECI_M1D0_MODE1, \b PECI_M1D0_MODE2,
//! \b PECI_M1D0_MODE3, \b PECI_M1D1_MODE1, \b PECI_M1D1_MODE2, or
//! \b PECI_M1D1_MODE3.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags,
unsigned long ulIntMode)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Get the current mask value.
//
ulTemp = HWREG(ulBase + PECI_O_IM);
//
// Clear the bit/bit-fields that are configured, based on the value
// in the flags parameter.
//
ulTemp &= ~ulIntFlags;
//
// Set/Enable the bit/bit-fields based on the value in the flags and mode
// parameter. The flags parameter will alter the bits in the lower half
// of the mask, while the mode will alter the bit fields in the upper
// half of the mask.
//
ulTemp |= (0x0000FFFF & ulIntFlags);
ulTemp |= (0xFFFF0000 & ulIntMode);
HWREG(ulBase + PECI_O_IM) = ulTemp;
}
//*****************************************************************************
//
//! Disables individual PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated PECI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e ulIntFlags parameter can be any of the following values:
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Disable the specified interrupts.
//
HWREG(ulBase + PECI_O_IM) &= ~ulIntFlags;
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the PECI module base address.
//! \param bMasked is \b false if the raw interrupt status is required or
//! \b true if the masked interrupt status is required.
//!
//! This function returns the interrupt status for the PECI module. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! The interpretation of the PECI_DOMAIN_MnDm fields vary based on the mode
//! value programed using the PECIIntEnable() function for the field. Each
//! field may take on one of the following values:
//! \b PECI_MnDm_MODE1_HIGH, \b PECI_MnDm_MODE2_MID, \b PECI_MnDm_MODE2_HIGH,
//! \b PECI_MnDm_MODE3_LOW, \b PECI_MnDm_MODE3_MID, or \b PECI_MnDm_MODE3_HIGH.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b PECI_READ, \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1,
//! \b PECI_M1D0, or \b PECI_M1D1.
//
//*****************************************************************************
unsigned long
PECIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + PECI_O_MIS));
}
else
{
return(HWREG(ulBase + PECI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears PECI interrupt sources.
//!
//! \param ulBase specifies the PECI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified PECI interrupt sources are cleared so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupts from being recognized again immediately upon exit. The
//! \e ulIntFlags parameter can consist of any combination of the \b PECI_READ,
//! \b PECI_ERR, \b PECI_AC, \b PECI_M0D0, \b PECI_M0D1, \b PECI_M1D0, or
//! \b PECI_M1D1 values.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + PECI_O_IC) = ulIntFlags;
}
//*****************************************************************************
//
//! Sends a PECI Advanced Command.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function sends a PECI Advanced Command. If the interface is not IDLE,
//! it waits for the interface to become IDLE then sends the command. The
//! function parameters are used to populate the message control fields before
//! activating the command.
//!
//! \return None.
//
//*****************************************************************************
void
PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Wait for the interface to be idle.
//
while(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF)
{
}
//
// Fill in the registers for the advanced command.
//
HWREG(ulBase + PECI_O_ACARG) = ulArg;
HWREG(ulBase + PECI_O_ACRDWR0) = ulData0;
HWREG(ulBase + PECI_O_ACRDWR1) = ulData1;
HWREG(ulBase + PECI_O_ACADDR) = (ucHidRe << 24) |
(ucSize << 16) |
(ucDomain << 8) |
(ucProcAdd << 0);
//
// Now, issue the command.
//
HWREG(ulBase + PECI_O_ACCMD) = ucCmd;
}
//*****************************************************************************
//
//! Sends a PECI Advanced Command (non blocking).
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function sends a PECI Advanced Command. If the interface is not IDLE,
//! it returns immediately. Otherwise, it sends the the command. The function
//! paramters are used to populate the message control fields before activating
//! the command.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
PECIAdvCmdSendNonBlocking(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1)
{
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// Check for the interface to be idle.
// If not, return immediately.
//
if(HWREG(ulBase + PECI_O_ACCODE) == 0xFFFFFFFF)
{
return(0);
}
//
// Send the command.
//
PECIAdvCmdSend(ulBase, ucCmd, ucHidRe, ucDomain, ucProcAdd, ulArg,
ucSize, ulData0, ulData1);
//
// Return, indicating that the command has been issued.
//
return(1);
}
//*****************************************************************************
//
//! Obtains status of previous PECI Advanced Command.
//!
//! \param ulBase specifies the PECI module base address.
//!
//! This function gets the status of a previously issued PECI Advanced Command.
//! If the command has completed, and the data pointers are non-zero, the data
//! registers are read and saved.
//!
//! \return -1 if command has not yet been completed, otherwise, the return
//! code associated with the Advanced Command.
//
//*****************************************************************************
unsigned long
PECIAdvCmdStatusGet(unsigned long ulBase, unsigned long *pulData0,
unsigned long *pulData1)
{
unsigned long ulCode;
//
// Check the arguments.
//
ASSERT(ulBase == PECI0_BASE);
//
// If the command has completed, optionally read and save the data
// registers.
//
ulCode = HWREG(ulBase + PECI_O_ACCODE);
if(ulCode != 0xFFFFFFFF)
{
if(pulData0 != (void *)0)
{
*pulData0 = HWREG(ulBase + PECI_O_ACRDWR0);
}
if(pulData1 != (void *)0)
{
*pulData1 = HWREG(ulBase + PECI_O_ACRDWR1);
}
}
//
// Return the command code from the most recently completed command.
//
return(ulCode);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// peci.h - Prototypes for Platform Environment Control Interface (PECI)
// driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PECI_H__
#define __PECI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to PECIConfigDomain, PECIEnableDomain,
// PECIDisableDomain, PECIReadDomainValue, PECIReadDomainMax, and
// PECIClearDomain as the ulDomain parameter.
//
//*****************************************************************************
#define PECI_DOMAIN_M0D0 0 // Microprocessor 0 / Domain 0
#define PECI_DOMAIN_M0D1 1 // Microprocessor 0 / Domain 1
#define PECI_DOMAIN_M1D0 2 // Microprocessor 1 / Domain 0
#define PECI_DOMAIN_M1D1 3 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable, PECIIntDisable, and PECIIntClear
// as the ulIntFlags parameter and returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_READ 0x00000001 // End of PECI Poll
#define PECI_ERR 0x00000002 // Error on PECI Poll
#define PECI_AC 0x00000004 // Advanced Command Complete
#define PECI_M0D0 0x00030000 // Microprocessor 0 / Domain 0
#define PECI_M0D1 0x000C0000 // Microprocessor 0 / Domain 1
#define PECI_M1D0 0x00300000 // Microprocessor 1 / Domain 0
#define PECI_M1D1 0x00C00000 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Additional values that can be returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_M0D0_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D0_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D0_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D0_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D0_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D0_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D1_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D1_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D1_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D1_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D0_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D0_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D0_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D0_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D1_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D1_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D1_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D1_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable as the ulIntMode parameter.
//
//*****************************************************************************
#define PECI_M0D0_MODE1 0x00010000 // Domain Interrupt Mode 1
#define PECI_M0D0_MODE2 0x00020000 // Domain Interrupt Mode 2
#define PECI_M0D0_MODE3 0x00030000 // Domain Interrupt Mode 3
#define PECI_M0D1_MODE1 0x00040000 // Domain Interrupt Mode 1
#define PECI_M0D1_MODE2 0x00080000 // Domain Interrupt Mode 2
#define PECI_M0D1_MODE3 0x000C0000 // Domain Interrupt Mode 3
#define PECI_M1D0_MODE1 0x00100000 // Domain Interrupt Mode 1
#define PECI_M1D0_MODE2 0x00200000 // Domain Interrupt Mode 2
#define PECI_M1D0_MODE3 0x00300000 // Domain Interrupt Mode 3
#define PECI_M1D1_MODE1 0x00400000 // Domain Interrupt Mode 1
#define PECI_M1D1_MODE2 0x00800000 // Domain Interrupt Mode 2
#define PECI_M1D1_MODE3 0x00C00000 // Domain Interrupt Mode 3
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long ulBaud, unsigned long ulPoll,
unsigned long ulOffset, unsigned long ulRetry);
extern void PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long *pulBaud, unsigned long *pulPoll,
unsigned long *pulOffset, unsigned long *pulRetry);
extern void PECIBypassEnable(unsigned long ulBase);
extern void PECIBypassDisable(unsigned long ulBase);
extern void PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain,
unsigned long ulHigh, unsigned long ulLow);
extern void PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain,
unsigned long *pulHigh, unsigned long *pulLow);
extern void PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain);
extern unsigned long PECIDomainValueGet(unsigned long ulBase,
unsigned long ulDomain);
extern unsigned long PECIDomainMaxReadGet(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainMaxReadClear(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void PECIIntUnregister(unsigned long ulBase);
extern void PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags,
unsigned long ulIntMode);
extern void PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long PECIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdSendNonBlocking(unsigned long ulBase,
unsigned char ucCmd,
unsigned char ucHidRe,
unsigned char ucDomain,
unsigned char ucProcAdd,
unsigned long ulArg,
unsigned char ucSize,
unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdStatusGet(unsigned long ulBase,
unsigned long *pulData0,
unsigned long *pulData1);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PECI_H__

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//*****************************************************************************
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PWM_H__
#define __PWM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are passed to PWMGenConfigure() as the ulConfig
// parameter and specify the configuration of the PWM generator.
//
//*****************************************************************************
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
#define PWM_GEN_MODE_FAULT_LATCHED \
0x00040000 // Fault is latched
#define PWM_GEN_MODE_FAULT_UNLATCHED \
0x00000000 // Fault is not latched
#define PWM_GEN_MODE_FAULT_MINPER \
0x00020000 // Enable min fault period
#define PWM_GEN_MODE_FAULT_NO_MINPER \
0x00000000 // Disable min fault period
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
#define PWM_GEN_MODE_FAULT_LEGACY \
0x00000000 // Disable extended fault support
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
// immediately
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
0x0000A800 // Deadband updates locally
// synchronized
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
0x0000FC00 // Deadband updates globally
// synchronized
#define PWM_GEN_MODE_GEN_NO_SYNC \
0x00000000 // Generator mode updates occur
// immediately
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
0x00000280 // Generator mode updates locally
// synchronized
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
0x000003C0 // Generator mode updates globally
// synchronized
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM generator interrupts and
// triggers.
//
//*****************************************************************************
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
//*****************************************************************************
//
// Defines for enabling, disabling, and clearing PWM interrupts.
//
//*****************************************************************************
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
#ifndef DEPRECATED
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
#endif
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
//*****************************************************************************
//
// Defines to identify the generators within a module.
//
//*****************************************************************************
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
//*****************************************************************************
//
// Defines to identify the outputs within a module.
//
//*****************************************************************************
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_0.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_0 0
#define PWM_FAULT_FAULT0 0x00000001
#define PWM_FAULT_FAULT1 0x00000002
#define PWM_FAULT_FAULT2 0x00000004
#define PWM_FAULT_FAULT3 0x00000008
#define PWM_FAULT_ACMP0 0x00010000
#define PWM_FAULT_ACMP1 0x00020000
#define PWM_FAULT_ACMP2 0x00040000
//*****************************************************************************
//
// Defines to identify each of the possible fault trigger conditions in
// PWM_FAULT_GROUP_1.
//
//*****************************************************************************
#define PWM_FAULT_GROUP_1 1
#define PWM_FAULT_DCMP0 0x00000001
#define PWM_FAULT_DCMP1 0x00000002
#define PWM_FAULT_DCMP2 0x00000004
#define PWM_FAULT_DCMP3 0x00000008
#define PWM_FAULT_DCMP4 0x00000010
#define PWM_FAULT_DCMP5 0x00000020
#define PWM_FAULT_DCMP6 0x00000040
#define PWM_FAULT_DCMP7 0x00000080
//*****************************************************************************
//
// Defines to identify the sense of each of the external FAULTn signals
//
//*****************************************************************************
#define PWM_FAULT0_SENSE_HIGH 0x00000000
#define PWM_FAULT0_SENSE_LOW 0x00000001
#define PWM_FAULT1_SENSE_HIGH 0x00000000
#define PWM_FAULT1_SENSE_LOW 0x00000002
#define PWM_FAULT2_SENSE_HIGH 0x00000000
#define PWM_FAULT2_SENSE_LOW 0x00000004
#define PWM_FAULT3_SENSE_HIGH 0x00000000
#define PWM_FAULT3_SENSE_LOW 0x00000008
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulConfig);
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulPeriod);
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
unsigned long ulGen);
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
unsigned long ulWidth);
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
unsigned long ulPWMOut);
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
unsigned short usRise, unsigned short usFall);
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bEnable);
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bInvert);
extern void PWMOutputFaultLevel(unsigned long ulBase,
unsigned long ulPWMOutBits,
tBoolean bDriveHigh);
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
tBoolean bFaultSuppress);
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
void (*pfnIntHandler)(void));
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
extern void PWMFaultIntRegister(unsigned long ulBase,
void (*pfnIntHandler)(void));
extern void PWMFaultIntUnregister(unsigned long ulBase);
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
unsigned long ulIntTrig);
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
tBoolean bMasked);
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulInts);
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
extern void PWMFaultIntClear(unsigned long ulBase);
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PWMFaultIntClearExt(unsigned long ulBase,
unsigned long ulFaultInts);
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
unsigned long ulMinFaultPeriod,
unsigned long ulFaultSenses);
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
unsigned long ulGen,
unsigned long ulGroup);
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
unsigned long ulGroup,
unsigned long ulFaultTriggers);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PWM_H__

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//*****************************************************************************
//
// qei.c - Driver for the Quadrature Encoder with Index.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup qei_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_qei.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/qei.h"
//*****************************************************************************
//
//! Enables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the quadrature encoder module. It must be
//! configured before it is enabled.
//!
//! \sa QEIConfigure()
//!
//! \return None.
//
//*****************************************************************************
void
QEIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;
}
//*****************************************************************************
//
//! Disables the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the quadrature encoder module.
//!
//! \return None.
//
//*****************************************************************************
void
QEIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the QEI module.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
}
//*****************************************************************************
//
//! Configures the quadrature encoder.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulConfig is the configuration for the quadrature encoder. See below
//! for a description of this parameter.
//! \param ulMaxPosition specifies the maximum position value.
//!
//! This will configure the operation of the quadrature encoder. The
//! \e ulConfig parameter provides the configuration of the encoder and is the
//! logical OR of several values:
//!
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
//! on channel A or on both channels A and B should be counted by the
//! position integrator and velocity accumulator.
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
//! position integrator should be reset when the index pulse is detected.
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
//! quadrature signals are being provided on ChA and ChB, or if a direction
//! signal and a clock are being provided instead.
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
//! provided on ChA and ChB should be swapped before being processed.
//!
//! \e ulMaxPosition is the maximum value of the position integrator, and is
//! the value used to reset the position capture when in index reset mode and
//! moving in the reverse (negative) direction.
//!
//! \return None.
//
//*****************************************************************************
void
QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Write the new configuration to the hardware.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
ulConfig);
//
// Set the maximum position.
//
HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;
}
//*****************************************************************************
//
//! Gets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current position of the encoder. Depending upon the
//! configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter will not be aligned with the index pulse yet).
//!
//! \return The current position of the encoder.
//
//*****************************************************************************
unsigned long
QEIPositionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the current position counter.
//
return(HWREG(ulBase + QEI_O_POS));
}
//*****************************************************************************
//
//! Sets the current encoder position.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPosition is the new position for the encoder.
//!
//! This sets the current position of the encoder; the encoder position will
//! then be measured relative to this value.
//!
//! \return None.
//
//*****************************************************************************
void
QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Set the position counter.
//
HWREG(ulBase + QEI_O_POS) = ulPosition;
}
//*****************************************************************************
//
//! Gets the current direction of rotation.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current direction of rotation. In this case, current
//! means the most recently detected direction of the encoder; it may not be
//! presently moving but this is the direction it last moved before it stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
//
//*****************************************************************************
long
QEIDirectionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the direction of rotation.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
}
//*****************************************************************************
//
//! Gets the encoder error indicator.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the error indicator for the quadrature encoder. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
//*****************************************************************************
tBoolean
QEIErrorGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the error indicator.
//
return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
}
//*****************************************************************************
//
//! Enables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the velocity capture in the quadrature
//! encoder module. It must be configured before it is enabled. Velocity
//! capture will not occur if the quadrature encoder is not enabled.
//!
//! \sa QEIVelocityConfigure() and QEIEnable()
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;
}
//*****************************************************************************
//
//! Disables the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the velocity capture in the quadrature
//! encoder module.
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the velocity capture.
//
HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
}
//*****************************************************************************
//
//! Configures the velocity capture.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPreDiv specifies the predivider applied to the input quadrature
//! signal before it is counted; can be one of \b QEI_VELDIV_1,
//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
//! \param ulPeriod specifies the number of clock ticks over which to measure
//! the velocity; must be non-zero.
//!
//! This will configure the operation of the velocity capture portion of the
//! quadrature encoder. The position increment signal is predivided as
//! specified by \e ulPreDiv before being accumulated by the velocity capture.
//! The divided signal is accumulated over \e ulPeriod system clock before
//! being saved and resetting the accumulator.
//!
//! \return None.
//
//*****************************************************************************
void
QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));
ASSERT(ulPeriod != 0);
//
// Set the velocity predivider.
//
HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
~(QEI_CTL_VELDIV_M)) | ulPreDiv);
//
// Set the timer period.
//
HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the current encoder speed.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current speed of the encoder. The value returned is the
//! number of pulses detected in the specified time period; this number can be
//! multiplied by the number of time periods per second and divided by the
//! number of pulses per revolution to obtain the number of revolutions per
//! second.
//!
//! \return Returns the number of pulses captured in the given time period.
//
//*****************************************************************************
unsigned long
QEIVelocityGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return the speed capture value.
//
return(HWREG(ulBase + QEI_O_SPEED));
}
//*****************************************************************************
//
//! Registers an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param pfnHandler is a pointer to the function to be called when the
//! quadrature encoder interrupt occurs.
//!
//! This sets the handler to be called when a quadrature encoder interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
//! It is the interrupt handler's responsibility to clear the interrupt source
//! via QEIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Determine the interrupt number based on the QEI module.
//
ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the quadrature encoder interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the quadrature encoder interrupt.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This function will clear the handler to be called when a quadrature encoder
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Determine the interrupt number based on the QEI module.
//
ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Enables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Enables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Enable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Disables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Disable the specified interrupts.
//
HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the quadrature encoder module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
//
//*****************************************************************************
unsigned long
QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + QEI_O_ISC));
}
else
{
return(HWREG(ulBase + QEI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears quadrature encoder interrupt sources.
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! The specified quadrature encoder interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to keep
//! it from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + QEI_O_ISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __QEI_H__
#define __QEI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to QEIConfigure as the ulConfig paramater.
//
//*****************************************************************************
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
//*****************************************************************************
//
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
//
//*****************************************************************************
#define QEI_VELDIV_1 0x00000000 // Predivide by 1
#define QEI_VELDIV_2 0x00000040 // Predivide by 2
#define QEI_VELDIV_4 0x00000080 // Predivide by 4
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
#define QEI_VELDIV_16 0x00000100 // Predivide by 16
#define QEI_VELDIV_32 0x00000140 // Predivide by 32
#define QEI_VELDIV_64 0x00000180 // Predivide by 64
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
//*****************************************************************************
//
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
//
//*****************************************************************************
#define QEI_INTERROR 0x00000008 // Phase error detected
#define QEI_INTDIR 0x00000004 // Direction change
#define QEI_INTTIMER 0x00000002 // Velocity timer expired
#define QEI_INTINDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void QEIEnable(unsigned long ulBase);
extern void QEIDisable(unsigned long ulBase);
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxPosition);
extern unsigned long QEIPositionGet(unsigned long ulBase);
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
extern long QEIDirectionGet(unsigned long ulBase);
extern tBoolean QEIErrorGet(unsigned long ulBase);
extern void QEIVelocityEnable(unsigned long ulBase);
extern void QEIVelocityDisable(unsigned long ulBase);
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
unsigned long ulPeriod);
extern unsigned long QEIVelocityGet(unsigned long ulBase);
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void QEIIntUnregister(unsigned long ulBase);
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __QEI_H__

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This project will build the Stellaris Peripheral Driver Library.
-------------------------------------------------------------------------------
Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
Software License Agreement
Texas Instruments (TI) is supplying this software for use solely and
exclusively on TI's microcontroller products. The software is owned by
TI and/or its suppliers, and is protected under applicable copyright
laws. You may not combine this software with "viral" open-source
software in order to form a larger program.
THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 8049 of the Stellaris Peripheral Driver Library.

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//*****************************************************************************
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ssi_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ssi.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/ssi.h"
//*****************************************************************************
//
// A mapping of timer base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulSSIIntMap[][2] =
{
{ SSI0_BASE, INT_SSI0 },
{ SSI1_BASE, INT_SSI1 },
{ SSI2_BASE, INT_SSI2 },
{ SSI3_BASE, INT_SSI3 },
};
//*****************************************************************************
//
//! \internal
//! Checks a SSI base address.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function determines if a SSI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
SSIBaseValid(unsigned long ulBase)
{
return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) ||
(ulBase == SSI2_BASE) || (ulBase == SSI3_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the SSI interrupt number.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! Given a SSI base address, returns the corresponding interrupt number.
//!
//! \return Returns a SSI interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SSIIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps SSI base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) /
sizeof(g_ppulSSIIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulSSIIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulSSIIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Configures the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
//! \param ulProtocol specifies the data transfer protocol.
//! \param ulMode specifies the mode of operation.
//! \param ulBitRate specifies the clock rate.
//! \param ulDataWidth specifies number of bits transferred per frame.
//!
//! This function configures the synchronous serial interface. It sets
//! the SSI protocol, mode of operation, bit rate, and data width.
//!
//! The \e ulProtocol parameter defines the data frame format. The
//! \e ulProtocol parameter can be one of the following values:
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
//! frame formats imply the following polarity and phase configurations:
//!
//! <pre>
//! Polarity Phase Mode
//! 0 0 SSI_FRF_MOTO_MODE_0
//! 0 1 SSI_FRF_MOTO_MODE_1
//! 1 0 SSI_FRF_MOTO_MODE_2
//! 1 1 SSI_FRF_MOTO_MODE_3
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if a slave, the SSI can be
//! configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SSI_MODE_MASTER,
//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSSI >= 2 * bit rate (master mode)
//! - FSSI >= 12 * bit rate (slave modes)
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The \e ulDataWidth parameter defines the width of the data transfers, and
//! can be a value between 4 and 16, inclusive.
//!
//! The peripheral clock is the same as the processor clock. This is the value
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original SSIConfig() API and performs the same
//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
//! this API.
//!
//! \return None.
//
//*****************************************************************************
void
SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate, unsigned long ulDataWidth)
{
unsigned long ulMaxBitRate;
unsigned long ulRegVal;
unsigned long ulPreDiv;
unsigned long ulSCR;
unsigned long ulSPH_SPO;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
(ulProtocol == SSI_FRF_MOTO_MODE_3) ||
(ulProtocol == SSI_FRF_TI) ||
(ulProtocol == SSI_FRF_NMW));
ASSERT((ulMode == SSI_MODE_MASTER) ||
(ulMode == SSI_MODE_SLAVE) ||
(ulMode == SSI_MODE_SLAVE_OD));
ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
//
// Set the mode.
//
ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
HWREG(ulBase + SSI_O_CR1) = ulRegVal;
//
// Set the clock predivider.
//
ulMaxBitRate = ulSSIClk / ulBitRate;
ulPreDiv = 0;
do
{
ulPreDiv += 2;
ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
}
while(ulSCR > 255);
HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
//
// Set protocol and clock rate.
//
ulSPH_SPO = (ulProtocol & 3) << 6;
ulProtocol &= SSI_CR0_FRF_M;
ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
HWREG(ulBase + SSI_O_CR0) = ulRegVal;
}
//*****************************************************************************
//
//! Enables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function enables operation of the synchronous serial interface. The
//! synchronous serial interface must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SSIEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
}
//*****************************************************************************
//
//! Disables the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function disables operation of the synchronous serial interface.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
//
HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an SSI interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
//! it is the interrupt handler's responsibility to clear the interrupt source
//! via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = SSIIntNumberGet(ulBase);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(ulInt, pfnHandler);
//
// Enable the synchronous serial interface interrupt.
//
IntEnable(ulInt);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the synchronous serial interface.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function will clear the handler to be called when a SSI
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntUnregister(unsigned long ulBase)
{
unsigned long ulInt;
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = SSIIntNumberGet(ulBase);
//
// Disable the interrupt.
//
IntDisable(ulInt);
//
// Unregister the interrupt handler.
//
IntUnregister(ulInt);
}
//*****************************************************************************
//
//! Enables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SSI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor. The \e ulIntFlags parameter can be any of the
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Enable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
//! values.
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Disable the specified interrupts.
//
HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase specifies the SSI module base address.
//! \param bMasked is \b false if the raw interrupt status is required or
//! \b true if the masked interrupt status is required.
//!
//! This function returns the interrupt status for the SSI module. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
//
//*****************************************************************************
unsigned long
SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + SSI_O_MIS));
}
else
{
return(HWREG(ulBase + SSI_O_RIS));
}
}
//*****************************************************************************
//
//! Clears SSI interrupt sources.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SSI interrupt sources are cleared so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupts from being recognized again immediately upon exit. The
//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
//! \b SSI_RXOR values.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested interrupt sources.
//
HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData is the data to be transmitted over the SSI interface.
//!
//! This function places the supplied data into the transmit FIFO of the
//! specified SSI module.
//!
//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
//! where N is the data width as configured by SSIConfigSetExpClk(). For
//! example, if the interface is configured for 8-bit data width, the upper 24
//! bits of \e ulData are discarded.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataPut(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Wait until there is space.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
{
}
//
// Write the data to the SSI.
//
HWREG(ulBase + SSI_O_DR) = ulData;
}
//*****************************************************************************
//
//! Puts a data element into the SSI transmit FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param ulData is the data to be transmitted over the SSI interface.
//!
//! This function places the supplied data into the transmit FIFO of the
//! specified SSI module. If there is no space in the FIFO, then this function
//! returns a zero.
//!
//! This function replaces the original SSIDataNonBlockingPut() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
//! where N is the data width as configured by SSIConfigSetExpClk(). For
//! example, if the interface is configured for 8-bit data width, the upper 24
//! bits of \e ulData are discarded.
//!
//! \return Returns the number of elements written to the SSI transmit FIFO.
//
//*****************************************************************************
long
SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
//
// Check for space to write.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
{
HWREG(ulBase + SSI_O_DR) = ulData;
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SSI interface.
//!
//! This function gets received data from the receive FIFO of the specified
//! SSI module and places that data into the location specified by the
//! \e pulData parameter.
//!
//! \note Only the lower N bits of the value written to \e pulData contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! contain valid data.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDataGet(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Wait until there is data to be read.
//
while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
{
}
//
// Read data from SSI.
//
*pulData = HWREG(ulBase + SSI_O_DR);
}
//*****************************************************************************
//
//! Gets a data element from the SSI receive FIFO.
//!
//! \param ulBase specifies the SSI module base address.
//! \param pulData is a pointer to a storage location for data that was
//! received over the SSI interface.
//!
//! This function gets received data from the receive FIFO of the specified SSI
//! module and places that data into the location specified by the \e ulData
//! parameter. If there is no data in the FIFO, then this function returns a
//! zero.
//!
//! This function replaces the original SSIDataNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>ssi.h</tt> to map
//! the original API to this API.
//!
//! \note Only the lower N bits of the value written to \e pulData contain
//! valid data, where N is the data width as configured by
//! SSIConfigSetExpClk(). For example, if the interface is configured for
//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
//! contain valid data.
//!
//! \return Returns the number of elements read from the SSI receive FIFO.
//
//*****************************************************************************
long
SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Check for data to read.
//
if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
{
*pulData = HWREG(ulBase + SSI_O_DR);
return(1);
}
else
{
return(0);
}
}
//*****************************************************************************
//
//! Enable SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified SSI DMA features are enabled. The SSI can be
//! configured to use DMA for transmit and/or receive data transfers.
//! The \e ulDMAFlags parameter is the logical OR of any of the following
//! values:
//!
//! - SSI_DMA_RX - enable DMA for receive
//! - SSI_DMA_TX - enable DMA for transmit
//!
//! \note The uDMA controller must also be set up before DMA can be used
//! with the SSI.
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Set the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
}
//*****************************************************************************
//
//! Disable SSI DMA operation.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to disable.
//!
//! This function is used to disable SSI DMA features that were enabled
//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
//! \e ulDMAFlags parameter is the logical OR of any of the following values:
//!
//! - SSI_DMA_RX - disable DMA for receive
//! - SSI_DMA_TX - disable DMA for transmit
//!
//! \return None.
//
//*****************************************************************************
void
SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
}
//*****************************************************************************
//
//! Determines whether the SSI transmitter is busy or not.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware. If \b false is returned, then the transmit FIFO
//! is empty and all bits of the last transmitted word have left the hardware
//! shift register.
//!
//! \return Returns \b true if the SSI is transmitting or \b false if all
//! transmissions are complete.
//
//*****************************************************************************
tBoolean
SSIBusy(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Determine if the SSI is busy.
//
return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
}
//*****************************************************************************
//
//! Sets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulSource is the baud clock source for the SSI.
//!
//! This function allows the baud clock source for the SSI to be selected.
//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! Changing the baud clock source will change the data rate generated by the
//! SSI. Therefore, the data rate should be reconfigured after any change to
//! the SSI clock source.
//!
//! \note The ability to specify the SSI baud clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC));
//
// Set the SSI clock source.
//
HWREG(ulBase + SSI_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! This function returns the data clock source for the specified SSI. The
//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! \note The ability to specify the SSI data clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
SSIClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return the SSI clock source.
//
return(HWREG(ulBase + SSI_O_CC));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SSI_H__
#define __SSI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
// as the ulIntFlags parameter, and returned by SSIIntStatus.
//
//*****************************************************************************
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
#define SSI_RXTO 0x00000002 // RX timeout
#define SSI_RXOR 0x00000001 // RX overrun
//*****************************************************************************
//
// Values that can be passed to SSIConfigSetExpClk.
//
//*****************************************************************************
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
#define SSI_FRF_TI 0x00000010 // TI frame format
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
#define SSI_MODE_MASTER 0x00000000 // SSI master
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
//*****************************************************************************
//
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
//
//*****************************************************************************
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
unsigned long ulProtocol, unsigned long ulMode,
unsigned long ulBitRate,
unsigned long ulDataWidth);
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SSIDataGetNonBlocking(unsigned long ulBase,
unsigned long *pulData);
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
extern void SSIDisable(unsigned long ulBase);
extern void SSIEnable(unsigned long ulBase);
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern tBoolean SSIBusy(unsigned long ulBase);
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
//*****************************************************************************
//
// Several SSI APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define SSIConfig(a, b, c, d, e) \
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
#define SSIDataNonBlockingGet(a, b) \
SSIDataGetNonBlocking(a, b)
#define SSIDataNonBlockingPut(a, b) \
SSIDataPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SSI_H__

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//*****************************************************************************
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSCTL_H__
#define __SYSCTL_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to the
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
// is 3) can only be used with the SysCtlPeripheralPresent() API.
//
//*****************************************************************************
#ifndef DEPRECATED
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
#endif
#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
#ifndef DEPRECATED
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
#ifndef DEPRECATED
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
#endif
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
#endif
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
#endif
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPinPresent() API
// as the ulPin parameter.
//
//*****************************************************************************
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOSet() API as
// the ulVoltage value, or returned by the SysCtlLDOGet() API.
//
//*****************************************************************************
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlLDOConfigSet() API.
//
//*****************************************************************************
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlIntEnable(),
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
// by the SysCtlIntStatus() API.
//
//*****************************************************************************
#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlResetCauseClear()
// API or returned by the SysCtlResetCauseGet() API.
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlBrownOutConfigSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPWMClockSet() API
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
// API.
//
//*****************************************************************************
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlADCSpeedSet() API
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
// API.
//
//*****************************************************************************
#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlClockSet() API as
// the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPIOSCCalibrate()
// API as the ulType parameter.
//
//*****************************************************************************
#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlMOSCConfigSet() API
// as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
extern void SysCtlPeripheralClockGating(tBoolean bEnable);
extern void SysCtlIntRegister(void (*pfnHandler)(void));
extern void SysCtlIntUnregister(void);
extern void SysCtlIntEnable(unsigned long ulInts);
extern void SysCtlIntDisable(unsigned long ulInts);
extern void SysCtlIntClear(unsigned long ulInts);
extern unsigned long SysCtlIntStatus(tBoolean bMasked);
extern void SysCtlLDOSet(unsigned long ulVoltage);
extern unsigned long SysCtlLDOGet(void);
extern void SysCtlLDOConfigSet(unsigned long ulConfig);
extern void SysCtlReset(void);
extern void SysCtlSleep(void);
extern void SysCtlDeepSleep(void);
extern unsigned long SysCtlResetCauseGet(void);
extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
extern unsigned long SysCtlADCSpeedGet(void);
extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
extern void SysCtlPLLVerificationSet(tBoolean bEnable);
extern void SysCtlClkVerificationClear(void);
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
extern void SysCtlUSBPLLEnable(void);
extern void SysCtlUSBPLLDisable(void);
extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
unsigned long ulMClk);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSCTL_H__

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bsp/lm4f232/Libraries/driverlib/sysexc.c Normal file
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//*****************************************************************************
//
// sysexc.c - Routines for the System Exception Module.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup sysexc_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_sysexc.h"
#include "inc/hw_types.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Registers an interrupt handler for the system exception interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the system
//! exception interrupt occurs.
//!
//! This function places the address of the system exception interrupt handler
//! into the interrupt vector table in SRAM. It also enables the global
//! interrupt in the interrupt controller; specific system exception interrupts
//! must be enabled via SysExcIntEnable(). It is the interrupt handler's
//! responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_SYSEXC, pfnHandler);
//
// Enable the system exception interrupt.
//
IntEnable(INT_SYSEXC);
}
//*****************************************************************************
//
//! Unregisters the system exception interrupt handler.
//!
//! This function removes the system exception interrupt handler from the
//! vector table in SRAM. It also masks off the system exception interrupt in
//! the interrupt controller so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntUnregister(void)
{
//
// Disable the system exception interrupt.
//
IntDisable(INT_SYSEXC);
//
// Unregister the system exception interrupt handler.
//
IntUnregister(INT_SYSEXC);
}
//*****************************************************************************
//
//! Enables individual system exception interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated system exception interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(SYSEXC_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual system exception interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated system exception interrupt sources.
//! Only sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(SYSEXC_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current system exception interrupt status.
//!
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This function returns the system exception interrupt status. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current system exception interrupt status, enumerated
//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC,
//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and
//! \b SYSEXC_INT_FP_IDC.
//
//*****************************************************************************
unsigned long
SysExcIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(SYSEXC_MIS));
}
else
{
return(HWREG(SYSEXC_RIS));
}
}
//*****************************************************************************
//
//! Clears system exception interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified system exception interrupt sources are cleared, so that they
//! no longer assert. This function must be called in the interrupt handler to
//! keep the interrupt from being recognized again immediately upon exit.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
SysExcIntClear(unsigned long ulIntFlags)
{
//
// Clear the requested interrupt sources.
//
HWREG(SYSEXC_IC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// sysexc.h - Prototypes for the System Exception Module routines.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSEXC_H__
#define __SYSEXC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
// SysExcIntClear as the ulIntFlags parameter, and returned from
// SysExcIntStatus.
//
//*****************************************************************************
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void SysExcIntRegister(void (*pfnHandler)(void));
extern void SysExcIntUnregister(void);
extern void SysExcIntEnable(unsigned long ulIntFlags);
extern void SysExcIntDisable(unsigned long ulIntFlags);
extern unsigned long SysExcIntStatus(tBoolean bMasked);
extern void SysExcIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSEXC_H__

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//*****************************************************************************
//
// systick.c - Driver for the SysTick timer in NVIC.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This will start the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function will cause the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force this. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This will stop the SysTick counter. If an interrupt handler has been
//! registered, it will no longer be called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This sets the handler to be called when a SysTick interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function will clear the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function will enable the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler does not need to clear the SysTick
//! interrupt source as this is done automatically by NVIC when the interrupt
//! handler is called.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function will disable the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter; must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
//! the next clock after the SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps; this
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter; this will
//! be a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// systick.h - Prototypes for the SysTick driver.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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//*****************************************************************************
//
// timer.h - Prototypes for the timer module
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
tBoolean bEnable);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerControlWaitOnTrigger(unsigned long ulBase,
unsigned long ulTimer,
tBoolean bWait);
extern void TimerRTCEnable(unsigned long ulBase);
extern void TimerRTCDisable(unsigned long ulBase);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerLoadGet64(unsigned long ulBase);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern unsigned long long TimerValueGet64(unsigned long ulBase);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue);
extern unsigned long long TimerMatchGet64(unsigned long ulBase);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers);
//*****************************************************************************
//
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
// instead to return the timer to its reset state.
//
//*****************************************************************************
#ifndef DEPRECATED
extern void TimerQuiesce(unsigned long ulBase);
#endif
//*****************************************************************************
//
// These values for TimerConfigure have been deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer
#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer
#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer
#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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//*****************************************************************************
//
// uart.h - Defines and Macros for the UART.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
// UARTHandshakeOutputGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
#define UART_OUTPUT_DTR 0x00000400
//*****************************************************************************
//
// Values that can be returned from UARTHandshakeInputsGet().
//
//*****************************************************************************
#define UART_INPUT_RI 0x00000100
#define UART_INPUT_DCD 0x00000004
#define UART_INPUT_DSR 0x00000002
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// Values that can be passed to UARTClockSourceSet() or returned from
// UARTClockSourceGet().
//
//*****************************************************************************
#define UART_CLOCK_SYSTEM 0x00000000
#define UART_CLOCK_PIOSC 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
extern void UARTDisableSIR(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTSmartCardEnable(unsigned long ulBase);
extern void UARTSmartCardDisable(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
extern void UART9BitEnable(unsigned long ulBase);
extern void UART9BitDisable(unsigned long ulBase);
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
unsigned char ucMask);
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
//*****************************************************************************
//
// Several UART APIs have been renamed, with the original function name being
// deprecated. These defines provide backward compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
#include "driverlib/sysctl.h"
#define UARTConfigSet(a, b, c) \
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
#define UARTConfigGet(a, b, c) \
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
#define UARTCharNonBlockingGet(a) \
UARTCharGetNonBlocking(a)
#define UARTCharNonBlockingPut(a, b) \
UARTCharPutNonBlocking(a, b)
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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//*****************************************************************************
//
// udma.h - Prototypes and macros for the uDMA controller.
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __UDMA_H__
#define __UDMA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup udma_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
// fields are used by the uDMA controller and normally it is not necessary for
// software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
//
// The ending source address of the data transfer.
//
volatile void *pvSrcEndAddr;
//
// The ending destination address of the data transfer.
//
volatile void *pvDstEndAddr;
//
// The channel control mode.
//
volatile unsigned long ulControl;
//
// An unused location.
//
volatile unsigned long ulSpare;
}
tDMAControlTable;
//*****************************************************************************
//
//! A helper macro for building scatter-gather task table entries.
//!
//! \param ulTransferCount is the count of items to transfer for this task.
//! \param ulItemSize is the bit size of the items to transfer for this task.
//! \param ulSrcIncrement is the bit size increment for source data.
//! \param pvSrcAddr is the starting address of the data to transfer.
//! \param ulDstIncrement is the bit size increment for destination data.
//! \param pvDstAddr is the starting address of the destination data.
//! \param ulArbSize is the arbitration size to use for the transfer task.
//! \param ulMode is the transfer mode for this task.
//!
//! This macro is intended to be used to help populate a table of uDMA tasks
//! for a scatter-gather transfer. This macro will calculate the values for
//! the fields of a task structure entry based on the input parameters.
//!
//! There are specific requirements for the values of each parameter. No
//! checking is done so it is up to the caller to ensure that correct values
//! are used for the parameters.
//!
//! The \e ulTransferCount parameter is the number of items that will be
//! transferred by this task. It must be in the range 1-1024.
//!
//! The \e ulItemSize parameter is the bit size of the transfer data. It must
//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
//!
//! The \e ulSrcIncrement parameter is the increment size for the source data.
//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
//!
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
//! data.
//!
//! The \e ulDstIncrement parameter is the increment size for the destination
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
//!
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
//! location where the data will be transferred.
//!
//! The \e ulArbSize parameter is the arbitration size for the transfer, and
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
//! powers of 2, from 1 to 1024.
//!
//! The \e ulMode parameter is the mode to use for this transfer task. It
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
//! that normally all tasks will be one of the scatter-gather modes while the
//! last task is a task list will be AUTO or BASIC.
//!
//! This macro is intended to be used to initialize individual entries of
//! a structure of tDMAControlTable type, like this:
//!
//! \verbatim
//! tDMAControlTable MyTaskList[] =
//! {
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
//! UDMA_SRC_INC_8, MySourceBuf,
//! UDMA_DST_INC_8, MyDestBuf,
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
//! uDMATaskStructEntry(Task2Count, ... ),
//! }
//! \endverbatim
//!
//! \return Nothing; this is not a function.
//
//*****************************************************************************
#define uDMATaskStructEntry(ulTransferCount, \
ulItemSize, \
ulSrcIncrement, \
pvSrcAddr, \
ulDstIncrement, \
pvDstAddr, \
ulArbSize, \
ulMode) \
{ \
(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
((ulSrcIncrement) >> 26)) - 1]))), \
(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
((ulDstIncrement) >> 30)) - 1]))), \
(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
(((ulTransferCount) - 1) << 4) | \
((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
//
//*****************************************************************************
#define UDMA_ATTR_USEBURST 0x00000001
#define UDMA_ATTR_ALTSELECT 0x00000002
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
#define UDMA_ATTR_REQMASK 0x00000008
#define UDMA_ATTR_ALL 0x0000000F
//*****************************************************************************
//
// DMA control modes that can be passed to uDMAModeSet() and returned
// uDMAModeGet().
//
//*****************************************************************************
#define UDMA_MODE_STOP 0x00000000
#define UDMA_MODE_BASIC 0x00000001
#define UDMA_MODE_AUTO 0x00000002
#define UDMA_MODE_PINGPONG 0x00000003
#define UDMA_MODE_MEM_SCATTER_GATHER \
0x00000004
#define UDMA_MODE_PER_SCATTER_GATHER \
0x00000006
#define UDMA_MODE_ALT_SELECT 0x00000001
//*****************************************************************************
//
// Channel configuration values that can be passed to uDMAControlSet().
//
//*****************************************************************************
#define UDMA_DST_INC_8 0x00000000
#define UDMA_DST_INC_16 0x40000000
#define UDMA_DST_INC_32 0x80000000
#define UDMA_DST_INC_NONE 0xc0000000
#define UDMA_SRC_INC_8 0x00000000
#define UDMA_SRC_INC_16 0x04000000
#define UDMA_SRC_INC_32 0x08000000
#define UDMA_SRC_INC_NONE 0x0c000000
#define UDMA_SIZE_8 0x00000000
#define UDMA_SIZE_16 0x11000000
#define UDMA_SIZE_32 0x22000000
#define UDMA_ARB_1 0x00000000
#define UDMA_ARB_2 0x00004000
#define UDMA_ARB_4 0x00008000
#define UDMA_ARB_8 0x0000c000
#define UDMA_ARB_16 0x00010000
#define UDMA_ARB_32 0x00014000
#define UDMA_ARB_64 0x00018000
#define UDMA_ARB_128 0x0001c000
#define UDMA_ARB_256 0x00020000
#define UDMA_ARB_512 0x00024000
#define UDMA_ARB_1024 0x00028000
#define UDMA_NEXT_USEBURST 0x00000008
//*****************************************************************************
//
// Channel numbers to be passed to API functions that require a channel number
// ID.
//
//*****************************************************************************
#define UDMA_CHANNEL_USBEP1RX 0
#define UDMA_CHANNEL_USBEP1TX 1
#define UDMA_CHANNEL_USBEP2RX 2
#define UDMA_CHANNEL_USBEP2TX 3
#define UDMA_CHANNEL_USBEP3RX 4
#define UDMA_CHANNEL_USBEP3TX 5
#define UDMA_CHANNEL_ETH0RX 6
#define UDMA_CHANNEL_ETH0TX 7
#define UDMA_CHANNEL_UART0RX 8
#define UDMA_CHANNEL_UART0TX 9
#define UDMA_CHANNEL_SSI0RX 10
#define UDMA_CHANNEL_SSI0TX 11
#define UDMA_CHANNEL_ADC0 14
#define UDMA_CHANNEL_ADC1 15
#define UDMA_CHANNEL_ADC2 16
#define UDMA_CHANNEL_ADC3 17
#define UDMA_CHANNEL_TMR0A 18
#define UDMA_CHANNEL_TMR0B 19
#define UDMA_CHANNEL_TMR1A 20
#define UDMA_CHANNEL_TMR1B 21
#define UDMA_CHANNEL_UART1RX 22
#define UDMA_CHANNEL_UART1TX 23
#define UDMA_CHANNEL_SSI1RX 24
#define UDMA_CHANNEL_SSI1TX 25
#define UDMA_CHANNEL_I2S0RX 28
#define UDMA_CHANNEL_I2S0TX 29
#define UDMA_CHANNEL_SW 30
//*****************************************************************************
//
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
// control structure should be used.
//
//*****************************************************************************
#define UDMA_PRI_SELECT 0x00000000
#define UDMA_ALT_SELECT 0x00000020
//*****************************************************************************
//
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
// uDMAIntUnregister().
//
//*****************************************************************************
#define UDMA_INT_SW 62
#define UDMA_INT_ERR 63
//*****************************************************************************
//
// Channel numbers to be passed to API functions that require a channel number
// ID. These are for secondary peripheral assignments.
//
//*****************************************************************************
#define UDMA_SEC_CHANNEL_UART2RX_0 \
0
#define UDMA_SEC_CHANNEL_UART2TX_1 \
1
#define UDMA_SEC_CHANNEL_TMR3A 2
#define UDMA_SEC_CHANNEL_TMR3B 3
#define UDMA_SEC_CHANNEL_TMR2A_4 \
4
#define UDMA_SEC_CHANNEL_TMR2B_5 \
5
#define UDMA_SEC_CHANNEL_TMR2A_6 \
6
#define UDMA_SEC_CHANNEL_TMR2B_7 \
7
#define UDMA_SEC_CHANNEL_UART1RX \
8
#define UDMA_SEC_CHANNEL_UART1TX \
9
#define UDMA_SEC_CHANNEL_SSI1RX 10
#define UDMA_SEC_CHANNEL_SSI1TX 11
#define UDMA_SEC_CHANNEL_UART2RX_12 \
12
#define UDMA_SEC_CHANNEL_UART2TX_13 \
13
#define UDMA_SEC_CHANNEL_TMR2A_14 \
14
#define UDMA_SEC_CHANNEL_TMR2B_15 \
15
#define UDMA_SEC_CHANNEL_TMR1A 18
#define UDMA_SEC_CHANNEL_TMR1B 19
#define UDMA_SEC_CHANNEL_EPI0RX 20
#define UDMA_SEC_CHANNEL_EPI0TX 21
#define UDMA_SEC_CHANNEL_ADC10 24
#define UDMA_SEC_CHANNEL_ADC11 25
#define UDMA_SEC_CHANNEL_ADC12 26
#define UDMA_SEC_CHANNEL_ADC13 27
#define UDMA_SEC_CHANNEL_SW 30
//*****************************************************************************
//
// uDMA default/secondary peripheral selections, to be passed to
// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
//
//*****************************************************************************
#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
0x00000001
#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
0x00000002
#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
0x00000004
#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
0x00000008
#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
0x00000010
#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
0x00000020
#define UDMA_DEF_ETH0RX_SEC_TMR2A \
0x00000040
#define UDMA_DEF_ETH0TX_SEC_TMR2B \
0x00000080
#define UDMA_DEF_UART0RX_SEC_UART1RX \
0x00000100
#define UDMA_DEF_UART0TX_SEC_UART1TX \
0x00000200
#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
0x00000400
#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
0x00000800
#define UDMA_DEF_RESERVED_SEC_UART2RX \
0x00001000
#define UDMA_DEF_RESERVED_SEC_UART2TX \
0x00002000
#define UDMA_DEF_ADC00_SEC_TMR2A \
0x00004000
#define UDMA_DEF_ADC01_SEC_TMR2B \
0x00008000
#define UDMA_DEF_ADC02_SEC_RESERVED \
0x00010000
#define UDMA_DEF_ADC03_SEC_RESERVED \
0x00020000
#define UDMA_DEF_TMR0A_SEC_TMR1A \
0x00040000
#define UDMA_DEF_TMR0B_SEC_TMR1B \
0x00080000
#define UDMA_DEF_TMR1A_SEC_EPI0RX \
0x00100000
#define UDMA_DEF_TMR1B_SEC_EPI0TX \
0x00200000
#define UDMA_DEF_UART1RX_SEC_RESERVED \
0x00400000
#define UDMA_DEF_UART1TX_SEC_RESERVED \
0x00800000
#define UDMA_DEF_SSI1RX_SEC_ADC10 \
0x01000000
#define UDMA_DEF_SSI1TX_SEC_ADC11 \
0x02000000
#define UDMA_DEF_RESERVED_SEC_ADC12 \
0x04000000
#define UDMA_DEF_RESERVED_SEC_ADC13 \
0x08000000
#define UDMA_DEF_I2S0RX_SEC_RESERVED \
0x10000000
#define UDMA_DEF_I2S0TX_SEC_RESERVED \
0x20000000
//*****************************************************************************
//
// Values that can be passed to uDMAChannelMapConfigure() to select peripheral
// mapping for each channel. The channels named RESERVED may be assigned
// to a peripheral in future parts.
//
//*****************************************************************************
//
// Channel 0
//
#define UDMA_CH0_USB0EP1RX 0x00000000
#define UDMA_CH0_UART2RX 0x00010000
#define UDMA_CH0_RESERVED2 0x00020000
#define UDMA_CH0_TIMER4A 0x00030000
#define UDMA_CH0_RESERVED4 0x00040000
//
// Channel 1
//
#define UDMA_CH1_USB0EP1TX 0x00000001
#define UDMA_CH1_UART2TX 0x00010001
#define UDMA_CH1_RESERVED2 0x00020001
#define UDMA_CH1_TIMER4B 0x00030001
#define UDMA_CH1_RESERVED4 0x00040001
//
// Channel 2
//
#define UDMA_CH2_USB0EP2RX 0x00000002
#define UDMA_CH2_TIMER3A 0x00010002
#define UDMA_CH2_RESERVED2 0x00020002
#define UDMA_CH2_RESERVED3 0x00030002
#define UDMA_CH2_RESERVED4 0x00040002
//
// Channel 3
//
#define UDMA_CH3_USB0EP2TX 0x00000003
#define UDMA_CH3_TIMER3B 0x00010003
#define UDMA_CH3_RESERVED2 0x00020003
#define UDMA_CH3_LPC0_3 0x00030003
#define UDMA_CH3_RESERVED4 0x00040003
//
// Channel 4
//
#define UDMA_CH4_USB0EP3RX 0x00000004
#define UDMA_CH4_TIMER2A 0x00010004
#define UDMA_CH4_RESERVED2 0x00020004
#define UDMA_CH4_GPIOA 0x00030004
#define UDMA_CH4_RESERVED4 0x00040004
//
// Channel 5
//
#define UDMA_CH5_USB0EP3TX 0x00000005
#define UDMA_CH5_TIMER2B 0x00010005
#define UDMA_CH5_RESERVED2 0x00020005
#define UDMA_CH5_GPIOB 0x00030005
#define UDMA_CH5_RESERVED4 0x00040005
//
// Channel 6
//
#define UDMA_CH6_RESERVED0 0x00000006
#define UDMA_CH6_TIMER2A 0x00010006
#define UDMA_CH6_UART5RX 0x00020006
#define UDMA_CH6_GPIOC 0x00030006
#define UDMA_CH6_I2C0RX 0x00040006
//
// Channel 7
//
#define UDMA_CH7_RESERVED0 0x00000007
#define UDMA_CH7_TIMER2B 0x00010007
#define UDMA_CH7_UART5TX 0x00020007
#define UDMA_CH7_GPIOD 0x00030007
#define UDMA_CH7_I2C0TX 0x00040007
//
// Channel 8
//
#define UDMA_CH8_UART0RX 0x00000008
#define UDMA_CH8_UART1RX 0x00010008
#define UDMA_CH8_RESERVED2 0x00020008
#define UDMA_CH8_TIMER5A 0x00030008
#define UDMA_CH8_I2C1RX 0x00040008
//
// Channel 9
//
#define UDMA_CH9_UART0TX 0x00000009
#define UDMA_CH9_UART1TX 0x00010009
#define UDMA_CH9_RESERVED2 0x00020009
#define UDMA_CH9_TIMER5B 0x00030009
#define UDMA_CH9_I2C1TX 0x00040009
//
// Channel 10
//
#define UDMA_CH10_SSI0RX 0x0000000A
#define UDMA_CH10_SSI1RX 0x0001000A
#define UDMA_CH10_UART6RX 0x0002000A
#define UDMA_CH10_WTIMER0A 0x0003000A
#define UDMA_CH10_I2C2RX 0x0004000A
//
// Channel 11
//
#define UDMA_CH11_SSI0TX 0x0000000B
#define UDMA_CH11_SSI1TX 0x0001000B
#define UDMA_CH11_UART6TX 0x0002000B
#define UDMA_CH11_WTIMER0B 0x0003000B
#define UDMA_CH11_I2C2TX 0x0004000B
//
// Channel 12
//
#define UDMA_CH12_RESERVED0 0x0000000C
#define UDMA_CH12_UART2RX 0x0001000C
#define UDMA_CH12_SSI2RX 0x0002000C
#define UDMA_CH12_WTIMER1A 0x0003000C
#define UDMA_CH12_GPIOK 0x0004000C
//
// Channel 13
//
#define UDMA_CH13_RESERVED0 0x0000000D
#define UDMA_CH13_UART2TX 0x0001000D
#define UDMA_CH13_SSI2TX 0x0002000D
#define UDMA_CH13_WTIMER1B 0x0003000D
#define UDMA_CH13_GPIOL 0x0004000D
//
// Channel 14
//
#define UDMA_CH14_ADC0_0 0x0000000E
#define UDMA_CH14_TIMER2A 0x0001000E
#define UDMA_CH14_SSI3RX 0x0002000E
#define UDMA_CH14_GPIOE 0x0003000E
#define UDMA_CH14_GPIOM 0x0004000E
//
// Channel 15
//
#define UDMA_CH15_ADC0_1 0x0000000F
#define UDMA_CH15_TIMER2B 0x0001000F
#define UDMA_CH15_SSI3TX 0x0002000F
#define UDMA_CH15_GPIOF 0x0003000F
#define UDMA_CH15_GPION 0x0004000F
//
// Channel 16
//
#define UDMA_CH16_ADC0_2 0x00000010
#define UDMA_CH16_RESERVED1 0x00010010
#define UDMA_CH16_UART3RX 0x00020010
#define UDMA_CH16_WTIMER2A 0x00030010
#define UDMA_CH16_GPIOP 0x00040010
//
// Channel 17
//
#define UDMA_CH17_ADC0_3 0x00000011
#define UDMA_CH17_RESERVED1 0x00010011
#define UDMA_CH17_UART3TX 0x00020011
#define UDMA_CH17_WTIMER2B 0x00030011
#define UDMA_CH17_RESERVED4 0x00040011
//
// Channel 18
//
#define UDMA_CH18_TIMER0A 0x00000012
#define UDMA_CH18_TIMER1A 0x00010012
#define UDMA_CH18_UART4RX 0x00020012
#define UDMA_CH18_GPIOB 0x00030012
#define UDMA_CH18_I2C3RX 0x00040012
//
// Channel 19
//
#define UDMA_CH19_TIMER0B 0x00000013
#define UDMA_CH19_TIMER1B 0x00010013
#define UDMA_CH19_UART4TX 0x00020013
#define UDMA_CH19_GPIOG 0x00030013
#define UDMA_CH19_I2C3TX 0x00040013
//
// Channel 20
//
#define UDMA_CH20_TIMER1A 0x00000014
#define UDMA_CH20_RESERVED1 0x00010014
#define UDMA_CH20_UART7RX 0x00020014
#define UDMA_CH20_GPIOH 0x00030014
#define UDMA_CH20_I2C4RX 0x00040014
//
// Channel 21
//
#define UDMA_CH21_TIMER1B 0x00000015
#define UDMA_CH21_RESERVED1 0x00010015
#define UDMA_CH21_UART7TX 0x00020015
#define UDMA_CH21_GPIOJ 0x00030015
#define UDMA_CH21_I2C4TX 0x00040015
//
// Channel 22
//
#define UDMA_CH22_UART1RX 0x00000016
#define UDMA_CH22_RESERVED1 0x00010016
#define UDMA_CH22_RESERVED2 0x00020016
#define UDMA_CH22_LPC0_2 0x00030016
#define UDMA_CH22_I2C5RX 0x00040016
//
// Channel 23
//
#define UDMA_CH23_UART1TX 0x00000017
#define UDMA_CH23_RESERVED1 0x00010017
#define UDMA_CH23_RESERVED2 0x00020017
#define UDMA_CH23_LPC0_1 0x00030017
#define UDMA_CH23_I2C5TX 0x00040017
//
// Channel 24
//
#define UDMA_CH24_SSI1RX 0x00000018
#define UDMA_CH24_ADC1_0 0x00010018
#define UDMA_CH24_RESERVED2 0x00020018
#define UDMA_CH24_WTIMER3A 0x00030018
#define UDMA_CH24_GPIOQ 0x00040018
//
// Channel 25
//
#define UDMA_CH25_SSI1TX 0x00000019
#define UDMA_CH25_ADC1_1 0x00010019
#define UDMA_CH25_RESERVED2 0x00020019
#define UDMA_CH25_WTIMER3B 0x00030019
#define UDMA_CH25_RESERVED4 0x00040019
//
// Channel 26
//
#define UDMA_CH26_RESERVED0 0x0000001A
#define UDMA_CH26_ADC1_2 0x0001001A
#define UDMA_CH26_RESERVED2 0x0002001A
#define UDMA_CH26_WTIMER4A 0x0003001A
#define UDMA_CH26_RESERVED4 0x0004001A
//
// Channel 27
//
#define UDMA_CH27_RESERVED0 0x0000001B
#define UDMA_CH27_ADC1_3 0x0001001B
#define UDMA_CH27_RESERVED2 0x0002001B
#define UDMA_CH27_WTIMER4B 0x0003001B
#define UDMA_CH27_RESERVED4 0x0004001B
//
// Channel 28
//
#define UDMA_CH28_RESERVED0 0x0000001C
#define UDMA_CH28_RESERVED1 0x0001001C
#define UDMA_CH28_RESERVED2 0x0002001C
#define UDMA_CH28_WTIMER5A 0x0003001C
#define UDMA_CH28_RESERVED4 0x0004001C
//
// Channel 29
//
#define UDMA_CH29_RESERVED0 0x0000001D
#define UDMA_CH29_RESERVED1 0x0001001D
#define UDMA_CH29_RESERVED2 0x0002001D
#define UDMA_CH29_WTIMER5B 0x0003001D
#define UDMA_CH29_RESERVED4 0x0004001D
//
// Channel 30
//
#define UDMA_CH30_SW 0x0000001E
#define UDMA_CH30_RESERVED1 0x0001001E
#define UDMA_CH30_RESERVED2 0x0002001E
#define UDMA_CH30_RESERVED3 0x0003001E
#define UDMA_CH30_RESERVED4 0x0004001E
//
// Channel 31
//
#define UDMA_CH31_RESERVED0 0x0000001F
#define UDMA_CH31_RESERVED1 0x0001001F
#define UDMA_CH31_RESERVED2 0x0002001F
#define UDMA_CH31_LPC0_0 0x0003001F
#define UDMA_CH31_RESERVED4 0x0004001F
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannelNum);
extern void uDMAChannelDisable(unsigned long ulChannelNum);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void *uDMAControlAlternateBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannelNum);
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
unsigned ulTaskCount, void *pvTaskList,
unsigned long ulIsPeriphSG);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
extern void uDMAChannelAssign(unsigned long ulMapping);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UDMA_H__

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//*****************************************************************************
//
// usb.h - Prototypes for the USB Interface Driver.
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __USB_H__
#define __USB_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following are values that can be passed to USBIntEnableControl() and
// USBIntDisableControl() as the ulFlags parameter, and are returned from
// USBIntStatusControl().
//
//*****************************************************************************
#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources
#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts
#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error
#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected
#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected
#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected
#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected
#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected
#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled
#define USB_INTCTRL_RESET 0x00000004 // Reset signaled
#define USB_INTCTRL_RESUME 0x00000002 // Resume detected
#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected
#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid
#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected
//*****************************************************************************
//
// The following are values that can be passed to USBIntEnableEndpoint() and
// USBIntDisableEndpoint() as the ulFlags parameter, and are returned from
// USBIntStatusEndpoint().
//
//*****************************************************************************
#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts
#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts
#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt
#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt
#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt
#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt
#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt
#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt
#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt
#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt
#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt
#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt
#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt
#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt
#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt
#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt
#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt
#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts
#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt
#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt
#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts
#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt
#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt
#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts
#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt
#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt
#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt
#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt
#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt
#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt
#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt
#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt
#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt
#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt
#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt
#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt
#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt
#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt
#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt
#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt
//*****************************************************************************
//
// The following are values that are returned from USBSpeedGet().
//
//*****************************************************************************
#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
//*****************************************************************************
//
// The following are values that are returned from USBEndpointStatus(). The
// USB_HOST_* values are used when the USB controller is in host mode and the
// USB_DEV_* values are used when the USB controller is in device mode.
//
//*****************************************************************************
#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts
#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received
#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond
#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
// (ISOC Mode)
#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
// specified timeout period
#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
// device
#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts
#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
// specified timeout period
#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
// (ISOC mode)
#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
// device
#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
// specified timeout period
#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
// device
#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
// a full FIFO
#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
// to come
#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
// Data End seen
#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
//*****************************************************************************
//
// The following are values that can be passed to USBHostEndpointConfig() and
// USBDevEndpointConfigSet() as the ulFlags parameter.
//
//*****************************************************************************
#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint
#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint
//*****************************************************************************
//
// The following are values that can be passed to USBHostPwrConfig() as
// the ulFlags parameter.
//
//*****************************************************************************
#define USB_HOST_PWRFLT_LOW 0x00000010
#define USB_HOST_PWRFLT_HIGH 0x00000030
#define USB_HOST_PWRFLT_EP_NONE 0x00000000
#define USB_HOST_PWRFLT_EP_TRI 0x00000140
#define USB_HOST_PWRFLT_EP_LOW 0x00000240
#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
#ifndef DEPRECATED
#define USB_HOST_PWREN_LOW 0x00000002
#define USB_HOST_PWREN_HIGH 0x00000003
#define USB_HOST_PWREN_VBLOW 0x00000002
#define USB_HOST_PWREN_VBHIGH 0x00000003
#endif
#define USB_HOST_PWREN_MAN_LOW 0x00000000
#define USB_HOST_PWREN_MAN_HIGH 0x00000001
#define USB_HOST_PWREN_AUTOLOW 0x00000002
#define USB_HOST_PWREN_AUTOHIGH 0x00000003
#define USB_HOST_PWREN_FILTER 0x00010000
//*****************************************************************************
//
// The following are special values that can be passed to
// USBHostEndpointConfig() as the ulNAKPollInterval parameter.
//
//*****************************************************************************
#define MAX_NAK_LIMIT 31 // Maximum NAK interval
#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
//*****************************************************************************
//
// This value specifies the maximum size of transfers on endpoint 0 as 64
// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
//
//*****************************************************************************
#define MAX_PACKET_SIZE_EP0 64
//*****************************************************************************
//
// These values are used to indicate which endpoint to access.
//
//*****************************************************************************
#define USB_EP_0 0x00000000 // Endpoint 0
#define USB_EP_1 0x00000010 // Endpoint 1
#define USB_EP_2 0x00000020 // Endpoint 2
#define USB_EP_3 0x00000030 // Endpoint 3
#define USB_EP_4 0x00000040 // Endpoint 4
#define USB_EP_5 0x00000050 // Endpoint 5
#define USB_EP_6 0x00000060 // Endpoint 6
#define USB_EP_7 0x00000070 // Endpoint 7
#define USB_EP_8 0x00000080 // Endpoint 8
#define USB_EP_9 0x00000090 // Endpoint 9
#define USB_EP_10 0x000000A0 // Endpoint 10
#define USB_EP_11 0x000000B0 // Endpoint 11
#define USB_EP_12 0x000000C0 // Endpoint 12
#define USB_EP_13 0x000000D0 // Endpoint 13
#define USB_EP_14 0x000000E0 // Endpoint 14
#define USB_EP_15 0x000000F0 // Endpoint 15
#define NUM_USB_EP 16 // Number of supported endpoints
//*****************************************************************************
//
// These macros allow conversion between 0-based endpoint indices and the
// USB_EP_x values required when calling various USB APIs.
//
//*****************************************************************************
#define INDEX_TO_USB_EP(x) ((x) << 4)
#define USB_EP_TO_INDEX(x) ((x) >> 4)
//*****************************************************************************
//
// The following are values that can be passed to USBFIFOConfigSet() as the
// ulFIFOSize parameter.
//
//*****************************************************************************
#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO
#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO
// (occupying 16 bytes)
#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO
// (occupying 32 bytes)
#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO
// (occupying 64 bytes)
#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO
// (occupying 128 bytes)
#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO
// (occupying 256 bytes)
#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO
// (occupying 512 bytes)
#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO
// (occupying 1024 bytes)
#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO
// (occupying 2048 bytes)
#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO
// (occupying 4096 bytes)
//*****************************************************************************
//
// This macro allow conversion from a FIFO size label as defined above to
// a number of bytes
//
//*****************************************************************************
#define USB_FIFO_SIZE_DB_FLAG 0x00000010
#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
(((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
//*****************************************************************************
//
// The following are values that can be passed to USBEndpointDataSend() as the
// ulTransType parameter.
//
//*****************************************************************************
#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
#define USB_TRANS_IN 0x00000102 // Normal IN transaction
#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
// endpoint 0 in device mode)
#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
// 0)
#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
// 0)
//*****************************************************************************
//
// The following are values are returned by the USBModeGet function.
//
//*****************************************************************************
#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
// mode.
#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
// Device mode.
#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
// set.
#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of
// the cable Session Valid.
#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of
// the cable A valid.
#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
// the cable.
#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
// the cable.
#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long USBDevAddrGet(unsigned long ulBase);
extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
extern void USBDevConnect(unsigned long ulBase);
extern void USBDevDisconnect(unsigned long ulBase);
extern void USBDevEndpointConfigSet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulMaxPacketSize,
unsigned long ulFlags);
extern void USBDevEndpointConfigGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long *pulMaxPacketSize,
unsigned long *pulFlags);
extern void USBDevEndpointDataAck(unsigned long ulBase,
unsigned long ulEndpoint,
tBoolean bIsLastPacket);
extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBDevEndpointStallClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBDevEndpointStatusClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBEndpointDataAvail(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBEndpointDMADisable(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned char *pucData, unsigned long *pulSize);
extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
unsigned char *pucData, unsigned long ulSize);
extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulTransType);
extern void USBEndpointDataToggleClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBEndpointStatus(unsigned long ulBase,
unsigned long ulEndpoint);
extern unsigned long USBFIFOAddrGet(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long *pulFIFOAddress,
unsigned long *pulFIFOSize,
unsigned long ulFlags);
extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFIFOAddress,
unsigned long ulFIFOSize, unsigned long ulFlags);
extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBFrameNumberGet(unsigned long ulBase);
extern unsigned long USBHostAddrGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulAddr, unsigned long ulFlags);
extern void USBHostEndpointConfig(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulMaxPacketSize,
unsigned long ulNAKPollInterval,
unsigned long ulTargetEndpoint,
unsigned long ulFlags);
extern void USBHostEndpointDataAck(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBHostEndpointDataToggle(unsigned long ulBase,
unsigned long ulEndpoint,
tBoolean bDataToggle,
unsigned long ulFlags);
extern void USBHostEndpointStatusClear(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern unsigned long USBHostHubAddrGet(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulFlags);
extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
unsigned long ulAddr, unsigned long ulFlags);
extern void USBHostPwrDisable(unsigned long ulBase);
extern void USBHostPwrEnable(unsigned long ulBase);
extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags);
#ifndef DEPRECATED
#define USBHostPwrFaultConfig USBHostPwrConfig
#endif
extern void USBHostPwrFaultDisable(unsigned long ulBase);
extern void USBHostPwrFaultEnable(unsigned long ulBase);
extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
extern void USBHostRequestINClear(unsigned long ulBase,
unsigned long ulEndpoint);
extern void USBHostRequestStatus(unsigned long ulBase);
extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
extern unsigned long USBHostSpeedGet(unsigned long ulBase);
extern void USBHostSuspend(unsigned long ulBase);
extern void USBIntDisableControl(unsigned long ulBase,
unsigned long ulIntFlags);
extern void USBIntEnableControl(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long USBIntStatusControl(unsigned long ulBase);
extern void USBIntDisableEndpoint(unsigned long ulBase,
unsigned long ulIntFlags);
extern void USBIntEnableEndpoint(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long USBIntStatusEndpoint(unsigned long ulBase);
extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void USBIntUnregister(unsigned long ulBase);
extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
extern unsigned long USBModeGet(unsigned long ulBase);
extern void USBEndpointDMAChannel(unsigned long ulBase,
unsigned long ulEndpoint,
unsigned long ulChannel);
extern void USBHostMode(unsigned long ulBase);
extern void USBDevMode(unsigned long ulBase);
extern void USBOTGMode(unsigned long ulBase);
extern void USBPHYPowerOff(unsigned long ulBase);
extern void USBPHYPowerOn(unsigned long ulBase);
//*****************************************************************************
//
// Several USB APIs have been renamed, with the original function name being
// deprecated. These defines and function protypes provide backward
// compatibility.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are values that can be passed to USBIntEnable() and
// USBIntDisable() as the ulIntFlags parameter, and are returned from
// USBIntStatus().
//
//*****************************************************************************
#define USB_INT_ALL 0xFF030E0F // All Interrupt sources
#define USB_INT_STATUS 0xFF000000 // Status Interrupts
#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error
#define USB_INT_SESSION_START 0x40000000 // Session Start Detected
#define USB_INT_SESSION_END 0x20000000 // Session End Detected
#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected
#define USB_INT_CONNECT 0x10000000 // Device Connect Detected
#define USB_INT_SOF 0x08000000 // Start of Frame Detected
#define USB_INT_BABBLE 0x04000000 // Babble signaled
#define USB_INT_RESET 0x04000000 // Reset signaled
#define USB_INT_RESUME 0x02000000 // Resume detected
#define USB_INT_SUSPEND 0x01000000 // Suspend detected
#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid
#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected
#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts
#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts
#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt
#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt
#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt
#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt
#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt
#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt
#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts
#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts
#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt
#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt
#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt
#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt
#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt
#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt
#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt
#define USBDevEndpointConfig USBDevEndpointConfigSet
extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long USBIntStatus(unsigned long ulBase);
#endif
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __USB_H__

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bsp/lm4f232/Libraries/driverlib/watchdog.c Normal file
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@ -0,0 +1,616 @@
//*****************************************************************************
//
// watchdog.c - Driver for the Watchdog Timer Module.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup watchdog_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_watchdog.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
#include "driverlib/watchdog.h"
//*****************************************************************************
//
//! Determines if the watchdog timer is enabled.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! if it is not.
//
//*****************************************************************************
tBoolean
WatchdogRunning(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// See if the watchdog timer module is enabled, and return.
//
return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog timer module.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Enables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogResetEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
}
//*****************************************************************************
//
//! Disables the watchdog timer reset.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Disables the capability of the watchdog timer to issue a reset to the
//! processor upon a second timeout condition.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogResetDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable the watchdog reset.
//
HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogLock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
// register causes the lock to go into effect.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
}
//*****************************************************************************
//
//! Disables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogUnlock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Unlock watchdog register writes.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
}
//*****************************************************************************
//
//! Gets the state of the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
//
//*****************************************************************************
tBoolean
WatchdogLockState(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the lock state.
//
return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
}
//*****************************************************************************
//
//! Sets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value is immediately loaded into the watchdog
//! timer counter. If the \e ulLoadVal parameter is 0, then an interrupt is
//! immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Set the load register.
//
HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
}
//*****************************************************************************
//
//! Gets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function gets the value that is loaded into the watchdog timer when
//! the count reaches zero for the first time.
//!
//! \sa WatchdogReloadSet()
//!
//! \return None.
//
//*****************************************************************************
unsigned long
WatchdogReloadGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the load register.
//
return(HWREG(ulBase + WDT_O_LOAD));
}
//*****************************************************************************
//
//! Gets the current watchdog timer value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function reads the current value of the watchdog timer.
//!
//! \return Returns the current value of the watchdog timer.
//
//*****************************************************************************
unsigned long
WatchdogValueGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Get the current watchdog timer register value.
//
return(HWREG(ulBase + WDT_O_VALUE));
}
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note For parts with a watchdog timer module that has the ability to
//! generate an NMI instead of a standard interrupt, this function will
//! register the standard watchdog interrupt handler. To register the NMI
//! watchdog handler, use IntRegister() to register the handler for the
//! \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Register the interrupt handler.
//
IntRegister(INT_WATCHDOG, pfnHandler);
//
// Enable the watchdog timer interrupt.
//
IntEnable(INT_WATCHDOG);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note For parts with a watchdog timer module that has the ability to
//! generate an NMI instead of a standard interrupt, this function will
//! unregister the standard watchdog interrupt handler. To unregister the NMI
//! watchdog handler, use IntUnregister() to unregister the handler for the
//! \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable the interrupt.
//
IntDisable(INT_WATCHDOG);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_WATCHDOG);
}
//*****************************************************************************
//
//! Enables the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables the watchdog timer interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable the watchdog interrupt.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Gets the current watchdog timer interrupt status.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, where a 1 indicates that the
//! watchdog interrupt is active, and a 0 indicates that it is not active.
//
//*****************************************************************************
unsigned long
WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + WDT_O_MIS));
}
else
{
return(HWREG(ulBase + WDT_O_RIS));
}
}
//*****************************************************************************
//
//! Clears the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Clear the interrupt source.
//
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
//*****************************************************************************
//
//! Sets the type of interrupt generated by the watchdog.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulType is the type of interrupt to generate.
//!
//! This function sets the type of interrupt that is generated if the watchdog
//! timer expires. \e ulType can be either \b WATCHDOG_INT_TYPE_INT to
//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
//! generate a non-maskable interrupt (NMI).
//!
//! When configured to generate an NMI, the watchdog interrupt must still be
//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
//! NMI handler with WatchdogIntClear().
//!
//! \note The ability to select an NMI interrupt varies with the Stellaris part
//! in use. Please consult the datasheet for the part you are using to
//! determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
ASSERT((ulType == WATCHDOG_INT_TYPE_INT) ||
(ulType == WATCHDOG_INT_TYPE_NMI));
//
// Set the interrupt type.
//
HWREG(ulBase + WDT_O_CTL) =
(HWREG(ulBase + WDT_O_CTL) & ~WDT_CTL_INTTYPE) | ulType;
}
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Enable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
}
//*****************************************************************************
//
//! Disables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function disables the debug mode stall of the watchdog timer. By
//! doing so, the watchdog timer continues to count regardless of the processor
//! debug state.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
//
// Disable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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//*****************************************************************************
//
// watchdog.h - Prototypes for the Watchdog Timer API
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The type of interrupt that can be generated by the watchdog.
//
//*****************************************************************************
#define WATCHDOG_INT_TYPE_INT 0x00000000
#define WATCHDOG_INT_TYPE_NMI 0x00000004
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogResetEnable(unsigned long ulBase);
extern void WatchdogResetDisable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern void WatchdogIntEnable(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

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//*****************************************************************************
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __ASMDEFS_H__
#define __ASMDEFS_H__
//*****************************************************************************
//
// The defines required for code_red.
//
//*****************************************************************************
#ifdef codered
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // codered
//*****************************************************************************
//
// The defines required for EW-ARM.
//
//*****************************************************************************
#ifdef ewarm
//
// Section headers.
//
#define __LIBRARY__ module
#define __TEXT__ rseg CODE:CODE(2)
#define __DATA__ rseg DATA:DATA(2)
#define __BSS__ rseg DATA:DATA(2)
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
//
// Assembler nmenonics.
//
#define __ALIGN__ alignrom 2
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__ thumb
#define __WORD__ dcd
#define __INLINE_DATA__ data
#endif // ewarm
//*****************************************************************************
//
// The defines required for GCC.
//
//*****************************************************************************
#if defined(gcc)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // gcc
//*****************************************************************************
//
// The defines required for RV-MDK.
//
//*****************************************************************************
#ifdef rvmdk
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
thumb
require8
preserve8
//
// Section headers.
//
#define __LIBRARY__ ;
#define __TEXT__ area ||.text||, code, readonly, align=2
#define __DATA__ area ||.data||, data, align=2
#define __BSS__ area ||.bss||, noinit, align=2
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
//
// Assembler nmenonics.
//
#define __ALIGN__ align 4
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__
#define __WORD__ dcd
#define __INLINE_DATA__
#endif // rvmdk
//*****************************************************************************
//
// The defines required for Sourcery G++.
//
//*****************************************************************************
#if defined(sourcerygxx)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // sourcerygxx
#endif // __ASMDEF_H__

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bsp/lm4f232/Libraries/inc/cr_project.xml Normal file
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<!--
Configuration file for Code Red project inc
Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
Software License Agreement
Texas Instruments (TI) is supplying this software for use solely and
exclusively on TI's microcontroller products. The software is owned by
TI and/or its suppliers, and is protected under applicable copyright
laws. You may not combine this software with "viral" open-source
software in order to form a larger program.
THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, FOR ANY REASON WHATSOEVER.
This is part of revision 8049 of the Stellaris Firmware Development Package.
-->
<project>
<import src=".">
<exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|sgxx|Uv2|uvopt|uvproj|cmd)}</exclude>
</import>
</project>

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bsp/lm4f232/Libraries/inc/hw_adc.h Normal file
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//*****************************************************************************
//
// hw_can.h - Defines and macros used when accessing the CAN controllers.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_CAN_H__
#define __HW_CAN_H__
//*****************************************************************************
//
// The following are defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_CTL 0x00000000 // CAN Control
#define CAN_O_STS 0x00000004 // CAN Status
#define CAN_O_ERR 0x00000008 // CAN Error Counter
#define CAN_O_BIT 0x0000000C // CAN Bit Timing
#define CAN_O_INT 0x00000010 // CAN Interrupt
#define CAN_O_TST 0x00000014 // CAN Test
#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
// Extension
#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_CTL register.
//
//*****************************************************************************
#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
#define CAN_CTL_INIT 0x00000001 // Initialization
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_STS register.
//
//*****************************************************************************
#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
#define CAN_STS_EWARN 0x00000040 // Warning Status
#define CAN_STS_EPASS 0x00000020 // Error Passive
#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
// Successfully
#define CAN_STS_LEC_M 0x00000007 // Last Error Code
#define CAN_STS_LEC_NONE 0x00000000 // No Error
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
#define CAN_STS_LEC_FORM 0x00000002 // Format Error
#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_ERR register.
//
//*****************************************************************************
#define CAN_ERR_RP 0x00008000 // Received Error Passive
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
#define CAN_ERR_REC_S 8
#define CAN_ERR_TEC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BIT register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
#define CAN_BIT_TSEG2_S 12
#define CAN_BIT_TSEG1_S 8
#define CAN_BIT_SJW_S 6
#define CAN_BIT_BRP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_INT register.
//
//*****************************************************************************
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TST register.
//
//*****************************************************************************
#define CAN_TST_RX 0x00000080 // Receive Observation
#define CAN_TST_TX_M 0x00000060 // Transmit Control
#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
#define CAN_TST_LBACK 0x00000010 // Loopback Mode
#define CAN_TST_SILENT 0x00000008 // Silent Mode
#define CAN_TST_BASIC 0x00000004 // Basic Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_BRPE register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
#define CAN_BRPE_BRPE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
//
//*****************************************************************************
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32
#define CAN_IF1CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
//
//*****************************************************************************
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
//
//*****************************************************************************
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
#define CAN_IF1MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
//
//*****************************************************************************
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
#define CAN_IF1MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
//
//*****************************************************************************
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
#define CAN_IF1ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
//
//*****************************************************************************
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
#define CAN_IF1ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
//
//*****************************************************************************
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF1MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
//
//*****************************************************************************
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
//
//*****************************************************************************
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
#define CAN_IF1DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
//
//*****************************************************************************
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
#define CAN_IF1DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
//
//*****************************************************************************
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
#define CAN_IF1DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
//
//*****************************************************************************
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
// it is interpreted as 0x20, or
// object 32
#define CAN_IF2CRQ_MNUM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
//
//*****************************************************************************
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
//
//*****************************************************************************
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
#define CAN_IF2MSK1_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
//
//*****************************************************************************
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
#define CAN_IF2MSK2_IDMSK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
//
//*****************************************************************************
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
#define CAN_IF2ARB1_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
//
//*****************************************************************************
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
#define CAN_IF2ARB2_ID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
//
//*****************************************************************************
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
#define CAN_IF2MCTL_DLC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
//
//*****************************************************************************
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
#define CAN_IF2DA1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
//
//*****************************************************************************
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
#define CAN_IF2DA2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
//
//*****************************************************************************
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
#define CAN_IF2DB1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
//
//*****************************************************************************
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
#define CAN_IF2DB2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ1_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
#define CAN_TXRQ2_TXRQST_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA1 register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA1_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_NWDA2 register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
#define CAN_NWDA2_NEWDAT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1INT register.
//
//*****************************************************************************
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG1INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2INT register.
//
//*****************************************************************************
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
#define CAN_MSG2INT_INTPND_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
//
//*****************************************************************************
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG1VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
//
//*****************************************************************************
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
#define CAN_MSG2VAL_MSGVAL_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the CAN register offsets.
//
//*****************************************************************************
#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg
#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg
#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg
#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_STS
// register.
//
//*****************************************************************************
#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_ERR
// register.
//
//*****************************************************************************
#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_BIT
// register.
//
//*****************************************************************************
#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_INT
// register.
//
//*****************************************************************************
#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_TST
// register.
//
//*****************************************************************************
#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_BRPE
// register.
//
//*****************************************************************************
#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_TXRQ1
// register.
//
//*****************************************************************************
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_TXRQ2
// register.
//
//*****************************************************************************
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_NWDA1
// register.
//
//*****************************************************************************
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_NWDA2
// register.
//
//*****************************************************************************
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_MSGINT1
// register.
//
//*****************************************************************************
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_MSGINT2
// register.
//
//*****************************************************************************
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1
// register.
//
//*****************************************************************************
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2
// register.
//
//*****************************************************************************
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the can
// registers.
//
//*****************************************************************************
#define CAN_RV_IF1MSK2 0x0000FFFF
#define CAN_RV_IF1MSK1 0x0000FFFF
#define CAN_RV_IF2MSK1 0x0000FFFF
#define CAN_RV_IF2MSK2 0x0000FFFF
#define CAN_RV_BIT 0x00002301
#define CAN_RV_CTL 0x00000001
#define CAN_RV_IF1CRQ 0x00000001
#define CAN_RV_IF2CRQ 0x00000001
#define CAN_RV_TXRQ2 0x00000000
#define CAN_RV_IF2DB1 0x00000000
#define CAN_RV_INT 0x00000000
#define CAN_RV_IF1DB2 0x00000000
#define CAN_RV_BRPE 0x00000000
#define CAN_RV_IF2DA2 0x00000000
#define CAN_RV_MSGVAL2 0x00000000
#define CAN_RV_TXRQ1 0x00000000
#define CAN_RV_IF1MCTL 0x00000000
#define CAN_RV_IF1DB1 0x00000000
#define CAN_RV_STS 0x00000000
#define CAN_RV_MSGINT1 0x00000000
#define CAN_RV_IF1DA2 0x00000000
#define CAN_RV_TST 0x00000000
#define CAN_RV_IF1ARB1 0x00000000
#define CAN_RV_IF1ARB2 0x00000000
#define CAN_RV_NWDA2 0x00000000
#define CAN_RV_IF2CMSK 0x00000000
#define CAN_RV_NWDA1 0x00000000
#define CAN_RV_IF1DA1 0x00000000
#define CAN_RV_IF2DA1 0x00000000
#define CAN_RV_IF2MCTL 0x00000000
#define CAN_RV_MSGVAL1 0x00000000
#define CAN_RV_IF1CMSK 0x00000000
#define CAN_RV_ERR 0x00000000
#define CAN_RV_IF2ARB2 0x00000000
#define CAN_RV_MSGINT2 0x00000000
#define CAN_RV_IF2ARB1 0x00000000
#define CAN_RV_IF2DB2 0x00000000
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
// and CAN_IF1CRQ registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
// and CAN_IF2CMSK registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
// and CAN_IF2MSK1 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
// and CAN_IF2MSK2 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
// and CAN_IF2ARB1 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFARB1_ID 0x0000FFFF // Identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
// and CAN_IF2ARB2 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
#define CAN_IFARB2_DIR 0x00002000 // Message direction
#define CAN_IFARB2_ID 0x00001FFF // Message identifier
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
// and CAN_IF2MCTL registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
#define CAN_IFMCTL_DLC 0x0000000F // Data length code
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA1
// and CAN_IF2DA1 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DA2
// and CAN_IF2DA2 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB1
// and CAN_IF2DB1 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the CAN_IF1DB2
// and CAN_IF2DB2 registers.
// Note: All bits may not be available in all registers.
//
//*****************************************************************************
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
#endif
#endif // __HW_CAN_H__

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bsp/lm4f232/Libraries/inc/hw_comp.h Normal file
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@ -0,0 +1,291 @@
//*****************************************************************************
//
// hw_comp.h - Macros used when accessing the comparator hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_COMP_H__
#define __HW_COMP_H__
//*****************************************************************************
//
// The following are defines for the Comparator register offsets.
//
//*****************************************************************************
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
// Interrupt Status
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
// Status
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
// Enable
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
// Voltage Control
#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
// Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACMIS register.
//
//*****************************************************************************
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
// Status
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
// Status
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACRIS register.
//
//*****************************************************************************
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACINTEN register.
//
//*****************************************************************************
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACREFCTL
// register.
//
//*****************************************************************************
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
#define COMP_ACREFCTL_VREF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
//
//*****************************************************************************
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
//
//*****************************************************************************
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
// (VIREF)
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
//
//*****************************************************************************
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
//
//*****************************************************************************
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
// (VIREF)
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
//
//*****************************************************************************
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
//
//*****************************************************************************
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
// (VIREF)
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
//*****************************************************************************
//
// The following are defines for the bit fields in the COMP_O_PP register.
//
//*****************************************************************************
#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Comparator register offsets.
//
//*****************************************************************************
#define COMP_O_MIS 0x00000000 // Interrupt status register
#define COMP_O_RIS 0x00000004 // Raw interrupt status register
#define COMP_O_INTEN 0x00000008 // Interrupt enable register
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_O_REFCTL
// register.
//
//*****************************************************************************
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
#define COMP_REFCTL_VREF_SHIFT 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_MIS,
// COMP_RIS, and COMP_INTEN registers.
//
//*****************************************************************************
#define COMP_INT_2 0x00000004 // Comp2 interrupt
#define COMP_INT_1 0x00000002 // Comp1 interrupt
#define COMP_INT_0 0x00000001 // Comp0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
//
//*****************************************************************************
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
// COMP_ACCTL1, and COMP_ACCTL2 registers.
//
//*****************************************************************************
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the comparator
// registers.
//
//*****************************************************************************
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
#define COMP_RV_MIS 0x00000000 // Interrupt status register
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg
#endif
#endif // __HW_COMP_H__

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//*****************************************************************************
//
// hw_eeprom.h - Macros used when accessing the EEPROM controller.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EEPROM_H__
#define __HW_EEPROM_H__
//*****************************************************************************
//
// The following are defines for the EEPROM register offsets.
//
//*****************************************************************************
#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
// Status
#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
#define EEPROM_EEPROMPP 0x400AFFC0 // EEPROM
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESIZE register.
//
//*****************************************************************************
#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
#define EEPROM_EESIZE_WORDCNT_S 0
#define EEPROM_EESIZE_BLKCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
//
//*****************************************************************************
#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
#define EEPROM_EEBLOCK_BLOCK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEOFFSET
// register.
//
//*****************************************************************************
#define EEPROM_EEOFFSET_OFFSET_M \
0x0000000F // Current Address Offset
#define EEPROM_EEOFFSET_OFFSET_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWR register.
//
//*****************************************************************************
#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
#define EEPROM_EERDWR_VALUE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EERDWRINC
// register.
//
//*****************************************************************************
#define EEPROM_EERDWRINC_VALUE_M \
0xFFFFFFFF // EEPROM Read or Write Data with
// Increment
#define EEPROM_EERDWRINC_VALUE_S \
0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDONE register.
//
//*****************************************************************************
#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EESUPP register.
//
//*****************************************************************************
#define EEPROM_EESUPP_START 0x00000001 // Start Erase
#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEUNLOCK
// register.
//
//*****************************************************************************
#define EEPROM_EEUNLOCK_UNLOCK_M \
0xFFFFFFFF // EEPROM Unlock
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPROT register.
//
//*****************************************************************************
#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
#define EEPROM_EEPROT_PROT_RWNPW \
0x00000000 // This setting is the default. If
// there is no password, the block
// is not protected and is readable
// and writable
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
// block is readable or writable
// only when unlocked
#define EEPROM_EEPROT_PROT_RONPW \
0x00000002 // If there is no password, the
// block is readable, not writable
#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
//
//*****************************************************************************
#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS0_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
//
//*****************************************************************************
#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS1_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
//
//*****************************************************************************
#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
#define EEPROM_EEPASS2_PASS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEINT register.
//
//*****************************************************************************
#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEHIDE register.
//
//*****************************************************************************
#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEDBGME register.
//
//*****************************************************************************
#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
#define EEPROM_EEDBGME_KEY_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EEPROM_EEPROMPP
// register.
//
//*****************************************************************************
#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size
#define EEPROM_EEPROMPP_SIZE_S 0
#endif // __HW_EEPROM_H__

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//*****************************************************************************
//
// hw_epi.h - Macros for use in accessing the EPI registers.
//
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_EPI_H__
#define __HW_EPI_H__
//*****************************************************************************
//
// The following are defines for the External Peripheral Interface register
// offsets.
//
//*****************************************************************************
#define EPI_O_CFG 0x00000000 // EPI Configuration
#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
// Configuration
#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
// Configuration 2
#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
#define EPI_O_STAT 0x00000060 // EPI Status
#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_CFG register.
//
//*****************************************************************************
#define EPI_CFG_BLKEN 0x00000010 // Block Enable
#define EPI_CFG_MODE_M 0x0000000F // Mode Select
#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_BAUD register.
//
//*****************************************************************************
#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
#define EPI_BAUD_COUNT1_S 16
#define EPI_BAUD_COUNT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG register.
//
//*****************************************************************************
#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
#define EPI_HB16CFG_WRWS_M 0x000000C0 // CS0n Write Wait States
#define EPI_HB16CFG_WRWS_0 0x00000000 // No wait states
#define EPI_HB16CFG_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB16CFG_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB16CFG_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB16CFG_RDWS_M 0x00000030 // CS0n Read Wait States
#define EPI_HB16CFG_RDWS_0 0x00000000 // No wait states
#define EPI_HB16CFG_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB16CFG_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB16CFG_RDWS_3 0x00000030 // 3 wait states
#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
#define EPI_HB16CFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_GPCFG register.
//
//*****************************************************************************
#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable
#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin
#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
#define EPI_GPCFG_RW 0x00200000 // Read and Write
#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads
#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
// cannot be used with 24-bit data
#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
// cannot be used with data sizes
// other than 8
#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
#define EPI_GPCFG_FRMCNT_S 22
#define EPI_GPCFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
//
//*****************************************************************************
#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range
#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50 - 100 MHz
#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
#define EPI_SDRAMCFG_RFSH_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG register.
//
//*****************************************************************************
#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
#define EPI_HB8CFG_WRHIGH 0x00200000 // CS0n WRITE Strobe Polarity
#define EPI_HB8CFG_RDHIGH 0x00100000 // CS0n READ Strobe Polarity
#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
#define EPI_HB8CFG_MAXWAIT_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
//
//*****************************************************************************
#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode
#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states
#define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states
#define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
//
//*****************************************************************************
#define EPI_HB16CFG2_WORD 0x80000000 // Word Access Mode
#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
#define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states
#define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state
#define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states
#define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states
#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
#define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states
#define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state
#define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states
#define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
//
//*****************************************************************************
#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
//
//*****************************************************************************
#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
// 0x00 to 0xFF
#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
// 0x0000 to 0xFFFF
#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
// 0x00.0000 to 0xFF.FFFF
#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range:
// 0x000.0000 to 0xFFF.FFFF
#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
// 0x00 to 0xFF
#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
// 0x0000 to 0xFFFF
#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
// 0x00.0000 to 0xFF.FFFF
#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range:
// 0x000.0000 to 0xFFF.FFFF
#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
//
//*****************************************************************************
#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR0 register.
//
//*****************************************************************************
#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address
#define EPI_RADDR0_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
//
//*****************************************************************************
#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
#define EPI_RPSTD0_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
//
//*****************************************************************************
#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RADDR1 register.
//
//*****************************************************************************
#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address
#define EPI_RADDR1_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
//
//*****************************************************************************
#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
#define EPI_RPSTD1_POSTCNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_STAT register.
//
//*****************************************************************************
#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low
#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
#define EPI_STAT_WBUSY 0x00000020 // Write Busy
#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
#define EPI_STAT_ACTIVE 0x00000001 // Register Active
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
//
//*****************************************************************************
#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count
#define EPI_RFIFOCNT_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO register.
//
//*****************************************************************************
#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO1
// register.
//
//*****************************************************************************
#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO2
// register.
//
//*****************************************************************************
#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO3
// register.
//
//*****************************************************************************
#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO4
// register.
//
//*****************************************************************************
#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO4_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO5
// register.
//
//*****************************************************************************
#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO5_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO6
// register.
//
//*****************************************************************************
#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO6_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_READFIFO7
// register.
//
//*****************************************************************************
#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
#define EPI_READFIFO7_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
//
//*****************************************************************************
#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are 1 to 4
// spaces available in the WFIFO
#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are 1 to 3
// spaces available in the WFIFO
#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are 1 to 2
// spaces available in the WFIFO
#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
// available in the WFIFO
#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
// entries in the NBRFIFO
#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
// in the NBRFIFO
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
//
//*****************************************************************************
#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
#define EPI_WFIFOCNT_WTAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_IM register.
//
//*****************************************************************************
#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask
#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask
#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_RIS register.
//
//*****************************************************************************
#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_MIS register.
//
//*****************************************************************************
#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the EPI_O_EISC register.
//
//*****************************************************************************
#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
#define EPI_EISC_TOUT 0x00000001 // Timeout Error
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the EPI_O_BAUD
// register.
//
//*****************************************************************************
#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter
#define EPI_BAUD_COUNT_S 0
#endif
#endif // __HW_EPI_H__

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bsp/lm4f232/Libraries/inc/hw_ethernet.h Normal file
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//*****************************************************************************
//
// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
//
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_ETHERNET_H__
#define __HW_ETHERNET_H__
//*****************************************************************************
//
// The following are defines for the Ethernet MAC register offsets.
//
//*****************************************************************************
#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
// Status/Acknowledge
#define MAC_O_IACK 0x00000000 // Ethernet MAC Raw Interrupt
// Status/Acknowledge
#define MAC_O_IM 0x00000004 // Ethernet MAC Interrupt Mask
#define MAC_O_RCTL 0x00000008 // Ethernet MAC Receive Control
#define MAC_O_TCTL 0x0000000C // Ethernet MAC Transmit Control
#define MAC_O_DATA 0x00000010 // Ethernet MAC Data
#define MAC_O_IA0 0x00000014 // Ethernet MAC Individual Address
// 0
#define MAC_O_IA1 0x00000018 // Ethernet MAC Individual Address
// 1
#define MAC_O_THR 0x0000001C // Ethernet MAC Threshold
#define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control
#define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider
#define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address
#define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit
// Data
#define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive
// Data
#define MAC_O_NP 0x00000034 // Ethernet MAC Number of Packets
#define MAC_O_TR 0x00000038 // Ethernet MAC Transmission
// Request
#define MAC_O_TS 0x0000003C // Ethernet MAC Timer Support
#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
#define MAC_O_MDIX 0x00000044 // Ethernet PHY MDIX
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_RIS register.
//
//*****************************************************************************
#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt
#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete
#define MAC_RIS_RXER 0x00000010 // Receive Error
#define MAC_RIS_FOV 0x00000008 // FIFO Overrun
#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty
#define MAC_RIS_TXER 0x00000002 // Transmit Error
#define MAC_RIS_RXINT 0x00000001 // Packet Received
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_IACK register.
//
//*****************************************************************************
#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete
#define MAC_IACK_RXER 0x00000010 // Clear Receive Error
#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun
#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty
#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error
#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_IM register.
//
//*****************************************************************************
#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete
#define MAC_IM_RXERM 0x00000010 // Mask Receive Error
#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun
#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty
#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error
#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_RCTL register.
//
//*****************************************************************************
#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO
#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC
#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames
#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_TCTL register.
//
//*****************************************************************************
#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode
#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding
#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_DATA register.
//
//*****************************************************************************
#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data
#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data
#define MAC_DATA_RXDATA_S 0
#define MAC_DATA_TXDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_IA0 register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4
#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3
#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2
#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1
#define MAC_IA0_MACOCT4_S 24
#define MAC_IA0_MACOCT3_S 16
#define MAC_IA0_MACOCT2_S 8
#define MAC_IA0_MACOCT1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_IA1 register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6
#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5
#define MAC_IA1_MACOCT6_S 8
#define MAC_IA1_MACOCT5_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_THR register.
//
//*****************************************************************************
#define MAC_THR_THRESH_M 0x0000003F // Threshold Value
#define MAC_THR_THRESH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MCTL register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address
#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type
#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable
#define MAC_MCTL_REGADR_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MDV register.
//
//*****************************************************************************
#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
#define MAC_MDV_DIV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MADD register.
//
//*****************************************************************************
#define MAC_MADD_PHYADR_M 0x0000001F // PHY Address
#define MAC_MADD_PHYADR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MTXD register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data
#define MAC_MTXD_MDTX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MRXD register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data
#define MAC_MRXD_MDRX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_NP register.
//
//*****************************************************************************
#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
// FIFO
#define MAC_NP_NPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_TR register.
//
//*****************************************************************************
#define MAC_TR_NEWTX 0x00000001 // New Transmission
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_TS register.
//
//*****************************************************************************
#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_LED register.
//
//*****************************************************************************
#define MAC_LED_LED1_M 0x00000F00 // LED1 Source
#define MAC_LED_LED1_LINK 0x00000000 // Link OK
#define MAC_LED_LED1_RXTX 0x00000100 // RX or TX Activity (Default LED1)
#define MAC_LED_LED1_100 0x00000500 // 100BASE-TX mode
#define MAC_LED_LED1_10 0x00000600 // 10BASE-T mode
#define MAC_LED_LED1_DUPLEX 0x00000700 // Full-Duplex
#define MAC_LED_LED1_LINKACT 0x00000800 // Link OK & Blink=RX or TX
// Activity
#define MAC_LED_LED0_M 0x0000000F // LED0 Source
#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_MDIX register.
//
//*****************************************************************************
#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable
//*****************************************************************************
//
// The following are defines for the Ethernet Controller PHY registers.
//
//*****************************************************************************
#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
// 0 - Control
#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
// 1 - Status
#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
// 2 - PHY Identifier 1
#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
// 3 - PHY Identifier 2
#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
// 4 - Auto-Negotiation
// Advertisement
#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
// 5 - Auto-Negotiation Link
// Partner Base Page Ability
#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
// 6 - Auto-Negotiation Expansion
#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
// 16 - Vendor-Specific
#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
// 17 - Mode Control/Status
#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
// 18 - Diagnostic
#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
// 19 - Transceiver Control
#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
// 23 - LED Configuration
#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
// 24 -MDI/MDIX Control
#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
// 27 - Special Control/Status
#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
// 29 - Interrupt Status
#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
// 30 - Interrupt Mask
#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
// 31 - PHY Special Control/Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR0 register.
//
//*****************************************************************************
#define PHY_MR0_RESET 0x00008000 // Reset Registers
#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
#define PHY_MR0_PWRDN 0x00000800 // Power Down
#define PHY_MR0_ISO 0x00000400 // Isolate
#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
#define PHY_MR0_COLT 0x00000080 // Collision Test
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR1 register.
//
//*****************************************************************************
#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
// Suppressed
#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
#define PHY_MR1_LINK 0x00000004 // Link Made
#define PHY_MR1_JAB 0x00000002 // Jabber Condition
#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR2 register.
//
//*****************************************************************************
#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
// Identifier[21:6]
#define PHY_MR2_OUI_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR3 register.
//
//*****************************************************************************
#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
// Identifier[5:0]
#define PHY_MR3_MN_M 0x000003F0 // Model Number
#define PHY_MR3_RN_M 0x0000000F // Revision Number
#define PHY_MR3_OUI_S 10
#define PHY_MR3_MN_S 4
#define PHY_MR3_RN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR4 register.
//
//*****************************************************************************
#define PHY_MR4_NP 0x00008000 // Next Page
#define PHY_MR4_RF 0x00002000 // Remote Fault
#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3]
#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2]
#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1]
#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0]
#define PHY_MR4_S_M 0x0000001F // Selector Field
#define PHY_MR4_S_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR5 register.
//
//*****************************************************************************
#define PHY_MR5_NP 0x00008000 // Next Page
#define PHY_MR5_ACK 0x00004000 // Acknowledge
#define PHY_MR5_RF 0x00002000 // Remote Fault
#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
#define PHY_MR5_S_M 0x0000001F // Selector Field
#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
#define PHY_MR5_A_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR6 register.
//
//*****************************************************************************
#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
#define PHY_MR6_PRX 0x00000002 // New Page Received
#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
// Able
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR16 register.
//
//*****************************************************************************
#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
#define PHY_MR16_SR_S 6
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR17 register.
//
//*****************************************************************************
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
// Interrupt Enable
#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
// Enable
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
// Interrupt Enable
#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
// Interrupt
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
#define PHY_MR17_ENON 0x00000002 // Energy On
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR18 register.
//
//*****************************************************************************
#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
#define PHY_MR18_RATE 0x00000400 // Rate
#define PHY_MR18_RXSD 0x00000200 // Receive Detection
#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR19 register.
//
//*****************************************************************************
#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
// loss
#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
// loss
#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
// loss
#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
// loss
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR23 register.
//
//*****************************************************************************
#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source
#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
// Activity
#define PHY_MR23_LED0_M 0x0000000F // LED0 Source
#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR24 register.
//
//*****************************************************************************
#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode
#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable
#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration
#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete
#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed
#define PHY_MR24_MDIX_SD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR27 register.
//
//*****************************************************************************
#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR29 register.
//
//*****************************************************************************
#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt
#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
// Interrupt
#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt
#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt
#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge
#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault
#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR30 register.
//
//*****************************************************************************
#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled
#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
// Interrupt Enabled
#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled
#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled
#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
// Enabled
#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault Enabled
#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
// Enabled
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR31 register.
//
//*****************************************************************************
#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done
#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value
#define PHY_MR31_SPEED_10HD 0x00000004 // 10BASE-T half duplex
#define PHY_MR31_SPEED_100HD 0x00000008 // 100BASE-T half duplex
#define PHY_MR31_SPEED_10FD 0x00000014 // 10BASE-T full duplex
#define PHY_MR31_SPEED_100FD 0x00000018 // 100BASE-T full duplex
#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Ethernet MAC register offsets.
//
//*****************************************************************************
#define MAC_O_IS 0x00000000 // Interrupt Status Register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_IS
// register.
//
//*****************************************************************************
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
#define MAC_IS_RXER 0x00000010 // RX Error
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
#define MAC_IS_TXER 0x00000002 // TX Error
#define MAC_IS_RXINT 0x00000001 // RX Packet Available
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_IA0
// register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_IA1
// register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_THR
// register.
//
//*****************************************************************************
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_MCTL
// register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_MDV
// register.
//
//*****************************************************************************
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_MTXD
// register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_MRXD
// register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_O_NP
// register.
//
//*****************************************************************************
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PHY_MR23
// register.
//
//*****************************************************************************
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
#define PHY_MR23_LED1_COL 0x00000040 // Collision
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
#define PHY_MR23_LED0_COL 0x00000004 // Collision
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the MAC
// registers.
//
//*****************************************************************************
#define MAC_RV_MDV 0x00000080
#define MAC_RV_IM 0x0000007F
#define MAC_RV_THR 0x0000003F
#define MAC_RV_RCTL 0x00000008
#define MAC_RV_IA0 0x00000000
#define MAC_RV_TCTL 0x00000000
#define MAC_RV_DATA 0x00000000
#define MAC_RV_MRXD 0x00000000
#define MAC_RV_TR 0x00000000
#define MAC_RV_IS 0x00000000
#define MAC_RV_NP 0x00000000
#define MAC_RV_MCTL 0x00000000
#define MAC_RV_MTXD 0x00000000
#define MAC_RV_IA1 0x00000000
#define MAC_RV_IACK 0x00000000
#define MAC_RV_MADD 0x00000000
#endif
#endif // __HW_ETHERNET_H__

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//*****************************************************************************
//
// hw_fan.h - Macros used when accessing the fan control hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_FAN_H__
#define __HW_FAN_H__
//*****************************************************************************
//
// The following are defines for the Fan Control register offsets.
//
//*****************************************************************************
#define FAN_O_STS 0x00000000 // FAN Status
#define FAN_O_CTL 0x00000004 // FAN Control
#define FAN_O_CH0 0x00000010 // FAN Channel Command
#define FAN_O_CMD0 0x00000014 // FAN Channel Command
#define FAN_O_CST0 0x00000018 // FAN Channel Status
#define FAN_O_CH1 0x00000020 // FAN Channel Setup
#define FAN_O_CMD1 0x00000024 // FAN Channel Command
#define FAN_O_CST1 0x00000028 // FAN Channel Status
#define FAN_O_CH2 0x00000030 // FAN Channel Setup
#define FAN_O_CMD2 0x00000034 // FAN Channel Command
#define FAN_O_CST2 0x00000038 // FAN Channel Status
#define FAN_O_CH3 0x00000040 // FAN Channel Setup
#define FAN_O_CMD3 0x00000044 // FAN Channel Command
#define FAN_O_CST3 0x00000048 // FAN Channel Status
#define FAN_O_CH4 0x00000050 // FAN Channel Setup
#define FAN_O_CMD4 0x00000054 // FAN Channel Command
#define FAN_O_CST4 0x00000058 // FAN Channel Status
#define FAN_O_CH5 0x00000060 // FAN Channel Setup
#define FAN_O_CMD5 0x00000064 // FAN Channel Command
#define FAN_O_CST5 0x00000068 // FAN Channel Status
#define FAN_O_CH6 0x00000070 // FAN Channel Setup
#define FAN_O_CMD6 0x00000074 // FAN Channel Command
#define FAN_O_CST6 0x00000078 // FAN Channel Status
#define FAN_O_CH7 0x00000080 // FAN Channel Setup
#define FAN_O_CMD7 0x00000084 // FAN Channel Command
#define FAN_O_CST7 0x00000088 // FAN Channel Status
#define FAN_O_IM 0x00000090 // FAN Interrupt Mask
#define FAN_O_RIS 0x00000094 // FAN Raw Interrupt Status
#define FAN_O_MIS 0x00000098 // FAN Masked Interrupt Status
#define FAN_O_IC 0x0000009C // FAN Interrupt Clear
#define FAN_O_PP 0x00000FC0 // FAN Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_STS register.
//
//*****************************************************************************
#define FAN_STS_FANCNT_M 0x000F0000 // Fan Count
#define FAN_STS_ST5_M 0x00000C00 // Fan 5 Status
#define FAN_STS_ST5_STALLED 0x00000000 // Stalled
#define FAN_STS_ST5_CHANGING 0x00000400 // Changing
#define FAN_STS_ST5_LOCKED 0x00000800 // Locked
#define FAN_STS_ST5_UNBALANCED 0x00000C00 // Unbalanced Spin
#define FAN_STS_ST4_M 0x00000300 // Fan 4 Status
#define FAN_STS_ST3_M 0x000000C0 // Fan 3 Status
#define FAN_STS_ST2_M 0x00000030 // Fan 2 Status
#define FAN_STS_ST1_M 0x0000000C // Fan 1 Status
#define FAN_STS_ST0_M 0x00000003 // Fan 0 Status
#define FAN_STS_FANCNT_S 16
#define FAN_STS_ST4_S 8
#define FAN_STS_ST3_S 6
#define FAN_STS_ST2_S 4
#define FAN_STS_ST1_S 2
#define FAN_STS_ST0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CTL register.
//
//*****************************************************************************
#define FAN_CTL_E5 0x00000020 // Fan 5 Enable
#define FAN_CTL_E4 0x00000010 // Fan 4 Enable
#define FAN_CTL_E3 0x00000008 // Fan 3 Enable
#define FAN_CTL_E2 0x00000004 // Fan 2 Enable
#define FAN_CTL_E1 0x00000002 // Fan 1 Enable
#define FAN_CTL_E0 0x00000001 // Fan 0 Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH0 register.
//
//*****************************************************************************
#define FAN_CH0_ASTART 0x00008000 // Auto Restart
#define FAN_CH0_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH0_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH0_STPER_M 0x00000700 // Start Period
#define FAN_CH0_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH0_START_NOFAST 0x00000000 // No fast start
#define FAN_CH0_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH0_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH0_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH0_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH0_AVG_0 0x00000000 // No averaging
#define FAN_CH0_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH0_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH0_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH0_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH0_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH0_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH0_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH0_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH0_MAN 0x00000001 // Control Type
#define FAN_CH0_HYST_S 11
#define FAN_CH0_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD0 register.
//
//*****************************************************************************
#define FAN_CMD0_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD0_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD0_DC_S 16
#define FAN_CMD0_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST0 register.
//
//*****************************************************************************
#define FAN_CST0_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST0_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST0_COUNT_S 16
#define FAN_CST0_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH1 register.
//
//*****************************************************************************
#define FAN_CH1_ASTART 0x00008000 // Auto Restart
#define FAN_CH1_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH1_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH1_STPER_M 0x00000700 // Start Period
#define FAN_CH1_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH1_START_NOFAST 0x00000000 // No fast start
#define FAN_CH1_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH1_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH1_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH1_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH1_AVG_0 0x00000000 // No averaging
#define FAN_CH1_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH1_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH1_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH1_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH1_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH1_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH1_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH1_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH1_MAN 0x00000001 // Control Type
#define FAN_CH1_HYST_S 11
#define FAN_CH1_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD1 register.
//
//*****************************************************************************
#define FAN_CMD1_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD1_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD1_DC_S 16
#define FAN_CMD1_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST1 register.
//
//*****************************************************************************
#define FAN_CST1_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST1_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST1_COUNT_S 16
#define FAN_CST1_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH2 register.
//
//*****************************************************************************
#define FAN_CH2_ASTART 0x00008000 // Auto Restart
#define FAN_CH2_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH2_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH2_STPER_M 0x00000700 // Start Period
#define FAN_CH2_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH2_START_NOFAST 0x00000000 // No fast start
#define FAN_CH2_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH2_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH2_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH2_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH2_AVG_0 0x00000000 // No averaging
#define FAN_CH2_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH2_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH2_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH2_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH2_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH2_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH2_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH2_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH2_MAN 0x00000001 // Control Type
#define FAN_CH2_HYST_S 11
#define FAN_CH2_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD2 register.
//
//*****************************************************************************
#define FAN_CMD2_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD2_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD2_DC_S 16
#define FAN_CMD2_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST2 register.
//
//*****************************************************************************
#define FAN_CST2_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST2_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST2_COUNT_S 16
#define FAN_CST2_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH3 register.
//
//*****************************************************************************
#define FAN_CH3_ASTART 0x00008000 // Auto Restart
#define FAN_CH3_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH3_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH3_STPER_M 0x00000700 // Start Period
#define FAN_CH3_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH3_START_NOFAST 0x00000000 // No fast start
#define FAN_CH3_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH3_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH3_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH3_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH3_AVG_0 0x00000000 // No averaging
#define FAN_CH3_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH3_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH3_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH3_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH3_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH3_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH3_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH3_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH3_MAN 0x00000001 // Control Type
#define FAN_CH3_HYST_S 11
#define FAN_CH3_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD3 register.
//
//*****************************************************************************
#define FAN_CMD3_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD3_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD3_DC_S 16
#define FAN_CMD3_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST3 register.
//
//*****************************************************************************
#define FAN_CST3_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST3_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST3_COUNT_S 16
#define FAN_CST3_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH4 register.
//
//*****************************************************************************
#define FAN_CH4_ASTART 0x00008000 // Auto Restart
#define FAN_CH4_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH4_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH4_STPER_M 0x00000700 // Start Period
#define FAN_CH4_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH4_START_NOFAST 0x00000000 // No fast start
#define FAN_CH4_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH4_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH4_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH4_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH4_AVG_0 0x00000000 // No averaging
#define FAN_CH4_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH4_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH4_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH4_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH4_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH4_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH4_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH4_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH4_MAN 0x00000001 // Control Type
#define FAN_CH4_HYST_S 11
#define FAN_CH4_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD4 register.
//
//*****************************************************************************
#define FAN_CMD4_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD4_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD4_DC_S 16
#define FAN_CMD4_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST4 register.
//
//*****************************************************************************
#define FAN_CST4_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST4_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST4_COUNT_S 16
#define FAN_CST4_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH5 register.
//
//*****************************************************************************
#define FAN_CH5_ASTART 0x00008000 // Auto Restart
#define FAN_CH5_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH5_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH5_STPER_M 0x00000700 // Start Period
#define FAN_CH5_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH5_START_NOFAST 0x00000000 // No fast start
#define FAN_CH5_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH5_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH5_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH5_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH5_AVG_0 0x00000000 // No averaging
#define FAN_CH5_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH5_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH5_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH5_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH5_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH5_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH5_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH5_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH5_MAN 0x00000001 // Control Type
#define FAN_CH5_HYST_S 11
#define FAN_CH5_STPER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD5 register.
//
//*****************************************************************************
#define FAN_CMD5_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD5_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD5_DC_S 16
#define FAN_CMD5_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST5 register.
//
//*****************************************************************************
#define FAN_CST5_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST5_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST5_COUNT_S 16
#define FAN_CST5_RPM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH6 register.
//
//*****************************************************************************
#define FAN_CH6_MAN 0x00000001 // Control Type
#define FAN_CH6_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH6_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH6_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH6_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH6_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH6_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH6_AVG_0 0x00000000 // No averaging
#define FAN_CH6_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH6_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH6_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH6_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH6_START_NOFAST 0x00000000 // No fast start
#define FAN_CH6_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH6_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH6_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH6_STPER_M 0x00000700 // Start Period
#define FAN_CH6_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH6_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH6_ASTART 0x00008000 // Auto Restart
#define FAN_CH6_STPER_S 8
#define FAN_CH6_HYST_S 11
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD6 register.
//
//*****************************************************************************
#define FAN_CMD6_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD6_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD6_RPM_S 0
#define FAN_CMD6_DC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST6 register.
//
//*****************************************************************************
#define FAN_CST6_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST6_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST6_RPM_S 0
#define FAN_CST6_COUNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CH7 register.
//
//*****************************************************************************
#define FAN_CH7_MAN 0x00000001 // Control Type
#define FAN_CH7_PPR_M 0x0000000C // Pulse per Revolution on
// Tachometer
#define FAN_CH7_PPR_1 0x00000000 // 1 pulse per revolution
#define FAN_CH7_PPR_2 0x00000004 // 2 pulses per revolution
#define FAN_CH7_PPR_4 0x00000008 // 4 pulses per revolution
#define FAN_CH7_PPR_8 0x0000000C // 8 pulses per revolution
#define FAN_CH7_AVG_M 0x00000030 // Averaging of Tachometer
#define FAN_CH7_AVG_0 0x00000000 // No averaging
#define FAN_CH7_AVG_2 0x00000010 // Average 2 edges
#define FAN_CH7_AVG_4 0x00000020 // Average 4 edges
#define FAN_CH7_AVG_8 0x00000030 // Average 8 edges
#define FAN_CH7_START_M 0x000000C0 // Fast Start Rule
#define FAN_CH7_START_NOFAST 0x00000000 // No fast start
#define FAN_CH7_START_50DC 0x00000040 // 50% duty cycle
#define FAN_CH7_START_75DC 0x00000080 // 75% duty cycle
#define FAN_CH7_START_100DC 0x000000C0 // 100% duty cycle
#define FAN_CH7_STPER_M 0x00000700 // Start Period
#define FAN_CH7_HYST_M 0x00003800 // Hysteresis Adjustment on PID
// Adjust
#define FAN_CH7_ACCEL 0x00004000 // Acceleration and Deceleration
// Rule
#define FAN_CH7_ASTART 0x00008000 // Auto Restart
#define FAN_CH7_STPER_S 8
#define FAN_CH7_HYST_S 11
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CMD7 register.
//
//*****************************************************************************
#define FAN_CMD7_RPM_M 0x00001FFF // Fan Speed (in RPM)
#define FAN_CMD7_DC_M 0x01FF0000 // PWM Duty Cycle
#define FAN_CMD7_RPM_S 0
#define FAN_CMD7_DC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_CST7 register.
//
//*****************************************************************************
#define FAN_CST7_RPM_M 0x00001FFF // Last Read RPM Speed Computed
#define FAN_CST7_COUNT_M 0x07FF0000 // Last Read Tachometer Count
#define FAN_CST7_RPM_S 0
#define FAN_CST7_COUNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_IM register.
//
//*****************************************************************************
#define FAN_IM_C5INT1IM 0x00400000 // Channel 5 Interrupt 1 Mask
#define FAN_IM_C5INT0IM 0x00200000 // Channel 5 Interrupt 0 Mask
#define FAN_IM_C5STALLIM 0x00100000 // Channel 5 Stall Interrupt Mask
#define FAN_IM_C4INT1IM 0x00040000 // Channel 4 Interrupt 1 Mask
#define FAN_IM_C4INT0IM 0x00020000 // Channel 4 Interrupt 0 Mask
#define FAN_IM_C4STALLIM 0x00010000 // Channel 4 Stall Interrupt Mask
#define FAN_IM_C3INT1IM 0x00004000 // Channel 3 Interrupt 1 Mask
#define FAN_IM_C3INT0IM 0x00002000 // Channel 3 Interrupt 0 Mask
#define FAN_IM_C3STALLIM 0x00001000 // Channel 3 Stall Interrupt Mask
#define FAN_IM_C2INT1IM 0x00000400 // Channel 2 Interrupt 1 Mask
#define FAN_IM_C2INT0IM 0x00000200 // Channel 2 Interrupt 0 Mask
#define FAN_IM_C2STALLIM 0x00000100 // Channel 2 Stall Interrupt Mask
#define FAN_IM_C1INT1IM 0x00000040 // Channel 1 Interrupt 1 Mask
#define FAN_IM_C1INT0IM 0x00000020 // Channel 1 Interrupt 0 Mask
#define FAN_IM_C1STALLIM 0x00000010 // Channel 1 Stall Interrupt Mask
#define FAN_IM_C0INT1IM 0x00000004 // Channel 0 Interrupt 1 Mask
#define FAN_IM_C0INT0IM 0x00000002 // Channel 0 Interrupt 0 Mask
#define FAN_IM_C0STALLIM 0x00000001 // Channel 0 Stall Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_RIS register.
//
//*****************************************************************************
#define FAN_RIS_C5INT1RIS 0x00400000 // Channel 5 Raw Interrupt 1 Status
#define FAN_RIS_C5INT0RIS 0x00200000 // Channel 5 Raw Interrupt 0 Status
#define FAN_RIS_C5STALLRIS 0x00100000 // Channel 5 Raw Stall Interrupt
// Status
#define FAN_RIS_C4INT1RIS 0x00040000 // Channel 4 Raw Interrupt 1 Status
#define FAN_RIS_C4INT0RIS 0x00020000 // Channel 4 Raw Interrupt 0 Status
#define FAN_RIS_C4STALLRIS 0x00010000 // Channel 4 Raw Stall Interrupt
// Status
#define FAN_RIS_C3INT1RIS 0x00004000 // Channel 3 Raw Interrupt 1 Status
#define FAN_RIS_C3INT0RIS 0x00002000 // Channel 3 Raw Interrupt 0 Status
#define FAN_RIS_C3STALLRIS 0x00001000 // Channel 3 Raw Stall Interrupt
// Status
#define FAN_RIS_C2INT1RIS 0x00000400 // Channel 2 Raw Interrupt 1 Status
#define FAN_RIS_C2INT0RIS 0x00000200 // Channel 2 Raw Interrupt 0 Status
#define FAN_RIS_C2STALLRIS 0x00000100 // Channel 2 Raw Stall Interrupt
// Status
#define FAN_RIS_C1INT1RIS 0x00000040 // Channel 1 Raw Interrupt 1 Status
#define FAN_RIS_C1INT0RIS 0x00000020 // Channel 1 Raw Interrupt 0 Status
#define FAN_RIS_C1STALLRIS 0x00000010 // Channel 1 Raw Stall Interrupt
// Status
#define FAN_RIS_C0INT1RIS 0x00000004 // Channel 0 Raw Interrupt 1 Status
#define FAN_RIS_C0INT0RIS 0x00000002 // Channel 0 Raw Interrupt 0 Status
#define FAN_RIS_C0STALLRIS 0x00000001 // Channel 0 Raw Stall Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_MIS register.
//
//*****************************************************************************
#define FAN_MIS_C5INT1MIS 0x00400000 // Channel 5 Masked Interrupt 1
// Status
#define FAN_MIS_C5INT0MIS 0x00200000 // Channel 5 Masked Interrupt 0
// Status
#define FAN_MIS_C5STALLMIS 0x00100000 // Channel 5 Masked Stall Interrupt
// Status
#define FAN_MIS_C54NT1MIS 0x00040000 // Channel 4 Masked Interrupt 1
// Status
#define FAN_MIS_C4INT0MIS 0x00020000 // Channel 4 Masked Interrupt 0
// Status
#define FAN_MIS_C4STALLMIS 0x00010000 // Channel 4 Masked Stall Interrupt
// Status
#define FAN_MIS_C3INT1MIS 0x00004000 // Channel 3 Masked Interrupt 1
// Status
#define FAN_MIS_C3INT0MIS 0x00002000 // Channel 3 Masked Interrupt 0
// Status
#define FAN_MIS_C3STALLMIS 0x00001000 // Channel 3 Masked Stall Interrupt
// Status
#define FAN_MIS_C2INT1MIS 0x00000400 // Channel 2 Masked Interrupt 1
// Status
#define FAN_MIS_C2INT0MIS 0x00000200 // Channel 2 Masked Interrupt 0
// Status
#define FAN_MIS_C2STALLMIS 0x00000100 // Channel 2 Masked Stall Interrupt
// Status
#define FAN_MIS_C1INT1MIS 0x00000040 // Channel 1 Masked Interrupt 1
// Status
#define FAN_MIS_C1INT0MIS 0x00000020 // Channel 1 Masked Interrupt 0
// Status
#define FAN_MIS_C1STALLMIS 0x00000010 // Channel 1 Masked Stall Interrupt
// Status
#define FAN_MIS_C0INT1MIS 0x00000004 // Channel 0 Masked Interrupt 1
// Status
#define FAN_MIS_C0INT0MIS 0x00000002 // Channel 0 Masked Interrupt 0
// Status
#define FAN_MIS_C0STALLMIS 0x00000001 // Channel 0 Masked Stall Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_IC register.
//
//*****************************************************************************
#define FAN_IC_C5INT1IC 0x00400000 // Channel 5 Interrupt 1 Clear
#define FAN_IC_C5INT0IC 0x00200000 // Channel 5 Interrupt 0 Clear
#define FAN_IC_C5STALLIC 0x00100000 // Channel 5 Stall Interrupt Clear
#define FAN_IC_C4INT1IC 0x00040000 // Channel 4 Interrupt 1 Clear
#define FAN_IC_C4INT0IC 0x00020000 // Channel 4 Interrupt 0 Clear
#define FAN_IC_C4STALLIC 0x00010000 // Channel 4 Stall Interrupt Clear
#define FAN_IC_C3INT1IC 0x00004000 // Channel 3 Interrupt 1 Clear
#define FAN_IC_C53INT0IC 0x00002000 // Channel 3 Interrupt 0 Clear
#define FAN_IC_C3STALLIC 0x00001000 // Channel 3 Stall Interrupt Clear
#define FAN_IC_C2INT1IC 0x00000400 // Channel 2 Interrupt 1 Clear
#define FAN_IC_C2INT0IC 0x00000200 // Channel 2 Interrupt 0 Clear
#define FAN_IC_C2STALLIC 0x00000100 // Channel 2 Stall Interrupt Clear
#define FAN_IC_C1INT1IC 0x00000040 // Channel 1 Interrupt 1 Clear
#define FAN_IC_C1INT0IC 0x00000020 // Channel 1 Interrupt 0 Clear
#define FAN_IC_C1STALLIC 0x00000010 // Channel 1 Stall Interrupt Clear
#define FAN_IC_C0INT1IC 0x00000004 // Channel 0 Interrupt 1 Clear
#define FAN_IC_C0INT0IC 0x00000002 // Channel 0 Interrupt 0 Clear
#define FAN_IC_C0STALLIC 0x00000001 // Channel 0 Stall Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the FAN_O_PP register.
//
//*****************************************************************************
#define FAN_PP_CHAN_M 0x0000000F // Channel Count
#define FAN_PP_CHAN_S 0
#endif // __HW_FAN_H__

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bsp/lm4f232/Libraries/inc/hw_flash.h Normal file
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//*****************************************************************************
//
// hw_flash.h - Macros used when accessing the flash controller.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_FLASH_H__
#define __HW_FLASH_H__
//*****************************************************************************
//
// The following are defines for the FLASH register offsets.
//
//*****************************************************************************
#define FLASH_FMA 0x400FD000 // Flash Memory Address
#define FLASH_FMD 0x400FD004 // Flash Memory Data
#define FLASH_FMC 0x400FD008 // Flash Memory Control
#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
// Status
#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
// Interrupt Status and Clear
#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
#define FLASH_FCTL 0x400FD0F8 // Flash Control
#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
#define FLASH_FSIZE 0x400FDFC0 // Flash Size
#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
#define FLASH_RMCTL 0x400FE0F0 // ROM Control
#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
// Enable
#define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program
// Enable
#define FLASH_USECRL 0x400FE140 // USec Reload
#define FLASH_USERDBG 0x400FE1D0 // User Debug
#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
#define FLASH_USERREG0 0x400FE1E0 // User Register 0
#define FLASH_USERREG1 0x400FE1E4 // User Register 1
#define FLASH_USERREG2 0x400FE1E8 // User Register 2
#define FLASH_USERREG3 0x400FE1EC // User Register 3
#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
// Enable 0
#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
// Enable 1
#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
// Enable 2
#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
// Enable 3
#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
// Enable 4
#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
// Enable 5
#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
// Enable 6
#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
// Enable 7
#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
// Enable 0
#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
// Enable 1
#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
// Enable 2
#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
// Enable 3
#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
// Enable 4
#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
// Enable 5
#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
// Enable 6
#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
// Enable 7
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMA register.
//
//*****************************************************************************
#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
#define FLASH_FMA_OFFSET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMD register.
//
//*****************************************************************************
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
#define FLASH_FMD_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCRIS register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
// Status
#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCIM register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCMISC register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
// Clear
#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
// and Clear
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
// Status and Clear
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
// and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMC2 register.
//
//*****************************************************************************
#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBVAL register.
//
//*****************************************************************************
#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FCTL register.
//
//*****************************************************************************
#define FLASH_FCTL_USDACK 0x00000002 // User Shut Down Acknowledge
#define FLASH_FCTL_USDREQ 0x00000001 // User Shut Down Request
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FWBN register.
//
//*****************************************************************************
#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FSIZE register.
//
//*****************************************************************************
#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_SSIZE register.
//
//*****************************************************************************
#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
//
//*****************************************************************************
#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_RMCTL register.
//
//*****************************************************************************
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USECRL register.
//
//*****************************************************************************
#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value
#define FLASH_USECRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERDBG register.
//
//*****************************************************************************
#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written
#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data
#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1
#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0
#define FLASH_USERDBG_DATA_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_BOOTCFG register.
//
//*****************************************************************************
#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG0 register.
//
//*****************************************************************************
#define FLASH_USERREG0_NW 0x80000000 // Not Written
#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG0_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG1 register.
//
//*****************************************************************************
#define FLASH_USERREG1_NW 0x80000000 // Not Written
#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG1_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG2 register.
//
//*****************************************************************************
#define FLASH_USERREG2_NW 0x80000000 // Not Written
#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG2_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_USERREG3 register.
//
//*****************************************************************************
#define FLASH_USERREG3_NW 0x80000000 // Not Written
#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data
#define FLASH_USERREG3_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the FLASH_FMPRE and
// FLASH_FMPPE registers.
//
//*****************************************************************************
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
//*****************************************************************************
//
// The following are defines for the erase size of the FLASH block that is
// erased by an erase operation, and the protect size is the size of the FLASH
// block that is protected by each protection register.
//
//*****************************************************************************
#define FLASH_PROTECT_SIZE 0x00000800
#define FLASH_ERASE_SIZE 0x00000400
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the FLASH register offsets.
//
//*****************************************************************************
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FMC
// register.
//
//*****************************************************************************
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
#define FLASH_FMC_WRKEY_S 16
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FCRIS
// register.
//
//*****************************************************************************
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FCIM
// register.
//
//*****************************************************************************
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_FCMISC
// register.
//
//*****************************************************************************
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_RMVER
// register.
//
//*****************************************************************************
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
// DriverLib
#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
0x03000000 // Stellaris Boot Loader &
// DriverLib with AES and SAFERTOS
#define FLASH_RMVER_CONT_LM_AES2 \
0x05000000 // Stellaris Boot Loader &
// DriverLib with AES
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
#define FLASH_RMVER_VER_S 8
#define FLASH_RMVER_REV_S 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the FLASH_USECRL
// register.
//
//*****************************************************************************
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
#define FLASH_USECRL_SHIFT 0
#endif
#endif // __HW_FLASH_H__

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//*****************************************************************************
//
// hw_gpio.h - Defines and Macros for GPIO hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_GPIO_H__
#define __HW_GPIO_H__
//*****************************************************************************
//
// The following are defines for the GPIO register offsets.
//
//*****************************************************************************
#define GPIO_O_DATA 0x00000000 // GPIO Data
#define GPIO_O_DIR 0x00000400 // GPIO Direction
#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
#define GPIO_O_LOCK 0x00000520 // GPIO Lock
#define GPIO_O_CR 0x00000524 // GPIO Commit
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_LOCK register.
//
//*****************************************************************************
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
// and may be modified
#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
// and may not be modified
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
// DustDevil-class devices and
// later
//*****************************************************************************
//
// The following are defines for the bit fields in the GPIO_O_SI register.
//
//*****************************************************************************
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the GPIO register offsets.
//
//*****************************************************************************
#define GPIO_O_PeriphID4 0x00000FD0
#define GPIO_O_PeriphID5 0x00000FD4
#define GPIO_O_PeriphID6 0x00000FD8
#define GPIO_O_PeriphID7 0x00000FDC
#define GPIO_O_PeriphID0 0x00000FE0
#define GPIO_O_PeriphID1 0x00000FE4
#define GPIO_O_PeriphID2 0x00000FE8
#define GPIO_O_PeriphID3 0x00000FEC
#define GPIO_O_PCellID0 0x00000FF0
#define GPIO_O_PCellID1 0x00000FF4
#define GPIO_O_PCellID2 0x00000FF8
#define GPIO_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the GPIO Register reset values.
//
//*****************************************************************************
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
#define GPIO_RV_PCellID1 0x000000F0
#define GPIO_RV_PCellID3 0x000000B1
#define GPIO_RV_PeriphID0 0x00000061
#define GPIO_RV_PeriphID1 0x00000010
#define GPIO_RV_PCellID0 0x0000000D
#define GPIO_RV_PCellID2 0x00000005
#define GPIO_RV_PeriphID2 0x00000004
#define GPIO_RV_LOCK 0x00000001 // Lock register RV
#define GPIO_RV_PeriphID7 0x00000000
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
#define GPIO_RV_PeriphID4 0x00000000
#define GPIO_RV_PeriphID5 0x00000000
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
#define GPIO_RV_PeriphID6 0x00000000
#define GPIO_RV_PeriphID3 0x00000000
#define GPIO_RV_DATA 0x00000000 // Data register reset value
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
#endif
#endif // __HW_GPIO_H__

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//*****************************************************************************
//
// hw_hibernate.h - Defines and Macros for the Hibernation module.
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_HIBERNATE_H__
#define __HW_HIBERNATE_H__
//*****************************************************************************
//
// The following are defines for the Hibernation module register addresses.
//
//*****************************************************************************
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
#define HIB_CTL 0x400FC010 // Hibernation Control
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
// Status
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
#define HIB_DATA 0x400FC030 // Hibernation Data
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCC register.
//
//*****************************************************************************
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
#define HIB_RTCC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM0 register.
//
//*****************************************************************************
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
#define HIB_RTCM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCM1 register.
//
//*****************************************************************************
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
#define HIB_RTCM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCLD register.
//
//*****************************************************************************
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
#define HIB_RTCLD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_CTL register.
//
//*****************************************************************************
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
#define HIB_CTL_OSCHYS 0x00040000 // 32
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
// Comparator
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IM register.
//
//*****************************************************************************
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
// Interrupt Mask
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
// Mask
#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RIS register.
//
//*****************************************************************************
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
// Interrupt Status
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
// Status
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
// Interrupt Status
#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_MIS register.
//
//*****************************************************************************
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Status
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Status
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Status
#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
// Status
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
// Status
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_IC register.
//
//*****************************************************************************
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
// Interrupt Clear
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
// Interrupt Clear
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
// Interrupt Clear
#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
// Clear
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCT register.
//
//*****************************************************************************
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
#define HIB_RTCT_TRIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_RTCSS register.
//
//*****************************************************************************
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
#define HIB_RTCSS_RTCSSM_S 16
#define HIB_RTCSS_RTCSSC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the HIB_DATA register.
//
//*****************************************************************************
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
#define HIB_DATA_RTD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Hibernation module register
// addresses.
//
//*****************************************************************************
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCC
// register.
//
//*****************************************************************************
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCM0
// register.
//
//*****************************************************************************
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCM1
// register.
//
//*****************************************************************************
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCLD
// register.
//
//*****************************************************************************
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RIS
// register.
//
//*****************************************************************************
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_MIS
// register.
//
//*****************************************************************************
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_RTCT
// register.
//
//*****************************************************************************
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the HIB_DATA
// register.
//
//*****************************************************************************
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
#endif
#endif // __HW_HIBERNATE_H__

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//*****************************************************************************
//
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
#define I2C_O_SDR 0x00000008 // I2C Slave Data
#define I2C_O_MDR 0x00000008 // I2C Master Data
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
// Status
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
// Status
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
#define I2C_O_SACKCTL 0x00000020 // I2C ACK Control
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
// Count
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//*****************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_RS 0x00000001 // Receive not send
#define I2C_MSA_SA_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//*****************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//*****************************************************************************
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//*****************************************************************************
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_QCMD 0x00000020 // Quick Command
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_STOP 0x00000004 // Generate STOP
#define I2C_MCS_START 0x00000002 // Generate START
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//*****************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//*****************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
#define I2C_MDR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//*****************************************************************************
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
#define I2C_MTPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//*****************************************************************************
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//*****************************************************************************
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//*****************************************************************************
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//*****************************************************************************
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//*****************************************************************************
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//*****************************************************************************
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//*****************************************************************************
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//*****************************************************************************
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//*****************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//*****************************************************************************
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//*****************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//*****************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//*****************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//*****************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//*****************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
// register.
//
//*****************************************************************************
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
// register.
//
//*****************************************************************************
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
// register.
//
//*****************************************************************************
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C_O_SICR
// register.
//
//*****************************************************************************
#define I2C_SICR_IC 0x00000001 // Clear Interrupt
//*****************************************************************************
//
// The following are deprecated defines for the I2C master register offsets.
//
//*****************************************************************************
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
#define I2C_MASTER_O_DR 0x00000008 // Data register
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
//*****************************************************************************
//
// The following are deprecated defines for the I2C slave register offsets.
//
//*****************************************************************************
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
#define I2C_SLAVE_O_DR 0x00000008 // Data register
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C master
// slave address register.
//
//*****************************************************************************
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
#define I2C_MASTER_SA_SA_SHIFT 1
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Control and Status register.
//
//*****************************************************************************
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
#define I2C_MASTER_CS_START 0x00000002 // Start
#define I2C_MASTER_CS_RUN 0x00000001 // Run
//*****************************************************************************
//
// The following are deprecated defines for the values used in determining the
// contents of the I2C Master Timer Period register.
//
//*****************************************************************************
#define I2C_SCL_FAST 400000 // SCL fast frequency
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Raw Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Master
// Configuration register.
//
//*****************************************************************************
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Own
// Address register.
//
//*****************************************************************************
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Control/Status register.
//
//*****************************************************************************
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Mask register.
//
//*****************************************************************************
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave Raw
// Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Masked Interrupt Status register.
//
//*****************************************************************************
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the I2C Slave
// Interrupt Clear register.
//
//*****************************************************************************
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
#endif
#endif // __HW_I2C_H__

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//*****************************************************************************
//
// hw_i2s.h - Macros for use in accessing the I2S registers.
//
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_I2S_H__
#define __HW_I2S_H__
//*****************************************************************************
//
// The following are defines for the Inter-Integrated Circuit Sound register
// offsets.
//
//*****************************************************************************
#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
// Configuration
#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
// and Mask
#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
// Mask
#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFO register.
//
//*****************************************************************************
#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data
#define I2S_TXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXCFG register.
//
//*****************************************************************************
#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data
#define I2S_TXCFG_DLY 0x10000000 // Data Delay
#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity
#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity
#define I2S_TXCFG_WM_M 0x03000000 // Write Mode
#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty
#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave
#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size
#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size
#define I2S_TXCFG_SSZ_S 10
#define I2S_TXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
//
//*****************************************************************************
#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
#define I2S_TXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXISM register.
//
//*****************************************************************************
#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
// Interrupt
#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_TXLEV register.
//
//*****************************************************************************
#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
#define I2S_TXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFO register.
//
//*****************************************************************************
#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data
#define I2S_RXFIFO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
// register.
//
//*****************************************************************************
#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode
#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXCFG register.
//
//*****************************************************************************
#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data
#define I2S_RXCFG_DLY 0x10000000 // Data Delay
#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity
#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity
#define I2S_RXCFG_RM 0x01000000 // Read Mode
#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave
#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size
#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size
#define I2S_RXCFG_SSZ_S 10
#define I2S_RXCFG_SDSZ_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
//
//*****************************************************************************
#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
#define I2S_RXLIMIT_LIMIT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXISM register.
//
//*****************************************************************************
#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
// Interrupt
#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RXLEV register.
//
//*****************************************************************************
#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
#define I2S_RXLEV_LEVEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_CFG register.
//
//*****************************************************************************
#define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK
#define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK
#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable
#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IM register.
//
//*****************************************************************************
#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_RIS register.
//
//*****************************************************************************
#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_MIS register.
//
//*****************************************************************************
#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request
#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error
#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request
//*****************************************************************************
//
// The following are defines for the bit fields in the I2S_O_IC register.
//
//*****************************************************************************
#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error
#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error
#endif // __HW_I2S_H__

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//*****************************************************************************
//
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
#define INT_GPIOE 20 // GPIO Port E
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
#define INT_PWM0_FAULT 25 // PWM0 Fault
#define INT_PWM0_0 26 // PWM0 Generator 0
#define INT_PWM0_1 27 // PWM0 Generator 1
#define INT_PWM0_2 28 // PWM0 Generator 2
#define INT_QEI0 29 // Quadrature Encoder 0
#define INT_ADC0SS0 30 // ADC0 Sequence 0
#define INT_ADC0SS1 31 // ADC0 Sequence 1
#define INT_ADC0SS2 32 // ADC0 Sequence 2
#define INT_ADC0SS3 33 // ADC0 Sequence 3
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
#define INT_COMP1 42 // Analog Comparator 1
#define INT_COMP2 43 // Analog Comparator 2
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
#define INT_FLASH 45 // FLASH Control
#define INT_GPIOF 46 // GPIO Port F
#define INT_GPIOG 47 // GPIO Port G
#define INT_GPIOH 48 // GPIO Port H
#define INT_UART2 49 // UART2 Rx and Tx
#define INT_SSI1 50 // SSI1 Rx and Tx
#define INT_TIMER3A 51 // Timer 3 subtimer A
#define INT_TIMER3B 52 // Timer 3 subtimer B
#define INT_I2C1 53 // I2C1 Master and Slave
#define INT_QEI1 54 // Quadrature Encoder 1
#define INT_CAN0 55 // CAN0
#define INT_CAN1 56 // CAN1
#define INT_CAN2 57 // CAN2
#define INT_ETH 58 // Ethernet
#define INT_HIBERNATE 59 // Hibernation module
#define INT_USB0 60 // USB 0 Controller
#define INT_PWM0_3 61 // PWM0 Generator 3
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
#define INT_ADC1SS0 64 // ADC1 Sequence 0
#define INT_ADC1SS1 65 // ADC1 Sequence 1
#define INT_ADC1SS2 66 // ADC1 Sequence 2
#define INT_ADC1SS3 67 // ADC1 Sequence 3
#define INT_I2S0 68 // I2S0
#define INT_EPI0 69 // EPI0
#define INT_GPIOJ 70 // GPIO Port J
#define INT_GPIOK 71 // GPIO Port K
#define INT_GPIOL 72 // GPIO Port L
#define INT_SSI2 73 // SSI2
#define INT_SSI3 74 // SSI3
#define INT_UART3 75 // UART3
#define INT_UART4 76 // UART4
#define INT_UART5 77 // UART5
#define INT_UART6 78 // UART6
#define INT_UART7 79 // UART7
#define INT_I2C2 84 // I2C2
#define INT_I2C3 85 // I2C3
#define INT_TIMER4A 86 // Timer 4A
#define INT_TIMER4B 87 // Timer 4B
#define INT_TIMER5A 108 // Timer 5A
#define INT_TIMER5B 109 // Timer 5B
#define INT_WTIMER0A 110 // Wide Timer 0A
#define INT_WTIMER0B 111 // Wide Timer 0B
#define INT_WTIMER1A 112 // Wide Timer 1A
#define INT_WTIMER1B 113 // Wide Timer 1B
#define INT_WTIMER2A 114 // Wide Timer 2A
#define INT_WTIMER2B 115 // Wide Timer 2B
#define INT_WTIMER3A 116 // Wide Timer 3A
#define INT_WTIMER3B 117 // Wide Timer 3B
#define INT_WTIMER4A 118 // Wide Timer 4A
#define INT_WTIMER4B 119 // Wide Timer 4B
#define INT_WTIMER5A 120 // Wide Timer 5A
#define INT_WTIMER5B 121 // Wide Timer 5B
#define INT_SYSEXC 122 // System Exception (imprecise)
#define INT_PECI0 123 // PECI 0
#define INT_LPC0 124 // LPC 0
#define INT_I2C4 125 // I2C4
#define INT_I2C5 126 // I2C5
#define INT_GPIOM 127 // GPIO Port M
#define INT_GPION 128 // GPIO Port N
#define INT_FAN0 130 // FAN 0
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
#define INT_GPIOP1 133 // GPIO Port P1
#define INT_GPIOP2 134 // GPIO Port P2
#define INT_GPIOP3 135 // GPIO Port P3
#define INT_GPIOP4 136 // GPIO Port P4
#define INT_GPIOP5 137 // GPIO Port P5
#define INT_GPIOP6 138 // GPIO Port P6
#define INT_GPIOP7 139 // GPIO Port P7
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
#define INT_GPIOQ1 141 // GPIO Port Q1
#define INT_GPIOQ2 142 // GPIO Port Q2
#define INT_GPIOQ3 143 // GPIO Port Q3
#define INT_GPIOQ4 144 // GPIO Port Q4
#define INT_GPIOQ5 145 // GPIO Port Q5
#define INT_GPIOQ6 146 // GPIO Port Q6
#define INT_GPIOQ7 147 // GPIO Port Q7
#define INT_PWM1_0 150 // PWM1 Generator 0
#define INT_PWM1_1 151 // PWM1 Generator 1
#define INT_PWM1_2 152 // PWM1 Generator 2
#define INT_PWM1_3 153 // PWM1 Generator 3
#define INT_PWM1_FAULT 154 // PWM1 Fault
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#define NUM_INTERRUPTS 155
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_SSI 23 // SSI Rx and Tx
#define INT_I2C 24 // I2C Master and Slave
#define INT_PWM_FAULT 25 // PWM Fault
#define INT_PWM0 26 // PWM Generator 0
#define INT_PWM1 27 // PWM Generator 1
#define INT_PWM2 28 // PWM Generator 2
#define INT_QEI 29 // Quadrature Encoder
#define INT_ADC0 30 // ADC Sequence 0
#define INT_ADC1 31 // ADC Sequence 1
#define INT_ADC2 32 // ADC Sequence 2
#define INT_ADC3 33 // ADC Sequence 3
#define INT_PWM3 61 // PWM Generator 3
#endif
#endif // __HW_INTS_H__

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//*****************************************************************************
//
// hw_lpc.h - Macros used when accessing the LPC hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_LPC_H__
#define __HW_LPC_H__
//*****************************************************************************
//
// The following are defines for the LPC register addresses.
//
//*****************************************************************************
#define LPC_O_CTL 0x00000000 // LPC Control
#define LPC_O_STS 0x00000004 // LPC Status
#define LPC_O_IRQCTL 0x00000008 // LPC IRQ Control
#define LPC_O_IRQST 0x0000000C // LPC IRQ Status
#define LPC_O_CH0CTL 0x00000010 // LPC Channel 0 Control
#define LPC_O_CH0ST 0x00000014 // LPC Channel 0 Status
#define LPC_O_CH0ADR 0x00000018 // LPC Channel 0 Address
#define LPC_O_CH1CTL 0x00000020 // LPC Channel 1 Control
#define LPC_O_CH1ST 0x00000024 // LPC Channel 1 Status
#define LPC_O_CH1ADR 0x00000028 // LPC Channel 1 Address
#define LPC_O_CH2CTL 0x00000030 // LPC Channel 2 Control
#define LPC_O_CH2ST 0x00000034 // LPC Channel 2 Status
#define LPC_O_CH2ADR 0x00000038 // LPC Channel 2 Address
#define LPC_O_CH3CTL 0x00000040 // LPC Channel 3 Control
#define LPC_O_CH3ST 0x00000044 // LPC Channel 3 Status
#define LPC_O_CH3ADR 0x00000048 // LPC Channel 3 Address
#define LPC_O_CH4CTL 0x00000050 // LPC Channel 4 Control
#define LPC_O_CH4ST 0x00000054 // LPC Channel 4 Status
#define LPC_O_CH4ADR 0x00000058 // LPC Channel 4 Address
#define LPC_O_CH5CTL 0x00000060 // LPC Channel 5 Control
#define LPC_O_CH5ST 0x00000064 // LPC Channel 5 Status
#define LPC_O_CH5ADR 0x00000068 // LPC Channel 5 Address
#define LPC_O_CH6CTL 0x00000070 // LPC Channel 6 Control
#define LPC_O_CH6ST 0x00000074 // LPC Channel 6 Status
#define LPC_O_CH6ADR 0x00000078 // LPC Channel 6 Address
#define LPC_O_CH7CTL 0x00000080 // LPC Channel 7 / COMx Control
#define LPC_O_CH7ST 0x00000084 // LPC Channel 7 / COMx Status
#define LPC_O_CH7ADR 0x00000088 // LPC Channel 7 / COMx Address
#define LPC_O_STSADDR 0x000000A0 // LPC Status Block Address
#define LPC_O_IM 0x00000100 // LPC Interrupt Mask
#define LPC_O_RIS 0x00000104 // LPC Raw Interrupt Status
#define LPC_O_MIS 0x00000108 // LPC Masked Interrupt Status
#define LPC_O_IC 0x0000010C // LPC Interrupt Clear
#define LPC_O_DMACX 0x00000120 // LPC DMA and COMx Control
#define LPC_O_POOL 0x00000400 // LPC Register Pool
#define LPC_O_PP 0x00000FC0 // LPC Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CTL register.
//
//*****************************************************************************
#define LPC_CTL_SCICNT_M 0x00000C00 // LPC0SCI Pulse Length
#define LPC_CTL_SCICNT_0 0x00000000 // No pulse occurs on the LPC0SCI
// pin
#define LPC_CTL_SCICNT_2 0x00000400 // The pulse on the LPC0SCI pin is
// 2 LPC0CLK periods
#define LPC_CTL_SCICNT_4 0x00000800 // The pulse on the LPC0SCI pin is
// 4 LPC0CLK periods
#define LPC_CTL_SCICNT_8 0x00000C00 // The pulse on the LPC0SCI pin is
// 8 LPC0CLK periods
#define LPC_CTL_SCI 0x00000200 // Start SCI Pulse
#define LPC_CTL_WAKE 0x00000100 // Restart the LPC Bus
#define LPC_CTL_CE7 0x00000080 // Enable Channel 7
#define LPC_CTL_CE6 0x00000040 // Enable Channel 6
#define LPC_CTL_CE5 0x00000020 // Enable Channel 5
#define LPC_CTL_CE4 0x00000010 // Enable Channel 4
#define LPC_CTL_CE3 0x00000008 // Enable Channel 3
#define LPC_CTL_CE2 0x00000004 // Enable Channel 2
#define LPC_CTL_CE1 0x00000002 // Enable Channel 1
#define LPC_CTL_CE0 0x00000001 // Enable Channel 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_STS register.
//
//*****************************************************************************
#define LPC_STS_CHCNT_M 0x00700000 // Number of Channels
#define LPC_STS_POOLSZ_M 0x00070000 // Register Pool Size
#define LPC_STS_POOLSZ_256 0x00010000 // 256 bytes
#define LPC_STS_POOLSZ_512 0x00020000 // 512 bytes
#define LPC_STS_POOLSZ_768 0x00030000 // 768 bytes
#define LPC_STS_POOLSZ_1024 0x00040000 // 1024 bytes
#define LPC_STS_RST 0x00000400 // LPC is in Reset
#define LPC_STS_BUSY 0x00000200 // LPC is Busy
#define LPC_STS_SLEEP 0x00000100 // LPC is in Sleep Mode
#define LPC_STS_CA7 0x00000080 // Channel 7 Active
#define LPC_STS_CA6 0x00000040 // Channel 6 Active
#define LPC_STS_CA5 0x00000020 // Channel 5 Active
#define LPC_STS_CA4 0x00000010 // Channel 4 Active
#define LPC_STS_CA3 0x00000008 // Channel 3 Active
#define LPC_STS_CA2 0x00000004 // Channel 2 Active
#define LPC_STS_CA1 0x00000002 // Channel 1 Active
#define LPC_STS_CA0 0x00000001 // Channel 0 Active
#define LPC_STS_CHCNT_S 20
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IRQCTL register.
//
//*****************************************************************************
#define LPC_IRQCTL_I15 0x80000000 // Manual IRQ15 State
#define LPC_IRQCTL_I14 0x40000000 // Manual IRQ14 State
#define LPC_IRQCTL_I13 0x20000000 // Manual IRQ13 State
#define LPC_IRQCTL_I12 0x10000000 // Manual IRQ12 State
#define LPC_IRQCTL_I11 0x08000000 // Manual IRQ11 State
#define LPC_IRQCTL_I10 0x04000000 // Manual IRQ10 State
#define LPC_IRQCTL_I9 0x02000000 // Manual IRQ9 State
#define LPC_IRQCTL_I8 0x01000000 // Manual IRQ8 State
#define LPC_IRQCTL_I7 0x00800000 // Manual IRQ7 State
#define LPC_IRQCTL_I6 0x00400000 // Manual IRQ6 State
#define LPC_IRQCTL_I5 0x00200000 // Manual IRQ5 State
#define LPC_IRQCTL_I4 0x00100000 // Manual IRQ4 State
#define LPC_IRQCTL_I3 0x00080000 // Manual IRQ3 State
#define LPC_IRQCTL_I2 0x00040000 // Manual IRQ2 State
#define LPC_IRQCTL_I1 0x00020000 // Manual IRQ1 State
#define LPC_IRQCTL_AH 0x00010000 // Active High Control
#define LPC_IRQCTL_PULSE 0x00000004 // Pulse IRQ States
#define LPC_IRQCTL_ONCHG 0x00000002 // Initiate on Change
#define LPC_IRQCTL_SND 0x00000001 // Initiate Immediately
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IRQST register.
//
//*****************************************************************************
#define LPC_IRQST_I15 0x80000000 // Host IRQ15 State
#define LPC_IRQST_I14 0x40000000 // IRQ14 State
#define LPC_IRQST_I13 0x20000000 // IRQ13 State
#define LPC_IRQST_I12 0x10000000 // IRQ12 State
#define LPC_IRQST_I11 0x08000000 // IRQ11 State
#define LPC_IRQST_I10 0x04000000 // IRQ10 State
#define LPC_IRQST_I9 0x02000000 // IRQ9 State
#define LPC_IRQST_I8 0x01000000 // IRQ8 State
#define LPC_IRQST_I7 0x00800000 // IRQ7 State
#define LPC_IRQST_I6 0x00400000 // IRQ6 State
#define LPC_IRQST_I5 0x00200000 // IRQ5 State
#define LPC_IRQST_I4 0x00100000 // IRQ4 State
#define LPC_IRQST_I3 0x00080000 // IRQ3 State
#define LPC_IRQST_I2 0x00040000 // IRQ2 State
#define LPC_IRQST_I1 0x00020000 // IRQ1 State
#define LPC_IRQST_I0 0x00010000 // IRQ0 State
#define LPC_IRQST_SIRQ 0x00000004 // Pulse IRQ States
#define LPC_IRQST_CONT 0x00000001 // Initiate Immediately
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0CTL register.
//
//*****************************************************************************
#define LPC_CH0CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH0CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH0CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH0CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH0CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH0CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH0CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH0CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH0CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH0CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH0CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH0CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH0CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH0CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH0CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH0CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH0CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH0CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH0CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH0CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH0CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH0CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH0CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH0CTL_IRQSEL2_S 28
#define LPC_CH0CTL_IRQSEL1_S 24
#define LPC_CH0CTL_IRQSEL0_S 20
#define LPC_CH0CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0ST register.
//
//*****************************************************************************
#define LPC_CH0ST_USER_M 0x00001F00 // User Data
#define LPC_CH0ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH0ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH0ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH0ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH0ST_CMD 0x00000008 // Command or Data
#define LPC_CH0ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH0ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH0ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH0ADR register.
//
//*****************************************************************************
#define LPC_CH0ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH0ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH0ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH0ADR_ADDRH_S 16
#define LPC_CH0ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1CTL register.
//
//*****************************************************************************
#define LPC_CH1CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH1CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH1CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH1CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH1CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH1CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH1CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH1CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH1CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH1CTL_IRQEN0_TRGI2 0x00020000 // Trigger 2
#define LPC_CH1CTL_IRQEN0_TRGI3 0x00030000 // Trigger 3
#define LPC_CH1CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH1CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH1CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH1CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH1CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH1CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH1CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH1CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH1CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH1CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH1CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH1CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH1CTL_IRQSEL2_S 28
#define LPC_CH1CTL_IRQSEL1_S 24
#define LPC_CH1CTL_IRQSEL0_S 20
#define LPC_CH1CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1ST register.
//
//*****************************************************************************
#define LPC_CH1ST_USER_M 0x00001F00 // User Data
#define LPC_CH1ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH1ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH1ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH1ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH1ST_CMD 0x00000008 // Command or Data
#define LPC_CH1ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH1ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH1ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH1ADR register.
//
//*****************************************************************************
#define LPC_CH1ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH1ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH1ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH1ADR_ADDRH_S 16
#define LPC_CH1ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2CTL register.
//
//*****************************************************************************
#define LPC_CH2CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH2CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH2CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH2CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH2CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH2CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH2CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH2CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH2CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH2CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH2CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH2CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH2CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH2CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH2CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH2CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH2CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH2CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH2CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH2CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH2CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH2CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH2CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH2CTL_IRQSEL2_S 28
#define LPC_CH2CTL_IRQSEL1_S 24
#define LPC_CH2CTL_IRQSEL0_S 20
#define LPC_CH2CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2ST register.
//
//*****************************************************************************
#define LPC_CH2ST_USER_M 0x00001F00 // User Data
#define LPC_CH2ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH2ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH2ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH2ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH2ST_CMD 0x00000008 // Command or Data
#define LPC_CH2ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH2ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH2ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH2ADR register.
//
//*****************************************************************************
#define LPC_CH2ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH2ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH2ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH2ADR_ADDRH_S 16
#define LPC_CH2ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3CTL register.
//
//*****************************************************************************
#define LPC_CH3CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH3CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH3CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH3CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH3CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH3CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH3CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH3CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH3CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH3CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH3CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH3CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH3CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH3CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH3CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH3CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH3CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH3CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH3CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH3CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH3CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH3CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH3CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH3CTL_IRQSEL2_S 28
#define LPC_CH3CTL_IRQSEL1_S 24
#define LPC_CH3CTL_IRQSEL0_S 20
#define LPC_CH3CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3ST register.
//
//*****************************************************************************
#define LPC_CH3ST_USER_M 0x00001F00 // User Data
#define LPC_CH3ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH3ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH3ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH3ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH3ST_CMD 0x00000008 // Command or Data
#define LPC_CH3ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH3ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH3ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH3ADR register.
//
//*****************************************************************************
#define LPC_CH3ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH3ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH3ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
#define LPC_CH3ADR_ADDRH_S 16
#define LPC_CH3ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4CTL register.
//
//*****************************************************************************
#define LPC_CH4CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH4CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH4CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH4CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH4CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH4CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH4CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH4CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH4CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH4CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH4CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH4CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH4CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH4CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH4CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH4CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH4CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH4CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH4CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH4CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH4CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH4CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH4CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH4CTL_IRQSEL2_S 28
#define LPC_CH4CTL_IRQSEL1_S 24
#define LPC_CH4CTL_IRQSEL0_S 20
#define LPC_CH4CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4ST register.
//
//*****************************************************************************
#define LPC_CH4ST_USER_M 0x00001F00 // User Data
#define LPC_CH4ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH4ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH4ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH4ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH4ST_CMD 0x00000008 // Command or Data
#define LPC_CH4ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH4ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH4ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH4ADR register.
//
//*****************************************************************************
#define LPC_CH4ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH4ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH4ADR_ADDRH_S 16
#define LPC_CH4ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5CTL register.
//
//*****************************************************************************
#define LPC_CH5CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH5CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH5CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH5CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH5CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH5CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH5CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH5CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH5CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH5CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH5CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH5CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH5CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH5CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH5CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH5CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH5CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH5CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH5CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH5CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH5CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH5CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH5CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH5CTL_IRQSEL2_S 28
#define LPC_CH5CTL_IRQSEL1_S 24
#define LPC_CH5CTL_IRQSEL0_S 20
#define LPC_CH5CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5ST register.
//
//*****************************************************************************
#define LPC_CH5ST_USER_M 0x00001F00 // User Data
#define LPC_CH5ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH5ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH5ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH5ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH5ST_CMD 0x00000008 // Command or Data
#define LPC_CH5ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH5ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH5ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH5ADR register.
//
//*****************************************************************************
#define LPC_CH5ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH5ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH5ADR_ADDRH_S 16
#define LPC_CH5ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6CTL register.
//
//*****************************************************************************
#define LPC_CH6CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH6CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH6CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH6CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH6CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH6CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH6CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH6CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
#define LPC_CH6CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
#define LPC_CH6CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
#define LPC_CH6CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH6CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH6CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH6CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH6CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH6CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH6CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH6CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH6CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH6CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH6CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH6CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH6CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH6CTL_IRQSEL2_S 28
#define LPC_CH6CTL_IRQSEL1_S 24
#define LPC_CH6CTL_IRQSEL0_S 20
#define LPC_CH6CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6ST register.
//
//*****************************************************************************
#define LPC_CH6ST_USER_M 0x00001F00 // User Data
#define LPC_CH6ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH6ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH6ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH6ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH6ST_CMD 0x00000008 // Command or Data
#define LPC_CH6ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH6ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH6ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH6ADR register.
//
//*****************************************************************************
#define LPC_CH6ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH6ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH6ADR_ADDRH_S 16
#define LPC_CH6ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7CTL register.
//
//*****************************************************************************
#define LPC_CH7CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
#define LPC_CH7CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
#define LPC_CH7CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
#define LPC_CH7CTL_CX 0x00080000 // IRQ Enable 2
#define LPC_CH7CTL_IRQEN2 0x00080000 // IRQ Enable 2
#define LPC_CH7CTL_IRQEN1 0x00040000 // IRQ Enable 1
#define LPC_CH7CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
#define LPC_CH7CTL_IRQEN0_AUTO 0x00000000 // The automatic IRQ trigger is
// disabled
#define LPC_CH7CTL_IRQEN0_MST 0x00010000 // If TYPE is set, the IRQ selected
// by IRQSEL0 is triggered when the
// master wins arbitration (the
// HW1ST bit is set)
#define LPC_CH7CTL_IRQEN0_SLV 0x00020000 // If TYPE is set, the IRQ selected
// by IRQSEL0 is triggered when the
// slave wins arbitration (the
// SW1ST bit is set)
#define LPC_CH7CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
#define LPC_CH7CTL_ARBDIS 0x00008000 // Arbitration Disabled
#define LPC_CH7CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
#define LPC_CH7CTL_AMASK_M 0x0000001C // Address Mask for Ranges
#define LPC_CH7CTL_AMASK_4 0x00000000 // Address mask of 0x3; mailbox
// size of 4 bytes for an endpoint
// range or used for single
// endpoints
#define LPC_CH7CTL_AMASK_8 0x00000004 // Address mask of 0x7; mailbox
// size of 8 bytes
#define LPC_CH7CTL_AMASK_16 0x00000008 // Address mask of 0xF; mailbox
// size of 16 bytes
#define LPC_CH7CTL_AMASK_32 0x0000000C // Address mask of 0x1F; mailbox
// size of 32 bytes
#define LPC_CH7CTL_AMASK_64 0x00000010 // Address mask of 0x3F; mailbox
// size of 64 bytes
#define LPC_CH7CTL_AMASK_128 0x00000014 // Address mask of 0x7F; mailbox
// size of 128 bytes
#define LPC_CH7CTL_AMASK_256 0x00000018 // Address mask of 0xFF; mailbox
// size of 256 bytes
#define LPC_CH7CTL_AMASK_512 0x0000001C // Address mask of 0x1FF; mailbox
// size of 512 bytes
#define LPC_CH7CTL_TYPE 0x00000001 // Channel Type
#define LPC_CH7CTL_IRQSEL2_S 28
#define LPC_CH7CTL_IRQSEL1_S 24
#define LPC_CH7CTL_IRQSEL0_S 20
#define LPC_CH7CTL_OFFSET_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7ST register.
//
//*****************************************************************************
#define LPC_CH7ST_USER_M 0x00001F00 // User Data
#define LPC_CH7ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH7ST_HW1ST 0x00000040 // Host Wrote First
#define LPC_CH7ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH7ST_SW1ST 0x00000010 // Slave Wrote First
#define LPC_CH7ST_CMD 0x00000008 // Command or Data
#define LPC_CH7ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH7ST_TOH 0x00000001 // To-Host Transaction
#define LPC_CH7ST_USER_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_CH7ADR register.
//
//*****************************************************************************
#define LPC_CH7ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_CH7ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_CH7ADR_ADDRH_S 16
#define LPC_CH7ADR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_STSADDR register.
//
//*****************************************************************************
#define LPC_STSADDR_ADDRH_M 0xFFFF0000 // Upper Address Match
#define LPC_STSADDR_ADDRL_M 0x0000FFF8 // Lower Address Match
#define LPC_STSADDR_ENA 0x00000001 // Enable Status Block
#define LPC_STSADDR_ADDRH_S 16
#define LPC_STSADDR_ADDRL_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IM register.
//
//*****************************************************************************
#define LPC_IM_RSTIM 0x80000000 // Reset State Interrupt Mask
#define LPC_IM_SLEEPIM 0x40000000 // Sleep State Interrupt Mask
#define LPC_IM_COMXIM 0x20000000 // COMx Interrupt Mask
#define LPC_IM_SIRQIM 0x10000000 // SERIRQ Frame Complete Interrupt
// Mask
#define LPC_IM_CH6IM3 0x08000000 // Channel 6 Interrupt Mask 3
#define LPC_IM_CH6IM2 0x04000000 // Channel 6 Interrupt Mask 2
#define LPC_IM_CH6IM1 0x02000000 // Channel 6 Interrupt Mask 1
#define LPC_IM_CH6IM0 0x01000000 // Channel 6 Interrupt Mask 0
#define LPC_IM_CH5IM3 0x00800000 // Channel 5 Interrupt Mask 3
#define LPC_IM_CH5IM2 0x00400000 // Channel 5 Interrupt Mask 2
#define LPC_IM_CH5IM1 0x00200000 // Channel 5 Interrupt Mask 1
#define LPC_IM_CH5IM0 0x00100000 // Channel 5 Interrupt Mask 0
#define LPC_IM_CH4IM3 0x00080000 // Channel 4 Interrupt Mask 3
#define LPC_IM_CH4IM2 0x00040000 // Channel 4 Interrupt Mask 2
#define LPC_IM_CH4IM1 0x00020000 // Channel 4 Interrupt Mask 1
#define LPC_IM_CH4IM0 0x00010000 // Channel 4 Interrupt Mask 0
#define LPC_IM_CH3IM3 0x00008000 // Channel 3 Interrupt Mask 3
#define LPC_IM_CH3IM2 0x00004000 // Channel 3 Interrupt Mask 2
#define LPC_IM_CH3IM1 0x00002000 // Channel 3 Interrupt Mask 1
#define LPC_IM_CH3IM0 0x00001000 // Channel 3 Interrupt Mask 0
#define LPC_IM_CH2IM3 0x00000800 // Channel 2 Interrupt Mask 3
#define LPC_IM_CH2IM2 0x00000400 // Channel 2 Interrupt Mask 2
#define LPC_IM_CH2IM1 0x00000200 // Channel 2 Interrupt Mask 1
#define LPC_IM_CH2IM0 0x00000100 // Channel 2 Interrupt Mask 0
#define LPC_IM_CH1IM3 0x00000080 // Channel 1 Interrupt Mask 3
#define LPC_IM_CH1IM2 0x00000040 // Channel 1 Interrupt Mask 2
#define LPC_IM_CH1IM1 0x00000020 // Channel 1 Interrupt Mask 1
#define LPC_IM_CH1IM0 0x00000010 // Channel 1 Interrupt Mask 0
#define LPC_IM_CH0IM3 0x00000008 // Channel 0 Interrupt Mask 3
#define LPC_IM_CH0IM2 0x00000004 // Channel 0 Interrupt Mask 2
#define LPC_IM_CH0IM1 0x00000002 // Channel 0 Interrupt Mask 1
#define LPC_IM_CH0IM0 0x00000001 // Channel 0 Interrupt Mask 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_RIS register.
//
//*****************************************************************************
#define LPC_RIS_RSTRIS 0x80000000 // Reset State Raw Interrupt Status
#define LPC_RIS_SLEEPRIS 0x40000000 // Sleep State Raw Interrupt Status
#define LPC_RIS_COMXRIS 0x20000000 // COMx Raw Interrupt Status
#define LPC_RIS_SIRQRIS 0x10000000 // SERIRQ Frame Complete Raw
// Interrupt Status
#define LPC_RIS_CH6RIS3 0x08000000 // Channel 6 Raw Interrupt Status 3
#define LPC_RIS_CH6RIS2 0x04000000 // Channel 6 Raw Interrupt Status 2
#define LPC_RIS_CH6RIS1 0x02000000 // Channel 6 Raw Interrupt Status 1
#define LPC_RIS_CH6RIS0 0x01000000 // Channel 6 Raw Interrupt Status 0
#define LPC_RIS_CH5RIS3 0x00800000 // Channel 5 Raw Interrupt Status 3
#define LPC_RIS_CH5RIS2 0x00400000 // Channel 5 Raw Interrupt Status 2
#define LPC_RIS_CH5RIS1 0x00200000 // Channel 5 Raw Interrupt Status 1
#define LPC_RIS_CH5RIS0 0x00100000 // Channel 5 Raw Interrupt Status 0
#define LPC_RIS_CH4RIS3 0x00080000 // Channel 4 Raw Interrupt Status 3
#define LPC_RIS_CH4RIS2 0x00040000 // Channel 4 Raw Interrupt Status 2
#define LPC_RIS_CH4RIS1 0x00020000 // Channel 4 Raw Interrupt Status 1
#define LPC_RIS_CH4RIS0 0x00010000 // Channel 4 Raw Interrupt Status 0
#define LPC_RIS_CH3RIS3 0x00008000 // Channel 3 Raw Interrupt Status 3
#define LPC_RIS_CH3RIS2 0x00004000 // Channel 3 Raw Interrupt Status 2
#define LPC_RIS_CH3RIS1 0x00002000 // Channel 3 Raw Interrupt Status 1
#define LPC_RIS_CH3RIS0 0x00001000 // Channel 3 Raw Interrupt Status 0
#define LPC_RIS_CH2RIS3 0x00000800 // Channel 2 Raw Interrupt Status 3
#define LPC_RIS_CH2RIS2 0x00000400 // Channel 2 Raw Interrupt Status 2
#define LPC_RIS_CH2RIS1 0x00000200 // Channel 2 Raw Interrupt Status 1
#define LPC_RIS_CH2RIS0 0x00000100 // Channel 2 Raw Interrupt Status 0
#define LPC_RIS_CH1RIS3 0x00000080 // Channel 1 Raw Interrupt Status 3
#define LPC_RIS_CH1RIS2 0x00000040 // Channel 1 Raw Interrupt Status 2
#define LPC_RIS_CH1RIS1 0x00000020 // Channel 1 Raw Interrupt Status 1
#define LPC_RIS_CH1RIS0 0x00000010 // Channel 1 Raw Interrupt Status 0
#define LPC_RIS_CH0RIS3 0x00000008 // Channel 0 Raw Interrupt Status 3
#define LPC_RIS_CH0RIS2 0x00000004 // Channel 0 Raw Interrupt Status 2
#define LPC_RIS_CH0RIS1 0x00000002 // Channel 0 Raw Interrupt Status 1
#define LPC_RIS_CH0RIS0 0x00000001 // Channel 0 Raw Interrupt Status 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_MIS register.
//
//*****************************************************************************
#define LPC_MIS_RSTMIS 0x80000000 // Reset State Masked Interrupt
// Status
#define LPC_MIS_SLEEPMIS 0x40000000 // Sleep State Masked Interrupt
// Status
#define LPC_MIS_COMXMIS 0x20000000 // COMx Masked Interrupt Status
#define LPC_MIS_SIRQMIS 0x10000000 // SERIRQ Frame Complete Masked
// Interrupt Status
#define LPC_MIS_CH6MIS3 0x08000000 // Channel 6 Masked Interrupt
// Status 3
#define LPC_MIS_CH6MIS2 0x04000000 // Channel 6 Masked Interrupt
// Status 2
#define LPC_MIS_CH6MIS1 0x02000000 // Channel 6 Masked Interrupt
// Status 1
#define LPC_MIS_CH6MIS0 0x01000000 // Channel 6 Masked Interrupt
// Status 0
#define LPC_MIS_CH5MIS3 0x00800000 // Channel 5 Masked Interrupt
// Status 3
#define LPC_MIS_CH5MIS2 0x00400000 // Channel 5 Masked Interrupt
// Status 2
#define LPC_MIS_CH5MIS1 0x00200000 // Channel 5 Masked Interrupt
// Status 1
#define LPC_MIS_CH5MIS0 0x00100000 // Channel 5 Masked Interrupt
// Status 0
#define LPC_MIS_CH4MIS3 0x00080000 // Channel 4 Masked Interrupt
// Status 3
#define LPC_MIS_CH4MIS2 0x00040000 // Channel 4 Masked Interrupt
// Status 2
#define LPC_MIS_CH4MIS1 0x00020000 // Channel 4 Masked Interrupt
// Status 1
#define LPC_MIS_CH4MIS0 0x00010000 // Channel 4 Masked Interrupt
// Status 0
#define LPC_MIS_CH3MIS3 0x00008000 // Channel 3 Masked Interrupt
// Status 3
#define LPC_MIS_CH3MIS2 0x00004000 // Channel 3 Masked Interrupt
// Status 2
#define LPC_MIS_CH3MIS1 0x00002000 // Channel 3 Masked Interrupt
// Status 1
#define LPC_MIS_CH3MIS0 0x00001000 // Channel 3 Masked Interrupt
// Status 0
#define LPC_MIS_CH2MIS3 0x00000800 // Channel 2 Masked Interrupt
// Status 3
#define LPC_MIS_CH2MIS2 0x00000400 // Channel 2 Masked Interrupt
// Status 2
#define LPC_MIS_CH2MIS1 0x00000200 // Channel 2 Masked Interrupt
// Status 1
#define LPC_MIS_CH2MIS0 0x00000100 // Channel 2 Masked Interrupt
// Status 0
#define LPC_MIS_CH1MIS3 0x00000080 // Channel 1 Masked Interrupt
// Status 3
#define LPC_MIS_CH1MIS2 0x00000040 // Channel 1 Masked Interrupt
// Status 2
#define LPC_MIS_CH1MIS1 0x00000020 // Channel 1 Masked Interrupt
// Status 1
#define LPC_MIS_CH1MIS0 0x00000010 // Channel 1 Masked Interrupt
// Status 0
#define LPC_MIS_CH0MIS3 0x00000008 // Channel 0 Masked Interrupt
// Status 3
#define LPC_MIS_CH0MIS2 0x00000004 // Channel 0 Masked Interrupt
// Status 2
#define LPC_MIS_CH0MIS1 0x00000002 // Channel 0 Masked Interrupt
// Status 1
#define LPC_MIS_CH0MIS0 0x00000001 // Channel 0 Masked Interrupt
// Status 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_IC register.
//
//*****************************************************************************
#define LPC_IC_RSTIC 0x80000000 // Reset State Interrupt Clear
#define LPC_IC_SLEEPIC 0x40000000 // Sleep State Interrupt Clear
#define LPC_IC_COMXIC 0x20000000 // COMx Interrupt Clear
#define LPC_IC_SIRQRIC 0x10000000 // SERIRQ Frame Complete Interrupt
// Clear
#define LPC_IC_CH6IC3 0x08000000 // Channel 6 Interrupt Clear 3
#define LPC_IC_CH6IC2 0x04000000 // Channel 6 Interrupt Clear 2
#define LPC_IC_CH6IC1 0x02000000 // Channel 6 Interrupt Clear 1
#define LPC_IC_CH6IC0 0x01000000 // Channel 6 Interrupt Clear 0
#define LPC_IC_CH5IC3 0x00800000 // Channel 5 Interrupt Clear 3
#define LPC_IC_CH5IC2 0x00400000 // Channel 5 Interrupt Clear 2
#define LPC_IC_CH5IC1 0x00200000 // Channel 5 Interrupt Clear 1
#define LPC_IC_CH5IC0 0x00100000 // Channel 5 Interrupt Clear 0
#define LPC_IC_CH4IC3 0x00080000 // Channel 4 Interrupt Clear 3
#define LPC_IC_CH4IC2 0x00040000 // Channel 4 Interrupt Clear 2
#define LPC_IC_CH4IC1 0x00020000 // Channel 4 Interrupt Clear 1
#define LPC_IC_CH4IC0 0x00010000 // Channel 4 Interrupt Clear 0
#define LPC_IC_CH3IC3 0x00008000 // Channel 3 Interrupt Clear 3
#define LPC_IC_CH3IC2 0x00004000 // Channel 3 Interrupt Clear 2
#define LPC_IC_CH3IC1 0x00002000 // Channel 3 Interrupt Clear 1
#define LPC_IC_CH3IC0 0x00001000 // Channel 3 Interrupt Clear 0
#define LPC_IC_CH2IC3 0x00000800 // Channel 2 Interrupt Clear 3
#define LPC_IC_CH2IC2 0x00000400 // Channel 2 Interrupt Clear 2
#define LPC_IC_CH2IC1 0x00000200 // Channel 2 Interrupt Clear 1
#define LPC_IC_CH2IC0 0x00000100 // Channel 2 Interrupt Clear 0
#define LPC_IC_CH1IC3 0x00000080 // Channel 1 Interrupt Clear 3
#define LPC_IC_CH1IC2 0x00000040 // Channel 1 Interrupt Clear 2
#define LPC_IC_CH1IC1 0x00000020 // Channel 1 Interrupt Clear 1
#define LPC_IC_CH1IC0 0x00000010 // Channel 1 Interrupt Clear 0
#define LPC_IC_CH0IC3 0x00000008 // Channel 0 Interrupt Clear 3
#define LPC_IC_CH0IC2 0x00000004 // Channel 0 Interrupt Clear 2
#define LPC_IC_CH0IC1 0x00000002 // Channel 0 Interrupt Clear 1
#define LPC_IC_CH0IC0 0x00000001 // Channel 0 Interrupt Clear 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_DMACX register.
//
//*****************************************************************************
#define LPC_DMACX_CXRES 0x02000000 // Raw Event State for COMx
#define LPC_DMACX_CXTXRES 0x01000000 // Raw Event State for COMx TX
#define LPC_DMACX_CXRXRES 0x00800000 // Raw Event State for COMx RX
#define LPC_DMACX_CXEM 0x00200000 // Event Mask for COMx
#define LPC_DMACX_CXTXEM 0x00100000 // Event Mask for COMx TX
#define LPC_DMACX_CXRXEM 0x00080000 // Event Mask for COMx RX
#define LPC_DMACX_CXACT_M 0x00060000 // COMx Action
#define LPC_DMACX_CXACT_FRMHNML 0x00000000 // Treat as normal FRMH model and
// let be full (and so marked as
// full)
#define LPC_DMACX_CXACT_FRMHIGN 0x00020000 // Ignore FRMH bytes and continue
// to mark FRMH as empty
#define LPC_DMACX_CXACT_FRMHDMA 0x00040000 // COMx DMA on FRMH byte (e.g. to
// memory)
#define LPC_DMACX_CXACT_UARTDMA 0x00060000 // COMx DMA model with UART
#define LPC_DMACX_COMX 0x00010000 // COMx Handling
#define LPC_DMACX_C3W 0x00000080 // Write Control for Channel 3
#define LPC_DMACX_C3R 0x00000040 // Read Control for Channel 3
#define LPC_DMACX_C2W 0x00000020 // Write Control for Channel 2
#define LPC_DMACX_C2R 0x00000010 // Read Control for Channel 2
#define LPC_DMACX_C1W 0x00000008 // Write Control for Channel 1
#define LPC_DMACX_C1R 0x00000004 // Read Control for Channel 1
#define LPC_DMACX_C0W 0x00000002 // Write Control for Channel 0
#define LPC_DMACX_C0R 0x00000001 // Read Control for Channel 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_POOL register.
//
//*****************************************************************************
#define LPC_POOL_BYTE3_M 0xFF000000 // Byte 3
#define LPC_POOL_BYTE2_M 0x00FF0000 // Byte 2
#define LPC_POOL_BYTE1_M 0x0000FF00 // Byte 1
#define LPC_POOL_BYTE0_M 0x000000FF // Byte 0
#define LPC_POOL_BYTE3_S 24
#define LPC_POOL_BYTE2_S 16
#define LPC_POOL_BYTE1_S 8
#define LPC_POOL_BYTE0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the LPC_O_PP register.
//
//*****************************************************************************
#define LPC_PP_COMX 0x00000010 // COMx Support Available
#define LPC_PP_CHANCNT_M 0x0000000F // Number of Channels (Excluding
// COMx)
#define LPC_PP_CHANCNT_S 0
#endif // __HW_LPC_H__

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//*****************************************************************************
//
// hw_memmap.h - Macros defining the memory map of Stellaris.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define FLASH_BASE 0x00000000 // FLASH memory
#define SRAM_BASE 0x20000000 // SRAM memory
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
#define SSI0_BASE 0x40008000 // SSI0
#define SSI1_BASE 0x40009000 // SSI1
#define SSI2_BASE 0x4000A000 // SSI2
#define SSI3_BASE 0x4000B000 // SSI3
#define UART0_BASE 0x4000C000 // UART0
#define UART1_BASE 0x4000D000 // UART1
#define UART2_BASE 0x4000E000 // UART2
#define UART3_BASE 0x4000F000 // UART3
#define UART4_BASE 0x40010000 // UART4
#define UART5_BASE 0x40011000 // UART5
#define UART6_BASE 0x40012000 // UART6
#define UART7_BASE 0x40013000 // UART7
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
#define QEI0_BASE 0x4002C000 // QEI0
#define QEI1_BASE 0x4002D000 // QEI1
#define TIMER0_BASE 0x40030000 // Timer0
#define TIMER1_BASE 0x40031000 // Timer1
#define TIMER2_BASE 0x40032000 // Timer2
#define TIMER3_BASE 0x40033000 // Timer3
#define TIMER4_BASE 0x40034000 // Timer4
#define TIMER5_BASE 0x40035000 // Timer5
#define WTIMER0_BASE 0x40036000 // Wide Timer0
#define WTIMER1_BASE 0x40037000 // Wide Timer1
#define ADC0_BASE 0x40038000 // ADC0
#define ADC1_BASE 0x40039000 // ADC1
#define COMP_BASE 0x4003C000 // Analog comparators
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
#define CAN0_BASE 0x40040000 // CAN0
#define CAN1_BASE 0x40041000 // CAN1
#define CAN2_BASE 0x40042000 // CAN2
#define ETH_BASE 0x40048000 // Ethernet
#define MAC_BASE 0x40048000 // Ethernet
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
#define USB0_BASE 0x40050000 // USB 0 Controller
#define I2S0_BASE 0x40054000 // I2S0
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
#define EEPROM_BASE 0x400AF000 // EEPROM memory
#define PECI0_BASE 0x400B0000 // Platform Environment Control
// Interface (PECI)
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
#define EPI0_BASE 0x400D0000 // EPI0
#define SYSEXC_BASE 0x400F9000 // System Exception Module
#define HIB_BASE 0x400FC000 // Hibernation Module
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
#define SYSCTL_BASE 0x400FE000 // System Control
#define UDMA_BASE 0x400FF000 // uDMA Controller
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the base address of the memories
// and peripherals.
//
//*****************************************************************************
#define WATCHDOG_BASE 0x40000000 // Watchdog
#define SSI_BASE 0x40008000 // SSI
#define I2C_MASTER_BASE 0x40020000 // I2C Master
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
#define PWM_BASE 0x40028000 // PWM
#define QEI_BASE 0x4002C000 // QEI
#define ADC_BASE 0x40038000 // ADC
#endif
#endif // __HW_MEMMAP_H__

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//*****************************************************************************
//
// hw_peci.h - Macros used when accessing the PECI hardware.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_PECI_H__
#define __HW_PECI_H__
//*****************************************************************************
//
// The following are defines for the PECI register addresses.
//
//*****************************************************************************
#define PECI_O_CTL 0x00000000 // PECI Control
#define PECI_O_DIV 0x00000004 // PECI Poll-Rate Divider
#define PECI_O_CMP 0x00000008 // PECI Comparator
#define PECI_O_M0D0C 0x00000010 // PECI Microprocessor 0 / Domain 0
// Control
#define PECI_O_M0D1C 0x00000014 // PECI Microprocessor 0 / Domain 1
// Control
#define PECI_O_M1D0C 0x00000018 // PECI Microprocessor 1 / Domain 0
// Control
#define PECI_O_M1D1C 0x0000001C // PECI Microprocessor 1 / Domain 1
// Control
#define PECI_O_M0D0 0x00000040 // PECI Microprocessor 0 / Domain 0
// Value
#define PECI_O_M0D1 0x00000044 // PECI Microprocessor 0 / Domain 1
// Value
#define PECI_O_M1D0 0x00000048 // PECI Microprocessor 1 / Domain 0
// Value
#define PECI_O_M1D1 0x0000004C // PECI Microprocessor 1 / Domain 1
// Value
#define PECI_O_IM 0x00000080 // PECI Interrupt Mask
#define PECI_O_RIS 0x00000084 // PECI Raw Interrupt Status
#define PECI_O_MIS 0x00000088 // PECI Masked Interrupt Status
#define PECI_O_IC 0x0000008C // PECI Interrupt Clear
#define PECI_O_ACADDR 0x00000100 // PECI Advanced Command Address
#define PECI_O_ACARG 0x00000104 // PECI Advanced Command Argument
#define PECI_O_ACRDWR0 0x00000108 // PECI Advanced Command Data 0
#define PECI_O_ACRDWR1 0x0000010C // PECI Advanced Command Data 1
#define PECI_O_ACCMD 0x00000110 // PECI Advanced Command
#define PECI_O_ACCODE 0x00000114 // PECI Advanced Command Completion
// Code
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_CTL register.
//
//*****************************************************************************
#define PECI_CTL_OFFSET_M 0xFFFF0000 // Offset Value
#define PECI_CTL_CRETRY_M 0x00007000 // Number of Controller Retries
#define PECI_CTL_BYERR 0x00000800 // Number of Retries
#define PECI_CTL_RXINV 0x00000400 // Invert PECI RX Input
#define PECI_CTL_M1D1EN 0x00000008 // Enable Microprocessor 1 and
// Domain 1
#define PECI_CTL_M1D0EN 0x00000004 // Enable Microprocessor 1 and
// Domain 0
#define PECI_CTL_M0D1EN 0x00000002 // Enable Microprocessor 0 and
// Domain 1
#define PECI_CTL_M0D0EN 0x00000001 // Enable Microprocessor 0 and
// Domain 0
#define PECI_CTL_OFFSET_S 16
#define PECI_CTL_CRETRY_S 12
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_DIV register.
//
//*****************************************************************************
#define PECI_DIV_BAUD_M 0xFFFF0000 // Initial Baud Rate
#define PECI_DIV_POLL_M 0x0000FFFF // Counter for Inter-Poll Delay
#define PECI_DIV_BAUD_S 16
#define PECI_DIV_POLL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_CMP register.
//
//*****************************************************************************
#define PECI_CMP_VREF_M 0x00000007 // Resistor Ladder Voltage Ref
#define PECI_CMP_VREF_0_5000V 0x00000000 // 0.5000
#define PECI_CMP_VREF_0_5125V 0x00000001 // 0.5125
#define PECI_CMP_VREF_0_5250V 0x00000002 // 0.5250
#define PECI_CMP_VREF_0_5375V 0x00000003 // 0.5375
#define PECI_CMP_VREF_0_5500V 0x00000004 // 0.5500
#define PECI_CMP_VREF_0_5625V 0x00000005 // 0.5625
#define PECI_CMP_VREF_0_6000V 0x00000006 // 0.6000
#define PECI_CMP_VREF_0_6625V 0x00000007 // 0.6625
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D0C register.
//
//*****************************************************************************
#define PECI_M0D0C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M0D0C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M0D0C_HITHR_S 16
#define PECI_M0D0C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D1C register.
//
//*****************************************************************************
#define PECI_M0D1C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M0D1C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M0D1C_HITHR_S 16
#define PECI_M0D1C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D0C register.
//
//*****************************************************************************
#define PECI_M1D0C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M1D0C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M1D0C_HITHR_S 16
#define PECI_M1D0C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D1C register.
//
//*****************************************************************************
#define PECI_M1D1C_HITHR_M 0xFFFF0000 // High Threshold
#define PECI_M1D1C_LOTHR_M 0x0000FFFF // Low Threshold
#define PECI_M1D1C_HITHR_S 16
#define PECI_M1D1C_LOTHR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D0 register.
//
//*****************************************************************************
#define PECI_M0D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M0D0_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M0D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M0D0_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M0D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M0D0_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M0D0_VALUE_TO 0x000081FD // Timeout error
#define PECI_M0D0_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M0D1 register.
//
//*****************************************************************************
#define PECI_M0D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M0D1_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M0D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M0D1_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M0D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M0D1_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M0D1_VALUE_TO 0x000081FD // Timeout error
#define PECI_M0D1_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D0 register.
//
//*****************************************************************************
#define PECI_M1D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M1D0_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M1D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M1D0_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M1D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M1D0_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M1D0_VALUE_TO 0x000081FD // Timeout error
#define PECI_M1D0_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_M1D1 register.
//
//*****************************************************************************
#define PECI_M1D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
#define PECI_M1D1_VALUE_M 0x0000FFFF // Last Value Read
#define PECI_M1D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
// on transmitted data
#define PECI_M1D1_VALUE_CRCRX 0x000081FA // CRC error on received data
#define PECI_M1D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
#define PECI_M1D1_VALUE_NEG 0x000081FC // Negotiation error
#define PECI_M1D1_VALUE_TO 0x000081FD // Timeout error
#define PECI_M1D1_MAXREAD_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_IM register.
//
//*****************************************************************************
#define PECI_IM_M1D1IM_M 0x00C00000 // Microprocessor 1 and Domain 1
// Interrupt Mask
#define PECI_IM_M1D1IM_HIGH 0x00400000 // Interrupt when value is above
// high threshold
#define PECI_IM_M1D1IM_CROSSUP 0x00800000 // Interrupt when crossing above
// either threshold
#define PECI_IM_M1D1IM_CROSSANY 0x00C00000 // Interrupt when crossing either
// threshold in either direction
#define PECI_IM_M1D0IM_M 0x00300000 // Microprocessor 1 and Domain 0
// Interrupt Mask
#define PECI_IM_M0D1IM_M 0x000C0000 // Microprocessor 0 and Domain 1
// Interrupt Mask
#define PECI_IM_M0D0IM_M 0x00030000 // Microprocessor 0 and Domain 0
// Interrupt Mask
#define PECI_IM_ACIM 0x00000004 // Advanced Command Interrupt Mask
#define PECI_IM_ERRIM 0x00000002 // Error Detected Interrupt Mask
#define PECI_IM_POLLIM 0x00000001 // Poll Completed Interrupt Mask
#define PECI_IM_M1D0IM_S 20
#define PECI_IM_M0D1IM_S 18
#define PECI_IM_M0D0IM_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_RIS register.
//
//*****************************************************************************
#define PECI_RIS_M1D1RIS_M 0x00C00000 // Microprocessor 1 and Domain 1
// Raw Interrupt Status
#define PECI_RIS_M1D0RIS_M 0x00300000 // Microprocessor 1 and Domain 0
// Raw Interrupt Status
#define PECI_RIS_M0D1RIS_M 0x000C0000 // Microprocessor 0 and Domain 1
// Raw Interrupt Status
#define PECI_RIS_M0D0RIS_M 0x00030000 // Microprocessor 0 and Domain 0
// Raw Interrupt Status
#define PECI_RIS_ACRIS 0x00000004 // Advanced Command Raw Interrupt
// Status
#define PECI_RIS_ERRRIS 0x00000002 // Error Detected Raw Interrupt
// Status
#define PECI_RIS_POLLRIS 0x00000001 // Poll Completed Raw Interrupt
// Status
#define PECI_RIS_M1D1RIS_S 22
#define PECI_RIS_M1D0RIS_S 20
#define PECI_RIS_M0D1RIS_S 18
#define PECI_RIS_M0D0RIS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_MIS register.
//
//*****************************************************************************
#define PECI_MIS_M1D1MIS_M 0x00C00000 // Microprocessor 1 and Domain 1
// Masked Interrupt Status
#define PECI_MIS_M1D0MIS_M 0x00300000 // Microprocessor 1 and Domain 0
// Masked Interrupt Status
#define PECI_MIS_M0D1MIS_M 0x000C0000 // Microprocessor 0 and Domain 1
// Masked Interrupt Status
#define PECI_MIS_M0D0MIS_M 0x00030000 // Microprocessor 0 and Domain 0
// Masked Interrupt Status
#define PECI_MIS_ACMIS 0x00000004 // Advanced Command Masked
// Interrupt Status
#define PECI_MIS_ERRMIS 0x00000002 // Error Detected Masked Interrupt
// Status
#define PECI_MIS_POLLMIS 0x00000001 // Poll Completed Masked Interrupt
// Status
#define PECI_MIS_M1D1MIS_S 22
#define PECI_MIS_M1D0MIS_S 20
#define PECI_MIS_M0D1MIS_S 18
#define PECI_MIS_M0D0MIS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_IC register.
//
//*****************************************************************************
#define PECI_IC_M1D1IC_M 0x00C00000 // Microprocessor 1 and Domain 1
// Interrupt Clear
#define PECI_IC_M1D0IC_M 0x00300000 // Microprocessor 1 and Domain 0
// Interrupt Clear
#define PECI_IC_M0D1IC_M 0x000C0000 // Microprocessor 0 and Domain 1
// Interrupt Clear
#define PECI_IC_M0D0IC_M 0x00030000 // Microprocessor 0 and Domain 0
// Interrupt Clear
#define PECI_IC_ACIC 0x00000004 // Advanced Command Interrupt Clear
#define PECI_IC_ERRIC 0x00000002 // Error Detected Interrupt Clear
#define PECI_IC_POLLIC 0x00000001 // Poll Completed Interrupt Clear
#define PECI_IC_M1D1IC_S 22
#define PECI_IC_M1D0IC_S 20
#define PECI_IC_M0D1IC_S 18
#define PECI_IC_M0D0IC_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACADDR register.
//
//*****************************************************************************
#define PECI_ACADDR_HIDRE_M 0xFF000000 // HostID and Retry
#define PECI_ACADDR_SIZE_M 0x00FF0000 // Size Override
#define PECI_ACADDR_DOMAIN_M 0x0000FF00 // Domain Select
#define PECI_ACADDR_PROCADD_M 0x000000FF // Processor Address
#define PECI_ACADDR_HIDRE_S 24
#define PECI_ACADDR_SIZE_S 16
#define PECI_ACADDR_DOMAIN_S 8
#define PECI_ACADDR_PROCADD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACARG register.
//
//*****************************************************************************
#define PECI_ACARG_ARG3_M 0xFF000000 // Argument 3
#define PECI_ACARG_ARG2_M 0x00FF0000 // Argument 2
#define PECI_ACARG_ARG1_M 0x0000FF00 // Argument 1
#define PECI_ACARG_ARG0_M 0x000000FF // Argument 0
#define PECI_ACARG_ARG3_S 24
#define PECI_ACARG_ARG2_S 16
#define PECI_ACARG_ARG1_S 8
#define PECI_ACARG_ARG0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACRDWR0 register.
//
//*****************************************************************************
#define PECI_ACRDWR0_D3_M 0xFF000000 // Data 3
#define PECI_ACRDWR0_D2_M 0x00FF0000 // Data 2
#define PECI_ACRDWR0_D1_M 0x0000FF00 // Data 1
#define PECI_ACRDWR0_D0_M 0x000000FF // Data 0
#define PECI_ACRDWR0_D3_S 24
#define PECI_ACRDWR0_D2_S 16
#define PECI_ACRDWR0_D1_S 8
#define PECI_ACRDWR0_D0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACRDWR1 register.
//
//*****************************************************************************
#define PECI_ACRDWR1_D3_M 0xFF000000 // Data 3
#define PECI_ACRDWR1_D2_M 0x00FF0000 // Data 2
#define PECI_ACRDWR1_D1_M 0x0000FF00 // Data 1
#define PECI_ACRDWR1_D0_M 0x000000FF // Data 0
#define PECI_ACRDWR1_D3_S 24
#define PECI_ACRDWR1_D2_S 16
#define PECI_ACRDWR1_D1_S 8
#define PECI_ACRDWR1_D0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACCMD register.
//
//*****************************************************************************
#define PECI_ACCMD_CMD_M 0x000000FF // Base Command
#define PECI_ACCMD_CMD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PECI_O_ACCODE register.
//
//*****************************************************************************
#define PECI_ACCODE_CODE_M 0xFFFFFFFF // Signed Completion Code
#endif // __HW_PECI_H__

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//*****************************************************************************
//
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_PWM_H__
#define __HW_PWM_H__
//*****************************************************************************
//
// The following are defines for the PWM register offsets.
//
//*****************************************************************************
#define PWM_O_CTL 0x00000000 // PWM Master Control
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion
#define PWM_O_FAULT 0x00000010 // PWM Output Fault
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
#define PWM_O_STATUS 0x00000020 // PWM Status
#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
#define PWM_O_ENUPD 0x00000028 // PWM Enable Update
#define PWM_O_0_CTL 0x00000040 // PWM0 Control
#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
// Enable
#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
// Falling-Edge-Delay
#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
#define PWM_O_1_CTL 0x00000080 // PWM1 Control
#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
// Enable
#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
// Falling-Edge-Delay
#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
// Enable
#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
// Falling-Edge-Delay
#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
#define PWM_O_3_CTL 0x00000100 // PWM3 Control
#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
// Enable
#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
// Falling-Edge-Delay
#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
#define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_CTL register.
//
//*****************************************************************************
#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_SYNC register.
//
//*****************************************************************************
#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENABLE register.
//
//*****************************************************************************
#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable
#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INVERT register.
//
//*****************************************************************************
#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal
#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal
#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULT register.
//
//*****************************************************************************
#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault
#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_INTEN register.
//
//*****************************************************************************
#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable
#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_RIS register.
//
//*****************************************************************************
#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted
#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ISC register.
//
//*****************************************************************************
#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted
#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_STATUS register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
//
//*****************************************************************************
#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value
#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value
#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value
#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value
#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value
#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value
#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_ENUPD register.
//
//*****************************************************************************
#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode
#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode
#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode
#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode
#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_CTL register.
//
//*****************************************************************************
#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_INTEN register.
//
//*****************************************************************************
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
// Down
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
// Down
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
// Down
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
// Up
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
// Down
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
// Up
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_RIS register.
//
//*****************************************************************************
#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
// Status
#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
// Status
#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_ISC register.
//
//*****************************************************************************
#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_LOAD register.
//
//*****************************************************************************
#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
#define PWM_X_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_COUNT register.
//
//*****************************************************************************
#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
#define PWM_X_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_CMPA register.
//
//*****************************************************************************
#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
#define PWM_X_CMPA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_CMPB register.
//
//*****************************************************************************
#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
#define PWM_X_CMPB_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_GENA register.
//
//*****************************************************************************
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_X_GENA_ACTCMPBD_NONE \
0x00000000 // Do nothing
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
#define PWM_X_GENA_ACTCMPBD_ZERO \
0x00000800 // Drive pwmA Low
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_X_GENA_ACTCMPBU_NONE \
0x00000000 // Do nothing
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
#define PWM_X_GENA_ACTCMPBU_ZERO \
0x00000200 // Drive pwmA Low
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_X_GENA_ACTCMPAD_NONE \
0x00000000 // Do nothing
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
#define PWM_X_GENA_ACTCMPAD_ZERO \
0x00000080 // Drive pwmA Low
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_X_GENA_ACTCMPAU_NONE \
0x00000000 // Do nothing
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
#define PWM_X_GENA_ACTCMPAU_ZERO \
0x00000020 // Drive pwmA Low
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_GENB register.
//
//*****************************************************************************
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
#define PWM_X_GENB_ACTCMPBD_NONE \
0x00000000 // Do nothing
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
#define PWM_X_GENB_ACTCMPBD_ZERO \
0x00000800 // Drive pwmB Low
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
#define PWM_X_GENB_ACTCMPBU_NONE \
0x00000000 // Do nothing
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
#define PWM_X_GENB_ACTCMPBU_ZERO \
0x00000200 // Drive pwmB Low
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
#define PWM_X_GENB_ACTCMPAD_NONE \
0x00000000 // Do nothing
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
#define PWM_X_GENB_ACTCMPAD_ZERO \
0x00000080 // Drive pwmB Low
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
#define PWM_X_GENB_ACTCMPAU_NONE \
0x00000000 // Do nothing
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
#define PWM_X_GENB_ACTCMPAU_ZERO \
0x00000020 // Drive pwmB Low
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
//
//*****************************************************************************
#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
//
//*****************************************************************************
#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
#define PWM_X_DBRISE_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
//
//*****************************************************************************
#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
#define PWM_X_DBFALL_DELAY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
// register.
//
//*****************************************************************************
#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
// register.
//
//*****************************************************************************
#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
// register.
//
//*****************************************************************************
#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
#define PWM_X_MINFLTPER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
//
//*****************************************************************************
#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
// register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
// register.
//
//*****************************************************************************
#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_PP register.
//
//*****************************************************************************
#define PWM_PP_GCNT_M 0x0000000F // Generators
#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs
#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
#define PWM_PP_EFAULT 0x00000200 // Extended Fault
#define PWM_PP_ONE 0x00000400 // One-Shot Mode
#define PWM_PP_GCNT_S 0
#define PWM_PP_FCNT_S 4
//*****************************************************************************
//
// The following are defines for the bit fields in the PWM_O_PC register.
//
//*****************************************************************************
#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor
#define PWM_PC_PWMDIV_2 0x00000000 // /2
#define PWM_PC_PWMDIV_4 0x00000001 // /4
#define PWM_PC_PWMDIV_8 0x00000002 // /8
#define PWM_PC_PWMDIV_16 0x00000003 // /16
#define PWM_PC_PWMDIV_32 0x00000004 // /32
#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default)
#define PWM_PC_USEOPWMDIV 0x00000100 // Enable PWM Clock Divisor
//*****************************************************************************
//
// The following are defines for the PWM Generator standard offsets.
//
//*****************************************************************************
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
//*****************************************************************************
//
// The following are defines for the PWM Generator extended offsets.
//
//*****************************************************************************
#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PWM_O_CTL
// register.
//
//*****************************************************************************
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the PWM_O_STATUS
// register.
//
//*****************************************************************************
#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status
//*****************************************************************************
//
// The following are deprecated defines for the PWM Interrupt Register bit
// definitions.
//
//*****************************************************************************
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Interrupt Status Register
// bit definitions.
//
//*****************************************************************************
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Generator A/B Control
// Register bit definitions.
//
//*****************************************************************************
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Generator A/B Control
// Register action definitions.
//
//*****************************************************************************
#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
//*****************************************************************************
//
// The following are deprecated defines for the PWM_X Dead Band Control
// Register bit definitions.
//
//*****************************************************************************
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
//*****************************************************************************
//
// The following are deprecated defines for the PWM Register reset values.
//
//*****************************************************************************
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
#define PWM_RV_STATUS 0x00000000 // Status
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
// generator block
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
// count
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
// output pins
#define PWM_RV_RIS 0x00000000 // Raw interrupt status
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
// pins
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
// count
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
// pins
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
#define PWM_RV_INTEN 0x00000000 // Interrupt enable
#define PWM_RV_X_COUNT 0x00000000 // The current counter value
#endif
#endif // __HW_PWM_H__

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//*****************************************************************************
//
// hw_qei.h - Macros used when accessing the QEI hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_QEI_H__
#define __HW_QEI_H__
//*****************************************************************************
//
// The following are defines for the QEI register offsets.
//
//*****************************************************************************
#define QEI_O_CTL 0x00000000 // QEI Control
#define QEI_O_STAT 0x00000004 // QEI Status
#define QEI_O_POS 0x00000008 // QEI Position
#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
#define QEI_O_LOAD 0x00000010 // QEI Timer Load
#define QEI_O_TIME 0x00000014 // QEI Timer
#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
#define QEI_O_SPEED 0x0000001C // QEI Velocity
#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_CTL register.
//
//*****************************************************************************
#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
#define QEI_CTL_INVB 0x00000400 // Invert PhB
#define QEI_CTL_INVA 0x00000200 // Invert PhA
#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
#define QEI_CTL_SWAP 0x00000002 // Swap Signals
#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
#define QEI_CTL_FILTCNT_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_STAT register.
//
//*****************************************************************************
#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
#define QEI_STAT_ERROR 0x00000001 // Error Detected
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_POS register.
//
//*****************************************************************************
#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
// Value
#define QEI_POS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_MAXPOS register.
//
//*****************************************************************************
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
// Value
#define QEI_MAXPOS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_LOAD register.
//
//*****************************************************************************
#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
#define QEI_LOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_TIME register.
//
//*****************************************************************************
#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
#define QEI_TIME_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_COUNT register.
//
//*****************************************************************************
#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
#define QEI_COUNT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_SPEED register.
//
//*****************************************************************************
#define QEI_SPEED_M 0xFFFFFFFF // Velocity
#define QEI_SPEED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_INTEN register.
//
//*****************************************************************************
#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
// Enable
#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
// Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_RIS register.
//
//*****************************************************************************
#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
//*****************************************************************************
//
// The following are defines for the bit fields in the QEI_O_ISC register.
//
//*****************************************************************************
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the QEI_ISC
// register.
//
//*****************************************************************************
#define QEI_INT_ERROR 0x00000008 // Phase error detected
#define QEI_INT_DIR 0x00000004 // Direction change
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
#define QEI_INT_INDEX 0x00000001 // Index pulse detected
//*****************************************************************************
//
// The following are deprecated defines for the reset values for the QEI
// registers.
//
//*****************************************************************************
#define QEI_RV_POS 0x00000000 // Current position register
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
#define QEI_RV_CTL 0x00000000 // Configuration and control reg
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
#define QEI_RV_ISC 0x00000000 // Interrupt status register
#define QEI_RV_SPEED 0x00000000 // Velocity speed register
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
#define QEI_RV_STAT 0x00000000 // Status register
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
#define QEI_RV_TIME 0x00000000 // Velocity timer register
#endif
#endif // __HW_QEI_H__

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//*****************************************************************************
//
// hw_ssi.h - Macros used when accessing the SSI hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // SSI Control 0
#define SSI_O_CR1 0x00000004 // SSI Control 1
#define SSI_O_DR 0x00000008 // SSI Data
#define SSI_O_SR 0x0000000C // SSI Status
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
// Serial Frame Format
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
#define SSI_CR0_SCR_S 8
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_EOT 0x00000010 // End of Transmission
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
// Enable
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
// Mask
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
// Status
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
// Status
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
// Interrupt Status
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
// Interrupt Status
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
// Interrupt Status
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
// Interrupt Status
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
// Clear
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
// Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
// PLL bypass is in effect) or the
// PLL output (default)
#define SSI_CC_CS_PIOSC 0x00000001 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CR0
// register.
//
//*****************************************************************************
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
#define SSI_CR0_DSS 0x0000000F // Data size select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the SSI_O_CPSR
// register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
//*****************************************************************************
//
// The following are deprecated defines for the SSI controller's FIFO size.
//
//*****************************************************************************
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the interrupt
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
// registers.
//
//*****************************************************************************
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
#endif
#endif // __HW_SSI_H__

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//*****************************************************************************
//
// hw_sysexc.h - Macros used when accessing the system exception module.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_SYSEXC_H__
#define __HW_SYSEXC_H__
//*****************************************************************************
//
// The following are defines for the System Exception Module register
// addresses.
//
//*****************************************************************************
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
// Status
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
#define SYSEXC_MIS 0x400F9008 // System Exception Raw Interrupt
// Status
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_RIS register.
//
//*****************************************************************************
#define SYSEXC_RIS_IXCRIS 0x00000020 // Inexact Exception Flag
#define SYSEXC_RIS_OFCRIS 0x00000010 // Overflow Exception Flag
#define SYSEXC_RIS_UFCRIS 0x00000008 // Underflow Exception Flag
#define SYSEXC_RIS_IOCRIS 0x00000004 // Invalid Operation Flag
#define SYSEXC_RIS_DZCRIS 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_RIS_IDCRIS 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IM register.
//
//*****************************************************************************
#define SYSEXC_IM_IXCIM 0x00000020 // Inexact Exception Flag
#define SYSEXC_IM_OFCIM 0x00000010 // Overflow Exception Flag
#define SYSEXC_IM_UFCIM 0x00000008 // Underflow Exception Flag
#define SYSEXC_IM_IOCIM 0x00000004 // Invalid Operation Flag
#define SYSEXC_IM_DZCIM 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_IM_IDCIM 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_MIS register.
//
//*****************************************************************************
#define SYSEXC_MIS_IXCMIS 0x00000020 // Inexact Exception Flag
#define SYSEXC_MIS_OFCMIS 0x00000010 // Overflow Exception Flag
#define SYSEXC_MIS_UFCMIS 0x00000008 // Underflow Exception Flag
#define SYSEXC_MIS_IOCMIS 0x00000004 // Invalid Operation Flag
#define SYSEXC_MIS_DZCMIS 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_MIS_IDCMIS 0x00000001 // Input Denormal Exception Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the SYSEXC_IC register.
//
//*****************************************************************************
#define SYSEXC_IC_IXCIC 0x00000020 // Inexact Exception Flag
#define SYSEXC_IC_OFCIC 0x00000010 // Overflow Exception Flag
#define SYSEXC_IC_UFCIC 0x00000008 // Underflow Exception Flag
#define SYSEXC_IC_IOCIC 0x00000004 // Invalid Operation Flag
#define SYSEXC_IC_DZCIC 0x00000002 // Divide By 0 Exception Flag
#define SYSEXC_IC_IDCIC 0x00000001 // Input Denormal Exception Flag
#endif // __HW_SYSEXC_H__

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//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the Timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
// 5
#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
// 4
#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
// 3
#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
// 2
#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
// 1
#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
// 0
#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
// GPTM 32/64-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM 32/64-Bit
// Timer 0 is triggered
#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
// 5
#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
// affected
#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 5 is
// triggered
#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 5 is triggered
#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
// 4
#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
// affected
#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 4 is
// triggered
#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 4 is triggered
#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
// 3
#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
// affected
#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 3 is
// triggered
#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 3 is triggered
#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
// 2
#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
// affected
#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 2 is
// triggered
#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 2 is triggered
#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
// 1
#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
// affected
#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 1 is
// triggered
#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 1 is triggered
#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
// 0
#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
// affected
#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
// GPTM 16/32-Bit Timer 0 is
// triggered
#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM 16/32-Bit
// Timer 0 is triggered
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Mask
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
// Interrupt Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
// Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
// Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
// Interrupt Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
// Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
// Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Raw Interrupt Status
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
// Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
// Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
// Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
// Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
// Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
// Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Masked Interrupt Status
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
// Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
// Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
// Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
// Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Clear
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
// Interrupt Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
// Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
// Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
// Interrupt Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
// Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
// Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
#define TIMER_TAILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
#define TIMER_TBILR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
#define TIMER_TAMATCHR_TAMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
#define TIMER_TBMATCHR_TBMR_S 0
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
#define TIMER_TAPR_TAPSRH_S 8
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
#define TIMER_TBPR_TBPSRH_S 8
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
#define TIMER_TAPMR_TAPSMRH_S 8
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
#define TIMER_TBPMR_TBPSMRH_S 8
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
#define TIMER_TAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
#define TIMER_TBR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
#define TIMER_TAV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
// 32 bits each with a 16-bit
// prescale counter
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CFG
// register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CTL
// register.
//
//*****************************************************************************
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_RIS
// register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
// register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
// register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAR
// register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBR
// register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the timer
// registers.
//
//*****************************************************************************
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnMR
// register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPR
// register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPMR
// register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
#endif
#endif // __HW_TIMER_H__

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//*****************************************************************************
//
// hw_types.h - Common types and macros.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile unsigned long *)(x)))
#define HWREGH(x) \
(*((volatile unsigned short *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
//*****************************************************************************
//
// Helper Macros for determining silicon revisions, etc.
//
// These macros will be used by Driverlib at "run-time" to create necessary
// conditional code blocks that will allow a single version of the Driverlib
// "binary" code to support multiple(all) Stellaris silicon revisions.
//
// It is expected that these macros will be used inside of a standard 'C'
// conditional block of code, e.g.
//
// if(CLASS_IS_SANDSTORM)
// {
// do some Sandstorm-class specific code here.
// }
//
// By default, these macros will be defined as run-time checks of the
// appropriate register(s) to allow creation of run-time conditional code
// blocks for a common DriverLib across the entire Stellaris family.
//
// However, if code-space optimization is required, these macros can be "hard-
// coded" for a specific version of Stellaris silicon. Many compilers will
// then detect the "hard-coded" conditionals, and appropriately optimize the
// code blocks, eliminating any "unreachable" code. This would result in
// a smaller Driverlib, thus producing a smaller final application size, but
// at the cost of limiting the Driverlib binary to a specific Stellaris
// silicon revision.
//
//*****************************************************************************
#ifndef CLASS_IS_SANDSTORM
#define CLASS_IS_SANDSTORM \
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
#endif
#ifndef CLASS_IS_FURY
#define CLASS_IS_FURY \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
#endif
#ifndef CLASS_IS_DUSTDEVIL
#define CLASS_IS_DUSTDEVIL \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
#endif
#ifndef CLASS_IS_TEMPEST
#define CLASS_IS_TEMPEST \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
#endif
#ifndef CLASS_IS_FIRESTORM
#define CLASS_IS_FIRESTORM \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
#endif
#ifndef CLASS_IS_BLIZZARD
#define CLASS_IS_BLIZZARD \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
#endif
#ifndef REVISION_IS_A0
#define REVISION_IS_A0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A1
#define REVISION_IS_A1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_A2
#define REVISION_IS_A2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_B0
#define REVISION_IS_B0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_B1
#define REVISION_IS_B1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C0
#define REVISION_IS_C0 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
#endif
#ifndef REVISION_IS_C1
#define REVISION_IS_C1 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
#endif
#ifndef REVISION_IS_C2
#define REVISION_IS_C2 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
#endif
#ifndef REVISION_IS_C3
#define REVISION_IS_C3 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
#endif
#ifndef REVISION_IS_C5
#define REVISION_IS_C5 \
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
#endif
//*****************************************************************************
//
// Deprecated silicon class and revision detection macros.
//
//*****************************************************************************
#ifndef DEPRECATED
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
#define DEVICE_IS_FURY CLASS_IS_FURY
#define DEVICE_IS_REVA2 REVISION_IS_A2
#define DEVICE_IS_REVC1 REVISION_IS_C1
#define DEVICE_IS_REVC2 REVISION_IS_C2
#endif
#endif // __HW_TYPES_H__

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//*****************************************************************************
//
// hw_uart.h - Macros and defines used when accessing the UART hardware.
//
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000 // UART Data
#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
#define UART_O_FR 0x00000018 // UART Flag
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
// Divisor
#define UART_O_LCRH 0x0000002C // UART Line Control
#define UART_O_CTL 0x00000030 // UART Control
#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
#define UART_O_IM 0x00000038 // UART Interrupt Mask
#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
#define UART_O_ICR 0x00000044 // UART Interrupt Clear
#define UART_O_DMACTL 0x00000048 // UART DMA Control
#define UART_O_LCTL 0x00000090 // UART LIN Control
#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
#define UART_O_LTIM 0x00000098 // UART LIN Timer
#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
#define UART_O_CC 0x00000FC8 // UART Clock Configuration
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//*****************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//*****************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//*****************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//*****************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//*****************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//*****************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//*****************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//*****************************************************************************
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//*****************************************************************************
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//*****************************************************************************
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//*****************************************************************************
#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//*****************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//*****************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
// (default)
#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//*****************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
#define UART_LSS_TSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//*****************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITADDR
// register.
//
//*****************************************************************************
#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_9BITAMASK
// register.
//
//*****************************************************************************
#define UART_9BITAMASK_RANGE_M 0x0000FF00 // Self Address Range for 9-Bit
// Mode
#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_RANGE_S 8
#define UART_9BITAMASK_MASK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//*****************************************************************************
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//*****************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//*****************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
#define UART_CC_CS_PIOSC 0x00000001 // PIOSC
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
#define UART_O_PeriphID4 0x00000FD0
#define UART_O_PeriphID5 0x00000FD4
#define UART_O_PeriphID6 0x00000FD8
#define UART_O_PeriphID7 0x00000FDC
#define UART_O_PeriphID0 0x00000FE0
#define UART_O_PeriphID1 0x00000FE4
#define UART_O_PeriphID2 0x00000FE8
#define UART_O_PeriphID3 0x00000FEC
#define UART_O_PCellID0 0x00000FF0
#define UART_O_PCellID1 0x00000FF4
#define UART_O_PCellID2 0x00000FF8
#define UART_O_PCellID3 0x00000FFC
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_DR
// register.
//
//*****************************************************************************
#define UART_DR_DATA_MASK 0x000000FF // UART data
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_IBRD
// register.
//
//*****************************************************************************
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_FBRD
// register.
//
//*****************************************************************************
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_LCR_H
// register.
//
//*****************************************************************************
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
#define UART_LCR_H_WLEN 0x00000060 // Word length
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
#define UART_LCR_H_PEN 0x00000002 // Parity Enable
#define UART_LCR_H_BRK 0x00000001 // Send Break
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_IFLS
// register.
//
//*****************************************************************************
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UART_O_ICR
// register.
//
//*****************************************************************************
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
UART_RSR_FE)
//*****************************************************************************
//
// The following are deprecated defines for the Reset Values for UART
// Registers.
//
//*****************************************************************************
#define UART_RV_CTL 0x00000300
#define UART_RV_PCellID1 0x000000F0
#define UART_RV_PCellID3 0x000000B1
#define UART_RV_FR 0x00000090
#define UART_RV_PeriphID2 0x00000018
#define UART_RV_IFLS 0x00000012
#define UART_RV_PeriphID0 0x00000011
#define UART_RV_PCellID0 0x0000000D
#define UART_RV_PCellID2 0x00000005
#define UART_RV_PeriphID3 0x00000001
#define UART_RV_PeriphID4 0x00000000
#define UART_RV_LCR_H 0x00000000
#define UART_RV_PeriphID6 0x00000000
#define UART_RV_DR 0x00000000
#define UART_RV_RSR 0x00000000
#define UART_RV_ECR 0x00000000
#define UART_RV_PeriphID5 0x00000000
#define UART_RV_RIS 0x00000000
#define UART_RV_FBRD 0x00000000
#define UART_RV_IM 0x00000000
#define UART_RV_MIS 0x00000000
#define UART_RV_ICR 0x00000000
#define UART_RV_PeriphID1 0x00000000
#define UART_RV_PeriphID7 0x00000000
#define UART_RV_IBRD 0x00000000
#endif
#endif // __HW_UART_H__

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bsp/lm4f232/Libraries/inc/hw_udma.h Normal file
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//*****************************************************************************
//
// hw_udma.h - Macros for use in accessing the UDMA registers.
//
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8049 of the Stellaris Firmware Development Package.
//
//*****************************************************************************
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access register
// addresses.
//
//*****************************************************************************
#define UDMA_STAT 0x400FF000 // DMA Status
#define UDMA_CFG 0x400FF004 // DMA Configuration
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
// Base Pointer
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
// Status
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
// Set
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
// Clear
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_STAT register.
//
//*****************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
#define UDMA_STAT_STATE_RD_SRCENDP \
0x00000020 // Reading source end pointer
#define UDMA_STAT_STATE_RD_DSTENDP \
0x00000030 // Reading destination end pointer
#define UDMA_STAT_STATE_RD_SRCDAT \
0x00000040 // Reading source data
#define UDMA_STAT_STATE_WR_DSTDAT \
0x00000050 // Writing destination data
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
// clear
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
#define UDMA_STAT_STATE_DONE 0x00000090 // Done
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
#define UDMA_STAT_DMACHANS_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CFG register.
//
//*****************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CTLBASE register.
//
//*****************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
#define UDMA_CTLBASE_ADDR_S 10
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer
#define UDMA_ALTBASE_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTSET
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKSET
// register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKCLR
// register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHASGN register.
//
//*****************************************************************************
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
// assignment
#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
// assignment
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHIS register.
//
//*****************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
//
//*****************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
//
//*****************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
//
//*****************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
//
//*****************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_S 0
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the Micro Direct Memory Access
// register addresses.
//
//*****************************************************************************
#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UDMA_ENASET
// register.
//
//*****************************************************************************
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the UDMA_CHALT
// register.
//
//*****************************************************************************
#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
// Select
#endif
#endif // __HW_UDMA_H__

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