2014-07-18 17:17:56 +08:00
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//*****************************************************************************
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//
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// startup_gcc.c - Startup code for use with GNU tools.
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//
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2017-04-25 18:02:51 +08:00
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// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved.
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2014-07-18 17:17:56 +08:00
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// Software License Agreement
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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2021-06-26 12:37:09 +08:00
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//
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2017-04-25 18:02:51 +08:00
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// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package.
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2014-07-18 17:17:56 +08:00
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//
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//*****************************************************************************
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#include <stdint.h>
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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//*****************************************************************************
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//
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// Forward declaration of the default fault handlers.
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//
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//*****************************************************************************
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void ResetISR(void);
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static void NmiSR(void);
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static void FaultISR(void);
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static void IntDefaultHandler(void);
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//*****************************************************************************
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//
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// The entry point for the application.
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//
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//*****************************************************************************
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extern int main(void);
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extern void SysTick_Handler(void);
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extern void PendSV_Handler(void);
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2014-07-21 19:09:15 +08:00
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extern void UART0_IRQHandler(void);
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extern void HardFault_Handler(void);
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2014-07-18 17:17:56 +08:00
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//*****************************************************************************
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//
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// Reserve space for the system stack.
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//
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//*****************************************************************************
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static uint32_t pui32Stack[64];
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//*****************************************************************************
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//
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// The vector table. Note that the proper constructs must be placed on this to
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// ensure that it ends up at physical address 0x0000.0000.
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//
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//*****************************************************************************
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__attribute__ ((section(".isr_vector")))
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void (* const g_pfnVectors[])(void) =
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{
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(void (*)(void))((uint32_t)pui32Stack + sizeof(pui32Stack)),
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// The initial stack pointer
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ResetISR, // The reset handler
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NmiSR, // The NMI handler
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2014-07-21 19:09:15 +08:00
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HardFault_Handler, // The hard fault handler
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2014-07-18 17:17:56 +08:00
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IntDefaultHandler, // The MPU fault handler
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IntDefaultHandler, // The bus fault handler
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IntDefaultHandler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // SVCall handler
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IntDefaultHandler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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IntDefaultHandler, // GPIO Port A
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IntDefaultHandler, // GPIO Port B
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IntDefaultHandler, // GPIO Port C
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IntDefaultHandler, // GPIO Port D
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IntDefaultHandler, // GPIO Port E
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2014-07-21 19:09:15 +08:00
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UART0_IRQHandler, // UART0 Rx and Tx
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2014-07-18 17:17:56 +08:00
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IntDefaultHandler, // UART1 Rx and Tx
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IntDefaultHandler, // SSI0 Rx and Tx
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IntDefaultHandler, // I2C0 Master and Slave
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IntDefaultHandler, // PWM Fault
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IntDefaultHandler, // PWM Generator 0
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IntDefaultHandler, // PWM Generator 1
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IntDefaultHandler, // PWM Generator 2
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IntDefaultHandler, // Quadrature Encoder 0
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IntDefaultHandler, // ADC Sequence 0
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IntDefaultHandler, // ADC Sequence 1
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IntDefaultHandler, // ADC Sequence 2
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IntDefaultHandler, // ADC Sequence 3
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IntDefaultHandler, // Watchdog timer
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IntDefaultHandler, // Timer 0 subtimer A
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IntDefaultHandler, // Timer 0 subtimer B
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IntDefaultHandler, // Timer 1 subtimer A
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IntDefaultHandler, // Timer 1 subtimer B
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IntDefaultHandler, // Timer 2 subtimer A
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IntDefaultHandler, // Timer 2 subtimer B
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IntDefaultHandler, // Analog Comparator 0
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IntDefaultHandler, // Analog Comparator 1
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IntDefaultHandler, // Analog Comparator 2
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IntDefaultHandler, // System Control (PLL, OSC, BO)
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IntDefaultHandler, // FLASH Control
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IntDefaultHandler, // GPIO Port F
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IntDefaultHandler, // GPIO Port G
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IntDefaultHandler, // GPIO Port H
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IntDefaultHandler, // UART2 Rx and Tx
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IntDefaultHandler, // SSI1 Rx and Tx
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IntDefaultHandler, // Timer 3 subtimer A
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IntDefaultHandler, // Timer 3 subtimer B
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IntDefaultHandler, // I2C1 Master and Slave
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IntDefaultHandler, // CAN0
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IntDefaultHandler, // CAN1
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IntDefaultHandler, // Ethernet
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IntDefaultHandler, // Hibernate
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IntDefaultHandler, // USB0
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IntDefaultHandler, // PWM Generator 3
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IntDefaultHandler, // uDMA Software Transfer
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IntDefaultHandler, // uDMA Error
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IntDefaultHandler, // ADC1 Sequence 0
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IntDefaultHandler, // ADC1 Sequence 1
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IntDefaultHandler, // ADC1 Sequence 2
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IntDefaultHandler, // ADC1 Sequence 3
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IntDefaultHandler, // External Bus Interface 0
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IntDefaultHandler, // GPIO Port J
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IntDefaultHandler, // GPIO Port K
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IntDefaultHandler, // GPIO Port L
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IntDefaultHandler, // SSI2 Rx and Tx
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IntDefaultHandler, // SSI3 Rx and Tx
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IntDefaultHandler, // UART3 Rx and Tx
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IntDefaultHandler, // UART4 Rx and Tx
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IntDefaultHandler, // UART5 Rx and Tx
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IntDefaultHandler, // UART6 Rx and Tx
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IntDefaultHandler, // UART7 Rx and Tx
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IntDefaultHandler, // I2C2 Master and Slave
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IntDefaultHandler, // I2C3 Master and Slave
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IntDefaultHandler, // Timer 4 subtimer A
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IntDefaultHandler, // Timer 4 subtimer B
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IntDefaultHandler, // Timer 5 subtimer A
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IntDefaultHandler, // Timer 5 subtimer B
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IntDefaultHandler, // FPU
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // I2C4 Master and Slave
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IntDefaultHandler, // I2C5 Master and Slave
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IntDefaultHandler, // GPIO Port M
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IntDefaultHandler, // GPIO Port N
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0, // Reserved
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IntDefaultHandler, // Tamper
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IntDefaultHandler, // GPIO Port P (Summary or P0)
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IntDefaultHandler, // GPIO Port P1
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IntDefaultHandler, // GPIO Port P2
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IntDefaultHandler, // GPIO Port P3
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IntDefaultHandler, // GPIO Port P4
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IntDefaultHandler, // GPIO Port P5
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IntDefaultHandler, // GPIO Port P6
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IntDefaultHandler, // GPIO Port P7
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IntDefaultHandler, // GPIO Port Q (Summary or Q0)
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IntDefaultHandler, // GPIO Port Q1
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IntDefaultHandler, // GPIO Port Q2
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IntDefaultHandler, // GPIO Port Q3
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IntDefaultHandler, // GPIO Port Q4
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IntDefaultHandler, // GPIO Port Q5
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IntDefaultHandler, // GPIO Port Q6
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IntDefaultHandler, // GPIO Port Q7
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IntDefaultHandler, // GPIO Port R
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IntDefaultHandler, // GPIO Port S
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IntDefaultHandler, // SHA/MD5 0
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IntDefaultHandler, // AES 0
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IntDefaultHandler, // DES3DES 0
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IntDefaultHandler, // LCD Controller 0
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IntDefaultHandler, // Timer 6 subtimer A
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IntDefaultHandler, // Timer 6 subtimer B
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IntDefaultHandler, // Timer 7 subtimer A
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IntDefaultHandler, // Timer 7 subtimer B
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IntDefaultHandler, // I2C6 Master and Slave
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IntDefaultHandler, // I2C7 Master and Slave
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IntDefaultHandler, // HIM Scan Matrix Keyboard 0
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IntDefaultHandler, // One Wire 0
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IntDefaultHandler, // HIM PS/2 0
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IntDefaultHandler, // HIM LED Sequencer 0
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IntDefaultHandler, // HIM Consumer IR 0
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IntDefaultHandler, // I2C8 Master and Slave
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IntDefaultHandler, // I2C9 Master and Slave
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IntDefaultHandler // GPIO Port T
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};
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//*****************************************************************************
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//
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// The following are constructs created by the linker, indicating where the
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// the "data" and "bss" segments reside in memory. The initializers for the
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// for the "data" segment resides immediately following the "text" segment.
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//
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//*****************************************************************************
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2017-12-31 21:19:52 +08:00
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extern uint32_t _sidata;
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extern uint32_t _sdata;
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2014-07-18 17:17:56 +08:00
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extern uint32_t _edata;
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2017-12-31 21:19:52 +08:00
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extern uint32_t _sbss;
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2014-07-18 17:17:56 +08:00
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extern uint32_t _ebss;
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//*****************************************************************************
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//
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// This is the code that gets called when the processor first starts execution
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// following a reset event. Only the absolutely necessary set is performed,
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// after which the application supplied entry() routine is called. Any fancy
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// actions (such as making decisions based on the reset cause register, and
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// resetting the bits in that register) are left solely in the hands of the
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// application.
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//
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//*****************************************************************************
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2020-11-24 10:46:50 +08:00
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void ResetISR(void)
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2014-07-18 17:17:56 +08:00
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{
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uint32_t *pui32Src, *pui32Dest;
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//
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// Copy the data segment initializers from flash to SRAM.
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//
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2017-12-31 21:19:52 +08:00
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pui32Src = &_sidata;
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for(pui32Dest = &_sdata; pui32Dest < &_edata; )
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2014-07-18 17:17:56 +08:00
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{
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*pui32Dest++ = *pui32Src++;
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}
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//
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// Zero fill the bss segment.
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//
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2017-12-31 21:19:52 +08:00
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__asm(" ldr r0, =_sbss\n"
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2014-07-18 17:17:56 +08:00
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" ldr r1, =_ebss\n"
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" mov r2, #0\n"
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" .thumb_func\n"
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"zero_loop:\n"
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" cmp r0, r1\n"
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" it lt\n"
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" strlt r2, [r0], #4\n"
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" blt zero_loop");
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//
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// Enable the floating-point unit. This must be done here to handle the
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// case where main() uses floating-point and the function prologue saves
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// floating-point registers (which will fault if floating-point is not
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// enabled). Any configuration of the floating-point unit using DriverLib
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// APIs must be done here prior to the floating-point unit being enabled.
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//
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// Note that this does not use DriverLib since it might not be included in
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// this project.
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//
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HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
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~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
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NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
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//
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// Call the application's entry point.
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//
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2020-11-24 10:46:50 +08:00
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extern int entry(void);
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entry();
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2014-07-18 17:17:56 +08:00
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}
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//*****************************************************************************
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//
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// This is the code that gets called when the processor receives a NMI. This
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// simply enters an infinite loop, preserving the system state for examination
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// by a debugger.
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//
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//*****************************************************************************
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static void
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NmiSR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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{
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}
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}
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//*****************************************************************************
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//
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// This is the code that gets called when the processor receives a fault
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// interrupt. This simply enters an infinite loop, preserving the system state
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// for examination by a debugger.
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//
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//*****************************************************************************
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static void
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FaultISR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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{
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}
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}
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//*****************************************************************************
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//
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// This is the code that gets called when the processor receives an unexpected
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// interrupt. This simply enters an infinite loop, preserving the system state
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// for examination by a debugger.
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//
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//*****************************************************************************
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static void
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IntDefaultHandler(void)
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{
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//
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// Go into an infinite loop.
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//
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while(1)
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{
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|
}
|
|
|
|
|
}
|
