2014-07-18 17:17:56 +08:00
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//*****************************************************************************
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//
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// hw_hibernate.h - Defines and Macros for the Hibernation module.
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//
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2021-06-26 12:37:09 +08:00
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// Copyright (c) 2007-2020 Texas Instruments Incorporated. All rights reserved.
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2014-07-18 17:17:56 +08:00
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// Software License Agreement
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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2021-06-26 12:37:09 +08:00
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// documentation and/or other materials provided with the
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2014-07-18 17:17:56 +08:00
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// distribution.
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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2021-06-26 12:37:09 +08:00
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//
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2014-07-18 17:17:56 +08:00
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2021-06-26 12:37:09 +08:00
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//
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// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
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2014-07-18 17:17:56 +08:00
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//
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//*****************************************************************************
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#ifndef __HW_HIBERNATE_H__
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#define __HW_HIBERNATE_H__
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//*****************************************************************************
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//
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// The following are defines for the Hibernation module register addresses.
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//
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//*****************************************************************************
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#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
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#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
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#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
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#define HIB_CTL 0x400FC010 // Hibernation Control
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#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
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#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
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#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
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// Status
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#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
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#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
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#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
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#define HIB_IO 0x400FC02C // Hibernation IO Configuration
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#define HIB_DATA 0x400FC030 // Hibernation Data
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#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control
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#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0
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#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1
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#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0
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#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load
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#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0
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#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1
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#define HIB_LOCK 0x400FC360 // Hibernation Lock
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#define HIB_TPCTL 0x400FC400 // HIB Tamper Control
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#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status
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#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control
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#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0
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#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1
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#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2
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#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3
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#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4
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#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5
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#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6
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#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7
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#define HIB_PP 0x400FCFC0 // Hibernation Peripheral
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// Properties
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#define HIB_CC 0x400FCFC8 // Hibernation Clock Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCC register.
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//
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//*****************************************************************************
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#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
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#define HIB_RTCC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCM0 register.
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//
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//*****************************************************************************
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#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
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#define HIB_RTCM0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCLD register.
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//
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//*****************************************************************************
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#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
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#define HIB_RTCLD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CTL register.
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//
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//*****************************************************************************
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#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
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#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear
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#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select
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#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
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#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
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#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
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// Comparator
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#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
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#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
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#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
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#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
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#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
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#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
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#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
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#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
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#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
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#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable
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#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
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#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
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#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IM register.
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//
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//*****************************************************************************
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#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
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#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
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// Mask
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#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
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#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
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// Interrupt Mask
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#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
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#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
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// Mask
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#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RIS register.
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//
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//*****************************************************************************
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#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status
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#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw
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// Interrupt Status
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#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt
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// Status
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#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
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// Interrupt Status
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#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
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// Status
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#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
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// Interrupt Status
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#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_MIS register.
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//
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//*****************************************************************************
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#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
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#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
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// Mask
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#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
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#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
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// Interrupt Status
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#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
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// Interrupt Status
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#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
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// Interrupt Status
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#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
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// Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IC register.
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//
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//*****************************************************************************
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#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear
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#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
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// Clear
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#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear
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#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt
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// Clear
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#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear
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#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
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// Clear
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#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
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// Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCT register.
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//
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//*****************************************************************************
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#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
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#define HIB_RTCT_TRIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_RTCSS register.
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//
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//*****************************************************************************
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#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
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#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
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#define HIB_RTCSS_RTCSSM_S 16
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#define HIB_RTCSS_RTCSSC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_IO register.
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//
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//*****************************************************************************
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#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete
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#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable
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#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration
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// Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_DATA register.
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//
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//*****************************************************************************
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#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
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#define HIB_DATA_RTD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CALCTL register.
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//
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//*****************************************************************************
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#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode
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#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CAL0 register.
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//
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//*****************************************************************************
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#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load
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#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation
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#define HIB_CAL0_HR_M 0x001F0000 // Hours
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#define HIB_CAL0_MIN_M 0x00003F00 // Minutes
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#define HIB_CAL0_SEC_M 0x0000003F // Seconds
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#define HIB_CAL0_HR_S 16
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#define HIB_CAL0_MIN_S 8
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#define HIB_CAL0_SEC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CAL1 register.
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//
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//*****************************************************************************
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#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load
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#define HIB_CAL1_DOW_M 0x07000000 // Day of Week
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#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value
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#define HIB_CAL1_MON_M 0x00000F00 // Month
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#define HIB_CAL1_DOM_M 0x0000001F // Day of Month
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#define HIB_CAL1_DOW_S 24
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#define HIB_CAL1_YEAR_S 16
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#define HIB_CAL1_MON_S 8
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#define HIB_CAL1_DOM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CALLD0 register.
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//
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//*****************************************************************************
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#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation
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#define HIB_CALLD0_HR_M 0x001F0000 // Hours
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#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes
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#define HIB_CALLD0_SEC_M 0x0000003F // Seconds
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#define HIB_CALLD0_HR_S 16
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#define HIB_CALLD0_MIN_S 8
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#define HIB_CALLD0_SEC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CALLD1 register.
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//
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//*****************************************************************************
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#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week
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#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value
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#define HIB_CALLD1_MON_M 0x00000F00 // Month
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#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month
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#define HIB_CALLD1_DOW_S 24
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#define HIB_CALLD1_YEAR_S 16
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#define HIB_CALLD1_MON_S 8
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#define HIB_CALLD1_DOM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CALM0 register.
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//
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//*****************************************************************************
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#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation
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#define HIB_CALM0_HR_M 0x001F0000 // Hours
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#define HIB_CALM0_MIN_M 0x00003F00 // Minutes
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#define HIB_CALM0_SEC_M 0x0000003F // Seconds
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#define HIB_CALM0_HR_S 16
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#define HIB_CALM0_MIN_S 8
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#define HIB_CALM0_SEC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_CALM1 register.
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//
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//*****************************************************************************
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#define HIB_CALM1_DOM_M 0x0000001F // Day of Month
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#define HIB_CALM1_DOM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_LOCK register.
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//
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//*****************************************************************************
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#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock
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#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key
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#define HIB_LOCK_HIBLOCK_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_TPCTL register.
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//
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//*****************************************************************************
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#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper
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// Event
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#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event
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#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on
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// tamper event
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#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB
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// memory on tamper event
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#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB
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// memory on tamper event
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#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper
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// event
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#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear
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#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_TPSTAT register.
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//
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//*****************************************************************************
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#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status
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#define HIB_TPSTAT_STATE_DISABLED \
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0x00000000 // Tamper disabled
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#define HIB_TPSTAT_STATE_CONFIGED \
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0x00000004 // Tamper configured
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#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred
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#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status
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#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the HIB_TPIO register.
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//
|
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//*****************************************************************************
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#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering
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#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up
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// Enable
|
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#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level
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#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable
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#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering
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#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up
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// Enable
|
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#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level
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#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable
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#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering
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#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up
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// Enable
|
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#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level
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#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable
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#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering
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#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up
|
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|
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// Enable
|
|
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|
|
#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level
|
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|
|
#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable
|
|
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|
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|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG0 register.
|
|
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|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
|
|
|
|
#define HIB_TPLOG0_TIME_S 0
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG1 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32
|
|
|
|
|
#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
|
|
|
|
#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
|
|
|
|
#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
|
|
|
|
#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG2 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
|
|
|
|
#define HIB_TPLOG2_TIME_S 0
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG3 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32
|
|
|
|
|
#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
|
|
|
|
#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
|
|
|
|
#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
|
|
|
|
#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG4 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
|
|
|
|
#define HIB_TPLOG4_TIME_S 0
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG5 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32
|
|
|
|
|
#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
|
|
|
|
#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
|
|
|
|
#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
|
|
|
|
#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG6 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
|
|
|
|
|
#define HIB_TPLOG6_TIME_S 0
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_TPLOG7 register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32
|
|
|
|
|
#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger
|
|
|
|
|
#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger
|
|
|
|
|
#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger
|
|
|
|
|
#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_PP register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence
|
|
|
|
|
#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// The following are defines for the bit fields in the HIB_CC register.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable
|
|
|
|
|
|
|
|
|
|
#endif // __HW_HIBERNATE_H__
|
