add_unify_clip_grad_norm_op_on_gpu
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/**
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* Copyright 2021 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "backend/kernel_compiler/gpu/cuda_impl/clip_grad_norm_impl.cuh"
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// The implement of ScalingGradOp
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template <typename T>
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__global__ void ScalingGradKernel(const size_t size, const T *x, const float *scaling_factor, float *scaling_out_addr) {
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for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < size; i += gridDim.x * blockDim.x) {
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scaling_out_addr[i] = x[i] * (1.0 / scaling_factor[0]);
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}
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}
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template <>
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__global__ void ScalingGradKernel(const size_t size, const half *x, const float *scaling_factor,
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float *scaling_out_addr) {
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for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < size; i += gridDim.x * blockDim.x) {
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scaling_out_addr[i] = __half2float(x[i]) * (1.0 / scaling_factor[0]);
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}
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}
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template <typename T>
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void ScalingGradOp(const size_t size, const T *x, const float *scaling_factor, float *scaling_out_addr,
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cudaStream_t cuda_stream) {
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ScalingGradKernel<<<GET_BLOCKS(size), GET_THREADS, 0, cuda_stream>>>(size, x, scaling_factor, scaling_out_addr);
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}
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template void ScalingGradOp<float>(const size_t size, const float *x, const float *scaling_factor,
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float *scaling_out_addr, cudaStream_t cuda_stream);
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template void ScalingGradOp<half>(const size_t size, const half *x, const float *scaling_factor,
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float *scaling_out_addr, cudaStream_t cuda_stream);
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// The implement of ClipGradNormOp
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template <typename T>
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__global__ void ClipGradNormKernel(const size_t size, const float *x, const T *clip_norm, const float *reduce_sum_value,
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float *output_addr) {
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for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < size; i += gridDim.x * blockDim.x) {
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if (reduce_sum_value[0] > clip_norm[0]) {
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output_addr[i] = x[i] * clip_norm[0] / reduce_sum_value[0];
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} else {
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output_addr[i] = x[i];
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}
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}
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}
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template <>
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__global__ void ClipGradNormKernel(const size_t size, const float *x, const half *clip_norm,
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const float *reduce_sum_value, float *output_addr) {
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for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < size; i += gridDim.x * blockDim.x) {
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const float clip_norm_float = __half2float(clip_norm[0]);
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if (reduce_sum_value[0] > clip_norm_float) {
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output_addr[i] = x[i] * clip_norm_float / reduce_sum_value[0];
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} else {
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output_addr[i] = x[i];
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}
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}
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}
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template <typename T>
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void ClipGradNormOp(const size_t size, const float *x, const T *clip_norm, const float *reduce_sum_value,
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float *output_addr, cudaStream_t cuda_stream) {
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ClipGradNormKernel<<<GET_BLOCKS(size), GET_THREADS, 0, cuda_stream>>>(size, x, clip_norm, reduce_sum_value,
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output_addr);
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}
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template void ClipGradNormOp<float>(const size_t size, const float *x, const float *clip_norm,
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const float *reduce_sum_value, float *output_addr, cudaStream_t cuda_stream);
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template void ClipGradNormOp<half>(const size_t size, const float *x, const half *clip_norm,
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const float *reduce_sum_value, float *output_addr, cudaStream_t cuda_stream);
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/**
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* Copyright 2021 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_CLIP_GRAD_NORM_IMPL_H_
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#define MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_CLIP_GRAD_NORM_IMPL_H_
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#include "runtime/device/gpu/cuda_common.h"
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template <typename T>
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void ScalingGradOp(const size_t size, const T *x, const float *scaling_factor, float *scaling_out_addr,
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cudaStream_t cuda_stream);
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template <typename T>
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void ClipGradNormOp(const size_t size, const float *x, const T *clip_norm, const float *reduce_sum_value,
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float *output_addr, cudaStream_t cuda_stream);
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#endif // MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_CLIP_GRAD_NORM_IMPL_H_
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/**
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* Copyright 2021 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "backend/kernel_compiler/gpu/nn/clip_grad_norm_gpu_kernel.h"
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namespace mindspore::kernel {
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MS_REG_GPU_KERNEL_ONE(ClipGradNorm,
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KernelAttr()
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeFloat32)
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.AddInputAttr(kNumberTypeFloat32)
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.AddOutputAttr(kNumberTypeFloat32),
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ClipGradNormGpuKernel, float)
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MS_REG_GPU_KERNEL_ONE(ClipGradNorm,
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KernelAttr()
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeFloat16)
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.AddInputAttr(kNumberTypeFloat32)
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.AddOutputAttr(kNumberTypeFloat32),
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ClipGradNormGpuKernel, half)
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} // namespace mindspore::kernel
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/**
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* Copyright 2021 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_CLIP_GRAD_NORM_GPU_KERNEL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_CLIP_GRAD_NORM_GPU_KERNEL_H_
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#include <string>
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#include <vector>
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#include <algorithm>
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#include "utils/log_adapter.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
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#include "backend/kernel_compiler/gpu/kernel_constants.h"
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#include "backend/kernel_compiler/gpu/cuda_impl/clip_grad_norm_impl.cuh"
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namespace mindspore::kernel {
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constexpr size_t kArgMaxDim = 7;
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template <typename T>
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class ClipGradNormGpuKernel : public GpuKernel {
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public:
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ClipGradNormGpuKernel()
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: cudnn_handle_(nullptr),
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data_type_(CUDNN_DATA_FLOAT),
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nan_prop_(CUDNN_NOT_PROPAGATE_NAN),
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reduce_indices_(CUDNN_REDUCE_TENSOR_NO_INDICES),
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reduce_tensor_descriptor_(nullptr),
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input_descriptor_(nullptr),
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output_descriptor_(nullptr),
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all_match_(false),
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is_null_input_(false),
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x_size_(0),
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clip_norm_size_(0),
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scaling_factor_size_(0),
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output_size_(0),
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workspace_size_(0) {}
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~ClipGradNormGpuKernel() override { DestroyResource(); }
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const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
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const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
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const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
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bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
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const std::vector<AddressPtr> &outputs, void *stream_ptr) override {
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if (is_null_input_) {
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return true;
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}
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// Get address
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constexpr size_t input_num_expected = 3;
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constexpr size_t workspace_num_expected = 3;
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MS_EXCEPTION_IF_CHECK_FAIL(inputs.size() == input_num_expected, "Size not equal");
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MS_EXCEPTION_IF_CHECK_FAIL(workspace.size() == workspace_num_expected, "Size not equal");
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MS_EXCEPTION_IF_CHECK_FAIL(outputs.size() == 1, "Size not equal");
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constexpr size_t scaling_factor_index = 2;
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constexpr size_t reduce_out_index = 2;
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T *x_addr = GetDeviceAddress<T>(inputs, 0);
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T *clip_norm_addr = GetDeviceAddress<T>(inputs, 1);
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float *scaling_factor_addr = GetDeviceAddress<float>(inputs, scaling_factor_index);
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float *scaling_out_addr = GetDeviceAddress<float>(workspace, 0);
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float *reduce_workspace_addr = GetPossiblyNullDeviceAddress<float>(workspace, 1);
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float *reduce_out_addr = GetDeviceAddress<float>(workspace, reduce_out_index);
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float *output_addr = GetDeviceAddress<float>(outputs, 0);
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// Run gradient tensor scaling.
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ScalingGradOp(x_size_ / sizeof(T), x_addr, scaling_factor_addr, scaling_out_addr,
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reinterpret_cast<cudaStream_t>(stream_ptr));
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// Run reduce sum operation(keep_dims=True) for gradient tensor.
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constexpr size_t alpha = 1;
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constexpr size_t beta = 0;
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if (all_match_) {
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CHECK_CUDA_RET_WITH_EXCEPT(
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kernel_node_,
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cudaMemcpyAsync(reduce_out_addr, scaling_out_addr, workspace_size_list_[reduce_out_index],
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cudaMemcpyDeviceToDevice, reinterpret_cast<cudaStream_t>(stream_ptr)),
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"cudaMemcpyAsync for 'ClipGradNormGpuKernel' failed");
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} else {
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CHECK_CUDNN_RET_WITH_EXCEPT(
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kernel_node_,
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cudnnReduceTensor(cudnn_handle_, reduce_tensor_descriptor_, nullptr, 0, reduce_workspace_addr,
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workspace_size_list_[1], &alpha, input_descriptor_, scaling_out_addr, &beta,
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output_descriptor_, reduce_out_addr),
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"cudnnReduceTensor for 'ClipGradNormGpuKernel' failed");
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}
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// Update gradient tensor by argument 'clip_norm'
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ClipGradNormOp(output_size_ / sizeof(float), scaling_out_addr, clip_norm_addr, reduce_out_addr, output_addr,
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reinterpret_cast<cudaStream_t>(stream_ptr));
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return true;
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}
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bool Init(const CNodePtr &kernel_node) override {
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MS_EXCEPTION_IF_NULL(kernel_node);
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auto kernel_name = AnfAlgo::GetCNodeName(kernel_node);
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MS_EXCEPTION_IF_CHECK_FAIL(kernel_name == "ClipGradNorm", "Kernel name is not ClipGradNorm");
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kernel_node_ = kernel_node;
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// Init resource for cudnnreducetensor operation.
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InitResource();
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if (!CheckIONumber(kernel_node)) {
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return false;
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}
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// Check input and output shape
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auto input_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
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auto output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
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size_t input_dim = input_shape.size();
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if (!CheckValidShape(input_shape, output_shape, input_dim)) {
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return true;
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}
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// Init member variables.
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InitAxis(kernel_node, output_shape, SizeToInt(input_dim));
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clip_norm_size_ = sizeof(T);
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scaling_factor_size_ = sizeof(float);
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x_size_ = sizeof(T);
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output_size_ = sizeof(float);
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std::for_each(output_shape.begin(), output_shape.end(), [this](const size_t &v) {
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x_size_ *= v;
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output_size_ *= v;
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});
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InitShapeInfo(input_shape, output_shape);
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// Determine the reduce operation.
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CHECK_CUDNN_RET_WITH_EXCEPT(
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kernel_node_,
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cudnnSetReduceTensorDescriptor(reduce_tensor_descriptor_, CUDNN_REDUCE_TENSOR_NORM2, CUDNN_DATA_FLOAT, nan_prop_,
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reduce_indices_, CUDNN_32BIT_INDICES),
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"cudnnSetReduceTensorDescriptor failed");
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InitSizeLists();
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return true;
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}
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protected:
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void InitResource() override {
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cudnn_handle_ = device::gpu::GPUDeviceManager::GetInstance().GetCudnnHandle();
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CHECK_CUDNN_RET_WITH_EXCEPT(kernel_node_, cudnnCreateReduceTensorDescriptor(&reduce_tensor_descriptor_),
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"cudnnCreateReduceTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_EXCEPT(kernel_node_, cudnnCreateTensorDescriptor(&input_descriptor_),
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"cudnnCreateTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_EXCEPT(kernel_node_, cudnnCreateTensorDescriptor(&output_descriptor_),
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"cudnnCreateTensorDescriptor failed.");
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}
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void InitSizeLists() override {
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input_size_list_.emplace_back(x_size_);
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input_size_list_.emplace_back(clip_norm_size_);
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input_size_list_.emplace_back(scaling_factor_size_);
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output_size_list_.emplace_back(output_size_);
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// Init workspace size for gradient tensor scaling calculate.
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workspace_size_list_.emplace_back(output_size_);
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// Init workspace size for gradient tensor reduce sum calculate.
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CHECK_CUDNN_RET_WITH_EXCEPT(kernel_node_,
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cudnnGetReductionWorkspaceSize(cudnn_handle_, reduce_tensor_descriptor_,
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input_descriptor_, output_descriptor_, &workspace_size_),
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"cudnnGetReductionWorkspaceSize failed.");
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workspace_size_list_.emplace_back(workspace_size_);
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CHECK_CUDNN_RET_WITH_EXCEPT(kernel_node_, cudnnGetTensorSizeInBytes(output_descriptor_, &workspace_size_),
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"cudnnGetTensorSizeInBytes failed.");
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workspace_size_list_.emplace_back(workspace_size_);
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}
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private:
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void DestroyResource() noexcept {
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CHECK_CUDNN_RET_WITH_ERROR(kernel_node_, cudnnDestroyReduceTensorDescriptor(reduce_tensor_descriptor_),
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"cudnnDestroyReduceTensorDescriptor failed.");
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||||||
|
CHECK_CUDNN_RET_WITH_ERROR(kernel_node_, cudnnDestroyTensorDescriptor(input_descriptor_),
|
||||||
|
"cudnnDestroyTensorDescriptor failed.");
|
||||||
|
CHECK_CUDNN_RET_WITH_ERROR(kernel_node_, cudnnDestroyTensorDescriptor(output_descriptor_),
|
||||||
|
"cudnnDestroyTensorDescriptor failed.");
|
||||||
|
}
|
||||||
|
|
||||||
|
bool CheckIONumber(const CNodePtr &kernel_node) {
|
||||||
|
MS_EXCEPTION_IF_NULL(kernel_node);
|
||||||
|
constexpr size_t input_num_expected = 3;
|
||||||
|
size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
|
||||||
|
if (input_num != input_num_expected) {
|
||||||
|
MS_LOG(ERROR) << "The input number of kernel node [" << kernel_node->DebugString() << "] should be "
|
||||||
|
<< input_num_expected << ", but got " << input_num;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
|
||||||
|
if (output_num != 1) {
|
||||||
|
MS_LOG(ERROR) << "The output number of kernel node [" << kernel_node->DebugString() << "] should be " << 1
|
||||||
|
<< ", but got " << output_num;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool CheckValidShape(const std::vector<size_t> &input_shape, const std::vector<size_t> &output_shape,
|
||||||
|
size_t input_dim) {
|
||||||
|
is_null_input_ = CHECK_NULL_INPUT(input_shape) || CHECK_NULL_INPUT(output_shape);
|
||||||
|
if (is_null_input_) {
|
||||||
|
MS_LOG(WARNING) << "For 'ClipGradNormGpuKernel', input or output is null.";
|
||||||
|
InitSizeLists();
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
if (input_shape.size() != output_shape.size()) {
|
||||||
|
MS_LOG(EXCEPTION) << "The size of input shape: " << input_shape.size()
|
||||||
|
<< " and the size of output shape: " << output_shape.size() << " are different.";
|
||||||
|
}
|
||||||
|
if (input_dim > kArgMaxDim) {
|
||||||
|
MS_LOG(EXCEPTION) << "Broadcast operation is not supported when dim exceeds than " << kArgMaxDim;
|
||||||
|
}
|
||||||
|
CheckTensorSize({input_shape, output_shape});
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitAxis(const CNodePtr &kernel_node, const std::vector<size_t> &output_shape, int input_dim) {
|
||||||
|
MS_EXCEPTION_IF_NULL(kernel_node);
|
||||||
|
auto prim = AnfAlgo::GetCNodePrimitive(kernel_node);
|
||||||
|
MS_EXCEPTION_IF_NULL(prim);
|
||||||
|
if (prim->GetAttr("axis")->isa<ValueTuple>() || prim->GetAttr("axis")->isa<ValueList>()) {
|
||||||
|
std::vector<int64_t> attr_axis = GetAttr<std::vector<int64_t>>(kernel_node, "axis");
|
||||||
|
if (!attr_axis.empty()) {
|
||||||
|
std::vector<int> attr_axis_int;
|
||||||
|
(void)std::transform(attr_axis.begin(), attr_axis.end(), std::back_inserter(attr_axis_int),
|
||||||
|
[](const int64_t &v) { return LongToInt(v); });
|
||||||
|
for (const auto &v : attr_axis_int) {
|
||||||
|
v < 0 ? axis_.emplace_back(v + input_dim) : axis_.emplace_back(v);
|
||||||
|
}
|
||||||
|
std::sort(axis_.begin(), axis_.end());
|
||||||
|
auto multiple_ops = std::unique(axis_.begin(), axis_.end());
|
||||||
|
(void)axis_.erase(multiple_ops, axis_.end());
|
||||||
|
}
|
||||||
|
} else if (prim->GetAttr("axis")->isa<Int64Imm>()) {
|
||||||
|
int axis = LongToInt(GetAttr<int64_t>(kernel_node, "axis"));
|
||||||
|
axis < 0 ? axis_.emplace_back(axis + input_dim) : axis_.emplace_back(axis);
|
||||||
|
} else {
|
||||||
|
MS_LOG(EXCEPTION) << "The attribute axis type is invalid.";
|
||||||
|
}
|
||||||
|
|
||||||
|
bool exceed_bound =
|
||||||
|
std::any_of(axis_.begin(), axis_.end(), [&input_dim](const int &v) { return v < 0 || v >= input_dim; });
|
||||||
|
if (exceed_bound) {
|
||||||
|
MS_LOG(EXCEPTION) << "For 'ClipGradNormGpuKernel', the value of axis should be in range of [-" << input_dim
|
||||||
|
<< ", " << (input_dim - 1) << "].";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void InitShapeInfo(const std::vector<size_t> &input_shape, const std::vector<size_t> &output_shape) {
|
||||||
|
// Determine which dimension will be reduced.
|
||||||
|
std::vector<size_t> reduce_output_shape = output_shape;
|
||||||
|
if (axis_.empty()) {
|
||||||
|
std::fill(reduce_output_shape.begin(), reduce_output_shape.end(), 1);
|
||||||
|
} else {
|
||||||
|
std::for_each(axis_.begin(), axis_.end(), [&reduce_output_shape](const int &v) { reduce_output_shape[v] = 1; });
|
||||||
|
}
|
||||||
|
// Whether is all matched.
|
||||||
|
all_match_ = true;
|
||||||
|
input_shape_.resize(kArgMaxDim, 1);
|
||||||
|
output_shape_.resize(kArgMaxDim, 1);
|
||||||
|
reduce_output_shape_.resize(kArgMaxDim, 1);
|
||||||
|
for (size_t i = 0; i < output_shape.size(); ++i) {
|
||||||
|
input_shape_[i] = input_shape[i];
|
||||||
|
output_shape_[i] = output_shape[i];
|
||||||
|
reduce_output_shape_[i] = reduce_output_shape[i];
|
||||||
|
if (input_shape_[i] != reduce_output_shape_[i]) {
|
||||||
|
all_match_ = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
// Infer input and output descriptor.
|
||||||
|
InferInAndOutDesc(input_shape, reduce_output_shape);
|
||||||
|
}
|
||||||
|
|
||||||
|
void InferInAndOutDesc(const std::vector<size_t> &input_shape, const std::vector<size_t> &reduce_output_shape) {
|
||||||
|
constexpr size_t split_dim = 4;
|
||||||
|
constexpr size_t dim_idx_two = 2;
|
||||||
|
constexpr size_t dim_idx_three = 3;
|
||||||
|
if (input_shape.size() <= split_dim) {
|
||||||
|
std::vector<size_t> new_input_shape;
|
||||||
|
ShapeNdTo4d(input_shape, &new_input_shape);
|
||||||
|
CHECK_CUDNN_RET_WITH_EXCEPT(
|
||||||
|
kernel_node_,
|
||||||
|
cudnnSetTensor4dDescriptor(input_descriptor_, CUDNN_TENSOR_NCHW, data_type_, new_input_shape[0],
|
||||||
|
new_input_shape[1], new_input_shape[dim_idx_two], new_input_shape[dim_idx_three]),
|
||||||
|
"cudnnSetTensor4dDescriptor failed");
|
||||||
|
} else {
|
||||||
|
CudnnSetTensorNdDescriptor(input_shape, input_descriptor_, data_type_, kernel_node_);
|
||||||
|
}
|
||||||
|
if (reduce_output_shape.size() <= split_dim) {
|
||||||
|
std::vector<size_t> new_reduce_output_shape;
|
||||||
|
ShapeNdTo4d(reduce_output_shape, &new_reduce_output_shape);
|
||||||
|
CHECK_CUDNN_RET_WITH_EXCEPT(
|
||||||
|
kernel_node_,
|
||||||
|
cudnnSetTensor4dDescriptor(output_descriptor_, CUDNN_TENSOR_NCHW, data_type_, new_reduce_output_shape[0],
|
||||||
|
new_reduce_output_shape[1], new_reduce_output_shape[dim_idx_two],
|
||||||
|
new_reduce_output_shape[dim_idx_three]),
|
||||||
|
"cudnnSetTensor4dDescriptor failed");
|
||||||
|
} else {
|
||||||
|
CudnnSetTensorNdDescriptor(reduce_output_shape, output_descriptor_, data_type_, kernel_node_);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
cudnnHandle_t cudnn_handle_;
|
||||||
|
cudnnDataType_t data_type_;
|
||||||
|
cudnnNanPropagation_t nan_prop_;
|
||||||
|
cudnnReduceTensorIndices_t reduce_indices_;
|
||||||
|
cudnnReduceTensorDescriptor_t reduce_tensor_descriptor_;
|
||||||
|
cudnnTensorDescriptor_t input_descriptor_;
|
||||||
|
cudnnTensorDescriptor_t output_descriptor_;
|
||||||
|
|
||||||
|
bool all_match_{false};
|
||||||
|
bool is_null_input_{false};
|
||||||
|
size_t x_size_;
|
||||||
|
size_t clip_norm_size_;
|
||||||
|
size_t scaling_factor_size_;
|
||||||
|
size_t output_size_;
|
||||||
|
size_t workspace_size_;
|
||||||
|
std::vector<int> axis_;
|
||||||
|
std::vector<size_t> input_size_list_;
|
||||||
|
std::vector<size_t> output_size_list_;
|
||||||
|
std::vector<size_t> workspace_size_list_;
|
||||||
|
// Used for broadcast operation.
|
||||||
|
std::vector<size_t> input_shape_;
|
||||||
|
std::vector<size_t> output_shape_;
|
||||||
|
std::vector<size_t> reduce_output_shape_;
|
||||||
|
};
|
||||||
|
} // namespace mindspore::kernel
|
||||||
|
|
||||||
|
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_NN_CLIP_GRAD_NORM_GPU_KERNEL_H_
|
||||||
|
|
@ -1475,3 +1475,83 @@ class Cummin(Primitive):
|
||||||
def __init__(self, axis):
|
def __init__(self, axis):
|
||||||
"""Initialize Cummin"""
|
"""Initialize Cummin"""
|
||||||
validator.check_value_type('axis', axis, [int], self.name)
|
validator.check_value_type('axis', axis, [int], self.name)
|
||||||
|
|
||||||
|
|
||||||
|
class ClipGradNorm(PrimitiveWithInfer):
|
||||||
|
r"""
|
||||||
|
Clips gradient tensor to a maximum :math:`L_2`-norm.
|
||||||
|
|
||||||
|
First, the input gradient tensor will be scaled as:
|
||||||
|
|
||||||
|
.. math::
|
||||||
|
\text{output}(x) = x * \frac{1}{\text{scaling_factor}},
|
||||||
|
|
||||||
|
Then, the output gradient tensor remains the same if the :math:`L_2`-norm of the input gradient tensor
|
||||||
|
is not greater than the argument clip_norm. Otherwise the input gradient tensor will be normalized as:
|
||||||
|
|
||||||
|
.. math::
|
||||||
|
\text{output}(x) = \frac{x * \text{clip_norm}}{L_2(x)},
|
||||||
|
|
||||||
|
where :math:`L_2(x)` is the :math:`L_2`-norm of :math:`x`.
|
||||||
|
|
||||||
|
Args:
|
||||||
|
axis (Union[None, int, tuple(int)]): Computes the L2-norm along the specific dimension.
|
||||||
|
Default: None, all dimensions to calculate.
|
||||||
|
|
||||||
|
Inputs:
|
||||||
|
- **x** (Tensor) - The gradient tensor of shape N-D. The type must be float32 or float16.
|
||||||
|
- **clip_norm** (Tensor) - A scalar Tensor of shape :math:`()` or :math:`(1)`. The type keeps same with 'x'
|
||||||
|
- **scaling_factor** (Tensor) - A scalar Tensor of shape :math:`()` or :math:`(1)`, whose type is float32.
|
||||||
|
|
||||||
|
Outputs:
|
||||||
|
Tensor, clipped gradient tensor with the same shape as the `x`, whose type is float32.
|
||||||
|
|
||||||
|
Raises:
|
||||||
|
TypeError: If `axis` is not one of None, int, and tuple(int).
|
||||||
|
TypeError: If dtype of `x` is neither float16 nor float32.
|
||||||
|
TypeError: If shape of 'clip_norm' is neither '()' nor '(1)'.
|
||||||
|
TypeError: If shape of 'scaling_factor' is neither '()' nor '(1)'.
|
||||||
|
|
||||||
|
Supported Platforms:
|
||||||
|
``GPU``
|
||||||
|
|
||||||
|
Examples:
|
||||||
|
>>> clip_grad_norm = ops.ClipGradNorm()
|
||||||
|
>>> x = Tensor(np.random.randint(0, 10, [4, 16]), mindspore.float32)
|
||||||
|
>>> clip_norm = Tensor(np.array([100]).astype(np.float32))
|
||||||
|
>>> scaling_factor = Tensor(np.array([2]).astype(np.float32))
|
||||||
|
>>> output = clip_grad_norm(x, clip_norm, scaling_factor)
|
||||||
|
>>> print(output.shape)
|
||||||
|
(4, 16)
|
||||||
|
"""
|
||||||
|
|
||||||
|
@prim_attr_register
|
||||||
|
def __init__(self, axis=None):
|
||||||
|
"""Initialize ClipGradNorm"""
|
||||||
|
if axis is None:
|
||||||
|
axis = ()
|
||||||
|
axis = (axis,) if isinstance(axis, int) else axis
|
||||||
|
validator.check_value_type('axis', axis, [tuple], self.name)
|
||||||
|
if axis:
|
||||||
|
raise TypeError(f"For '{self.name}', the length of 'axis' only supports 0 now, but got {len(axis)}, "
|
||||||
|
f"It will be supported later!")
|
||||||
|
self.add_prim_attr('axis', axis)
|
||||||
|
self.init_attrs['axis'] = axis
|
||||||
|
self.axis = axis
|
||||||
|
|
||||||
|
def infer_shape(self, x_shape, clip_norm_shape, scaling_factor_shape):
|
||||||
|
x_dim = len(x_shape)
|
||||||
|
for _, value in enumerate(self.axis):
|
||||||
|
validator.check_int_range(value, -x_dim, x_dim, Rel.INC_LEFT, 'axis value', self.name)
|
||||||
|
clip_norm_dim = len(clip_norm_shape)
|
||||||
|
validator.check_int_range(clip_norm_dim, 0, 1, Rel.INC_BOTH, 'clip norm dim', self.name)
|
||||||
|
scaling_factor_dim = len(scaling_factor_shape)
|
||||||
|
validator.check_int_range(scaling_factor_dim, 0, 1, Rel.INC_BOTH, 'scaling factor dim', self.name)
|
||||||
|
return x_shape
|
||||||
|
|
||||||
|
def infer_dtype(self, x_type, clip_norm_type, scaling_factor_type):
|
||||||
|
validator.check_tensor_dtype_valid("x_type", x_type, [mstype.float16, mstype.float32], self.name)
|
||||||
|
validator.check_tensor_dtype_valid("clip_norm_type", clip_norm_type,
|
||||||
|
[mstype.float16, mstype.float32], self.name)
|
||||||
|
validator.check_tensor_dtype_valid("scaling_factor_type", scaling_factor_type, [mstype.float32], self.name)
|
||||||
|
return mstype.float32
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,93 @@
|
||||||
|
# Copyright 2021 Huawei Technologies Co., Ltd
|
||||||
|
#
|
||||||
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
# you may not use this file except in compliance with the License.
|
||||||
|
# You may obtain a copy of the License at
|
||||||
|
#
|
||||||
|
# http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
#
|
||||||
|
# Unless required by applicable law or agreed to in writing, software
|
||||||
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
# See the License for the specific language governing permissions and
|
||||||
|
# limitations under the License.
|
||||||
|
# ============================================================================
|
||||||
|
|
||||||
|
import numpy as np
|
||||||
|
import pytest
|
||||||
|
|
||||||
|
import mindspore as ms
|
||||||
|
import mindspore.nn as nn
|
||||||
|
import mindspore.context as context
|
||||||
|
from mindspore.ops import operations as P
|
||||||
|
from mindspore.ops.operations import _inner_ops
|
||||||
|
from mindspore.common.tensor import Tensor
|
||||||
|
|
||||||
|
|
||||||
|
@pytest.mark.level0
|
||||||
|
@pytest.mark.platform_x86_gpu_training
|
||||||
|
@pytest.mark.env_onecard
|
||||||
|
def test_clip_grad_norm():
|
||||||
|
"""
|
||||||
|
Feature: ClipGradNorm Operation function verification.
|
||||||
|
Description: The calculation results of 'ops.ClipGradNorm' should be same with the 'nn.ClipByNorm'.
|
||||||
|
Expectation: Normal output without assert wrong.
|
||||||
|
"""
|
||||||
|
clip_norm = Tensor(np.array([1.0]), ms.float16)
|
||||||
|
scaling_factor = Tensor(np.array([65536]), ms.float32)
|
||||||
|
|
||||||
|
# test input arg with shape(32, 3, 224, 224)
|
||||||
|
x = np.random.rand(32, 3, 224, 224) * 100 - 50
|
||||||
|
x = Tensor(x, ms.float16)
|
||||||
|
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
|
||||||
|
# test input arg with shape(60, 224, 224)
|
||||||
|
x = np.random.rand(60, 224, 224) * 100 - 50
|
||||||
|
x = Tensor(x, ms.float16)
|
||||||
|
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
|
||||||
|
# test input arg with shape(21128, 60)
|
||||||
|
x = np.random.rand(21128, 60) * 100 - 50
|
||||||
|
x = Tensor(x, ms.float16)
|
||||||
|
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
|
||||||
|
# test input args with shape(60)
|
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|
x = np.random.rand(60) * 100 - 50
|
||||||
|
x = Tensor(x, ms.float16)
|
||||||
|
context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
|
context.set_context(mode=context.PYNATIVE_MODE, device_target="GPU")
|
||||||
|
scaling_out = x * P.Reciprocal()(scaling_factor)
|
||||||
|
clip_by_norm_out = nn.ClipByNorm()(scaling_out, clip_norm)
|
||||||
|
clip_grad_norm_out = _inner_ops.ClipGradNorm()(x, clip_norm, scaling_factor)
|
||||||
|
assert np.allclose(clip_by_norm_out.asnumpy(), clip_grad_norm_out.asnumpy(), 0.00000001, 0.00000001)
|
||||||
Loading…
Reference in New Issue