llvm-project/llvm/lib/Target/Sparc
Daniel Sanders 41c072e63b Add infrastructure for support of multiple memory constraints.
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171

llvm-svn: 232027
2015-03-12 11:00:48 +00:00
..
AsmParser Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers. 2015-01-03 08:16:34 +00:00
Disassembler Pass an ArrayRef to MCDisassembler::getInstruction. 2014-11-12 02:04:27 +00:00
InstPrinter Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. 2015-02-19 11:38:11 +00:00
MCTargetDesc Remove the use of the subtarget in MCCodeEmitter creation and 2015-03-10 22:03:14 +00:00
TargetInfo
CMakeLists.txt Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
DelaySlotFiller.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
LLVMBuild.txt
Makefile Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
README.txt JIT support has been added awhile ago. 2014-08-30 14:52:34 +00:00
Sparc.h Reinstate "Nuke the old JIT." 2014-09-02 22:28:02 +00:00
Sparc.td [Sparc] Add VIS instructions to sparc backend. 2014-03-02 19:31:21 +00:00
SparcAsmPrinter.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcCallingConv.td The SPARCv9 ABI returns a float in %f0. 2014-01-12 04:13:17 +00:00
SparcFrameLowering.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcFrameLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcISelDAGToDAG.cpp Add infrastructure for support of multiple memory constraints. 2015-03-12 11:00:48 +00:00
SparcISelLowering.cpp Have getCallPreservedMask and getThisCallPreservedMask take a 2015-03-11 22:42:13 +00:00
SparcISelLowering.h getRegForInlineAsmConstraint wants to use TargetRegisterInfo for 2015-02-26 22:38:43 +00:00
SparcInstr64Bit.td Sparc: disable printing on longer "brX,pt" aliases 2014-05-16 09:41:35 +00:00
SparcInstrAliases.td Sparc: disable printing of jmp/call aliases (C++ does it) 2014-05-16 09:41:39 +00:00
SparcInstrFormats.td [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend. 2014-03-02 23:39:07 +00:00
SparcInstrInfo.cpp Remove the need to cache the subtarget in the Sparc TargetRegisterInfo 2015-03-12 05:55:26 +00:00
SparcInstrInfo.h Remove the need to cache the subtarget in the Sparc TargetRegisterInfo 2015-03-12 05:55:26 +00:00
SparcInstrInfo.td Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcInstrVIS.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcMCInstLower.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcRegisterInfo.cpp Remove the need to cache the subtarget in the Sparc TargetRegisterInfo 2015-03-12 05:55:26 +00:00
SparcRegisterInfo.h Remove some unnecessary forward declarations and put a couple more 2015-03-12 06:07:16 +00:00
SparcRegisterInfo.td [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3). 2014-03-02 02:12:33 +00:00
SparcSelectionDAGInfo.cpp Have SparcSelectionDAGInfo take a DataLayout to initialize since 2014-06-26 22:33:52 +00:00
SparcSelectionDAGInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcSubtarget.cpp Reuse a bunch of cached subtargets and remove getSubtarget calls 2015-01-30 23:46:43 +00:00
SparcSubtarget.h Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
SparcTargetMachine.cpp Move the DataLayout to the generic TargetMachine, making it mandatory. 2015-03-12 00:07:24 +00:00
SparcTargetMachine.h Move the DataLayout to the generic TargetMachine, making it mandatory. 2015-03-12 00:07:24 +00:00
SparcTargetObjectFile.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcTargetObjectFile.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetStreamer.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.