forked from OSchip/llvm-project
74 lines
2.8 KiB
LLVM
74 lines
2.8 KiB
LLVM
; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck \
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; RUN: %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S \
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; RUN: -passes=msan 2>&1 | FileCheck -check-prefix=CHECK \
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; RUN: -check-prefix=CHECK-ORIGINS %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck -check-prefix=CHECK -check-prefix=CHECK-ORIGINS %s
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; REQUIRES: x86-registered-target
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Store intrinsic.
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define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable sanitize_memory {
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call void @llvm.x86.sse.storeu.ps(i8* %p, <4 x float> %x)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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; CHECK-LABEL: @StoreIntrinsic
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; CHECK-NOT: br
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; CHECK-NOT: = or
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; CHECK: store <4 x i32> {{.*}} align 1
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; CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 1{{$}}
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; CHECK: ret void
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; Load intrinsic.
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define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable sanitize_memory {
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%call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p)
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ret <16 x i8> %call
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}
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declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind
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; CHECK-LABEL: @LoadIntrinsic
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; CHECK: load <16 x i8>, <16 x i8>* {{.*}} align 1
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; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, i32* {{.*}}
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; CHECK-NOT: br
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; CHECK-NOT: = or
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; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq
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; CHECK: store <16 x i8> {{.*}} @__msan_retval_tls
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; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], i32* @__msan_retval_origin_tls
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; CHECK: ret <16 x i8>
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; Simple NoMem intrinsic
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; Check that shadow is OR'ed, and origin is Select'ed
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; And no shadow checks!
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define <8 x i16> @Pmulhuw128(<8 x i16> %a, <8 x i16> %b) nounwind uwtable sanitize_memory {
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%call = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %call
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}
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declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b) nounwind
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; CHECK-LABEL: @Pmulhuw128
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; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
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; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls
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; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls
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; CHECK-NEXT: = or <8 x i16>
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; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128
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; CHECK-ORIGINS-NEXT: = icmp ne i128 {{.*}}, 0
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; CHECK-ORIGINS-NEXT: = select i1 {{.*}}, i32 {{.*}}, i32
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; CHECK-NEXT: call <8 x i16> @llvm.x86.sse2.pmulhu.w
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; CHECK-NEXT: store <8 x i16> {{.*}} @__msan_retval_tls
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; CHECK-ORIGINS: store i32 {{.*}} @__msan_retval_origin_tls
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; CHECK-NEXT: ret <8 x i16>
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