forked from OSchip/llvm-project
56 lines
1.9 KiB
LLVM
56 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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define void @julia__typed_vcat_20() #0 {
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; CHECK-LABEL: julia__typed_vcat_20:
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; CHECK: # %bb.0: # %top
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: li r30, 0
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %L139
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; CHECK-NEXT: #
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; CHECK-NEXT: addi r3, r3, -1
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; CHECK-NEXT: mtfprd f0, r3
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; CHECK-NEXT: xscvsxdsp f1, f0
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl __gnu_h2f_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bne+ cr0, .LBB0_1
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; CHECK-NEXT: # %bb.2: # %pass.1
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; CHECK-NEXT: bl __gnu_f2h_ieee
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; CHECK-NEXT: nop
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; CHECK-NEXT: sth r3, 0(r3)
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top:
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%.sroa.6.0.copyload = load i64, i64 addrspace(11)* null, align 8
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%0 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %.sroa.6.0.copyload, i64 0)
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%1 = extractvalue { i64, i1 } %0, 0
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br label %L139
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L139: ; preds = %L139, %top
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%value_phi21 = phi i64 [ %5, %L139 ], [ 1, %top ]
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%value_phi23 = phi i64 [ 0, %L139 ], [ 1, %top ]
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%2 = add nsw i64 %value_phi23, -1
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%3 = add i64 %2, 0
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%4 = sitofp i64 %3 to half
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store half %4, half addrspace(13)* undef, align 2
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%.not101.not = icmp eq i64 %value_phi21, 0
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%5 = add i64 %value_phi21, 1
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br i1 %.not101.not, label %pass.1, label %L139
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pass.1: ; preds = %L139
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unreachable
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) #0
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attributes #0 = { nounwind }
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