llvm-project/polly/test/CodeGen/MemAccess/simple_stride___%for.cond--...

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{
"context" : "{ : }",
"name" : "for.cond => for.end",
"statements" : [
{
"accesses" : [
{
"kind" : "read",
"relation" : "{ Stmt_for_body[i0] -> MemRef_B[0] }"
},
{
"kind" : "write",
"relation" : "{ Stmt_for_body[i0] -> MemRef_A[i0] }"
}
],
"domain" : "{ Stmt_for_body[i0] : i0 >= 0 and i0 <= 15 }",
"name" : "Stmt_for_body",
"schedule" : "{ Stmt_for_body[i0] -> [0, i0, 0] }"
}
]
}