forked from OSchip/llvm-project
87 lines
3.3 KiB
C++
87 lines
3.3 KiB
C++
//=- llvm/CodeGen/AntiDepBreaker.h - Anti-Dependence Breaking -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AntiDepBreaker class, which implements
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// anti-dependence breaking heuristics for post-register-allocation scheduling.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
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#define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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namespace llvm {
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/// This class works in conjunction with the post-RA scheduler to rename
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/// registers to break register anti-dependencies (WAR hazards).
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class LLVM_LIBRARY_VISIBILITY AntiDepBreaker {
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public:
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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DbgValueVector;
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virtual ~AntiDepBreaker();
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/// Initialize anti-dep breaking for a new basic block.
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virtual void StartBlock(MachineBasicBlock *BB) =0;
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/// Identifiy anti-dependencies within a basic-block region and break them by
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/// renaming registers. Return the number of anti-dependencies broken.
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virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned InsertPosIndex,
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DbgValueVector &DbgValues) = 0;
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/// Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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virtual void Observe(MachineInstr &MI, unsigned Count,
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unsigned InsertPosIndex) = 0;
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/// Finish anti-dep breaking for a basic block.
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virtual void FinishBlock() =0;
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/// Update DBG_VALUE if dependency breaker is updating
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/// other machine instruction to use NewReg.
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void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
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assert(MI.isDebugValue() && "MI is not DBG_VALUE!");
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if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
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MI.getOperand(0).setReg(NewReg);
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}
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/// Update all DBG_VALUE instructions that may be affected by the dependency
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/// breaker's update of ParentMI to use NewReg.
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void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
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unsigned OldReg, unsigned NewReg) {
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// The following code is dependent on the order in which the DbgValues are
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// constructed in ScheduleDAGInstrs::buildSchedGraph.
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MachineInstr *PrevDbgMI = nullptr;
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for (const auto &DV : make_range(DbgValues.crbegin(), DbgValues.crend())) {
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MachineInstr *PrevMI = DV.second;
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if ((PrevMI == ParentMI) || (PrevMI == PrevDbgMI)) {
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MachineInstr *DbgMI = DV.first;
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UpdateDbgValue(*DbgMI, OldReg, NewReg);
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PrevDbgMI = DbgMI;
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} else if (PrevDbgMI) {
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break; // If no match and already found a DBG_VALUE, we're done.
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}
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}
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}
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};
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}
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#endif
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