forked from OSchip/llvm-project
55 lines
1.8 KiB
C++
55 lines
1.8 KiB
C++
//===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#include "llvm/Config/config.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/DataTypes.h"
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#include <memory>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class Target;
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MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
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bool Is64Bit);
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}
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// Defines symbolic names for RISC-V registers.
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#define GET_REGINFO_ENUM
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#include "RISCVGenRegisterInfo.inc"
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// Defines symbolic names for RISC-V instructions.
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#define GET_INSTRINFO_ENUM
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#include "RISCVGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "RISCVGenSubtargetInfo.inc"
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#endif
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