llvm-project/llvm/lib/CodeGen
Jakob Stoklund Olesen fe6e07fd8a Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots.
This allows us to always keep the smaller slot for an instruction which is what
we want when a register has early clobber defines.

Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed.

llvm-svn: 128886
2011-04-05 15:18:18 +00:00
..
AsmPrinter Remove dead code. 2011-03-31 16:53:49 +00:00
SelectionDAG Revamp the SjLj "dispatch setup" intrinsic. 2011-04-05 01:37:43 +00:00
AggressiveAntiDepBreaker.cpp Simplify AggressiveAntiDepBreaker's use of register aliases. 2010-12-14 23:23:15 +00:00
AggressiveAntiDepBreaker.h Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. 2010-07-15 18:43:09 +00:00
AllocationOrder.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
AllocationOrder.h Try harder to get the hint by preferring to evict hint interference. 2011-02-25 01:04:22 +00:00
Analysis.cpp Minor code re-structuring. 2011-03-19 17:03:16 +00:00
AntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
BranchFolding.cpp Add more debugging output. 2011-02-21 23:39:48 +00:00
BranchFolding.h Tail merging pass shall not break up IT blocks. rdar://8115404 2010-06-22 01:18:16 +00:00
CMakeLists.txt Add an InterferenceCache class for caching per-block interference ranges. 2011-04-02 06:03:35 +00:00
CalcSpillWeights.cpp Recompute register class and hint for registers created during spilling. 2011-03-29 21:20:19 +00:00
CallingConvLower.cpp Improve readability with some whitespace! 2011-03-04 22:47:12 +00:00
CodeGen.cpp Stub out a new LiveDebugVariables pass. 2010-11-30 02:17:10 +00:00
CodePlacementOpt.cpp Fix some typos. 2011-03-02 04:03:46 +00:00
CriticalAntiDepBreaker.cpp Fix PostRA antidependence breaker. 2011-02-08 17:39:46 +00:00
CriticalAntiDepBreaker.h Typo. 2011-02-09 22:55:48 +00:00
DeadMachineInstructionElim.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
DwarfEHPrepare.cpp Remove PHINode::reserveOperandSpace(). Instead, add a parameter to 2011-03-30 11:28:46 +00:00
ELF.h Merge System into Support. 2010-11-29 18:16:10 +00:00
ELFCodeEmitter.cpp Get rid of a bunch of duplicated ELF enum values. 2010-07-16 07:53:29 +00:00
ELFCodeEmitter.h change EH related stuff (other than EH_LABEL) to use MCSymbol 2010-03-14 01:41:15 +00:00
ELFWriter.cpp Move broken HasCommonSymbols to ELFWriter.cpp. 2011-02-14 16:51:08 +00:00
ELFWriter.h Tidy some #includes and forward-declarations, and move the C binding code 2010-08-07 00:43:20 +00:00
EdgeBundles.cpp Add a hidden command line option to display edge bundle graphs as they are 2011-01-05 21:50:24 +00:00
ExpandISelPseudos.cpp Rename ExpandPseudos to ExpandISelPseudos to help clarify its role. 2010-11-18 18:45:06 +00:00
GCMetadata.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
GCMetadataPrinter.cpp mcize the gc metadata printing stuff. 2010-04-04 07:39:04 +00:00
GCStrategy.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
IfConversion.cpp Prune includes. 2010-11-06 11:45:59 +00:00
InlineSpiller.cpp Pick a conservative register class when creating a small live range for remat. 2011-03-31 03:54:44 +00:00
InterferenceCache.cpp Add an InterferenceCache class for caching per-block interference ranges. 2011-04-02 06:03:35 +00:00
InterferenceCache.h Add an InterferenceCache class for caching per-block interference ranges. 2011-04-02 06:03:35 +00:00
IntrinsicLowering.cpp Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call. 2011-01-08 01:24:27 +00:00
LLVMTargetMachine.cpp Integrated-As: Add support for setting the AllowTemporaryLabels flag via 2011-03-28 22:49:19 +00:00
LatencyPriorityQueue.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
LiveDebugVariables.cpp Reapply r128045 and r128051 with fixes. 2011-03-22 22:33:08 +00:00
LiveDebugVariables.h Emit DBG_VALUE instructions from LiveDebugVariables. 2010-12-03 21:47:10 +00:00
LiveInterval.cpp Replace a broken LiveInterval::MergeValueInAsValue() with something simpler. 2011-03-19 23:02:49 +00:00
LiveIntervalAnalysis.cpp Allow coalescing with reserved physregs in certain cases: 2011-04-04 21:00:03 +00:00
LiveIntervalUnion.cpp Add tags to live interval unions to avoid using stale queries. 2011-02-09 21:52:03 +00:00
LiveIntervalUnion.h Fix bug found by valgrind. 2011-03-31 15:14:11 +00:00
LiveRangeEdit.cpp Treat clones the same as their origin. 2011-03-30 02:52:39 +00:00
LiveRangeEdit.h Treat clones the same as their origin. 2011-03-30 02:52:39 +00:00
LiveStackAnalysis.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
LiveVariables.cpp Reduce vector reallocations. 2011-03-08 17:28:36 +00:00
LocalStackSlotAllocation.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
LowerSubregs.cpp Trailing whitespace. 2011-02-25 22:53:20 +00:00
MachineBasicBlock.cpp Add LiveIntervals::getLastSplitPoint(). 2011-02-04 19:33:11 +00:00
MachineCSE.cpp fit in 80 cols and use MBB::isSuccessor instead of a hand 2011-01-10 07:51:31 +00:00
MachineDominators.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
MachineFunction.cpp MachineConstantPoolValues are not uniqued, so they need to be freed if they 2011-02-22 08:54:30 +00:00
MachineFunctionAnalysis.cpp Clean up a funky pass registration that got passed over when I got rid of static constructors. 2011-01-04 00:55:21 +00:00
MachineFunctionPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineFunctionPrinterPass.cpp Reapply r110396, with fixes to appease the Linux buildbot gods. 2010-08-06 18:33:48 +00:00
MachineInstr.cpp Add FrameSetup MI flags 2011-03-05 18:43:04 +00:00
MachineLICM.cpp Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. 2011-03-07 21:56:36 +00:00
MachineLoopInfo.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
MachineLoopRanges.cpp Add MachineLoopRange comparators for sorting loop lists by number and by area. 2010-12-17 18:13:52 +00:00
MachineModuleInfo.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
MachineModuleInfoImpls.cpp Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that 2010-03-10 22:34:10 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns." 2011-02-21 23:21:26 +00:00
MachineSSAUpdater.cpp Fix PR7096. When a block containing multiple defs is tail duplicated, the 2010-05-10 17:14:26 +00:00
MachineSink.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
MachineVerifier.cpp Allow kill flags on two-address instructions. They are harmless. 2011-03-31 17:52:41 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
PHIElimination.cpp Add an option to disable critical edge splitting in PHIElimination. 2011-03-10 05:59:17 +00:00
PHIEliminationUtils.cpp Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
PHIEliminationUtils.h Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
Passes.cpp Use the fast register allocator by default for -O0 builds. 2010-06-03 00:39:06 +00:00
PeepholeOptimizer.cpp Add a peephole optimization to optimize pairs of bitcasts. e.g. 2011-03-15 05:13:13 +00:00
PostRASchedulerList.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
PreAllocSplitting.cpp Remove some checks for StrongPHIElim. These checks make it impossible to use an 2010-12-19 18:03:27 +00:00
ProcessImplicitDefs.cpp Place context in member variables instead of passing around pointers. 2011-03-14 20:57:14 +00:00
PrologEpilogInserter.cpp Allow a target to choose whether to prefer the scavenger emergency spill slot 2011-03-03 20:01:52 +00:00
PrologEpilogInserter.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
PseudoSourceValue.cpp Merge System into Support. 2010-11-29 18:16:10 +00:00
README.txt
RegAllocBase.h Tag cached interference with a user-provided tag instead of the virtual register number. 2011-03-16 22:56:11 +00:00
RegAllocBasic.cpp The basic register allocator must also use the inline spiller. 2011-03-31 23:02:17 +00:00
RegAllocFast.cpp Mark that the return is using EAX so that we don't use it for some other 2011-02-04 22:44:08 +00:00
RegAllocGreedy.cpp Stop precomputing last split points, query the SplitAnalysis cache on demand. 2011-04-05 04:20:29 +00:00
RegAllocLinearScan.cpp Allow coalescing with reserved physregs in certain cases: 2011-04-04 21:00:03 +00:00
RegAllocPBQP.cpp Make SpillIs an optional pointer. Avoid creating a bunch of temporary SmallVectors. 2011-03-10 01:21:58 +00:00
RegisterCoalescer.cpp Analysis groups need to initialize their default implementations. 2010-10-13 21:49:58 +00:00
RegisterScavenging.cpp Teach the register scavenger to take subregs into account when finding a free register. 2011-03-05 00:20:19 +00:00
RenderMachineFunction.cpp The variable liTRC is not used for anything useful, zap it 2010-10-21 16:04:43 +00:00
RenderMachineFunction.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
ScheduleDAG.cpp Introducing a new method of tracking register pressure. We can't 2011-02-04 03:18:17 +00:00
ScheduleDAGEmit.cpp Change all self assignments X=X to (void)X, so that we can turn on a 2010-12-23 00:58:24 +00:00
ScheduleDAGInstrs.cpp Do not model all INLINEASM instructions as having unmodelled side effects. 2011-01-07 23:50:32 +00:00
ScheduleDAGInstrs.h Properly model the latency of register defs which are 1) function returns or 2010-10-23 02:10:46 +00:00
ScheduleDAGPrinter.cpp Pass the graph to the DOTGraphTraits.getEdgeAttributes(). 2011-02-27 04:11:03 +00:00
ScoreboardHazardRecognizer.cpp Convert -enable-sched-cycles and -enable-sched-hazard to -disable 2011-01-21 05:51:33 +00:00
ShadowStackGC.cpp use ArgOperand API and CallSite to access arguments of CallInst 2010-06-25 08:48:19 +00:00
ShrinkWrapping.cpp Fix bug found by new clang warning. 2011-01-20 02:43:19 +00:00
SimpleRegisterCoalescing.cpp Allow coalescing with reserved physregs in certain cases: 2011-04-04 21:00:03 +00:00
SimpleRegisterCoalescing.h Extract physreg joining policy to a separate method. 2011-04-04 20:59:59 +00:00
SjLjEHPrepare.cpp Revamp the SjLj "dispatch setup" intrinsic. 2011-04-05 01:37:43 +00:00
SlotIndexes.cpp Use basic block numbers as indexes when mapping slot index ranges. 2011-04-02 06:03:31 +00:00
SpillPlacement.cpp Precompute block frequencies, pow() isn't free. 2011-03-04 00:58:40 +00:00
SpillPlacement.h Precompute block frequencies, pow() isn't free. 2011-03-04 00:58:40 +00:00
Spiller.cpp Change the Spiller interface to take a LiveRangeEdit reference. 2011-03-10 01:51:42 +00:00
Spiller.h Change the Spiller interface to take a LiveRangeEdit reference. 2011-03-10 01:51:42 +00:00
SplitKit.cpp Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots. 2011-04-05 15:18:18 +00:00
SplitKit.h Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots. 2011-04-05 15:18:18 +00:00
Splitter.cpp Begin adding static dependence information to passes, which will allow us to 2010-10-12 19:48:12 +00:00
Splitter.h Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 2010-10-19 17:21:58 +00:00
StackProtector.cpp Inline check that's used only once. 2011-03-29 17:12:55 +00:00
StackSlotColoring.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
StrongPHIElimination.cpp Add some statistics to StrongPHIElimination. 2011-02-14 02:09:18 +00:00
TailDuplication.cpp Update comments. 2011-02-04 01:10:12 +00:00
TargetInstrInfoImpl.cpp Convert -enable-sched-cycles and -enable-sched-hazard to -disable 2011-01-21 05:51:33 +00:00
TargetLoweringObjectFileImpl.cpp Reapply 127939 since Daniel fixed the breakage. <rdar://problem/9012638> 2011-03-19 02:42:31 +00:00
TwoAddressInstructionPass.cpp Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 2011-03-02 01:08:17 +00:00
UnreachableBlockElim.cpp Make more passes preserve dominators (or state that they preserve dominators if 2011-01-08 17:01:52 +00:00
VirtRegMap.cpp Don't completely eliminate identity copies that also modify super register liveness. 2011-03-31 17:55:25 +00:00
VirtRegMap.h This method belonged in VirtRegMap. 2011-02-19 00:38:43 +00:00
VirtRegRewriter.cpp Fix evil VirtRegRewriter bug. 2011-03-30 18:14:07 +00:00
VirtRegRewriter.h Code clean up. Move includes from VirtRegRewriter.h to VirtRegRewriter.cpp. 2010-04-06 17:19:55 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.