Matthias Braun c045c557b0 Relax fast register allocator related test cases; NFC ... - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532		2018-10-29 20:10:42 +00:00
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2008-11-17-Shl64.ll	…
2009-01-08-Crash.ll	…
2009-01-14-Remat-Crash.ll	…
2009-03-27-v2f64-param.ll	…
2009-07-15-store192.ll	…
2010-02-25-LSR-Crash.ll	…
2011-01-31-DAGCombineBug.ll	…
2011-08-01-DynamicAllocBug.ll	…
DbgValueOtherTargets.test	…
addsub64.ll	…
aliases.ll	…
align.ll	…
alignment.ll	…
ashr.ll	[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)	2018-07-15 16:27:07 +00:00
atomic.ll	…
basictest.ll	…
bigstructret.ll	…
byVal.ll	…
call.ll	…
codemodel.ll	…
constants.ll	…
dwarf_debug.ll	Relax fast register allocator related test cases; NFC	2018-10-29 20:10:42 +00:00
epilogue_prologue.ll	…
events.ll	…
exception.ll	…
float-intrinsics.ll	…
fneg.ll	…
getid.ll	…
globals.ll	…
indirectbr.ll	…
inline-asm.ll	…
ladd_lsub_combine.ll	…
licm-ldwcp.ll	…
linkage.ll	…
lit.local.cfg	…
llvm-intrinsics.ll	…
load.ll	…
memcpy.ll	…
misc-intrinsics.ll	…
mkmsk.ll	…
mul64.ll	…
offset_folding.ll	…
private.ll	…
ps-intrinsics.ll	…
resources.ll	…
resources_combine.ll	…
scavenging.ll	…
section-name.ll	…
sext.ll	…
shedulingPreference.ll	…
sr-intrinsics.ll	…
store.ll	…
switch.ll	…
switch_long.ll	…
threads.ll	…
tls.ll	…
trampoline.ll	…
trap.ll	…
unaligned_load.ll	…
unaligned_store.ll	…
unaligned_store_combine.ll	…
varargs.ll	…
zext.ll	…
zextfree.ll	…