| .. |
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AsmParser
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[AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
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2018-03-12 17:29:24 +00:00 |
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Disassembler
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[AMDGPU][MC] Corrected GATHER4 opcodes
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2018-03-12 15:03:34 +00:00 |
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InstPrinter
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[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
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2018-01-15 18:49:15 +00:00 |
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MCTargetDesc
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AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer
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2018-02-16 23:04:11 +00:00 |
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TargetInfo
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Add backend name to Target to enable runtime info to be fed back into TableGen
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2017-11-15 23:55:44 +00:00 |
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Utils
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[AMDGPU] Add default ISA version targets
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2018-03-06 18:33:55 +00:00 |
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AMDGPU.h
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[AMDGPU] Change constant addr space to 4
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2018-02-13 18:00:25 +00:00 |
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AMDGPU.td
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AMDGPU: Add fast fmaf feature to gfx702
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2018-02-27 21:46:15 +00:00 |
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AMDGPUAliasAnalysis.cpp
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[AMDGPU] Change constant addr space to 4
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2018-02-13 18:00:25 +00:00 |
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AMDGPUAliasAnalysis.h
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Add option to stress calls
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2017-09-21 07:00:48 +00:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
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2017-08-31 21:56:16 +00:00 |
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AMDGPUAnnotateUniformValues.cpp
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AMDGPU: Fix converting unanalyzable global loads to SMRD
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2017-07-12 23:06:18 +00:00 |
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AMDGPUArgumentUsageInfo.cpp
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[CodeGen] Rename functions PrintReg* to printReg*
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2017-11-28 12:42:37 +00:00 |
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AMDGPUArgumentUsageInfo.h
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[AMDGPU] Fixed MSVC build break
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2017-08-04 10:53:07 +00:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU] do not generate .AMDGPU.config for amdpal os type
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2018-02-06 13:39:38 +00:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] add labels to +DumpCode output
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2017-12-08 14:09:34 +00:00 |
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AMDGPUCallLowering.cpp
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[AMDGPU] Change constant addr space to 4
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2018-02-13 18:00:25 +00:00 |
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AMDGPUCallLowering.h
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AMDGPU: Start defining a calling convention
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2017-05-17 21:56:25 +00:00 |
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AMDGPUCallingConv.td
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AMDGPU: Initial implementation of calls
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2017-08-01 19:54:18 +00:00 |
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AMDGPUCodeGenPrepare.cpp
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Reapply "AMDGPU: Add 32-bit constant address space"
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2018-02-09 16:57:57 +00:00 |
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AMDGPUFrameLowering.cpp
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…
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AMDGPUFrameLowering.h
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Move TargetFrameLowering.h to CodeGen where it's implemented
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2017-11-03 22:32:11 +00:00 |
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Use a more correct getValueMapping
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2018-03-01 21:08:51 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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Revert: r327172 "Correct load-op-store cycle detection analysis"
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2018-03-10 02:16:15 +00:00 |
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AMDGPUISelLowering.cpp
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Pass Divergence Analysis data to Selection DAG to drive divergence
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2018-03-05 15:12:21 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: Fix build warning about override
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2018-03-05 16:25:10 +00:00 |
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AMDGPUInline.cpp
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[AMDGPU] Port of HSAIL inliner
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2017-09-20 04:25:58 +00:00 |
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AMDGPUInstrInfo.cpp
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Reapply "AMDGPU: Add 32-bit constant address space"
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2018-02-09 16:57:57 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPU: Fix layering issue
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2018-02-09 16:57:48 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
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2018-01-31 20:18:04 +00:00 |
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AMDGPUInstructionSelector.cpp
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Reapply "AMDGPU: Add 32-bit constant address space"
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2018-02-09 16:57:57 +00:00 |
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AMDGPUInstructionSelector.h
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[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
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2017-11-16 00:46:35 +00:00 |
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AMDGPUInstructions.td
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[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
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2018-03-09 17:41:39 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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Rename AttributeSet to AttributeList
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2017-03-21 16:57:19 +00:00 |
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AMDGPUIntrinsicInfo.h
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…
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AMDGPUIntrinsics.td
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AMDGPU: Remove legacy bfe intrinsics
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2017-04-03 18:08:08 +00:00 |
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AMDGPULegalizerInfo.cpp
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AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT
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2018-03-12 13:35:53 +00:00 |
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AMDGPULegalizerInfo.h
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AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
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2018-03-08 16:24:16 +00:00 |
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AMDGPULibCalls.cpp
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Make helpers static. NFC.
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2017-11-24 14:55:41 +00:00 |
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AMDGPULibFunc.cpp
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[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
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2017-11-04 17:37:43 +00:00 |
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AMDGPULibFunc.h
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[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
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2017-11-04 17:37:43 +00:00 |
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AMDGPULowerIntrinsics.cpp
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Extend memcpy expansion in Transform/Utils to handle wider operand types.
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2017-07-07 02:00:06 +00:00 |
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AMDGPUMCInstLower.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AMDGPUMCInstLower.h
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…
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AMDGPUMachineCFGStructurizer.cpp
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
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AMDGPUMachineFunction.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AMDGPUMachineFunction.h
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Sort the remaining #include lines in include/... and lib/....
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2017-06-06 11:49:48 +00:00 |
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AMDGPUMachineModuleInfo.cpp
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AMDGPU: Implement memory model
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2017-07-21 21:19:23 +00:00 |
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AMDGPUMachineModuleInfo.h
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AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
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2017-09-07 16:14:21 +00:00 |
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AMDGPUMacroFusion.cpp
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AMDGPU: Add macro fusion schedule DAG mutation
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2017-07-06 20:57:05 +00:00 |
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AMDGPUMacroFusion.h
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AMDGPU: Add macro fusion schedule DAG mutation
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2017-07-06 20:57:05 +00:00 |
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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[AMDGPU] Fix lowering enqueue kernel when kernel has no name
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2018-03-12 16:34:06 +00:00 |
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AMDGPUOpenCLImageTypeLoweringPass.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
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AMDGPUPTNote.h
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AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
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2017-10-12 18:59:54 +00:00 |
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AMDGPUPromoteAlloca.cpp
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AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
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2018-02-16 19:14:17 +00:00 |
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AMDGPURegAsmNames.inc.cpp
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AMDGPU: Work around build special casing .inc files
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2017-06-08 19:25:21 +00:00 |
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AMDGPURegisterBankInfo.cpp
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AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT
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2018-03-12 13:35:53 +00:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Define instruction mapping for G_OR
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2018-03-01 21:25:25 +00:00 |
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AMDGPURegisterBanks.td
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AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
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2018-03-01 19:27:10 +00:00 |
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AMDGPURegisterInfo.cpp
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
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AMDGPURegisterInfo.h
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[AMDGPU] Return true in enableMultipleCopyHints().
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2018-02-17 10:00:28 +00:00 |
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AMDGPURegisterInfo.td
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AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
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2017-07-29 03:44:07 +00:00 |
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AMDGPURewriteOutArguments.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
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AMDGPUSubtarget.cpp
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AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
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2018-03-08 16:24:16 +00:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
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2018-03-09 17:41:39 +00:00 |
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AMDGPUTargetMachine.cpp
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[AMDGPU] Change constant addr space to 4
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2018-02-13 18:00:25 +00:00 |
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AMDGPUTargetMachine.h
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(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
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2017-12-22 18:21:59 +00:00 |
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AMDGPUTargetObjectFile.cpp
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AMDGPU: Fix set but not used warnings related to AMDGPUAS
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2017-11-01 19:12:38 +00:00 |
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AMDGPUTargetObjectFile.h
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[AMDGPU] Get address space mapping by target triple environment
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2017-03-27 14:04:01 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
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2018-03-09 17:41:39 +00:00 |
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AMDGPUTargetTransformInfo.h
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[AMDGPU] Increased vector length for global/constant loads.
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2018-03-07 17:09:18 +00:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
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2017-10-17 21:27:42 +00:00 |
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AMDGPUUnifyMetadata.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-10 00:46:15 +00:00 |
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AMDILCFGStructurizer.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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AMDKernelCodeT.h
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[AMDGPU] Revert r310429 changes in AMDKernelCodeT.h which broke some build bots.
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2017-08-09 00:06:29 +00:00 |
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BUFInstructions.td
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[AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
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2018-03-12 17:29:24 +00:00 |
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CMakeLists.txt
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
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CaymanInstructions.td
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[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
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2017-12-07 10:40:31 +00:00 |
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DSInstructions.td
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[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
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2018-03-09 17:41:39 +00:00 |
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EvergreenInstructions.td
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AMDGPU: Select BFI patterns with 64-bit ints
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2018-02-07 00:21:34 +00:00 |
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FLATInstructions.td
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[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
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2017-11-27 17:14:35 +00:00 |
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GCNHazardRecognizer.cpp
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[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
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2017-12-07 20:34:25 +00:00 |
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GCNHazardRecognizer.h
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[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
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2017-12-07 20:34:25 +00:00 |
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GCNILPSched.cpp
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
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GCNIterativeScheduler.cpp
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[NFC] fix trivial typos in comments and documents
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2018-01-29 05:17:03 +00:00 |
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GCNIterativeScheduler.h
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AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
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2017-11-20 14:35:53 +00:00 |
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GCNMinRegStrategy.cpp
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[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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2017-08-08 23:53:55 +00:00 |
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GCNProcessors.td
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AMDGPU: Bring processors and features in sync with the spec
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2018-02-16 21:26:25 +00:00 |
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GCNRegPressure.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
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GCNRegPressure.h
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
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2017-12-13 02:51:04 +00:00 |
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GCNSchedStrategy.cpp
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[NFC] fix trivial typos in comments
|
2018-01-22 05:54:46 +00:00 |
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GCNSchedStrategy.h
|
fix typos in comments and error messges; NFC
|
2017-07-13 06:48:39 +00:00 |
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LLVMBuild.txt
|
…
|
|
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MIMGInstructions.td
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[AMDGPU][MC] Corrected GATHER4 opcodes
|
2018-03-12 15:03:34 +00:00 |
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R600ClauseMergePass.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
R600ControlFlowFinalizer.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
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R600Defines.h
|
…
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R600EmitClauseMarkers.cpp
|
Sort the remaining #include lines in include/... and lib/....
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2017-06-06 11:49:48 +00:00 |
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R600ExpandSpecialInstrs.cpp
|
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
|
2017-08-10 00:46:15 +00:00 |
|
R600FrameLowering.cpp
|
Sort the remaining #include lines in include/... and lib/....
|
2017-06-06 11:49:48 +00:00 |
|
R600FrameLowering.h
|
AMDGPU: Initial implementation of calls
|
2017-08-01 19:54:18 +00:00 |
|
R600ISelLowering.cpp
|
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
|
2017-12-04 23:07:28 +00:00 |
|
R600ISelLowering.h
|
Add DAG argument to canMergeStoresTo NFC.
|
2017-07-10 20:25:54 +00:00 |
|
R600InstrFormats.td
|
AMDGPU: Remove global isGCN predicates
|
2017-10-03 00:06:41 +00:00 |
|
R600InstrInfo.cpp
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600InstrInfo.h
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600Instructions.td
|
AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
|
2018-01-29 23:29:26 +00:00 |
|
R600Intrinsics.td
|
AMDGPU: Make intrinsics speculatable
|
2017-05-02 16:57:44 +00:00 |
|
R600MachineFunctionInfo.cpp
|
…
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|
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R600MachineFunctionInfo.h
|
…
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|
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R600MachineScheduler.cpp
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[CodeGen] Rename DEBUG_TYPE to match passnames
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2017-07-11 22:08:28 +00:00 |
|
R600MachineScheduler.h
|
…
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|
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R600OptimizeVectorRegisters.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
R600Packetizer.cpp
|
AMDGPU/R600: Initialize more passes
|
2017-08-02 22:19:45 +00:00 |
|
R600Processors.td
|
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
|
2017-12-04 23:07:28 +00:00 |
|
R600RegisterInfo.cpp
|
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
|
2018-01-24 18:09:53 +00:00 |
|
R600RegisterInfo.h
|
AMDGPU: Start defining a calling convention
|
2017-05-17 21:56:25 +00:00 |
|
R600RegisterInfo.td
|
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files
|
2017-07-29 03:44:07 +00:00 |
|
R600Schedule.td
|
…
|
|
|
R700Instructions.td
|
…
|
|
|
SIAnnotateControlFlow.cpp
|
AMDGPU: Error in SIAnnotateControlFlow instead of assert
|
2018-01-17 16:30:01 +00:00 |
|
SIDebuggerInsertNops.cpp
|
Sort the remaining #include lines in include/... and lib/....
|
2017-06-06 11:49:48 +00:00 |
|
SIDefines.h
|
AMDGPU/SI: Add d16 support for image intrinsics.
|
2018-01-18 22:08:53 +00:00 |
|
SIFixSGPRCopies.cpp
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
SIFixVGPRCopies.cpp
|
…
|
|
|
SIFixWWMLiveness.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SIFoldOperands.cpp
|
AMDGPU: Fix crash when constant folding with physreg operand
|
2018-03-10 16:05:35 +00:00 |
|
SIFrameLowering.cpp
|
[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
|
2018-02-26 14:46:43 +00:00 |
|
SIFrameLowering.h
|
[AMDGPU] AMDPAL scratch buffer support
|
2017-09-29 09:49:35 +00:00 |
|
SIISelLowering.cpp
|
[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
|
2018-03-09 17:41:39 +00:00 |
|
SIISelLowering.h
|
AMDGPU/SI: Add d16 support for buffer intrinsics.
|
2018-01-12 21:12:19 +00:00 |
|
SIInsertSkips.cpp
|
Fix compiler warning introduced in r325931. NFC.
|
2018-02-23 19:11:33 +00:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.
|
2018-02-19 19:19:59 +00:00 |
|
SIInsertWaits.cpp
|
[NFC] fix trivial typos in comments
|
2018-02-22 07:48:29 +00:00 |
|
SIInstrFormats.td
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
|
2018-02-23 18:25:08 +00:00 |
|
SIInstrInfo.cpp
|
[AMDGPU] added writelane intrinsic
|
2018-02-28 19:10:32 +00:00 |
|
SIInstrInfo.h
|
[AMDGPU][MC] Added lds support for MUBUF instructions
|
2018-02-21 13:13:48 +00:00 |
|
SIInstrInfo.td
|
[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
|
2018-03-09 17:41:39 +00:00 |
|
SIInstructions.td
|
AMDGPU/GCN: Promote i16 ctpop
|
2018-03-02 02:50:22 +00:00 |
|
SIIntrinsics.td
|
AMDGPU: Remove legacy export intrinsic
|
2017-04-04 16:34:39 +00:00 |
|
SILoadStoreOptimizer.cpp
|
AMDGPU: Track physreg uses in SILoadStoreOptimizer
|
2018-02-23 10:45:56 +00:00 |
|
SILowerControlFlow.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SILowerI1Copies.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SIMachineFunctionInfo.cpp
|
Reapply "AMDGPU: Add 32-bit constant address space"
|
2018-02-09 16:57:57 +00:00 |
|
SIMachineFunctionInfo.h
|
[AMDGPU] stop buffer_store being moved illegally
|
2018-02-20 10:03:38 +00:00 |
|
SIMachineScheduler.cpp
|
Rename LiveIntervalAnalysis.h to LiveIntervals.h
|
2017-12-13 02:51:04 +00:00 |
|
SIMachineScheduler.h
|
AMDGPU/SI: Force exports at the end for SI scheduler
|
2017-07-25 20:36:58 +00:00 |
|
SIMemoryLegalizer.cpp
|
[AMDGPU] More descriptive names in the memory legalizer
|
2018-02-09 06:05:33 +00:00 |
|
SIOptimizeExecMasking.cpp
|
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
|
2018-02-23 18:25:08 +00:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
MachineFunction: Return reference from getFunction(); NFC
|
2017-12-15 22:22:58 +00:00 |
|
SIPeepholeSDWA.cpp
|
Test commit - change comment slightly.
|
2018-03-11 03:27:50 +00:00 |
|
SIRegisterInfo.cpp
|
[AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not found
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2018-03-01 17:36:43 +00:00 |
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SIRegisterInfo.h
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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
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2018-01-24 18:09:53 +00:00 |
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SIRegisterInfo.td
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[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
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2018-01-10 14:22:19 +00:00 |
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SISchedule.td
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SIShrinkInstructions.cpp
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[AMDGPU] Shrinking V_SUBBREV_U32
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2018-02-24 01:32:32 +00:00 |
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SIWholeQuadMode.cpp
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MachineFunction: Return reference from getFunction(); NFC
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2017-12-15 22:22:58 +00:00 |
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SMInstructions.td
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Pass Divergence Analysis data to Selection DAG to drive divergence
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2018-03-05 15:12:21 +00:00 |
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SOPInstructions.td
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AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
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2017-10-24 10:26:59 +00:00 |
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VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td
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[AMDGPU] Copy impdefs from pseudo to real instructions
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2018-01-15 17:55:35 +00:00 |
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VOP2Instructions.td
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[AMDGPU] added writelane intrinsic
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2018-02-28 19:10:32 +00:00 |
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VOP3Instructions.td
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[AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9
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2018-03-09 07:21:43 +00:00 |
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VOP3PInstructions.td
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AMDGPU: Add max-mix-insts subtarget feature
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2017-10-25 07:00:51 +00:00 |
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VOPCInstructions.td
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[AMDGPU] Copy impdefs from pseudo to real instructions
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2018-01-15 17:55:35 +00:00 |
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VOPInstructions.td
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[MachineOperand][Target] MachineOperand::isRenamable semantics changes
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2018-02-23 18:25:08 +00:00 |
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