forked from OSchip/llvm-project
81 lines
4.3 KiB
TableGen
81 lines
4.3 KiB
TableGen
//=-HexagonScheduleV60.td - HexagonV60 Scheduling Definitions *- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
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// This file describes that machine information.
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//
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// |===========|==================================================|
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// | PIPELINE | Instruction Classes |
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// |===========|==================================================|
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// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
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// |-----------|--------------------------------------------------|
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// | SLOT1 | LD ST ALU32 |
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// |-----------|--------------------------------------------------|
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// | SLOT2 | XTYPE ALU32 J JR |
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// |-----------|--------------------------------------------------|
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// | SLOT3 | XTYPE ALU32 J CR |
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// |===========|==================================================|
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//
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//
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// In addition to using the above SLOTS, there are also six vector pipelines
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// in the CVI co-processor in the Hexagon V60 machine.
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//
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// |=========| |=========| |=========| |=========| |=========| |=========|
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// SLOT | CVI_LD | |CVI_MPY3 | |CVI_MPY2 | |CVI_SHIFT| |CVI_XLANE| | CVI_ST |
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// ==== |=========| |=========| |=========| |=========| |=========| |=========|
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// S0-3 | | | CVI_VA | | CVI_VA | | CVI_VA | | CVI_VA | | |
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// S2-3 | | | CVI_VX | | CVI_VX | | | | | | |
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// S0-3 | | | | | | | | | CVI_VP | | |
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// S0-3 | | | | | | | CVI_VS | | | | |
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// S0-1 |(CVI_LD) | | CVI_LD | | CVI_LD | | CVI_LD | | CVI_LD | | |
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// S0-1 |(C*TMP_LD) | | | | | | | | | |
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// S01 |(C*_LDU) | | | | | | | | C*_LDU | | |
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// S0 | | | CVI_ST | | CVI_ST | | CVI_ST | | CVI_ST | |(CVI_ST) |
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// S0 | | | | | | | | | | |(C*TMP_ST)
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// S01 | | | | | | | | | VSTU | |(C*_STU) |
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// |=========| |=========| |=========| |=========| |=========| |=========|
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// |=====================| |=====================|
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// | CVI_MPY2 & CVI_MPY3 | |CVI_XLANE & CVI_SHIFT|
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// |=====================| |=====================|
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// S0-3 | CVI_VA_DV | | CVI_VA_DV |
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// S0-3 | | | CVI_VP_DV |
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// S2-3 | CVI_VX_DV | | |
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// |=====================| |=====================|
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// |=====================================================================|
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// S0-3 | CVI_HIST Histogram |
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// S0123| CVI_VA_EXT Extract |
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// |=====================================================================|
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def HexagonV60ItinList : DepScalarItinV60, ScalarItin,
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DepHVXItinV60,
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HVXItin, PseudoItin {
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list<InstrItinData> ItinList =
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!listconcat(DepScalarItinV60_list, ScalarItin_list,
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DepHVXItinV60_list, HVXItin_list, PseudoItin_list);
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}
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def HexagonItinerariesV60 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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CVI_ALL_NOMEM, CVI_ZW],
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[Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>;
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def HexagonModelV60 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV60;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V60 Resource Definitions -
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//===----------------------------------------------------------------------===//
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