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llvm-project/llvm/unittests
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Schuyler Eldridge 63f417ef39
[ADT] Remove 0-width Asserts in APInt.getZExtValue 
Remove assertion that disallows getting a zero-extended value from a
zero-width APInt.  This check is too restrictive and makes it difficult
to use APInt to model zero-width things, e.g., zero-width wires in the
CIRCT project.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Reviewed By: lattner, darthscsi, nikic

Differential Revision: https://reviews.llvm.org/D114768
 		2021-11-30 17:03:12 -05:00
..
ADT [ADT] Remove 0-width Asserts in APInt.getZExtValue 2021-11-30 17:03:12 -05:00
Analysis [LoopInfo] Fix function getInductionVariable 2021-11-11 16:22:42 +08:00
AsmParser
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BinaryFormat [llvm][clang][NFC] updates inline licence info 2021-08-11 02:48:53 +00:00
Bitcode [AMDGPU] Set the default globals address space to 1 2020-11-20 15:46:53 +00:00
Bitstream PR51018: Remove explicit conversions from SmallString to StringRef to future-proof against C++23 2021-07-08 13:37:57 -07:00
CodeGen [DebugInfo][InstrRef] Avoid dropping fragment info during PHI elimination 2021-11-30 11:32:31 +00:00
DebugInfo [unittests] [DWARF] Generalize path separator expectations 2021-11-05 21:50:43 +02:00
Demangle [Demangle] Add support for D anonymous symbols 2021-11-29 16:05:48 -08:00
ExecutionEngine [JITLink] Fix splitBlock if there are symbols span across the boundary 2021-11-15 13:55:21 -08:00
FileCheck Bump googletest to 1.10.0 2021-05-14 19:16:31 +02:00
Frontend [MLIR][OpenMP] Fixed the missing inclusive clause in omp.wsloop and fix order clause 2021-10-28 14:18:05 +05:30
FuzzMutate [FuzzMutate] Add mutator to modify instruction flags. 2021-01-23 19:05:20 +00:00
IR [DebugInfo] Do not replace existing nodes from DICompileUnit 2021-11-29 19:46:10 -08:00
InterfaceStub [ifs][elfabi] Merge llvm-ifs/elfabi tools 2021-07-19 11:23:19 -07:00
LineEditor
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Linker [RGT] Recode more unreachable assertions and tautologies 2021-03-19 09:17:22 -07:00
MC Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
MI Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
MIR [Codegen] Set ARITH_FENCE as meta-instruction 2021-10-21 10:19:22 +08:00
Object [XCOFF] Improve error message context. 2021-10-11 02:52:20 +00:00
ObjectYAML
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Option [OptTable] Reapply Improve error message output for grouped short options 2021-09-03 11:13:52 +01:00
Passes [AIX] Enable rtl for plugins test 2021-10-22 12:08:22 -04:00
ProfileData Coverage: Fix iterated type for LineCoverageIterator 2021-11-16 14:39:30 -08:00
Remarks
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Support Recommit [ThreadPool] Support returning futures with results. 2021-11-25 20:07:53 +00:00
TableGen Make TableGenGlobalISel an object library 2021-06-05 15:04:33 +02:00
Target [AArch64] Always add -tune-cpu argument to -cc1 driver 2021-10-19 14:57:51 +01:00
TextAPI [llvm][TextAPI] add mapping from OS string to Platform 2021-05-06 16:25:56 -07:00
Transforms [LV] Record memory widening decisions (NFCI) 2021-10-18 18:03:35 +03:00
XRay Put back the trailing commas on TYPED_TEST_SUITE 2021-05-17 14:14:13 +02:00
tools [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
CMakeLists.txt [MIRPrinter] Add machine metadata support. 2021-06-19 12:48:08 -04:00
unittest.cfg.in
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